drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/init.h>
  39 #include <linux/string.h>
  40 #include <linux/slab.h>
  41
  42 #include <rdma/ib_verbs.h>
  43 #include <rdma/ib_cache.h>
  44 #include <rdma/ib_pack.h>
  45
  46 #include "mthca_dev.h"
  47 #include "mthca_cmd.h"
  48 #include "mthca_memfree.h"
  49 #include "mthca_wqe.h"
  50
  51 enum {
  52         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  53         MTHCA_ACK_REQ_FREQ       = 10,
  54         MTHCA_FLIGHT_LIMIT       = 9,
  55         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  56         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  57         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  58 };
  59
  60 enum {
  61         MTHCA_QP_STATE_RST  = 0,
  62         MTHCA_QP_STATE_INIT = 1,
  63         MTHCA_QP_STATE_RTR  = 2,
  64         MTHCA_QP_STATE_RTS  = 3,
  65         MTHCA_QP_STATE_SQE  = 4,
  66         MTHCA_QP_STATE_SQD  = 5,
  67         MTHCA_QP_STATE_ERR  = 6,
  68         MTHCA_QP_STATE_DRAINING = 7
  69 };
  70
  71 enum {
  72         MTHCA_QP_ST_RC  = 0x0,
  73         MTHCA_QP_ST_UC  = 0x1,
  74         MTHCA_QP_ST_RD  = 0x2,
  75         MTHCA_QP_ST_UD  = 0x3,
  76         MTHCA_QP_ST_MLX = 0x7
  77 };
  78
  79 enum {
  80         MTHCA_QP_PM_MIGRATED = 0x3,
  81         MTHCA_QP_PM_ARMED    = 0x0,
  82         MTHCA_QP_PM_REARM    = 0x1
  83 };
  84
  85 enum {
  86         /* qp_context flags */
  87         MTHCA_QP_BIT_DE  = 1 <<  8,
  88         /* params1 */
  89         MTHCA_QP_BIT_SRE = 1 << 15,
  90         MTHCA_QP_BIT_SWE = 1 << 14,
  91         MTHCA_QP_BIT_SAE = 1 << 13,
  92         MTHCA_QP_BIT_SIC = 1 <<  4,
  93         MTHCA_QP_BIT_SSC = 1 <<  3,
  94         /* params2 */
  95         MTHCA_QP_BIT_RRE = 1 << 15,
  96         MTHCA_QP_BIT_RWE = 1 << 14,
  97         MTHCA_QP_BIT_RAE = 1 << 13,
  98         MTHCA_QP_BIT_RIC = 1 <<  4,
  99         MTHCA_QP_BIT_RSC = 1 <<  3
 100 };
 101
 102 struct mthca_qp_path {
 103         __be32 port_pkey;
 104         u8     rnr_retry;
 105         u8     g_mylmc;
 106         __be16 rlid;
 107         u8     ackto;
 108         u8     mgid_index;
 109         u8     static_rate;
 110         u8     hop_limit;
 111         __be32 sl_tclass_flowlabel;
 112         u8     rgid[16];
 113 } __attribute__((packed));
 114
 115 struct mthca_qp_context {
 116         __be32 flags;
 117         __be32 tavor_sched_queue; /* Reserved on Arbel */
 118         u8     mtu_msgmax;
 119         u8     rq_size_stride;  /* Reserved on Tavor */
 120         u8     sq_size_stride;  /* Reserved on Tavor */
 121         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 122         __be32 usr_page;
 123         __be32 local_qpn;
 124         __be32 remote_qpn;
 125         u32    reserved1[2];
 126         struct mthca_qp_path pri_path;
 127         struct mthca_qp_path alt_path;
 128         __be32 rdd;
 129         __be32 pd;
 130         __be32 wqe_base;
 131         __be32 wqe_lkey;
 132         __be32 params1;
 133         __be32 reserved2;
 134         __be32 next_send_psn;
 135         __be32 cqn_snd;
 136         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 137         __be32 snd_db_index;    /* (debugging only entries) */
 138         __be32 last_acked_psn;
 139         __be32 ssn;
 140         __be32 params2;
 141         __be32 rnr_nextrecvpsn;
 142         __be32 ra_buff_indx;
 143         __be32 cqn_rcv;
 144         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 145         __be32 rcv_db_index;    /* (debugging only entries) */
 146         __be32 qkey;
 147         __be32 srqn;
 148         __be32 rmsn;
 149         __be16 rq_wqe_counter;  /* reserved on Tavor */
 150         __be16 sq_wqe_counter;  /* reserved on Tavor */
 151         u32    reserved3[18];
 152 } __attribute__((packed));
 153
 154 struct mthca_qp_param {
 155         __be32 opt_param_mask;
 156         u32    reserved1;
 157         struct mthca_qp_context context;
 158         u32    reserved2[62];
 159 } __attribute__((packed));
 160
 161 enum {
 162         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 163         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 164         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 165         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 166         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 167         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 168         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 169         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 170         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 171         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 172         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 173         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 174         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 175         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 176         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 177         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 178         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 179 };
 180
 181 static const u8 mthca_opcode[] = {
 182         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 183         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 184         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 185         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 186         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 187         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 188         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 189 };
 190
 191 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 192 {
 193         return qp->qpn >= dev->qp_table.sqp_start &&
 194                 qp->qpn <= dev->qp_table.sqp_start + 3;
 195 }
 196
 197 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 198 {
 199         return qp->qpn >= dev->qp_table.sqp_start &&
 200                 qp->qpn <= dev->qp_table.sqp_start + 1;
 201 }
 202
 203 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 204 {
 205         if (qp->is_direct)
 206                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 207         else
 208                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 209                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 210 }
 211
 212 static void *get_send_wqe(struct mthca_qp *qp, int n)
 213 {
 214         if (qp->is_direct)
 215                 return qp->queue.direct.buf + qp->send_wqe_offset +
 216                         (n << qp->sq.wqe_shift);
 217         else
 218                 return qp->queue.page_list[(qp->send_wqe_offset +
 219                                             (n << qp->sq.wqe_shift)) >>
 220                                            PAGE_SHIFT].buf +
 221                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 222                          (PAGE_SIZE - 1));
 223 }
 224
 225 static void mthca_wq_init(struct mthca_wq *wq)
 226 {
 227         spin_lock_init(&wq->lock);
 228         wq->next_ind  = 0;
 229         wq->last_comp = wq->max - 1;
 230         wq->head      = 0;
 231         wq->tail      = 0;
 232 }
 233
 234 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 235                     enum ib_event_type event_type)
 236 {
 237         struct mthca_qp *qp;
 238         struct ib_event event;
 239
 240         spin_lock(&dev->qp_table.lock);
 241         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 242         if (qp)
 243                 ++qp->refcount;
 244         spin_unlock(&dev->qp_table.lock);
 245
 246         if (!qp) {
 247                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 248                 return;
 249         }
 250
 251         if (event_type == IB_EVENT_PATH_MIG)
 252                 qp->port = qp->alt_port;
 253
 254         event.device      = &dev->ib_dev;
 255         event.event       = event_type;
 256         event.element.qp  = &qp->ibqp;
 257         if (qp->ibqp.event_handler)
 258                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 259
 260         spin_lock(&dev->qp_table.lock);
 261         if (!--qp->refcount)
 262                 wake_up(&qp->wait);
 263         spin_unlock(&dev->qp_table.lock);
 264 }
 265
 266 static int to_mthca_state(enum ib_qp_state ib_state)
 267 {
 268         switch (ib_state) {
 269         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 270         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 271         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 272         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 273         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 274         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 275         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 276         default:                return -1;
 277         }
 278 }
 279
 280 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 281
 282 static int to_mthca_st(int transport)
 283 {
 284         switch (transport) {
 285         case RC:  return MTHCA_QP_ST_RC;
 286         case UC:  return MTHCA_QP_ST_UC;
 287         case UD:  return MTHCA_QP_ST_UD;
 288         case RD:  return MTHCA_QP_ST_RD;
 289         case MLX: return MTHCA_QP_ST_MLX;
 290         default:  return -1;
 291         }
 292 }
 293
 294 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 295                         int attr_mask)
 296 {
 297         if (attr_mask & IB_QP_PKEY_INDEX)
 298                 sqp->pkey_index = attr->pkey_index;
 299         if (attr_mask & IB_QP_QKEY)
 300                 sqp->qkey = attr->qkey;
 301         if (attr_mask & IB_QP_SQ_PSN)
 302                 sqp->send_psn = attr->sq_psn;
 303 }
 304
 305 static void init_port(struct mthca_dev *dev, int port)
 306 {
 307         int err;
 308         u8 status;
 309         struct mthca_init_ib_param param;
 310
 311         memset(&param, 0, sizeof param);
 312
 313         param.port_width = dev->limits.port_width_cap;
 314         param.vl_cap     = dev->limits.vl_cap;
 315         param.mtu_cap    = dev->limits.mtu_cap;
 316         param.gid_cap    = dev->limits.gid_table_len;
 317         param.pkey_cap   = dev->limits.pkey_table_len;
 318
 319         err = mthca_INIT_IB(dev, &param, port, &status);
 320         if (err)
 321                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 322         if (status)
 323                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 324 }
 325
 326 static __be32 get_hw_access_flags(struct mthca_qp *qp, struct ib_qp_attr *attr,
 327                                   int attr_mask)
 328 {
 329         u8 dest_rd_atomic;
 330         u32 access_flags;
 331         u32 hw_access_flags = 0;
 332
 333         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 334                 dest_rd_atomic = attr->max_dest_rd_atomic;
 335         else
 336                 dest_rd_atomic = qp->resp_depth;
 337
 338         if (attr_mask & IB_QP_ACCESS_FLAGS)
 339                 access_flags = attr->qp_access_flags;
 340         else
 341                 access_flags = qp->atomic_rd_en;
 342
 343         if (!dest_rd_atomic)
 344                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 345
 346         if (access_flags & IB_ACCESS_REMOTE_READ)
 347                 hw_access_flags |= MTHCA_QP_BIT_RRE;
 348         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 349                 hw_access_flags |= MTHCA_QP_BIT_RAE;
 350         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 351                 hw_access_flags |= MTHCA_QP_BIT_RWE;
 352
 353         return cpu_to_be32(hw_access_flags);
 354 }
 355
 356 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
 357 {
 358         switch (mthca_state) {
 359         case MTHCA_QP_STATE_RST:      return IB_QPS_RESET;
 360         case MTHCA_QP_STATE_INIT:     return IB_QPS_INIT;
 361         case MTHCA_QP_STATE_RTR:      return IB_QPS_RTR;
 362         case MTHCA_QP_STATE_RTS:      return IB_QPS_RTS;
 363         case MTHCA_QP_STATE_DRAINING:
 364         case MTHCA_QP_STATE_SQD:      return IB_QPS_SQD;
 365         case MTHCA_QP_STATE_SQE:      return IB_QPS_SQE;
 366         case MTHCA_QP_STATE_ERR:      return IB_QPS_ERR;
 367         default:                      return -1;
 368         }
 369 }
 370
 371 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
 372 {
 373         switch (mthca_mig_state) {
 374         case 0:  return IB_MIG_ARMED;
 375         case 1:  return IB_MIG_REARM;
 376         case 3:  return IB_MIG_MIGRATED;
 377         default: return -1;
 378         }
 379 }
 380
 381 static int to_ib_qp_access_flags(int mthca_flags)
 382 {
 383         int ib_flags = 0;
 384
 385         if (mthca_flags & MTHCA_QP_BIT_RRE)
 386                 ib_flags |= IB_ACCESS_REMOTE_READ;
 387         if (mthca_flags & MTHCA_QP_BIT_RWE)
 388                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
 389         if (mthca_flags & MTHCA_QP_BIT_RAE)
 390                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
 391
 392         return ib_flags;
 393 }
 394
 395 static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr,
 396                                 struct mthca_qp_path *path)
 397 {
 398         memset(ib_ah_attr, 0, sizeof *path);
 399         ib_ah_attr->port_num      = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
 400
 401         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->limits.num_ports)
 402                 return;
 403
 404         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
 405         ib_ah_attr->sl            = be32_to_cpu(path->sl_tclass_flowlabel) >> 28;
 406         ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f;
 407         ib_ah_attr->static_rate   = mthca_rate_to_ib(dev,
 408                                                      path->static_rate & 0x7,
 409                                                      ib_ah_attr->port_num);
 410         ib_ah_attr->ah_flags      = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
 411         if (ib_ah_attr->ah_flags) {
 412                 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1);
 413                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
 414                 ib_ah_attr->grh.traffic_class =
 415                         (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff;
 416                 ib_ah_attr->grh.flow_label =
 417                         be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff;
 418                 memcpy(ib_ah_attr->grh.dgid.raw,
 419                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
 420         }
 421 }
 422
 423 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
 424                    struct ib_qp_init_attr *qp_init_attr)
 425 {
 426         struct mthca_dev *dev = to_mdev(ibqp->device);
 427         struct mthca_qp *qp = to_mqp(ibqp);
 428         int err;
 429         struct mthca_mailbox *mailbox;
 430         struct mthca_qp_param *qp_param;
 431         struct mthca_qp_context *context;
 432         int mthca_state;
 433         u8 status;
 434
 435         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 436         if (IS_ERR(mailbox))
 437                 return PTR_ERR(mailbox);
 438
 439         err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status);
 440         if (err)
 441                 goto out;
 442         if (status) {
 443                 mthca_warn(dev, "QUERY_QP returned status %02x\n", status);
 444                 err = -EINVAL;
 445                 goto out;
 446         }
 447
 448         qp_param    = mailbox->buf;
 449         context     = &qp_param->context;
 450         mthca_state = be32_to_cpu(context->flags) >> 28;
 451
 452         qp_attr->qp_state            = to_ib_qp_state(mthca_state);
 453         qp_attr->cur_qp_state        = qp_attr->qp_state;
 454         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
 455         qp_attr->path_mig_state      =
 456                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
 457         qp_attr->qkey                = be32_to_cpu(context->qkey);
 458         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
 459         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
 460         qp_attr->dest_qp_num         = be32_to_cpu(context->remote_qpn) & 0xffffff;
 461         qp_attr->qp_access_flags     =
 462                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
 463         qp_attr->cap.max_send_wr     = qp->sq.max;
 464         qp_attr->cap.max_recv_wr     = qp->rq.max;
 465         qp_attr->cap.max_send_sge    = qp->sq.max_gs;
 466         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
 467         qp_attr->cap.max_inline_data = qp->max_inline_data;
 468
 469         if (qp->transport == RC || qp->transport == UC) {
 470                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
 471                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
 472         }
 473
 474         qp_attr->pkey_index     = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
 475         qp_attr->alt_pkey_index = be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
 476
 477         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
 478         qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
 479
 480         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
 481
 482         qp_attr->max_dest_rd_atomic =
 483                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
 484         qp_attr->min_rnr_timer      =
 485                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
 486         qp_attr->port_num           = qp_attr->ah_attr.port_num;
 487         qp_attr->timeout            = context->pri_path.ackto >> 3;
 488         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
 489         qp_attr->rnr_retry          = context->pri_path.rnr_retry >> 5;
 490         qp_attr->alt_port_num       = qp_attr->alt_ah_attr.port_num;
 491         qp_attr->alt_timeout        = context->alt_path.ackto >> 3;
 492         qp_init_attr->cap           = qp_attr->cap;
 493
 494 out:
 495         mthca_free_mailbox(dev, mailbox);
 496         return err;
 497 }
 498
 499 static int mthca_path_set(struct mthca_dev *dev, struct ib_ah_attr *ah,
 500                           struct mthca_qp_path *path, u8 port)
 501 {
 502         path->g_mylmc     = ah->src_path_bits & 0x7f;
 503         path->rlid        = cpu_to_be16(ah->dlid);
 504         path->static_rate = mthca_get_rate(dev, ah->static_rate, port);
 505
 506         if (ah->ah_flags & IB_AH_GRH) {
 507                 if (ah->grh.sgid_index >= dev->limits.gid_table_len) {
 508                         mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
 509                                   ah->grh.sgid_index, dev->limits.gid_table_len-1);
 510                         return -1;
 511                 }
 512
 513                 path->g_mylmc   |= 1 << 7;
 514                 path->mgid_index = ah->grh.sgid_index;
 515                 path->hop_limit  = ah->grh.hop_limit;
 516                 path->sl_tclass_flowlabel =
 517                         cpu_to_be32((ah->sl << 28)                |
 518                                     (ah->grh.traffic_class << 20) |
 519                                     (ah->grh.flow_label));
 520                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 521         } else
 522                 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28);
 523
 524         return 0;
 525 }
 526
 527 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
 528 {
 529         struct mthca_dev *dev = to_mdev(ibqp->device);
 530         struct mthca_qp *qp = to_mqp(ibqp);
 531         enum ib_qp_state cur_state, new_state;
 532         struct mthca_mailbox *mailbox;
 533         struct mthca_qp_param *qp_param;
 534         struct mthca_qp_context *qp_context;
 535         u32 sqd_event = 0;
 536         u8 status;
 537         int err;
 538
 539         if (attr_mask & IB_QP_CUR_STATE) {
 540                 cur_state = attr->cur_qp_state;
 541         } else {
 542                 spin_lock_irq(&qp->sq.lock);
 543                 spin_lock(&qp->rq.lock);
 544                 cur_state = qp->state;
 545                 spin_unlock(&qp->rq.lock);
 546                 spin_unlock_irq(&qp->sq.lock);
 547         }
 548
 549         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
 550
 551         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
 552                 mthca_dbg(dev, "Bad QP transition (transport %d) "
 553                           "%d->%d with attr 0x%08x\n",
 554                           qp->transport, cur_state, new_state,
 555                           attr_mask);
 556                 return -EINVAL;
 557         }
 558
 559         if ((attr_mask & IB_QP_PKEY_INDEX) &&
 560              attr->pkey_index >= dev->limits.pkey_table_len) {
 561                 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
 562                           attr->pkey_index, dev->limits.pkey_table_len-1);
 563                 return -EINVAL;
 564         }
 565
 566         if ((attr_mask & IB_QP_PORT) &&
 567             (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
 568                 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
 569                 return -EINVAL;
 570         }
 571
 572         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
 573             attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
 574                 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
 575                           attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
 576                 return -EINVAL;
 577         }
 578
 579         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
 580             attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
 581                 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
 582                           attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
 583                 return -EINVAL;
 584         }
 585
 586         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 587         if (IS_ERR(mailbox))
 588                 return PTR_ERR(mailbox);
 589         qp_param = mailbox->buf;
 590         qp_context = &qp_param->context;
 591         memset(qp_param, 0, sizeof *qp_param);
 592
 593         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 594                                              (to_mthca_st(qp->transport) << 16));
 595         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 596         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 597                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 598         else {
 599                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 600                 switch (attr->path_mig_state) {
 601                 case IB_MIG_MIGRATED:
 602                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 603                         break;
 604                 case IB_MIG_REARM:
 605                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 606                         break;
 607                 case IB_MIG_ARMED:
 608                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 609                         break;
 610                 }
 611         }
 612
 613         /* leave tavor_sched_queue as 0 */
 614
 615         if (qp->transport == MLX || qp->transport == UD)
 616                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 617         else if (attr_mask & IB_QP_PATH_MTU) {
 618                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
 619                         mthca_dbg(dev, "path MTU (%u) is invalid\n",
 620                                   attr->path_mtu);
 621                         return -EINVAL;
 622                 }
 623                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 624         }
 625
 626         if (mthca_is_memfree(dev)) {
 627                 if (qp->rq.max)
 628                         qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
 629                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
 630
 631                 if (qp->sq.max)
 632                         qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
 633                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
 634         }
 635
 636         /* leave arbel_sched_queue as 0 */
 637
 638         if (qp->ibqp.uobject)
 639                 qp_context->usr_page =
 640                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 641         else
 642                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 643         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 644         if (attr_mask & IB_QP_DEST_QPN) {
 645                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 646         }
 647
 648         if (qp->transport == MLX)
 649                 qp_context->pri_path.port_pkey |=
 650                         cpu_to_be32(qp->port << 24);
 651         else {
 652                 if (attr_mask & IB_QP_PORT) {
 653                         qp_context->pri_path.port_pkey |=
 654                                 cpu_to_be32(attr->port_num << 24);
 655                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 656                 }
 657         }
 658
 659         if (attr_mask & IB_QP_PKEY_INDEX) {
 660                 qp_context->pri_path.port_pkey |=
 661                         cpu_to_be32(attr->pkey_index);
 662                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 663         }
 664
 665         if (attr_mask & IB_QP_RNR_RETRY) {
 666                 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
 667                         attr->rnr_retry << 5;
 668                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
 669                                                         MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
 670         }
 671
 672         if (attr_mask & IB_QP_AV) {
 673                 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
 674                                    attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
 675                         return -EINVAL;
 676
 677                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 678         }
 679
 680         if (attr_mask & IB_QP_TIMEOUT) {
 681                 qp_context->pri_path.ackto = attr->timeout << 3;
 682                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 683         }
 684
 685         if (attr_mask & IB_QP_ALT_PATH) {
 686                 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
 687                         mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
 688                                   attr->alt_pkey_index, dev->limits.pkey_table_len-1);
 689                         return -EINVAL;
 690                 }
 691
 692                 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
 693                         mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
 694                                 attr->alt_port_num);
 695                         return -EINVAL;
 696                 }
 697
 698                 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
 699                                    attr->alt_ah_attr.port_num))
 700                         return -EINVAL;
 701
 702                 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
 703                                                               attr->alt_port_num << 24);
 704                 qp_context->alt_path.ackto = attr->alt_timeout << 3;
 705                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
 706         }
 707
 708         /* leave rdd as 0 */
 709         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 710         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 711         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 712         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 713                                              (MTHCA_FLIGHT_LIMIT << 24) |
 714                                              MTHCA_QP_BIT_SWE);
 715         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 716                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 717         if (attr_mask & IB_QP_RETRY_CNT) {
 718                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 719                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 720         }
 721
 722         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 723                 if (attr->max_rd_atomic) {
 724                         qp_context->params1 |=
 725                                 cpu_to_be32(MTHCA_QP_BIT_SRE |
 726                                             MTHCA_QP_BIT_SAE);
 727                         qp_context->params1 |=
 728                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 729                 }
 730                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 731         }
 732
 733         if (attr_mask & IB_QP_SQ_PSN)
 734                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 735         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 736
 737         if (mthca_is_memfree(dev)) {
 738                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 739                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 740         }
 741
 742         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 743                 if (attr->max_dest_rd_atomic)
 744                         qp_context->params2 |=
 745                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 746
 747                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 748         }
 749
 750         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
 751                 qp_context->params2      |= get_hw_access_flags(qp, attr, attr_mask);
 752                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 753                                                         MTHCA_QP_OPTPAR_RRE |
 754                                                         MTHCA_QP_OPTPAR_RAE);
 755         }
 756
 757         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 758
 759         if (ibqp->srq)
 760                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
 761
 762         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 763                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 764                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 765         }
 766         if (attr_mask & IB_QP_RQ_PSN)
 767                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 768
 769         qp_context->ra_buff_indx =
 770                 cpu_to_be32(dev->qp_table.rdb_base +
 771                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 772                              dev->qp_table.rdb_shift));
 773
 774         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 775
 776         if (mthca_is_memfree(dev))
 777                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 778
 779         if (attr_mask & IB_QP_QKEY) {
 780                 qp_context->qkey = cpu_to_be32(attr->qkey);
 781                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 782         }
 783
 784         if (ibqp->srq)
 785                 qp_context->srqn = cpu_to_be32(1 << 24 |
 786                                                to_msrq(ibqp->srq)->srqn);
 787
 788         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
 789             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY               &&
 790             attr->en_sqd_async_notify)
 791                 sqd_event = 1 << 31;
 792
 793         err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
 794                               mailbox, sqd_event, &status);
 795         if (err)
 796                 goto out;
 797         if (status) {
 798                 mthca_warn(dev, "modify QP %d->%d returned status %02x.\n",
 799                            cur_state, new_state, status);
 800                 err = -EINVAL;
 801                 goto out;
 802         }
 803
 804         qp->state = new_state;
 805         if (attr_mask & IB_QP_ACCESS_FLAGS)
 806                 qp->atomic_rd_en = attr->qp_access_flags;
 807         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 808                 qp->resp_depth = attr->max_dest_rd_atomic;
 809         if (attr_mask & IB_QP_PORT)
 810                 qp->port = attr->port_num;
 811         if (attr_mask & IB_QP_ALT_PATH)
 812                 qp->alt_port = attr->alt_port_num;
 813
 814         if (is_sqp(dev, qp))
 815                 store_attrs(to_msqp(qp), attr, attr_mask);
 816
 817         /*
 818          * If we moved QP0 to RTR, bring the IB link up; if we moved
 819          * QP0 to RESET or ERROR, bring the link back down.
 820          */
 821         if (is_qp0(dev, qp)) {
 822                 if (cur_state != IB_QPS_RTR &&
 823                     new_state == IB_QPS_RTR)
 824                         init_port(dev, qp->port);
 825
 826                 if (cur_state != IB_QPS_RESET &&
 827                     cur_state != IB_QPS_ERR &&
 828                     (new_state == IB_QPS_RESET ||
 829                      new_state == IB_QPS_ERR))
 830                         mthca_CLOSE_IB(dev, qp->port, &status);
 831         }
 832
 833         /*
 834          * If we moved a kernel QP to RESET, clean up all old CQ
 835          * entries and reinitialize the QP.
 836          */
 837         if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
 838                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn,
 839                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 840                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
 841                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
 842                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 843
 844                 mthca_wq_init(&qp->sq);
 845                 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
 846
 847                 mthca_wq_init(&qp->rq);
 848                 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
 849
 850                 if (mthca_is_memfree(dev)) {
 851                         *qp->sq.db = 0;
 852                         *qp->rq.db = 0;
 853                 }
 854         }
 855
 856 out:
 857         mthca_free_mailbox(dev, mailbox);
 858         return err;
 859 }
 860
 861 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
 862 {
 863         /*
 864          * Calculate the maximum size of WQE s/g segments, excluding
 865          * the next segment and other non-data segments.
 866          */
 867         int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
 868
 869         switch (qp->transport) {
 870         case MLX:
 871                 max_data_size -= 2 * sizeof (struct mthca_data_seg);
 872                 break;
 873
 874         case UD:
 875                 if (mthca_is_memfree(dev))
 876                         max_data_size -= sizeof (struct mthca_arbel_ud_seg);
 877                 else
 878                         max_data_size -= sizeof (struct mthca_tavor_ud_seg);
 879                 break;
 880
 881         default:
 882                 max_data_size -= sizeof (struct mthca_raddr_seg);
 883                 break;
 884         }
 885
 886         return max_data_size;
 887 }
 888
 889 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
 890 {
 891         /* We don't support inline data for kernel QPs (yet). */
 892         return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
 893 }
 894
 895 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
 896                                  struct mthca_pd *pd,
 897                                  struct mthca_qp *qp)
 898 {
 899         int max_data_size = mthca_max_data_size(dev, qp,
 900                                                 min(dev->limits.max_desc_sz,
 901                                                     1 << qp->sq.wqe_shift));
 902
 903         qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
 904
 905         qp->sq.max_gs = min_t(int, dev->limits.max_sg,
 906                               max_data_size / sizeof (struct mthca_data_seg));
 907         qp->rq.max_gs = min_t(int, dev->limits.max_sg,
 908                                (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
 909                                 sizeof (struct mthca_next_seg)) /
 910                                sizeof (struct mthca_data_seg));
 911 }
 912
 913 /*
 914  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 915  * rq.max_gs and sq.max_gs must all be assigned.
 916  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 917  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 918  * queue)
 919  */
 920 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 921                                struct mthca_pd *pd,
 922                                struct mthca_qp *qp)
 923 {
 924         int size;
 925         int err = -ENOMEM;
 926
 927         size = sizeof (struct mthca_next_seg) +
 928                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 929
 930         if (size > dev->limits.max_desc_sz)
 931                 return -EINVAL;
 932
 933         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 934              qp->rq.wqe_shift++)
 935                 ; /* nothing */
 936
 937         size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
 938         switch (qp->transport) {
 939         case MLX:
 940                 size += 2 * sizeof (struct mthca_data_seg);
 941                 break;
 942
 943         case UD:
 944                 size += mthca_is_memfree(dev) ?
 945                         sizeof (struct mthca_arbel_ud_seg) :
 946                         sizeof (struct mthca_tavor_ud_seg);
 947                 break;
 948
 949         case UC:
 950                 size += sizeof (struct mthca_raddr_seg);
 951                 break;
 952
 953         case RC:
 954                 size += sizeof (struct mthca_raddr_seg);
 955                 /*
 956                  * An atomic op will require an atomic segment, a
 957                  * remote address segment and one scatter entry.
 958                  */
 959                 size = max_t(int, size,
 960                              sizeof (struct mthca_atomic_seg) +
 961                              sizeof (struct mthca_raddr_seg) +
 962                              sizeof (struct mthca_data_seg));
 963                 break;
 964
 965         default:
 966                 break;
 967         }
 968
 969         /* Make sure that we have enough space for a bind request */
 970         size = max_t(int, size, sizeof (struct mthca_bind_seg));
 971
 972         size += sizeof (struct mthca_next_seg);
 973
 974         if (size > dev->limits.max_desc_sz)
 975                 return -EINVAL;
 976
 977         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
 978              qp->sq.wqe_shift++)
 979                 ; /* nothing */
 980
 981         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
 982                                     1 << qp->sq.wqe_shift);
 983
 984         /*
 985          * If this is a userspace QP, we don't actually have to
 986          * allocate anything.  All we need is to calculate the WQE
 987          * sizes and the send_wqe_offset, so we're done now.
 988          */
 989         if (pd->ibpd.uobject)
 990                 return 0;
 991
 992         size = PAGE_ALIGN(qp->send_wqe_offset +
 993                           (qp->sq.max << qp->sq.wqe_shift));
 994
 995         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
 996                            GFP_KERNEL);
 997         if (!qp->wrid)
 998                 goto err_out;
 999
1000         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1001                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1002         if (err)
1003                 goto err_out;
1004
1005         return 0;
1006
1007 err_out:
1008         kfree(qp->wrid);
1009         return err;
1010 }
1011
1012 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1013                                struct mthca_qp *qp)
1014 {
1015         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1016                                        (qp->sq.max << qp->sq.wqe_shift)),
1017                        &qp->queue, qp->is_direct, &qp->mr);
1018         kfree(qp->wrid);
1019 }
1020
1021 static int mthca_map_memfree(struct mthca_dev *dev,
1022                              struct mthca_qp *qp)
1023 {
1024         int ret;
1025
1026         if (mthca_is_memfree(dev)) {
1027                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1028                 if (ret)
1029                         return ret;
1030
1031                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1032                 if (ret)
1033                         goto err_qpc;
1034
1035                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1036                                       qp->qpn << dev->qp_table.rdb_shift);
1037                 if (ret)
1038                         goto err_eqpc;
1039
1040         }
1041
1042         return 0;
1043
1044 err_eqpc:
1045         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1046
1047 err_qpc:
1048         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1049
1050         return ret;
1051 }
1052
1053 static void mthca_unmap_memfree(struct mthca_dev *dev,
1054                                 struct mthca_qp *qp)
1055 {
1056         mthca_table_put(dev, dev->qp_table.rdb_table,
1057                         qp->qpn << dev->qp_table.rdb_shift);
1058         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1059         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1060 }
1061
1062 static int mthca_alloc_memfree(struct mthca_dev *dev,
1063                                struct mthca_qp *qp)
1064 {
1065         int ret = 0;
1066
1067         if (mthca_is_memfree(dev)) {
1068                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1069                                                  qp->qpn, &qp->rq.db);
1070                 if (qp->rq.db_index < 0)
1071                         return ret;
1072
1073                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1074                                                  qp->qpn, &qp->sq.db);
1075                 if (qp->sq.db_index < 0)
1076                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1077         }
1078
1079         return ret;
1080 }
1081
1082 static void mthca_free_memfree(struct mthca_dev *dev,
1083                                struct mthca_qp *qp)
1084 {
1085         if (mthca_is_memfree(dev)) {
1086                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1087                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1088         }
1089 }
1090
1091 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1092                                  struct mthca_pd *pd,
1093                                  struct mthca_cq *send_cq,
1094                                  struct mthca_cq *recv_cq,
1095                                  enum ib_sig_type send_policy,
1096                                  struct mthca_qp *qp)
1097 {
1098         int ret;
1099         int i;
1100
1101         qp->refcount = 1;
1102         init_waitqueue_head(&qp->wait);
1103         qp->state        = IB_QPS_RESET;
1104         qp->atomic_rd_en = 0;
1105         qp->resp_depth   = 0;
1106         qp->sq_policy    = send_policy;
1107         mthca_wq_init(&qp->sq);
1108         mthca_wq_init(&qp->rq);
1109
1110         ret = mthca_map_memfree(dev, qp);
1111         if (ret)
1112                 return ret;
1113
1114         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1115         if (ret) {
1116                 mthca_unmap_memfree(dev, qp);
1117                 return ret;
1118         }
1119
1120         mthca_adjust_qp_caps(dev, pd, qp);
1121
1122         /*
1123          * If this is a userspace QP, we're done now.  The doorbells
1124          * will be allocated and buffers will be initialized in
1125          * userspace.
1126          */
1127         if (pd->ibpd.uobject)
1128                 return 0;
1129
1130         ret = mthca_alloc_memfree(dev, qp);
1131         if (ret) {
1132                 mthca_free_wqe_buf(dev, qp);
1133                 mthca_unmap_memfree(dev, qp);
1134                 return ret;
1135         }
1136
1137         if (mthca_is_memfree(dev)) {
1138                 struct mthca_next_seg *next;
1139                 struct mthca_data_seg *scatter;
1140                 int size = (sizeof (struct mthca_next_seg) +
1141                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1142
1143                 for (i = 0; i < qp->rq.max; ++i) {
1144                         next = get_recv_wqe(qp, i);
1145                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1146                                                    qp->rq.wqe_shift);
1147                         next->ee_nds = cpu_to_be32(size);
1148
1149                         for (scatter = (void *) (next + 1);
1150                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1151                              ++scatter)
1152                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1153                 }
1154
1155                 for (i = 0; i < qp->sq.max; ++i) {
1156                         next = get_send_wqe(qp, i);
1157                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1158                                                     qp->sq.wqe_shift) +
1159                                                    qp->send_wqe_offset);
1160                 }
1161         }
1162
1163         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1164         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1165
1166         return 0;
1167 }
1168
1169 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1170                              struct mthca_pd *pd, struct mthca_qp *qp)
1171 {
1172         int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1173
1174         /* Sanity check QP size before proceeding */
1175         if (cap->max_send_wr     > dev->limits.max_wqes ||
1176             cap->max_recv_wr     > dev->limits.max_wqes ||
1177             cap->max_send_sge    > dev->limits.max_sg   ||
1178             cap->max_recv_sge    > dev->limits.max_sg   ||
1179             cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1180                 return -EINVAL;
1181
1182         /*
1183          * For MLX transport we need 2 extra S/G entries:
1184          * one for the header and one for the checksum at the end
1185          */
1186         if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg)
1187                 return -EINVAL;
1188
1189         if (mthca_is_memfree(dev)) {
1190                 qp->rq.max = cap->max_recv_wr ?
1191                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1192                 qp->sq.max = cap->max_send_wr ?
1193                         roundup_pow_of_two(cap->max_send_wr) : 0;
1194         } else {
1195                 qp->rq.max = cap->max_recv_wr;
1196                 qp->sq.max = cap->max_send_wr;
1197         }
1198
1199         qp->rq.max_gs = cap->max_recv_sge;
1200         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1201                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1202                                     MTHCA_INLINE_CHUNK_SIZE) /
1203                               sizeof (struct mthca_data_seg));
1204
1205         return 0;
1206 }
1207
1208 int mthca_alloc_qp(struct mthca_dev *dev,
1209                    struct mthca_pd *pd,
1210                    struct mthca_cq *send_cq,
1211                    struct mthca_cq *recv_cq,
1212                    enum ib_qp_type type,
1213                    enum ib_sig_type send_policy,
1214                    struct ib_qp_cap *cap,
1215                    struct mthca_qp *qp)
1216 {
1217         int err;
1218
1219         switch (type) {
1220         case IB_QPT_RC: qp->transport = RC; break;
1221         case IB_QPT_UC: qp->transport = UC; break;
1222         case IB_QPT_UD: qp->transport = UD; break;
1223         default: return -EINVAL;
1224         }
1225
1226         err = mthca_set_qp_size(dev, cap, pd, qp);
1227         if (err)
1228                 return err;
1229
1230         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1231         if (qp->qpn == -1)
1232                 return -ENOMEM;
1233
1234         /* initialize port to zero for error-catching. */
1235         qp->port = 0;
1236
1237         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1238                                     send_policy, qp);
1239         if (err) {
1240                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1241                 return err;
1242         }
1243
1244         spin_lock_irq(&dev->qp_table.lock);
1245         mthca_array_set(&dev->qp_table.qp,
1246                         qp->qpn & (dev->limits.num_qps - 1), qp);
1247         spin_unlock_irq(&dev->qp_table.lock);
1248
1249         return 0;
1250 }
1251
1252 int mthca_alloc_sqp(struct mthca_dev *dev,
1253                     struct mthca_pd *pd,
1254                     struct mthca_cq *send_cq,
1255                     struct mthca_cq *recv_cq,
1256                     enum ib_sig_type send_policy,
1257                     struct ib_qp_cap *cap,
1258                     int qpn,
1259                     int port,
1260                     struct mthca_sqp *sqp)
1261 {
1262         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1263         int err;
1264
1265         sqp->qp.transport = MLX;
1266         err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1267         if (err)
1268                 return err;
1269
1270         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1271         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1272                                              &sqp->header_dma, GFP_KERNEL);
1273         if (!sqp->header_buf)
1274                 return -ENOMEM;
1275
1276         spin_lock_irq(&dev->qp_table.lock);
1277         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1278                 err = -EBUSY;
1279         else
1280                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1281         spin_unlock_irq(&dev->qp_table.lock);
1282
1283         if (err)
1284                 goto err_out;
1285
1286         sqp->qp.port      = port;
1287         sqp->qp.qpn       = mqpn;
1288         sqp->qp.transport = MLX;
1289
1290         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1291                                     send_policy, &sqp->qp);
1292         if (err)
1293                 goto err_out_free;
1294
1295         atomic_inc(&pd->sqp_count);
1296
1297         return 0;
1298
1299  err_out_free:
1300         /*
1301          * Lock CQs here, so that CQ polling code can do QP lookup
1302          * without taking a lock.
1303          */
1304         spin_lock_irq(&send_cq->lock);
1305         if (send_cq != recv_cq)
1306                 spin_lock(&recv_cq->lock);
1307
1308         spin_lock(&dev->qp_table.lock);
1309         mthca_array_clear(&dev->qp_table.qp, mqpn);
1310         spin_unlock(&dev->qp_table.lock);
1311
1312         if (send_cq != recv_cq)
1313                 spin_unlock(&recv_cq->lock);
1314         spin_unlock_irq(&send_cq->lock);
1315
1316  err_out:
1317         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1318                           sqp->header_buf, sqp->header_dma);
1319
1320         return err;
1321 }
1322
1323 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp)
1324 {
1325         int c;
1326
1327         spin_lock_irq(&dev->qp_table.lock);
1328         c = qp->refcount;
1329         spin_unlock_irq(&dev->qp_table.lock);
1330
1331         return c;
1332 }
1333
1334 void mthca_free_qp(struct mthca_dev *dev,
1335                    struct mthca_qp *qp)
1336 {
1337         u8 status;
1338         struct mthca_cq *send_cq;
1339         struct mthca_cq *recv_cq;
1340
1341         send_cq = to_mcq(qp->ibqp.send_cq);
1342         recv_cq = to_mcq(qp->ibqp.recv_cq);
1343
1344         /*
1345          * Lock CQs here, so that CQ polling code can do QP lookup
1346          * without taking a lock.
1347          */
1348         spin_lock_irq(&send_cq->lock);
1349         if (send_cq != recv_cq)
1350                 spin_lock(&recv_cq->lock);
1351
1352         spin_lock(&dev->qp_table.lock);
1353         mthca_array_clear(&dev->qp_table.qp,
1354                           qp->qpn & (dev->limits.num_qps - 1));
1355         --qp->refcount;
1356         spin_unlock(&dev->qp_table.lock);
1357
1358         if (send_cq != recv_cq)
1359                 spin_unlock(&recv_cq->lock);
1360         spin_unlock_irq(&send_cq->lock);
1361
1362         wait_event(qp->wait, !get_qp_refcount(dev, qp));
1363
1364         if (qp->state != IB_QPS_RESET)
1365                 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1366                                 NULL, 0, &status);
1367
1368         /*
1369          * If this is a userspace QP, the buffers, MR, CQs and so on
1370          * will be cleaned up in userspace, so all we have to do is
1371          * unref the mem-free tables and free the QPN in our table.
1372          */
1373         if (!qp->ibqp.uobject) {
1374                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn,
1375                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1376                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1377                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
1378                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1379
1380                 mthca_free_memfree(dev, qp);
1381                 mthca_free_wqe_buf(dev, qp);
1382         }
1383
1384         mthca_unmap_memfree(dev, qp);
1385
1386         if (is_sqp(dev, qp)) {
1387                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1388                 dma_free_coherent(&dev->pdev->dev,
1389                                   to_msqp(qp)->header_buf_size,
1390                                   to_msqp(qp)->header_buf,
1391                                   to_msqp(qp)->header_dma);
1392         } else
1393                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1394 }
1395
1396 /* Create UD header for an MLX send and build a data segment for it */
1397 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1398                             int ind, struct ib_send_wr *wr,
1399                             struct mthca_mlx_seg *mlx,
1400                             struct mthca_data_seg *data)
1401 {
1402         int header_size;
1403         int err;
1404         u16 pkey;
1405
1406         ib_ud_header_init(256, /* assume a MAD */
1407                           mthca_ah_grh_present(to_mah(wr->wr.ud.ah)),
1408                           &sqp->ud_header);
1409
1410         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1411         if (err)
1412                 return err;
1413         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1414         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1415                                   (sqp->ud_header.lrh.destination_lid ==
1416                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1417                                   (sqp->ud_header.lrh.service_level << 8));
1418         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1419         mlx->vcrc = 0;
1420
1421         switch (wr->opcode) {
1422         case IB_WR_SEND:
1423                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1424                 sqp->ud_header.immediate_present = 0;
1425                 break;
1426         case IB_WR_SEND_WITH_IMM:
1427                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1428                 sqp->ud_header.immediate_present = 1;
1429                 sqp->ud_header.immediate_data = wr->imm_data;
1430                 break;
1431         default:
1432                 return -EINVAL;
1433         }
1434
1435         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1436         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1437                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1438         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1439         if (!sqp->qp.ibqp.qp_num)
1440                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1441                                    sqp->pkey_index, &pkey);
1442         else
1443                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1444                                    wr->wr.ud.pkey_index, &pkey);
1445         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1446         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1447         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1448         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1449                                                sqp->qkey : wr->wr.ud.remote_qkey);
1450         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1451
1452         header_size = ib_ud_header_pack(&sqp->ud_header,
1453                                         sqp->header_buf +
1454                                         ind * MTHCA_UD_HEADER_SIZE);
1455
1456         data->byte_count = cpu_to_be32(header_size);
1457         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1458         data->addr       = cpu_to_be64(sqp->header_dma +
1459                                        ind * MTHCA_UD_HEADER_SIZE);
1460
1461         return 0;
1462 }
1463
1464 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1465                                     struct ib_cq *ib_cq)
1466 {
1467         unsigned cur;
1468         struct mthca_cq *cq;
1469
1470         cur = wq->head - wq->tail;
1471         if (likely(cur + nreq < wq->max))
1472                 return 0;
1473
1474         cq = to_mcq(ib_cq);
1475         spin_lock(&cq->lock);
1476         cur = wq->head - wq->tail;
1477         spin_unlock(&cq->lock);
1478
1479         return cur + nreq >= wq->max;
1480 }
1481
1482 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1483                           struct ib_send_wr **bad_wr)
1484 {
1485         struct mthca_dev *dev = to_mdev(ibqp->device);
1486         struct mthca_qp *qp = to_mqp(ibqp);
1487         void *wqe;
1488         void *prev_wqe;
1489         unsigned long flags;
1490         int err = 0;
1491         int nreq;
1492         int i;
1493         int size;
1494         int size0 = 0;
1495         u32 f0 = 0;
1496         int ind;
1497         u8 op0 = 0;
1498
1499         spin_lock_irqsave(&qp->sq.lock, flags);
1500
1501         /* XXX check that state is OK to post send */
1502
1503         ind = qp->sq.next_ind;
1504
1505         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1506                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1507                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1508                                         " %d max, %d nreq)\n", qp->qpn,
1509                                         qp->sq.head, qp->sq.tail,
1510                                         qp->sq.max, nreq);
1511                         err = -ENOMEM;
1512                         *bad_wr = wr;
1513                         goto out;
1514                 }
1515
1516                 wqe = get_send_wqe(qp, ind);
1517                 prev_wqe = qp->sq.last;
1518                 qp->sq.last = wqe;
1519
1520                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1521                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1522                 ((struct mthca_next_seg *) wqe)->flags =
1523                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1524                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1525                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1526                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1527                         cpu_to_be32(1);
1528                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1529                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1530                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1531
1532                 wqe += sizeof (struct mthca_next_seg);
1533                 size = sizeof (struct mthca_next_seg) / 16;
1534
1535                 switch (qp->transport) {
1536                 case RC:
1537                         switch (wr->opcode) {
1538                         case IB_WR_ATOMIC_CMP_AND_SWP:
1539                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1540                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1541                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1542                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1543                                         cpu_to_be32(wr->wr.atomic.rkey);
1544                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1545
1546                                 wqe += sizeof (struct mthca_raddr_seg);
1547
1548                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1549                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1550                                                 cpu_to_be64(wr->wr.atomic.swap);
1551                                         ((struct mthca_atomic_seg *) wqe)->compare =
1552                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1553                                 } else {
1554                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1555                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1556                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1557                                 }
1558
1559                                 wqe += sizeof (struct mthca_atomic_seg);
1560                                 size += (sizeof (struct mthca_raddr_seg) +
1561                                          sizeof (struct mthca_atomic_seg)) / 16;
1562                                 break;
1563
1564                         case IB_WR_RDMA_WRITE:
1565                         case IB_WR_RDMA_WRITE_WITH_IMM:
1566                         case IB_WR_RDMA_READ:
1567                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1568                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1569                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1570                                         cpu_to_be32(wr->wr.rdma.rkey);
1571                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1572                                 wqe += sizeof (struct mthca_raddr_seg);
1573                                 size += sizeof (struct mthca_raddr_seg) / 16;
1574                                 break;
1575
1576                         default:
1577                                 /* No extra segments required for sends */
1578                                 break;
1579                         }
1580
1581                         break;
1582
1583                 case UC:
1584                         switch (wr->opcode) {
1585                         case IB_WR_RDMA_WRITE:
1586                         case IB_WR_RDMA_WRITE_WITH_IMM:
1587                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1588                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1589                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1590                                         cpu_to_be32(wr->wr.rdma.rkey);
1591                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1592                                 wqe += sizeof (struct mthca_raddr_seg);
1593                                 size += sizeof (struct mthca_raddr_seg) / 16;
1594                                 break;
1595
1596                         default:
1597                                 /* No extra segments required for sends */
1598                                 break;
1599                         }
1600
1601                         break;
1602
1603                 case UD:
1604                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1605                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1606                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1607                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1608                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1609                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1610                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1611                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1612
1613                         wqe += sizeof (struct mthca_tavor_ud_seg);
1614                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1615                         break;
1616
1617                 case MLX:
1618                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1619                                                wqe - sizeof (struct mthca_next_seg),
1620                                                wqe);
1621                         if (err) {
1622                                 *bad_wr = wr;
1623                                 goto out;
1624                         }
1625                         wqe += sizeof (struct mthca_data_seg);
1626                         size += sizeof (struct mthca_data_seg) / 16;
1627                         break;
1628                 }
1629
1630                 if (wr->num_sge > qp->sq.max_gs) {
1631                         mthca_err(dev, "too many gathers\n");
1632                         err = -EINVAL;
1633                         *bad_wr = wr;
1634                         goto out;
1635                 }
1636
1637                 for (i = 0; i < wr->num_sge; ++i) {
1638                         ((struct mthca_data_seg *) wqe)->byte_count =
1639                                 cpu_to_be32(wr->sg_list[i].length);
1640                         ((struct mthca_data_seg *) wqe)->lkey =
1641                                 cpu_to_be32(wr->sg_list[i].lkey);
1642                         ((struct mthca_data_seg *) wqe)->addr =
1643                                 cpu_to_be64(wr->sg_list[i].addr);
1644                         wqe += sizeof (struct mthca_data_seg);
1645                         size += sizeof (struct mthca_data_seg) / 16;
1646                 }
1647
1648                 /* Add one more inline data segment for ICRC */
1649                 if (qp->transport == MLX) {
1650                         ((struct mthca_data_seg *) wqe)->byte_count =
1651                                 cpu_to_be32((1 << 31) | 4);
1652                         ((u32 *) wqe)[1] = 0;
1653                         wqe += sizeof (struct mthca_data_seg);
1654                         size += sizeof (struct mthca_data_seg) / 16;
1655                 }
1656
1657                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1658
1659                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1660                         mthca_err(dev, "opcode invalid\n");
1661                         err = -EINVAL;
1662                         *bad_wr = wr;
1663                         goto out;
1664                 }
1665
1666                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1667                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1668                                      qp->send_wqe_offset) |
1669                                     mthca_opcode[wr->opcode]);
1670                 wmb();
1671                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1672                         cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size |
1673                                     ((wr->send_flags & IB_SEND_FENCE) ?
1674                                     MTHCA_NEXT_FENCE : 0));
1675
1676                 if (!size0) {
1677                         size0 = size;
1678                         op0   = mthca_opcode[wr->opcode];
1679                 }
1680
1681                 ++ind;
1682                 if (unlikely(ind >= qp->sq.max))
1683                         ind -= qp->sq.max;
1684         }
1685
1686 out:
1687         if (likely(nreq)) {
1688                 __be32 doorbell[2];
1689
1690                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1691                                            qp->send_wqe_offset) | f0 | op0);
1692                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1693
1694                 wmb();
1695
1696                 mthca_write64(doorbell,
1697                               dev->kar + MTHCA_SEND_DOORBELL,
1698                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1699         }
1700
1701         qp->sq.next_ind = ind;
1702         qp->sq.head    += nreq;
1703
1704         spin_unlock_irqrestore(&qp->sq.lock, flags);
1705         return err;
1706 }
1707
1708 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1709                              struct ib_recv_wr **bad_wr)
1710 {
1711         struct mthca_dev *dev = to_mdev(ibqp->device);
1712         struct mthca_qp *qp = to_mqp(ibqp);
1713         __be32 doorbell[2];
1714         unsigned long flags;
1715         int err = 0;
1716         int nreq;
1717         int i;
1718         int size;
1719         int size0 = 0;
1720         int ind;
1721         void *wqe;
1722         void *prev_wqe;
1723
1724         spin_lock_irqsave(&qp->rq.lock, flags);
1725
1726         /* XXX check that state is OK to post receive */
1727
1728         ind = qp->rq.next_ind;
1729
1730         for (nreq = 0; wr; wr = wr->next) {
1731                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1732                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1733                                         " %d max, %d nreq)\n", qp->qpn,
1734                                         qp->rq.head, qp->rq.tail,
1735                                         qp->rq.max, nreq);
1736                         err = -ENOMEM;
1737                         *bad_wr = wr;
1738                         goto out;
1739                 }
1740
1741                 wqe = get_recv_wqe(qp, ind);
1742                 prev_wqe = qp->rq.last;
1743                 qp->rq.last = wqe;
1744
1745                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1746                 ((struct mthca_next_seg *) wqe)->ee_nds =
1747                         cpu_to_be32(MTHCA_NEXT_DBD);
1748                 ((struct mthca_next_seg *) wqe)->flags = 0;
1749
1750                 wqe += sizeof (struct mthca_next_seg);
1751                 size = sizeof (struct mthca_next_seg) / 16;
1752
1753                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1754                         err = -EINVAL;
1755                         *bad_wr = wr;
1756                         goto out;
1757                 }
1758
1759                 for (i = 0; i < wr->num_sge; ++i) {
1760                         ((struct mthca_data_seg *) wqe)->byte_count =
1761                                 cpu_to_be32(wr->sg_list[i].length);
1762                         ((struct mthca_data_seg *) wqe)->lkey =
1763                                 cpu_to_be32(wr->sg_list[i].lkey);
1764                         ((struct mthca_data_seg *) wqe)->addr =
1765                                 cpu_to_be64(wr->sg_list[i].addr);
1766                         wqe += sizeof (struct mthca_data_seg);
1767                         size += sizeof (struct mthca_data_seg) / 16;
1768                 }
1769
1770                 qp->wrid[ind] = wr->wr_id;
1771
1772                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1773                         cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1774                 wmb();
1775                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1776                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1777
1778                 if (!size0)
1779                         size0 = size;
1780
1781                 ++ind;
1782                 if (unlikely(ind >= qp->rq.max))
1783                         ind -= qp->rq.max;
1784
1785                 ++nreq;
1786                 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1787                         nreq = 0;
1788
1789                         doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1790                         doorbell[1] = cpu_to_be32(qp->qpn << 8);
1791
1792                         wmb();
1793
1794                         mthca_write64(doorbell,
1795                                       dev->kar + MTHCA_RECEIVE_DOORBELL,
1796                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1797
1798                         qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1799                         size0 = 0;
1800                 }
1801         }
1802
1803 out:
1804         if (likely(nreq)) {
1805                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1806                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1807
1808                 wmb();
1809
1810                 mthca_write64(doorbell,
1811                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1812                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1813         }
1814
1815         qp->rq.next_ind = ind;
1816         qp->rq.head    += nreq;
1817
1818         spin_unlock_irqrestore(&qp->rq.lock, flags);
1819         return err;
1820 }
1821
1822 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1823                           struct ib_send_wr **bad_wr)
1824 {
1825         struct mthca_dev *dev = to_mdev(ibqp->device);
1826         struct mthca_qp *qp = to_mqp(ibqp);
1827         __be32 doorbell[2];
1828         void *wqe;
1829         void *prev_wqe;
1830         unsigned long flags;
1831         int err = 0;
1832         int nreq;
1833         int i;
1834         int size;
1835         int size0 = 0;
1836         u32 f0 = 0;
1837         int ind;
1838         u8 op0 = 0;
1839
1840         spin_lock_irqsave(&qp->sq.lock, flags);
1841
1842         /* XXX check that state is OK to post send */
1843
1844         ind = qp->sq.head & (qp->sq.max - 1);
1845
1846         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1847                 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1848                         nreq = 0;
1849
1850                         doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1851                                                   ((qp->sq.head & 0xffff) << 8) |
1852                                                   f0 | op0);
1853                         doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1854
1855                         qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1856                         size0 = 0;
1857
1858                         /*
1859                          * Make sure that descriptors are written before
1860                          * doorbell record.
1861                          */
1862                         wmb();
1863                         *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1864
1865                         /*
1866                          * Make sure doorbell record is written before we
1867                          * write MMIO send doorbell.
1868                          */
1869                         wmb();
1870                         mthca_write64(doorbell,
1871                                       dev->kar + MTHCA_SEND_DOORBELL,
1872                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1873                 }
1874
1875                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1876                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1877                                         " %d max, %d nreq)\n", qp->qpn,
1878                                         qp->sq.head, qp->sq.tail,
1879                                         qp->sq.max, nreq);
1880                         err = -ENOMEM;
1881                         *bad_wr = wr;
1882                         goto out;
1883                 }
1884
1885                 wqe = get_send_wqe(qp, ind);
1886                 prev_wqe = qp->sq.last;
1887                 qp->sq.last = wqe;
1888
1889                 ((struct mthca_next_seg *) wqe)->flags =
1890                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1891                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1892                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1893                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1894                         cpu_to_be32(1);
1895                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1896                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1897                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1898
1899                 wqe += sizeof (struct mthca_next_seg);
1900                 size = sizeof (struct mthca_next_seg) / 16;
1901
1902                 switch (qp->transport) {
1903                 case RC:
1904                         switch (wr->opcode) {
1905                         case IB_WR_ATOMIC_CMP_AND_SWP:
1906                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1907                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1908                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1909                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1910                                         cpu_to_be32(wr->wr.atomic.rkey);
1911                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1912
1913                                 wqe += sizeof (struct mthca_raddr_seg);
1914
1915                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1916                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1917                                                 cpu_to_be64(wr->wr.atomic.swap);
1918                                         ((struct mthca_atomic_seg *) wqe)->compare =
1919                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1920                                 } else {
1921                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1922                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1923                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1924                                 }
1925
1926                                 wqe += sizeof (struct mthca_atomic_seg);
1927                                 size += (sizeof (struct mthca_raddr_seg) +
1928                                          sizeof (struct mthca_atomic_seg)) / 16;
1929                                 break;
1930
1931                         case IB_WR_RDMA_READ:
1932                         case IB_WR_RDMA_WRITE:
1933                         case IB_WR_RDMA_WRITE_WITH_IMM:
1934                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1935                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1936                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1937                                         cpu_to_be32(wr->wr.rdma.rkey);
1938                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1939                                 wqe += sizeof (struct mthca_raddr_seg);
1940                                 size += sizeof (struct mthca_raddr_seg) / 16;
1941                                 break;
1942
1943                         default:
1944                                 /* No extra segments required for sends */
1945                                 break;
1946                         }
1947
1948                         break;
1949
1950                 case UC:
1951                         switch (wr->opcode) {
1952                         case IB_WR_RDMA_WRITE:
1953                         case IB_WR_RDMA_WRITE_WITH_IMM:
1954                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1955                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1956                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1957                                         cpu_to_be32(wr->wr.rdma.rkey);
1958                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1959                                 wqe += sizeof (struct mthca_raddr_seg);
1960                                 size += sizeof (struct mthca_raddr_seg) / 16;
1961                                 break;
1962
1963                         default:
1964                                 /* No extra segments required for sends */
1965                                 break;
1966                         }
1967
1968                         break;
1969
1970                 case UD:
1971                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1972                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1973                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1974                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1975                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1976                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1977
1978                         wqe += sizeof (struct mthca_arbel_ud_seg);
1979                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
1980                         break;
1981
1982                 case MLX:
1983                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1984                                                wqe - sizeof (struct mthca_next_seg),
1985                                                wqe);
1986                         if (err) {
1987                                 *bad_wr = wr;
1988                                 goto out;
1989                         }
1990                         wqe += sizeof (struct mthca_data_seg);
1991                         size += sizeof (struct mthca_data_seg) / 16;
1992                         break;
1993                 }
1994
1995                 if (wr->num_sge > qp->sq.max_gs) {
1996                         mthca_err(dev, "too many gathers\n");
1997                         err = -EINVAL;
1998                         *bad_wr = wr;
1999                         goto out;
2000                 }
2001
2002                 for (i = 0; i < wr->num_sge; ++i) {
2003                         ((struct mthca_data_seg *) wqe)->byte_count =
2004                                 cpu_to_be32(wr->sg_list[i].length);
2005                         ((struct mthca_data_seg *) wqe)->lkey =
2006                                 cpu_to_be32(wr->sg_list[i].lkey);
2007                         ((struct mthca_data_seg *) wqe)->addr =
2008                                 cpu_to_be64(wr->sg_list[i].addr);
2009                         wqe += sizeof (struct mthca_data_seg);
2010                         size += sizeof (struct mthca_data_seg) / 16;
2011                 }
2012
2013                 /* Add one more inline data segment for ICRC */
2014                 if (qp->transport == MLX) {
2015                         ((struct mthca_data_seg *) wqe)->byte_count =
2016                                 cpu_to_be32((1 << 31) | 4);
2017                         ((u32 *) wqe)[1] = 0;
2018                         wqe += sizeof (struct mthca_data_seg);
2019                         size += sizeof (struct mthca_data_seg) / 16;
2020                 }
2021
2022                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2023
2024                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2025                         mthca_err(dev, "opcode invalid\n");
2026                         err = -EINVAL;
2027                         *bad_wr = wr;
2028                         goto out;
2029                 }
2030
2031                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2032                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
2033                                      qp->send_wqe_offset) |
2034                                     mthca_opcode[wr->opcode]);
2035                 wmb();
2036                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2037                         cpu_to_be32(MTHCA_NEXT_DBD | size |
2038                                     ((wr->send_flags & IB_SEND_FENCE) ?
2039                                      MTHCA_NEXT_FENCE : 0));
2040
2041                 if (!size0) {
2042                         size0 = size;
2043                         op0   = mthca_opcode[wr->opcode];
2044                 }
2045
2046                 ++ind;
2047                 if (unlikely(ind >= qp->sq.max))
2048                         ind -= qp->sq.max;
2049         }
2050
2051 out:
2052         if (likely(nreq)) {
2053                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
2054                                           ((qp->sq.head & 0xffff) << 8) |
2055                                           f0 | op0);
2056                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2057
2058                 qp->sq.head += nreq;
2059
2060                 /*
2061                  * Make sure that descriptors are written before
2062                  * doorbell record.
2063                  */
2064                 wmb();
2065                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2066
2067                 /*
2068                  * Make sure doorbell record is written before we
2069                  * write MMIO send doorbell.
2070                  */
2071                 wmb();
2072                 mthca_write64(doorbell,
2073                               dev->kar + MTHCA_SEND_DOORBELL,
2074                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2075         }
2076
2077         spin_unlock_irqrestore(&qp->sq.lock, flags);
2078         return err;
2079 }
2080
2081 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2082                              struct ib_recv_wr **bad_wr)
2083 {
2084         struct mthca_dev *dev = to_mdev(ibqp->device);
2085         struct mthca_qp *qp = to_mqp(ibqp);
2086         unsigned long flags;
2087         int err = 0;
2088         int nreq;
2089         int ind;
2090         int i;
2091         void *wqe;
2092
2093         spin_lock_irqsave(&qp->rq.lock, flags);
2094
2095         /* XXX check that state is OK to post receive */
2096
2097         ind = qp->rq.head & (qp->rq.max - 1);
2098
2099         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2100                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2101                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2102                                         " %d max, %d nreq)\n", qp->qpn,
2103                                         qp->rq.head, qp->rq.tail,
2104                                         qp->rq.max, nreq);
2105                         err = -ENOMEM;
2106                         *bad_wr = wr;
2107                         goto out;
2108                 }
2109
2110                 wqe = get_recv_wqe(qp, ind);
2111
2112                 ((struct mthca_next_seg *) wqe)->flags = 0;
2113
2114                 wqe += sizeof (struct mthca_next_seg);
2115
2116                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2117                         err = -EINVAL;
2118                         *bad_wr = wr;
2119                         goto out;
2120                 }
2121
2122                 for (i = 0; i < wr->num_sge; ++i) {
2123                         ((struct mthca_data_seg *) wqe)->byte_count =
2124                                 cpu_to_be32(wr->sg_list[i].length);
2125                         ((struct mthca_data_seg *) wqe)->lkey =
2126                                 cpu_to_be32(wr->sg_list[i].lkey);
2127                         ((struct mthca_data_seg *) wqe)->addr =
2128                                 cpu_to_be64(wr->sg_list[i].addr);
2129                         wqe += sizeof (struct mthca_data_seg);
2130                 }
2131
2132                 if (i < qp->rq.max_gs) {
2133                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2134                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2135                         ((struct mthca_data_seg *) wqe)->addr = 0;
2136                 }
2137
2138                 qp->wrid[ind] = wr->wr_id;
2139
2140                 ++ind;
2141                 if (unlikely(ind >= qp->rq.max))
2142                         ind -= qp->rq.max;
2143         }
2144 out:
2145         if (likely(nreq)) {
2146                 qp->rq.head += nreq;
2147
2148                 /*
2149                  * Make sure that descriptors are written before
2150                  * doorbell record.
2151                  */
2152                 wmb();
2153                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2154         }
2155
2156         spin_unlock_irqrestore(&qp->rq.lock, flags);
2157         return err;
2158 }
2159
2160 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2161                         int index, int *dbd, __be32 *new_wqe)
2162 {
2163         struct mthca_next_seg *next;
2164
2165         /*
2166          * For SRQs, all WQEs generate a CQE, so we're always at the
2167          * end of the doorbell chain.
2168          */
2169         if (qp->ibqp.srq) {
2170                 *new_wqe = 0;
2171                 return;
2172         }
2173
2174         if (is_send)
2175                 next = get_send_wqe(qp, index);
2176         else
2177                 next = get_recv_wqe(qp, index);
2178
2179         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2180         if (next->ee_nds & cpu_to_be32(0x3f))
2181                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2182                         (next->ee_nds & cpu_to_be32(0x3f));
2183         else
2184                 *new_wqe = 0;
2185 }
2186
2187 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2188 {
2189         int err;
2190         u8 status;
2191         int i;
2192
2193         spin_lock_init(&dev->qp_table.lock);
2194
2195         /*
2196          * We reserve 2 extra QPs per port for the special QPs.  The
2197          * special QP for port 1 has to be even, so round up.
2198          */
2199         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2200         err = mthca_alloc_init(&dev->qp_table.alloc,
2201                                dev->limits.num_qps,
2202                                (1 << 24) - 1,
2203                                dev->qp_table.sqp_start +
2204                                MTHCA_MAX_PORTS * 2);
2205         if (err)
2206                 return err;
2207
2208         err = mthca_array_init(&dev->qp_table.qp,
2209                                dev->limits.num_qps);
2210         if (err) {
2211                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2212                 return err;
2213         }
2214
2215         for (i = 0; i < 2; ++i) {
2216                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2217                                             dev->qp_table.sqp_start + i * 2,
2218                                             &status);
2219                 if (err)
2220                         goto err_out;
2221                 if (status) {
2222                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2223                                    "status %02x, aborting.\n",
2224                                    status);
2225                         err = -EINVAL;
2226                         goto err_out;
2227                 }
2228         }
2229         return 0;
2230
2231  err_out:
2232         for (i = 0; i < 2; ++i)
2233                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2234
2235         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2236         mthca_alloc_cleanup(&dev->qp_table.alloc);
2237
2238         return err;
2239 }
2240
2241 void mthca_cleanup_qp_table(struct mthca_dev *dev)
2242 {
2243         int i;
2244         u8 status;
2245
2246         for (i = 0; i < 2; ++i)
2247                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2248
2249         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2250         mthca_alloc_cleanup(&dev->qp_table.alloc);
2251 }