drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/init.h>
  39
  40 #include <ib_verbs.h>
  41 #include <ib_cache.h>
  42 #include <ib_pack.h>
  43
  44 #include "mthca_dev.h"
  45 #include "mthca_cmd.h"
  46 #include "mthca_memfree.h"
  47 #include "mthca_wqe.h"
  48
  49 enum {
  50         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  51         MTHCA_ACK_REQ_FREQ       = 10,
  52         MTHCA_FLIGHT_LIMIT       = 9,
  53         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  54         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  55         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  56 };
  57
  58 enum {
  59         MTHCA_QP_STATE_RST  = 0,
  60         MTHCA_QP_STATE_INIT = 1,
  61         MTHCA_QP_STATE_RTR  = 2,
  62         MTHCA_QP_STATE_RTS  = 3,
  63         MTHCA_QP_STATE_SQE  = 4,
  64         MTHCA_QP_STATE_SQD  = 5,
  65         MTHCA_QP_STATE_ERR  = 6,
  66         MTHCA_QP_STATE_DRAINING = 7
  67 };
  68
  69 enum {
  70         MTHCA_QP_ST_RC  = 0x0,
  71         MTHCA_QP_ST_UC  = 0x1,
  72         MTHCA_QP_ST_RD  = 0x2,
  73         MTHCA_QP_ST_UD  = 0x3,
  74         MTHCA_QP_ST_MLX = 0x7
  75 };
  76
  77 enum {
  78         MTHCA_QP_PM_MIGRATED = 0x3,
  79         MTHCA_QP_PM_ARMED    = 0x0,
  80         MTHCA_QP_PM_REARM    = 0x1
  81 };
  82
  83 enum {
  84         /* qp_context flags */
  85         MTHCA_QP_BIT_DE  = 1 <<  8,
  86         /* params1 */
  87         MTHCA_QP_BIT_SRE = 1 << 15,
  88         MTHCA_QP_BIT_SWE = 1 << 14,
  89         MTHCA_QP_BIT_SAE = 1 << 13,
  90         MTHCA_QP_BIT_SIC = 1 <<  4,
  91         MTHCA_QP_BIT_SSC = 1 <<  3,
  92         /* params2 */
  93         MTHCA_QP_BIT_RRE = 1 << 15,
  94         MTHCA_QP_BIT_RWE = 1 << 14,
  95         MTHCA_QP_BIT_RAE = 1 << 13,
  96         MTHCA_QP_BIT_RIC = 1 <<  4,
  97         MTHCA_QP_BIT_RSC = 1 <<  3
  98 };
  99
 100 struct mthca_qp_path {
 101         __be32 port_pkey;
 102         u8     rnr_retry;
 103         u8     g_mylmc;
 104         __be16 rlid;
 105         u8     ackto;
 106         u8     mgid_index;
 107         u8     static_rate;
 108         u8     hop_limit;
 109         __be32 sl_tclass_flowlabel;
 110         u8     rgid[16];
 111 } __attribute__((packed));
 112
 113 struct mthca_qp_context {
 114         __be32 flags;
 115         __be32 tavor_sched_queue; /* Reserved on Arbel */
 116         u8     mtu_msgmax;
 117         u8     rq_size_stride;  /* Reserved on Tavor */
 118         u8     sq_size_stride;  /* Reserved on Tavor */
 119         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 120         __be32 usr_page;
 121         __be32 local_qpn;
 122         __be32 remote_qpn;
 123         u32    reserved1[2];
 124         struct mthca_qp_path pri_path;
 125         struct mthca_qp_path alt_path;
 126         __be32 rdd;
 127         __be32 pd;
 128         __be32 wqe_base;
 129         __be32 wqe_lkey;
 130         __be32 params1;
 131         __be32 reserved2;
 132         __be32 next_send_psn;
 133         __be32 cqn_snd;
 134         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 135         __be32 snd_db_index;    /* (debugging only entries) */
 136         __be32 last_acked_psn;
 137         __be32 ssn;
 138         __be32 params2;
 139         __be32 rnr_nextrecvpsn;
 140         __be32 ra_buff_indx;
 141         __be32 cqn_rcv;
 142         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 143         __be32 rcv_db_index;    /* (debugging only entries) */
 144         __be32 qkey;
 145         __be32 srqn;
 146         __be32 rmsn;
 147         __be16 rq_wqe_counter;  /* reserved on Tavor */
 148         __be16 sq_wqe_counter;  /* reserved on Tavor */
 149         u32    reserved3[18];
 150 } __attribute__((packed));
 151
 152 struct mthca_qp_param {
 153         __be32 opt_param_mask;
 154         u32    reserved1;
 155         struct mthca_qp_context context;
 156         u32    reserved2[62];
 157 } __attribute__((packed));
 158
 159 enum {
 160         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 161         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 162         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 163         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 164         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 165         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 166         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 167         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 168         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 169         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 170         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 171         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 172         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 173         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 174         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 175         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 176         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 177 };
 178
 179 static const u8 mthca_opcode[] = {
 180         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 181         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 182         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 183         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 184         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 185         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 186         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 187 };
 188
 189 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 190 {
 191         return qp->qpn >= dev->qp_table.sqp_start &&
 192                 qp->qpn <= dev->qp_table.sqp_start + 3;
 193 }
 194
 195 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 196 {
 197         return qp->qpn >= dev->qp_table.sqp_start &&
 198                 qp->qpn <= dev->qp_table.sqp_start + 1;
 199 }
 200
 201 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 202 {
 203         if (qp->is_direct)
 204                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 205         else
 206                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 207                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 208 }
 209
 210 static void *get_send_wqe(struct mthca_qp *qp, int n)
 211 {
 212         if (qp->is_direct)
 213                 return qp->queue.direct.buf + qp->send_wqe_offset +
 214                         (n << qp->sq.wqe_shift);
 215         else
 216                 return qp->queue.page_list[(qp->send_wqe_offset +
 217                                             (n << qp->sq.wqe_shift)) >>
 218                                            PAGE_SHIFT].buf +
 219                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 220                          (PAGE_SIZE - 1));
 221 }
 222
 223 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 224                     enum ib_event_type event_type)
 225 {
 226         struct mthca_qp *qp;
 227         struct ib_event event;
 228
 229         spin_lock(&dev->qp_table.lock);
 230         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 231         if (qp)
 232                 atomic_inc(&qp->refcount);
 233         spin_unlock(&dev->qp_table.lock);
 234
 235         if (!qp) {
 236                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 237                 return;
 238         }
 239
 240         event.device      = &dev->ib_dev;
 241         event.event       = event_type;
 242         event.element.qp  = &qp->ibqp;
 243         if (qp->ibqp.event_handler)
 244                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 245
 246         if (atomic_dec_and_test(&qp->refcount))
 247                 wake_up(&qp->wait);
 248 }
 249
 250 static int to_mthca_state(enum ib_qp_state ib_state)
 251 {
 252         switch (ib_state) {
 253         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 254         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 255         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 256         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 257         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 258         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 259         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 260         default:                return -1;
 261         }
 262 }
 263
 264 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 265
 266 static int to_mthca_st(int transport)
 267 {
 268         switch (transport) {
 269         case RC:  return MTHCA_QP_ST_RC;
 270         case UC:  return MTHCA_QP_ST_UC;
 271         case UD:  return MTHCA_QP_ST_UD;
 272         case RD:  return MTHCA_QP_ST_RD;
 273         case MLX: return MTHCA_QP_ST_MLX;
 274         default:  return -1;
 275         }
 276 }
 277
 278 static const struct {
 279         int trans;
 280         u32 req_param[NUM_TRANS];
 281         u32 opt_param[NUM_TRANS];
 282 } state_table[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
 283         [IB_QPS_RESET] = {
 284                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 285                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 286                 [IB_QPS_INIT]  = {
 287                         .trans = MTHCA_TRANS_RST2INIT,
 288                         .req_param = {
 289                                 [UD]  = (IB_QP_PKEY_INDEX |
 290                                          IB_QP_PORT       |
 291                                          IB_QP_QKEY),
 292                                 [UC]  = (IB_QP_PKEY_INDEX |
 293                                          IB_QP_PORT       |
 294                                          IB_QP_ACCESS_FLAGS),
 295                                 [RC]  = (IB_QP_PKEY_INDEX |
 296                                          IB_QP_PORT       |
 297                                          IB_QP_ACCESS_FLAGS),
 298                                 [MLX] = (IB_QP_PKEY_INDEX |
 299                                          IB_QP_QKEY),
 300                         },
 301                         /* bug-for-bug compatibility with VAPI: */
 302                         .opt_param = {
 303                                 [MLX] = IB_QP_PORT
 304                         }
 305                 },
 306         },
 307         [IB_QPS_INIT]  = {
 308                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 309                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 310                 [IB_QPS_INIT]  = {
 311                         .trans = MTHCA_TRANS_INIT2INIT,
 312                         .opt_param = {
 313                                 [UD]  = (IB_QP_PKEY_INDEX |
 314                                          IB_QP_PORT       |
 315                                          IB_QP_QKEY),
 316                                 [UC]  = (IB_QP_PKEY_INDEX |
 317                                          IB_QP_PORT       |
 318                                          IB_QP_ACCESS_FLAGS),
 319                                 [RC]  = (IB_QP_PKEY_INDEX |
 320                                          IB_QP_PORT       |
 321                                          IB_QP_ACCESS_FLAGS),
 322                                 [MLX] = (IB_QP_PKEY_INDEX |
 323                                          IB_QP_QKEY),
 324                         }
 325                 },
 326                 [IB_QPS_RTR]   = {
 327                         .trans = MTHCA_TRANS_INIT2RTR,
 328                         .req_param = {
 329                                 [UC]  = (IB_QP_AV                  |
 330                                          IB_QP_PATH_MTU            |
 331                                          IB_QP_DEST_QPN            |
 332                                          IB_QP_RQ_PSN              |
 333                                          IB_QP_MAX_DEST_RD_ATOMIC),
 334                                 [RC]  = (IB_QP_AV                  |
 335                                          IB_QP_PATH_MTU            |
 336                                          IB_QP_DEST_QPN            |
 337                                          IB_QP_RQ_PSN              |
 338                                          IB_QP_MAX_DEST_RD_ATOMIC  |
 339                                          IB_QP_MIN_RNR_TIMER),
 340                         },
 341                         .opt_param = {
 342                                 [UD]  = (IB_QP_PKEY_INDEX |
 343                                          IB_QP_QKEY),
 344                                 [UC]  = (IB_QP_ALT_PATH     |
 345                                          IB_QP_ACCESS_FLAGS |
 346                                          IB_QP_PKEY_INDEX),
 347                                 [RC]  = (IB_QP_ALT_PATH     |
 348                                          IB_QP_ACCESS_FLAGS |
 349                                          IB_QP_PKEY_INDEX),
 350                                 [MLX] = (IB_QP_PKEY_INDEX |
 351                                          IB_QP_QKEY),
 352                         }
 353                 }
 354         },
 355         [IB_QPS_RTR]   = {
 356                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 357                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 358                 [IB_QPS_RTS]   = {
 359                         .trans = MTHCA_TRANS_RTR2RTS,
 360                         .req_param = {
 361                                 [UD]  = IB_QP_SQ_PSN,
 362                                 [UC]  = (IB_QP_SQ_PSN            |
 363                                          IB_QP_MAX_QP_RD_ATOMIC),
 364                                 [RC]  = (IB_QP_TIMEOUT           |
 365                                          IB_QP_RETRY_CNT         |
 366                                          IB_QP_RNR_RETRY         |
 367                                          IB_QP_SQ_PSN            |
 368                                          IB_QP_MAX_QP_RD_ATOMIC),
 369                                 [MLX] = IB_QP_SQ_PSN,
 370                         },
 371                         .opt_param = {
 372                                 [UD]  = (IB_QP_CUR_STATE             |
 373                                          IB_QP_QKEY),
 374                                 [UC]  = (IB_QP_CUR_STATE             |
 375                                          IB_QP_ALT_PATH              |
 376                                          IB_QP_ACCESS_FLAGS          |
 377                                          IB_QP_PKEY_INDEX            |
 378                                          IB_QP_PATH_MIG_STATE),
 379                                 [RC]  = (IB_QP_CUR_STATE             |
 380                                          IB_QP_ALT_PATH              |
 381                                          IB_QP_ACCESS_FLAGS          |
 382                                          IB_QP_PKEY_INDEX            |
 383                                          IB_QP_MIN_RNR_TIMER         |
 384                                          IB_QP_PATH_MIG_STATE),
 385                                 [MLX] = (IB_QP_CUR_STATE             |
 386                                          IB_QP_QKEY),
 387                         }
 388                 }
 389         },
 390         [IB_QPS_RTS]   = {
 391                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 392                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 393                 [IB_QPS_RTS]   = {
 394                         .trans = MTHCA_TRANS_RTS2RTS,
 395                         .opt_param = {
 396                                 [UD]  = (IB_QP_CUR_STATE             |
 397                                          IB_QP_QKEY),
 398                                 [UC]  = (IB_QP_ACCESS_FLAGS          |
 399                                          IB_QP_ALT_PATH              |
 400                                          IB_QP_PATH_MIG_STATE),
 401                                 [RC]  = (IB_QP_ACCESS_FLAGS          |
 402                                          IB_QP_ALT_PATH              |
 403                                          IB_QP_PATH_MIG_STATE        |
 404                                          IB_QP_MIN_RNR_TIMER),
 405                                 [MLX] = (IB_QP_CUR_STATE             |
 406                                          IB_QP_QKEY),
 407                         }
 408                 },
 409                 [IB_QPS_SQD]   = {
 410                         .trans = MTHCA_TRANS_RTS2SQD,
 411                 },
 412         },
 413         [IB_QPS_SQD]   = {
 414                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 415                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 416                 [IB_QPS_RTS]   = {
 417                         .trans = MTHCA_TRANS_SQD2RTS,
 418                         .opt_param = {
 419                                 [UD]  = (IB_QP_CUR_STATE             |
 420                                          IB_QP_QKEY),
 421                                 [UC]  = (IB_QP_CUR_STATE             |
 422                                          IB_QP_ALT_PATH              |
 423                                          IB_QP_ACCESS_FLAGS          |
 424                                          IB_QP_PATH_MIG_STATE),
 425                                 [RC]  = (IB_QP_CUR_STATE             |
 426                                          IB_QP_ALT_PATH              |
 427                                          IB_QP_ACCESS_FLAGS          |
 428                                          IB_QP_MIN_RNR_TIMER         |
 429                                          IB_QP_PATH_MIG_STATE),
 430                                 [MLX] = (IB_QP_CUR_STATE             |
 431                                          IB_QP_QKEY),
 432                         }
 433                 },
 434                 [IB_QPS_SQD]   = {
 435                         .trans = MTHCA_TRANS_SQD2SQD,
 436                         .opt_param = {
 437                                 [UD]  = (IB_QP_PKEY_INDEX            |
 438                                          IB_QP_QKEY),
 439                                 [UC]  = (IB_QP_AV                    |
 440                                          IB_QP_MAX_QP_RD_ATOMIC      |
 441                                          IB_QP_MAX_DEST_RD_ATOMIC    |
 442                                          IB_QP_CUR_STATE             |
 443                                          IB_QP_ALT_PATH              |
 444                                          IB_QP_ACCESS_FLAGS          |
 445                                          IB_QP_PKEY_INDEX            |
 446                                          IB_QP_PATH_MIG_STATE),
 447                                 [RC]  = (IB_QP_AV                    |
 448                                          IB_QP_TIMEOUT               |
 449                                          IB_QP_RETRY_CNT             |
 450                                          IB_QP_RNR_RETRY             |
 451                                          IB_QP_MAX_QP_RD_ATOMIC      |
 452                                          IB_QP_MAX_DEST_RD_ATOMIC    |
 453                                          IB_QP_CUR_STATE             |
 454                                          IB_QP_ALT_PATH              |
 455                                          IB_QP_ACCESS_FLAGS          |
 456                                          IB_QP_PKEY_INDEX            |
 457                                          IB_QP_MIN_RNR_TIMER         |
 458                                          IB_QP_PATH_MIG_STATE),
 459                                 [MLX] = (IB_QP_PKEY_INDEX            |
 460                                          IB_QP_QKEY),
 461                         }
 462                 }
 463         },
 464         [IB_QPS_SQE]   = {
 465                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 466                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 467                 [IB_QPS_RTS]   = {
 468                         .trans = MTHCA_TRANS_SQERR2RTS,
 469                         .opt_param = {
 470                                 [UD]  = (IB_QP_CUR_STATE             |
 471                                          IB_QP_QKEY),
 472                                 [UC]  = (IB_QP_CUR_STATE),
 473                                 [RC]  = (IB_QP_CUR_STATE             |
 474                                          IB_QP_MIN_RNR_TIMER),
 475                                 [MLX] = (IB_QP_CUR_STATE             |
 476                                          IB_QP_QKEY),
 477                         }
 478                 }
 479         },
 480         [IB_QPS_ERR] = {
 481                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 482                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR }
 483         }
 484 };
 485
 486 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 487                         int attr_mask)
 488 {
 489         if (attr_mask & IB_QP_PKEY_INDEX)
 490                 sqp->pkey_index = attr->pkey_index;
 491         if (attr_mask & IB_QP_QKEY)
 492                 sqp->qkey = attr->qkey;
 493         if (attr_mask & IB_QP_SQ_PSN)
 494                 sqp->send_psn = attr->sq_psn;
 495 }
 496
 497 static void init_port(struct mthca_dev *dev, int port)
 498 {
 499         int err;
 500         u8 status;
 501         struct mthca_init_ib_param param;
 502
 503         memset(&param, 0, sizeof param);
 504
 505         param.port_width = dev->limits.port_width_cap;
 506         param.vl_cap     = dev->limits.vl_cap;
 507         param.mtu_cap    = dev->limits.mtu_cap;
 508         param.gid_cap    = dev->limits.gid_table_len;
 509         param.pkey_cap   = dev->limits.pkey_table_len;
 510
 511         err = mthca_INIT_IB(dev, &param, port, &status);
 512         if (err)
 513                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 514         if (status)
 515                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 516 }
 517
 518 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
 519 {
 520         struct mthca_dev *dev = to_mdev(ibqp->device);
 521         struct mthca_qp *qp = to_mqp(ibqp);
 522         enum ib_qp_state cur_state, new_state;
 523         struct mthca_mailbox *mailbox;
 524         struct mthca_qp_param *qp_param;
 525         struct mthca_qp_context *qp_context;
 526         u32 req_param, opt_param;
 527         u8 status;
 528         int err;
 529
 530         if (attr_mask & IB_QP_CUR_STATE) {
 531                 if (attr->cur_qp_state != IB_QPS_RTR &&
 532                     attr->cur_qp_state != IB_QPS_RTS &&
 533                     attr->cur_qp_state != IB_QPS_SQD &&
 534                     attr->cur_qp_state != IB_QPS_SQE)
 535                         return -EINVAL;
 536                 else
 537                         cur_state = attr->cur_qp_state;
 538         } else {
 539                 spin_lock_irq(&qp->sq.lock);
 540                 spin_lock(&qp->rq.lock);
 541                 cur_state = qp->state;
 542                 spin_unlock(&qp->rq.lock);
 543                 spin_unlock_irq(&qp->sq.lock);
 544         }
 545
 546         if (attr_mask & IB_QP_STATE) {
 547                if (attr->qp_state < 0 || attr->qp_state > IB_QPS_ERR)
 548                         return -EINVAL;
 549                 new_state = attr->qp_state;
 550         } else
 551                 new_state = cur_state;
 552
 553         if (state_table[cur_state][new_state].trans == MTHCA_TRANS_INVALID) {
 554                 mthca_dbg(dev, "Illegal QP transition "
 555                           "%d->%d\n", cur_state, new_state);
 556                 return -EINVAL;
 557         }
 558
 559         req_param = state_table[cur_state][new_state].req_param[qp->transport];
 560         opt_param = state_table[cur_state][new_state].opt_param[qp->transport];
 561
 562         if ((req_param & attr_mask) != req_param) {
 563                 mthca_dbg(dev, "QP transition "
 564                           "%d->%d missing req attr 0x%08x\n",
 565                           cur_state, new_state,
 566                           req_param & ~attr_mask);
 567                 return -EINVAL;
 568         }
 569
 570         if (attr_mask & ~(req_param | opt_param | IB_QP_STATE)) {
 571                 mthca_dbg(dev, "QP transition (transport %d) "
 572                           "%d->%d has extra attr 0x%08x\n",
 573                           qp->transport,
 574                           cur_state, new_state,
 575                           attr_mask & ~(req_param | opt_param |
 576                                                  IB_QP_STATE));
 577                 return -EINVAL;
 578         }
 579
 580         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 581         if (IS_ERR(mailbox))
 582                 return PTR_ERR(mailbox);
 583         qp_param = mailbox->buf;
 584         qp_context = &qp_param->context;
 585         memset(qp_param, 0, sizeof *qp_param);
 586
 587         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 588                                              (to_mthca_st(qp->transport) << 16));
 589         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 590         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 591                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 592         else {
 593                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 594                 switch (attr->path_mig_state) {
 595                 case IB_MIG_MIGRATED:
 596                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 597                         break;
 598                 case IB_MIG_REARM:
 599                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 600                         break;
 601                 case IB_MIG_ARMED:
 602                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 603                         break;
 604                 }
 605         }
 606
 607         /* leave tavor_sched_queue as 0 */
 608
 609         if (qp->transport == MLX || qp->transport == UD)
 610                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 611         else if (attr_mask & IB_QP_PATH_MTU)
 612                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 613
 614         if (mthca_is_memfree(dev)) {
 615                 qp_context->rq_size_stride =
 616                         ((ffs(qp->rq.max) - 1) << 3) | (qp->rq.wqe_shift - 4);
 617                 qp_context->sq_size_stride =
 618                         ((ffs(qp->sq.max) - 1) << 3) | (qp->sq.wqe_shift - 4);
 619         }
 620
 621         /* leave arbel_sched_queue as 0 */
 622
 623         if (qp->ibqp.uobject)
 624                 qp_context->usr_page =
 625                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 626         else
 627                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 628         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 629         if (attr_mask & IB_QP_DEST_QPN) {
 630                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 631         }
 632
 633         if (qp->transport == MLX)
 634                 qp_context->pri_path.port_pkey |=
 635                         cpu_to_be32(to_msqp(qp)->port << 24);
 636         else {
 637                 if (attr_mask & IB_QP_PORT) {
 638                         qp_context->pri_path.port_pkey |=
 639                                 cpu_to_be32(attr->port_num << 24);
 640                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 641                 }
 642         }
 643
 644         if (attr_mask & IB_QP_PKEY_INDEX) {
 645                 qp_context->pri_path.port_pkey |=
 646                         cpu_to_be32(attr->pkey_index);
 647                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 648         }
 649
 650         if (attr_mask & IB_QP_RNR_RETRY) {
 651                 qp_context->pri_path.rnr_retry = attr->rnr_retry << 5;
 652                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY);
 653         }
 654
 655         if (attr_mask & IB_QP_AV) {
 656                 qp_context->pri_path.g_mylmc     = attr->ah_attr.src_path_bits & 0x7f;
 657                 qp_context->pri_path.rlid        = cpu_to_be16(attr->ah_attr.dlid);
 658                 qp_context->pri_path.static_rate = !!attr->ah_attr.static_rate;
 659                 if (attr->ah_attr.ah_flags & IB_AH_GRH) {
 660                         qp_context->pri_path.g_mylmc |= 1 << 7;
 661                         qp_context->pri_path.mgid_index = attr->ah_attr.grh.sgid_index;
 662                         qp_context->pri_path.hop_limit = attr->ah_attr.grh.hop_limit;
 663                         qp_context->pri_path.sl_tclass_flowlabel =
 664                                 cpu_to_be32((attr->ah_attr.sl << 28)                |
 665                                             (attr->ah_attr.grh.traffic_class << 20) |
 666                                             (attr->ah_attr.grh.flow_label));
 667                         memcpy(qp_context->pri_path.rgid,
 668                                attr->ah_attr.grh.dgid.raw, 16);
 669                 } else {
 670                         qp_context->pri_path.sl_tclass_flowlabel =
 671                                 cpu_to_be32(attr->ah_attr.sl << 28);
 672                 }
 673                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 674         }
 675
 676         if (attr_mask & IB_QP_TIMEOUT) {
 677                 qp_context->pri_path.ackto = attr->timeout;
 678                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 679         }
 680
 681         /* XXX alt_path */
 682
 683         /* leave rdd as 0 */
 684         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 685         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 686         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 687         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 688                                              (MTHCA_FLIGHT_LIMIT << 24) |
 689                                              MTHCA_QP_BIT_SRE           |
 690                                              MTHCA_QP_BIT_SWE           |
 691                                              MTHCA_QP_BIT_SAE);
 692         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 693                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 694         if (attr_mask & IB_QP_RETRY_CNT) {
 695                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 696                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 697         }
 698
 699         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 700                 qp_context->params1 |= cpu_to_be32(min(attr->max_rd_atomic ?
 701                                                        ffs(attr->max_rd_atomic) - 1 : 0,
 702                                                        7) << 21);
 703                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 704         }
 705
 706         if (attr_mask & IB_QP_SQ_PSN)
 707                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 708         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 709
 710         if (mthca_is_memfree(dev)) {
 711                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 712                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 713         }
 714
 715         if (attr_mask & IB_QP_ACCESS_FLAGS) {
 716                 /*
 717                  * Only enable RDMA/atomics if we have responder
 718                  * resources set to a non-zero value.
 719                  */
 720                 if (qp->resp_depth) {
 721                         qp_context->params2 |=
 722                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE ?
 723                                             MTHCA_QP_BIT_RWE : 0);
 724                         qp_context->params2 |=
 725                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_READ ?
 726                                             MTHCA_QP_BIT_RRE : 0);
 727                         qp_context->params2 |=
 728                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC ?
 729                                             MTHCA_QP_BIT_RAE : 0);
 730                 }
 731
 732                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 733                                                         MTHCA_QP_OPTPAR_RRE |
 734                                                         MTHCA_QP_OPTPAR_RAE);
 735
 736                 qp->atomic_rd_en = attr->qp_access_flags;
 737         }
 738
 739         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 740                 u8 rra_max;
 741
 742                 if (qp->resp_depth && !attr->max_dest_rd_atomic) {
 743                         /*
 744                          * Lowering our responder resources to zero.
 745                          * Turn off RDMA/atomics as responder.
 746                          * (RWE/RRE/RAE in params2 already zero)
 747                          */
 748                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 749                                                                 MTHCA_QP_OPTPAR_RRE |
 750                                                                 MTHCA_QP_OPTPAR_RAE);
 751                 }
 752
 753                 if (!qp->resp_depth && attr->max_dest_rd_atomic) {
 754                         /*
 755                          * Increasing our responder resources from
 756                          * zero.  Turn on RDMA/atomics as appropriate.
 757                          */
 758                         qp_context->params2 |=
 759                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_WRITE ?
 760                                             MTHCA_QP_BIT_RWE : 0);
 761                         qp_context->params2 |=
 762                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_READ ?
 763                                             MTHCA_QP_BIT_RRE : 0);
 764                         qp_context->params2 |=
 765                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_ATOMIC ?
 766                                             MTHCA_QP_BIT_RAE : 0);
 767
 768                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 769                                                                 MTHCA_QP_OPTPAR_RRE |
 770                                                                 MTHCA_QP_OPTPAR_RAE);
 771                 }
 772
 773                 for (rra_max = 0;
 774                      1 << rra_max < attr->max_dest_rd_atomic &&
 775                              rra_max < dev->qp_table.rdb_shift;
 776                      ++rra_max)
 777                         ; /* nothing */
 778
 779                 qp_context->params2      |= cpu_to_be32(rra_max << 21);
 780                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 781
 782                 qp->resp_depth = attr->max_dest_rd_atomic;
 783         }
 784
 785         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 786
 787         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 788                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 789                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 790         }
 791         if (attr_mask & IB_QP_RQ_PSN)
 792                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 793
 794         qp_context->ra_buff_indx =
 795                 cpu_to_be32(dev->qp_table.rdb_base +
 796                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 797                              dev->qp_table.rdb_shift));
 798
 799         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 800
 801         if (mthca_is_memfree(dev))
 802                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 803
 804         if (attr_mask & IB_QP_QKEY) {
 805                 qp_context->qkey = cpu_to_be32(attr->qkey);
 806                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 807         }
 808
 809         err = mthca_MODIFY_QP(dev, state_table[cur_state][new_state].trans,
 810                               qp->qpn, 0, mailbox, 0, &status);
 811         if (status) {
 812                 mthca_warn(dev, "modify QP %d returned status %02x.\n",
 813                            state_table[cur_state][new_state].trans, status);
 814                 err = -EINVAL;
 815         }
 816
 817         if (!err)
 818                 qp->state = new_state;
 819
 820         mthca_free_mailbox(dev, mailbox);
 821
 822         if (is_sqp(dev, qp))
 823                 store_attrs(to_msqp(qp), attr, attr_mask);
 824
 825         /*
 826          * If we are moving QP0 to RTR, bring the IB link up; if we
 827          * are moving QP0 to RESET or ERROR, bring the link back down.
 828          */
 829         if (is_qp0(dev, qp)) {
 830                 if (cur_state != IB_QPS_RTR &&
 831                     new_state == IB_QPS_RTR)
 832                         init_port(dev, to_msqp(qp)->port);
 833
 834                 if (cur_state != IB_QPS_RESET &&
 835                     cur_state != IB_QPS_ERR &&
 836                     (new_state == IB_QPS_RESET ||
 837                      new_state == IB_QPS_ERR))
 838                         mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status);
 839         }
 840
 841         return err;
 842 }
 843
 844 /*
 845  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 846  * rq.max_gs and sq.max_gs must all be assigned.
 847  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 848  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 849  * queue)
 850  */
 851 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 852                                struct mthca_pd *pd,
 853                                struct mthca_qp *qp)
 854 {
 855         int size;
 856         int err = -ENOMEM;
 857
 858         size = sizeof (struct mthca_next_seg) +
 859                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 860
 861         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 862              qp->rq.wqe_shift++)
 863                 ; /* nothing */
 864
 865         size = sizeof (struct mthca_next_seg) +
 866                 qp->sq.max_gs * sizeof (struct mthca_data_seg);
 867         switch (qp->transport) {
 868         case MLX:
 869                 size += 2 * sizeof (struct mthca_data_seg);
 870                 break;
 871         case UD:
 872                 if (mthca_is_memfree(dev))
 873                         size += sizeof (struct mthca_arbel_ud_seg);
 874                 else
 875                         size += sizeof (struct mthca_tavor_ud_seg);
 876                 break;
 877         default:
 878                 /* bind seg is as big as atomic + raddr segs */
 879                 size += sizeof (struct mthca_bind_seg);
 880         }
 881
 882         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
 883              qp->sq.wqe_shift++)
 884                 ; /* nothing */
 885
 886         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
 887                                     1 << qp->sq.wqe_shift);
 888
 889         /*
 890          * If this is a userspace QP, we don't actually have to
 891          * allocate anything.  All we need is to calculate the WQE
 892          * sizes and the send_wqe_offset, so we're done now.
 893          */
 894         if (pd->ibpd.uobject)
 895                 return 0;
 896
 897         size = PAGE_ALIGN(qp->send_wqe_offset +
 898                           (qp->sq.max << qp->sq.wqe_shift));
 899
 900         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
 901                            GFP_KERNEL);
 902         if (!qp->wrid)
 903                 goto err_out;
 904
 905         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
 906                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
 907         if (err)
 908                 goto err_out;
 909
 910         return 0;
 911
 912 err_out:
 913         kfree(qp->wrid);
 914         return err;
 915 }
 916
 917 static void mthca_free_wqe_buf(struct mthca_dev *dev,
 918                                struct mthca_qp *qp)
 919 {
 920         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
 921                                        (qp->sq.max << qp->sq.wqe_shift)),
 922                        &qp->queue, qp->is_direct, &qp->mr);
 923         kfree(qp->wrid);
 924 }
 925
 926 static int mthca_map_memfree(struct mthca_dev *dev,
 927                              struct mthca_qp *qp)
 928 {
 929         int ret;
 930
 931         if (mthca_is_memfree(dev)) {
 932                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
 933                 if (ret)
 934                         return ret;
 935
 936                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
 937                 if (ret)
 938                         goto err_qpc;
 939
 940                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
 941                                       qp->qpn << dev->qp_table.rdb_shift);
 942                 if (ret)
 943                         goto err_eqpc;
 944
 945         }
 946
 947         return 0;
 948
 949 err_eqpc:
 950         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
 951
 952 err_qpc:
 953         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
 954
 955         return ret;
 956 }
 957
 958 static void mthca_unmap_memfree(struct mthca_dev *dev,
 959                                 struct mthca_qp *qp)
 960 {
 961         mthca_table_put(dev, dev->qp_table.rdb_table,
 962                         qp->qpn << dev->qp_table.rdb_shift);
 963         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
 964         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
 965 }
 966
 967 static int mthca_alloc_memfree(struct mthca_dev *dev,
 968                                struct mthca_qp *qp)
 969 {
 970         int ret = 0;
 971
 972         if (mthca_is_memfree(dev)) {
 973                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
 974                                                  qp->qpn, &qp->rq.db);
 975                 if (qp->rq.db_index < 0)
 976                         return ret;
 977
 978                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
 979                                                  qp->qpn, &qp->sq.db);
 980                 if (qp->sq.db_index < 0)
 981                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
 982         }
 983
 984         return ret;
 985 }
 986
 987 static void mthca_free_memfree(struct mthca_dev *dev,
 988                                struct mthca_qp *qp)
 989 {
 990         if (mthca_is_memfree(dev)) {
 991                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
 992                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
 993         }
 994 }
 995
 996 static void mthca_wq_init(struct mthca_wq* wq)
 997 {
 998         spin_lock_init(&wq->lock);
 999         wq->next_ind  = 0;
1000         wq->last_comp = wq->max - 1;
1001         wq->head      = 0;
1002         wq->tail      = 0;
1003         wq->last      = NULL;
1004 }
1005
1006 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1007                                  struct mthca_pd *pd,
1008                                  struct mthca_cq *send_cq,
1009                                  struct mthca_cq *recv_cq,
1010                                  enum ib_sig_type send_policy,
1011                                  struct mthca_qp *qp)
1012 {
1013         int ret;
1014         int i;
1015
1016         atomic_set(&qp->refcount, 1);
1017         qp->state        = IB_QPS_RESET;
1018         qp->atomic_rd_en = 0;
1019         qp->resp_depth   = 0;
1020         qp->sq_policy    = send_policy;
1021         mthca_wq_init(&qp->sq);
1022         mthca_wq_init(&qp->rq);
1023
1024         ret = mthca_map_memfree(dev, qp);
1025         if (ret)
1026                 return ret;
1027
1028         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1029         if (ret) {
1030                 mthca_unmap_memfree(dev, qp);
1031                 return ret;
1032         }
1033
1034         /*
1035          * If this is a userspace QP, we're done now.  The doorbells
1036          * will be allocated and buffers will be initialized in
1037          * userspace.
1038          */
1039         if (pd->ibpd.uobject)
1040                 return 0;
1041
1042         ret = mthca_alloc_memfree(dev, qp);
1043         if (ret) {
1044                 mthca_free_wqe_buf(dev, qp);
1045                 mthca_unmap_memfree(dev, qp);
1046                 return ret;
1047         }
1048
1049         if (mthca_is_memfree(dev)) {
1050                 struct mthca_next_seg *next;
1051                 struct mthca_data_seg *scatter;
1052                 int size = (sizeof (struct mthca_next_seg) +
1053                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1054
1055                 for (i = 0; i < qp->rq.max; ++i) {
1056                         next = get_recv_wqe(qp, i);
1057                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1058                                                    qp->rq.wqe_shift);
1059                         next->ee_nds = cpu_to_be32(size);
1060
1061                         for (scatter = (void *) (next + 1);
1062                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1063                              ++scatter)
1064                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1065                 }
1066
1067                 for (i = 0; i < qp->sq.max; ++i) {
1068                         next = get_send_wqe(qp, i);
1069                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1070                                                     qp->sq.wqe_shift) +
1071                                                    qp->send_wqe_offset);
1072                 }
1073         }
1074
1075         return 0;
1076 }
1077
1078 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1079                              struct mthca_qp *qp)
1080 {
1081         /* Sanity check QP size before proceeding */
1082         if (cap->max_send_wr  > 65536 || cap->max_recv_wr  > 65536 ||
1083             cap->max_send_sge > 64    || cap->max_recv_sge > 64)
1084                 return -EINVAL;
1085
1086         if (mthca_is_memfree(dev)) {
1087                 qp->rq.max = cap->max_recv_wr ?
1088                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1089                 qp->sq.max = cap->max_send_wr ?
1090                         roundup_pow_of_two(cap->max_send_wr) : 0;
1091         } else {
1092                 qp->rq.max = cap->max_recv_wr;
1093                 qp->sq.max = cap->max_send_wr;
1094         }
1095
1096         qp->rq.max_gs = cap->max_recv_sge;
1097         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1098                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1099                                     MTHCA_INLINE_CHUNK_SIZE) /
1100                               sizeof (struct mthca_data_seg));
1101
1102         /*
1103          * For MLX transport we need 2 extra S/G entries:
1104          * one for the header and one for the checksum at the end
1105          */
1106         if ((qp->transport == MLX && qp->sq.max_gs + 2 > dev->limits.max_sg) ||
1107             qp->sq.max_gs > dev->limits.max_sg || qp->rq.max_gs > dev->limits.max_sg)
1108                 return -EINVAL;
1109
1110         return 0;
1111 }
1112
1113 int mthca_alloc_qp(struct mthca_dev *dev,
1114                    struct mthca_pd *pd,
1115                    struct mthca_cq *send_cq,
1116                    struct mthca_cq *recv_cq,
1117                    enum ib_qp_type type,
1118                    enum ib_sig_type send_policy,
1119                    struct ib_qp_cap *cap,
1120                    struct mthca_qp *qp)
1121 {
1122         int err;
1123
1124         err = mthca_set_qp_size(dev, cap, qp);
1125         if (err)
1126                 return err;
1127
1128         switch (type) {
1129         case IB_QPT_RC: qp->transport = RC; break;
1130         case IB_QPT_UC: qp->transport = UC; break;
1131         case IB_QPT_UD: qp->transport = UD; break;
1132         default: return -EINVAL;
1133         }
1134
1135         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1136         if (qp->qpn == -1)
1137                 return -ENOMEM;
1138
1139         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1140                                     send_policy, qp);
1141         if (err) {
1142                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1143                 return err;
1144         }
1145
1146         spin_lock_irq(&dev->qp_table.lock);
1147         mthca_array_set(&dev->qp_table.qp,
1148                         qp->qpn & (dev->limits.num_qps - 1), qp);
1149         spin_unlock_irq(&dev->qp_table.lock);
1150
1151         return 0;
1152 }
1153
1154 int mthca_alloc_sqp(struct mthca_dev *dev,
1155                     struct mthca_pd *pd,
1156                     struct mthca_cq *send_cq,
1157                     struct mthca_cq *recv_cq,
1158                     enum ib_sig_type send_policy,
1159                     struct ib_qp_cap *cap,
1160                     int qpn,
1161                     int port,
1162                     struct mthca_sqp *sqp)
1163 {
1164         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1165         int err;
1166
1167         err = mthca_set_qp_size(dev, cap, &sqp->qp);
1168         if (err)
1169                 return err;
1170
1171         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1172         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1173                                              &sqp->header_dma, GFP_KERNEL);
1174         if (!sqp->header_buf)
1175                 return -ENOMEM;
1176
1177         spin_lock_irq(&dev->qp_table.lock);
1178         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1179                 err = -EBUSY;
1180         else
1181                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1182         spin_unlock_irq(&dev->qp_table.lock);
1183
1184         if (err)
1185                 goto err_out;
1186
1187         sqp->port = port;
1188         sqp->qp.qpn       = mqpn;
1189         sqp->qp.transport = MLX;
1190
1191         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1192                                     send_policy, &sqp->qp);
1193         if (err)
1194                 goto err_out_free;
1195
1196         atomic_inc(&pd->sqp_count);
1197
1198         return 0;
1199
1200  err_out_free:
1201         /*
1202          * Lock CQs here, so that CQ polling code can do QP lookup
1203          * without taking a lock.
1204          */
1205         spin_lock_irq(&send_cq->lock);
1206         if (send_cq != recv_cq)
1207                 spin_lock(&recv_cq->lock);
1208
1209         spin_lock(&dev->qp_table.lock);
1210         mthca_array_clear(&dev->qp_table.qp, mqpn);
1211         spin_unlock(&dev->qp_table.lock);
1212
1213         if (send_cq != recv_cq)
1214                 spin_unlock(&recv_cq->lock);
1215         spin_unlock_irq(&send_cq->lock);
1216
1217  err_out:
1218         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1219                           sqp->header_buf, sqp->header_dma);
1220
1221         return err;
1222 }
1223
1224 void mthca_free_qp(struct mthca_dev *dev,
1225                    struct mthca_qp *qp)
1226 {
1227         u8 status;
1228         struct mthca_cq *send_cq;
1229         struct mthca_cq *recv_cq;
1230
1231         send_cq = to_mcq(qp->ibqp.send_cq);
1232         recv_cq = to_mcq(qp->ibqp.recv_cq);
1233
1234         /*
1235          * Lock CQs here, so that CQ polling code can do QP lookup
1236          * without taking a lock.
1237          */
1238         spin_lock_irq(&send_cq->lock);
1239         if (send_cq != recv_cq)
1240                 spin_lock(&recv_cq->lock);
1241
1242         spin_lock(&dev->qp_table.lock);
1243         mthca_array_clear(&dev->qp_table.qp,
1244                           qp->qpn & (dev->limits.num_qps - 1));
1245         spin_unlock(&dev->qp_table.lock);
1246
1247         if (send_cq != recv_cq)
1248                 spin_unlock(&recv_cq->lock);
1249         spin_unlock_irq(&send_cq->lock);
1250
1251         atomic_dec(&qp->refcount);
1252         wait_event(qp->wait, !atomic_read(&qp->refcount));
1253
1254         if (qp->state != IB_QPS_RESET)
1255                 mthca_MODIFY_QP(dev, MTHCA_TRANS_ANY2RST, qp->qpn, 0, NULL, 0, &status);
1256
1257         /*
1258          * If this is a userspace QP, the buffers, MR, CQs and so on
1259          * will be cleaned up in userspace, so all we have to do is
1260          * unref the mem-free tables and free the QPN in our table.
1261          */
1262         if (!qp->ibqp.uobject) {
1263                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn);
1264                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1265                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn);
1266
1267                 mthca_free_memfree(dev, qp);
1268                 mthca_free_wqe_buf(dev, qp);
1269         }
1270
1271         mthca_unmap_memfree(dev, qp);
1272
1273         if (is_sqp(dev, qp)) {
1274                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1275                 dma_free_coherent(&dev->pdev->dev,
1276                                   to_msqp(qp)->header_buf_size,
1277                                   to_msqp(qp)->header_buf,
1278                                   to_msqp(qp)->header_dma);
1279         } else
1280                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1281 }
1282
1283 /* Create UD header for an MLX send and build a data segment for it */
1284 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1285                             int ind, struct ib_send_wr *wr,
1286                             struct mthca_mlx_seg *mlx,
1287                             struct mthca_data_seg *data)
1288 {
1289         int header_size;
1290         int err;
1291         u16 pkey;
1292
1293         ib_ud_header_init(256, /* assume a MAD */
1294                           sqp->ud_header.grh_present,
1295                           &sqp->ud_header);
1296
1297         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1298         if (err)
1299                 return err;
1300         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1301         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1302                                   (sqp->ud_header.lrh.destination_lid ==
1303                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1304                                   (sqp->ud_header.lrh.service_level << 8));
1305         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1306         mlx->vcrc = 0;
1307
1308         switch (wr->opcode) {
1309         case IB_WR_SEND:
1310                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1311                 sqp->ud_header.immediate_present = 0;
1312                 break;
1313         case IB_WR_SEND_WITH_IMM:
1314                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1315                 sqp->ud_header.immediate_present = 1;
1316                 sqp->ud_header.immediate_data = wr->imm_data;
1317                 break;
1318         default:
1319                 return -EINVAL;
1320         }
1321
1322         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1323         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1324                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1325         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1326         if (!sqp->qp.ibqp.qp_num)
1327                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1328                                    sqp->pkey_index, &pkey);
1329         else
1330                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1331                                    wr->wr.ud.pkey_index, &pkey);
1332         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1333         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1334         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1335         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1336                                                sqp->qkey : wr->wr.ud.remote_qkey);
1337         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1338
1339         header_size = ib_ud_header_pack(&sqp->ud_header,
1340                                         sqp->header_buf +
1341                                         ind * MTHCA_UD_HEADER_SIZE);
1342
1343         data->byte_count = cpu_to_be32(header_size);
1344         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1345         data->addr       = cpu_to_be64(sqp->header_dma +
1346                                        ind * MTHCA_UD_HEADER_SIZE);
1347
1348         return 0;
1349 }
1350
1351 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1352                                     struct ib_cq *ib_cq)
1353 {
1354         unsigned cur;
1355         struct mthca_cq *cq;
1356
1357         cur = wq->head - wq->tail;
1358         if (likely(cur + nreq < wq->max))
1359                 return 0;
1360
1361         cq = to_mcq(ib_cq);
1362         spin_lock(&cq->lock);
1363         cur = wq->head - wq->tail;
1364         spin_unlock(&cq->lock);
1365
1366         return cur + nreq >= wq->max;
1367 }
1368
1369 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1370                           struct ib_send_wr **bad_wr)
1371 {
1372         struct mthca_dev *dev = to_mdev(ibqp->device);
1373         struct mthca_qp *qp = to_mqp(ibqp);
1374         void *wqe;
1375         void *prev_wqe;
1376         unsigned long flags;
1377         int err = 0;
1378         int nreq;
1379         int i;
1380         int size;
1381         int size0 = 0;
1382         u32 f0 = 0;
1383         int ind;
1384         u8 op0 = 0;
1385
1386         spin_lock_irqsave(&qp->sq.lock, flags);
1387
1388         /* XXX check that state is OK to post send */
1389
1390         ind = qp->sq.next_ind;
1391
1392         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1393                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1394                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1395                                         " %d max, %d nreq)\n", qp->qpn,
1396                                         qp->sq.head, qp->sq.tail,
1397                                         qp->sq.max, nreq);
1398                         err = -ENOMEM;
1399                         *bad_wr = wr;
1400                         goto out;
1401                 }
1402
1403                 wqe = get_send_wqe(qp, ind);
1404                 prev_wqe = qp->sq.last;
1405                 qp->sq.last = wqe;
1406
1407                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1408                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1409                 ((struct mthca_next_seg *) wqe)->flags =
1410                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1411                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1412                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1413                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1414                         cpu_to_be32(1);
1415                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1416                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1417                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1418
1419                 wqe += sizeof (struct mthca_next_seg);
1420                 size = sizeof (struct mthca_next_seg) / 16;
1421
1422                 switch (qp->transport) {
1423                 case RC:
1424                         switch (wr->opcode) {
1425                         case IB_WR_ATOMIC_CMP_AND_SWP:
1426                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1427                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1428                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1429                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1430                                         cpu_to_be32(wr->wr.atomic.rkey);
1431                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1432
1433                                 wqe += sizeof (struct mthca_raddr_seg);
1434
1435                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1436                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1437                                                 cpu_to_be64(wr->wr.atomic.swap);
1438                                         ((struct mthca_atomic_seg *) wqe)->compare =
1439                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1440                                 } else {
1441                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1442                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1443                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1444                                 }
1445
1446                                 wqe += sizeof (struct mthca_atomic_seg);
1447                                 size += sizeof (struct mthca_raddr_seg) / 16 +
1448                                         sizeof (struct mthca_atomic_seg);
1449                                 break;
1450
1451                         case IB_WR_RDMA_WRITE:
1452                         case IB_WR_RDMA_WRITE_WITH_IMM:
1453                         case IB_WR_RDMA_READ:
1454                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1455                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1456                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1457                                         cpu_to_be32(wr->wr.rdma.rkey);
1458                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1459                                 wqe += sizeof (struct mthca_raddr_seg);
1460                                 size += sizeof (struct mthca_raddr_seg) / 16;
1461                                 break;
1462
1463                         default:
1464                                 /* No extra segments required for sends */
1465                                 break;
1466                         }
1467
1468                         break;
1469
1470                 case UC:
1471                         switch (wr->opcode) {
1472                         case IB_WR_RDMA_WRITE:
1473                         case IB_WR_RDMA_WRITE_WITH_IMM:
1474                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1475                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1476                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1477                                         cpu_to_be32(wr->wr.rdma.rkey);
1478                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1479                                 wqe += sizeof (struct mthca_raddr_seg);
1480                                 size += sizeof (struct mthca_raddr_seg) / 16;
1481                                 break;
1482
1483                         default:
1484                                 /* No extra segments required for sends */
1485                                 break;
1486                         }
1487
1488                         break;
1489
1490                 case UD:
1491                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1492                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1493                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1494                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1495                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1496                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1497                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1498                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1499
1500                         wqe += sizeof (struct mthca_tavor_ud_seg);
1501                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1502                         break;
1503
1504                 case MLX:
1505                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1506                                                wqe - sizeof (struct mthca_next_seg),
1507                                                wqe);
1508                         if (err) {
1509                                 *bad_wr = wr;
1510                                 goto out;
1511                         }
1512                         wqe += sizeof (struct mthca_data_seg);
1513                         size += sizeof (struct mthca_data_seg) / 16;
1514                         break;
1515                 }
1516
1517                 if (wr->num_sge > qp->sq.max_gs) {
1518                         mthca_err(dev, "too many gathers\n");
1519                         err = -EINVAL;
1520                         *bad_wr = wr;
1521                         goto out;
1522                 }
1523
1524                 for (i = 0; i < wr->num_sge; ++i) {
1525                         ((struct mthca_data_seg *) wqe)->byte_count =
1526                                 cpu_to_be32(wr->sg_list[i].length);
1527                         ((struct mthca_data_seg *) wqe)->lkey =
1528                                 cpu_to_be32(wr->sg_list[i].lkey);
1529                         ((struct mthca_data_seg *) wqe)->addr =
1530                                 cpu_to_be64(wr->sg_list[i].addr);
1531                         wqe += sizeof (struct mthca_data_seg);
1532                         size += sizeof (struct mthca_data_seg) / 16;
1533                 }
1534
1535                 /* Add one more inline data segment for ICRC */
1536                 if (qp->transport == MLX) {
1537                         ((struct mthca_data_seg *) wqe)->byte_count =
1538                                 cpu_to_be32((1 << 31) | 4);
1539                         ((u32 *) wqe)[1] = 0;
1540                         wqe += sizeof (struct mthca_data_seg);
1541                         size += sizeof (struct mthca_data_seg) / 16;
1542                 }
1543
1544                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1545
1546                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1547                         mthca_err(dev, "opcode invalid\n");
1548                         err = -EINVAL;
1549                         *bad_wr = wr;
1550                         goto out;
1551                 }
1552
1553                 if (prev_wqe) {
1554                         ((struct mthca_next_seg *) prev_wqe)->nda_op =
1555                                 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1556                                              qp->send_wqe_offset) |
1557                                             mthca_opcode[wr->opcode]);
1558                         wmb();
1559                         ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1560                                 cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size);
1561                 }
1562
1563                 if (!size0) {
1564                         size0 = size;
1565                         op0   = mthca_opcode[wr->opcode];
1566                 }
1567
1568                 ++ind;
1569                 if (unlikely(ind >= qp->sq.max))
1570                         ind -= qp->sq.max;
1571         }
1572
1573 out:
1574         if (likely(nreq)) {
1575                 __be32 doorbell[2];
1576
1577                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1578                                            qp->send_wqe_offset) | f0 | op0);
1579                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1580
1581                 wmb();
1582
1583                 mthca_write64(doorbell,
1584                               dev->kar + MTHCA_SEND_DOORBELL,
1585                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1586         }
1587
1588         qp->sq.next_ind = ind;
1589         qp->sq.head    += nreq;
1590
1591         spin_unlock_irqrestore(&qp->sq.lock, flags);
1592         return err;
1593 }
1594
1595 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1596                              struct ib_recv_wr **bad_wr)
1597 {
1598         struct mthca_dev *dev = to_mdev(ibqp->device);
1599         struct mthca_qp *qp = to_mqp(ibqp);
1600         unsigned long flags;
1601         int err = 0;
1602         int nreq;
1603         int i;
1604         int size;
1605         int size0 = 0;
1606         int ind;
1607         void *wqe;
1608         void *prev_wqe;
1609
1610         spin_lock_irqsave(&qp->rq.lock, flags);
1611
1612         /* XXX check that state is OK to post receive */
1613
1614         ind = qp->rq.next_ind;
1615
1616         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1617                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1618                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1619                                         " %d max, %d nreq)\n", qp->qpn,
1620                                         qp->rq.head, qp->rq.tail,
1621                                         qp->rq.max, nreq);
1622                         err = -ENOMEM;
1623                         *bad_wr = wr;
1624                         goto out;
1625                 }
1626
1627                 wqe = get_recv_wqe(qp, ind);
1628                 prev_wqe = qp->rq.last;
1629                 qp->rq.last = wqe;
1630
1631                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1632                 ((struct mthca_next_seg *) wqe)->ee_nds =
1633                         cpu_to_be32(MTHCA_NEXT_DBD);
1634                 ((struct mthca_next_seg *) wqe)->flags = 0;
1635
1636                 wqe += sizeof (struct mthca_next_seg);
1637                 size = sizeof (struct mthca_next_seg) / 16;
1638
1639                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1640                         err = -EINVAL;
1641                         *bad_wr = wr;
1642                         goto out;
1643                 }
1644
1645                 for (i = 0; i < wr->num_sge; ++i) {
1646                         ((struct mthca_data_seg *) wqe)->byte_count =
1647                                 cpu_to_be32(wr->sg_list[i].length);
1648                         ((struct mthca_data_seg *) wqe)->lkey =
1649                                 cpu_to_be32(wr->sg_list[i].lkey);
1650                         ((struct mthca_data_seg *) wqe)->addr =
1651                                 cpu_to_be64(wr->sg_list[i].addr);
1652                         wqe += sizeof (struct mthca_data_seg);
1653                         size += sizeof (struct mthca_data_seg) / 16;
1654                 }
1655
1656                 qp->wrid[ind] = wr->wr_id;
1657
1658                 if (likely(prev_wqe)) {
1659                         ((struct mthca_next_seg *) prev_wqe)->nda_op =
1660                                 cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1661                         wmb();
1662                         ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1663                                 cpu_to_be32(MTHCA_NEXT_DBD | size);
1664                 }
1665
1666                 if (!size0)
1667                         size0 = size;
1668
1669                 ++ind;
1670                 if (unlikely(ind >= qp->rq.max))
1671                         ind -= qp->rq.max;
1672         }
1673
1674 out:
1675         if (likely(nreq)) {
1676                 __be32 doorbell[2];
1677
1678                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1679                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1680
1681                 wmb();
1682
1683                 mthca_write64(doorbell,
1684                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1685                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1686         }
1687
1688         qp->rq.next_ind = ind;
1689         qp->rq.head    += nreq;
1690
1691         spin_unlock_irqrestore(&qp->rq.lock, flags);
1692         return err;
1693 }
1694
1695 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1696                           struct ib_send_wr **bad_wr)
1697 {
1698         struct mthca_dev *dev = to_mdev(ibqp->device);
1699         struct mthca_qp *qp = to_mqp(ibqp);
1700         void *wqe;
1701         void *prev_wqe;
1702         unsigned long flags;
1703         int err = 0;
1704         int nreq;
1705         int i;
1706         int size;
1707         int size0 = 0;
1708         u32 f0 = 0;
1709         int ind;
1710         u8 op0 = 0;
1711
1712         spin_lock_irqsave(&qp->sq.lock, flags);
1713
1714         /* XXX check that state is OK to post send */
1715
1716         ind = qp->sq.head & (qp->sq.max - 1);
1717
1718         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1719                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1720                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1721                                         " %d max, %d nreq)\n", qp->qpn,
1722                                         qp->sq.head, qp->sq.tail,
1723                                         qp->sq.max, nreq);
1724                         err = -ENOMEM;
1725                         *bad_wr = wr;
1726                         goto out;
1727                 }
1728
1729                 wqe = get_send_wqe(qp, ind);
1730                 prev_wqe = qp->sq.last;
1731                 qp->sq.last = wqe;
1732
1733                 ((struct mthca_next_seg *) wqe)->flags =
1734                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1735                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1736                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1737                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1738                         cpu_to_be32(1);
1739                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1740                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1741                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1742
1743                 wqe += sizeof (struct mthca_next_seg);
1744                 size = sizeof (struct mthca_next_seg) / 16;
1745
1746                 switch (qp->transport) {
1747                 case RC:
1748                         switch (wr->opcode) {
1749                         case IB_WR_ATOMIC_CMP_AND_SWP:
1750                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1751                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1752                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1753                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1754                                         cpu_to_be32(wr->wr.atomic.rkey);
1755                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1756
1757                                 wqe += sizeof (struct mthca_raddr_seg);
1758
1759                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1760                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1761                                                 cpu_to_be64(wr->wr.atomic.swap);
1762                                         ((struct mthca_atomic_seg *) wqe)->compare =
1763                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1764                                 } else {
1765                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1766                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1767                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1768                                 }
1769
1770                                 wqe += sizeof (struct mthca_atomic_seg);
1771                                 size += sizeof (struct mthca_raddr_seg) / 16 +
1772                                         sizeof (struct mthca_atomic_seg);
1773                                 break;
1774
1775                         case IB_WR_RDMA_READ:
1776                         case IB_WR_RDMA_WRITE:
1777                         case IB_WR_RDMA_WRITE_WITH_IMM:
1778                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1779                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1780                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1781                                         cpu_to_be32(wr->wr.rdma.rkey);
1782                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1783                                 wqe += sizeof (struct mthca_raddr_seg);
1784                                 size += sizeof (struct mthca_raddr_seg) / 16;
1785                                 break;
1786
1787                         default:
1788                                 /* No extra segments required for sends */
1789                                 break;
1790                         }
1791
1792                         break;
1793
1794                 case UC:
1795                         switch (wr->opcode) {
1796                         case IB_WR_RDMA_WRITE:
1797                         case IB_WR_RDMA_WRITE_WITH_IMM:
1798                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1799                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1800                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1801                                         cpu_to_be32(wr->wr.rdma.rkey);
1802                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1803                                 wqe += sizeof (struct mthca_raddr_seg);
1804                                 size += sizeof (struct mthca_raddr_seg) / 16;
1805                                 break;
1806
1807                         default:
1808                                 /* No extra segments required for sends */
1809                                 break;
1810                         }
1811
1812                         break;
1813
1814                 case UD:
1815                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1816                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1817                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1818                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1819                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1820                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1821
1822                         wqe += sizeof (struct mthca_arbel_ud_seg);
1823                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
1824                         break;
1825
1826                 case MLX:
1827                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1828                                                wqe - sizeof (struct mthca_next_seg),
1829                                                wqe);
1830                         if (err) {
1831                                 *bad_wr = wr;
1832                                 goto out;
1833                         }
1834                         wqe += sizeof (struct mthca_data_seg);
1835                         size += sizeof (struct mthca_data_seg) / 16;
1836                         break;
1837                 }
1838
1839                 if (wr->num_sge > qp->sq.max_gs) {
1840                         mthca_err(dev, "too many gathers\n");
1841                         err = -EINVAL;
1842                         *bad_wr = wr;
1843                         goto out;
1844                 }
1845
1846                 for (i = 0; i < wr->num_sge; ++i) {
1847                         ((struct mthca_data_seg *) wqe)->byte_count =
1848                                 cpu_to_be32(wr->sg_list[i].length);
1849                         ((struct mthca_data_seg *) wqe)->lkey =
1850                                 cpu_to_be32(wr->sg_list[i].lkey);
1851                         ((struct mthca_data_seg *) wqe)->addr =
1852                                 cpu_to_be64(wr->sg_list[i].addr);
1853                         wqe += sizeof (struct mthca_data_seg);
1854                         size += sizeof (struct mthca_data_seg) / 16;
1855                 }
1856
1857                 /* Add one more inline data segment for ICRC */
1858                 if (qp->transport == MLX) {
1859                         ((struct mthca_data_seg *) wqe)->byte_count =
1860                                 cpu_to_be32((1 << 31) | 4);
1861                         ((u32 *) wqe)[1] = 0;
1862                         wqe += sizeof (struct mthca_data_seg);
1863                         size += sizeof (struct mthca_data_seg) / 16;
1864                 }
1865
1866                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1867
1868                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1869                         mthca_err(dev, "opcode invalid\n");
1870                         err = -EINVAL;
1871                         *bad_wr = wr;
1872                         goto out;
1873                 }
1874
1875                 if (likely(prev_wqe)) {
1876                         ((struct mthca_next_seg *) prev_wqe)->nda_op =
1877                                 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1878                                              qp->send_wqe_offset) |
1879                                             mthca_opcode[wr->opcode]);
1880                         wmb();
1881                         ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1882                                 cpu_to_be32(MTHCA_NEXT_DBD | size);
1883                 }
1884
1885                 if (!size0) {
1886                         size0 = size;
1887                         op0   = mthca_opcode[wr->opcode];
1888                 }
1889
1890                 ++ind;
1891                 if (unlikely(ind >= qp->sq.max))
1892                         ind -= qp->sq.max;
1893         }
1894
1895 out:
1896         if (likely(nreq)) {
1897                 __be32 doorbell[2];
1898
1899                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
1900                                           ((qp->sq.head & 0xffff) << 8) |
1901                                           f0 | op0);
1902                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1903
1904                 qp->sq.head += nreq;
1905
1906                 /*
1907                  * Make sure that descriptors are written before
1908                  * doorbell record.
1909                  */
1910                 wmb();
1911                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1912
1913                 /*
1914                  * Make sure doorbell record is written before we
1915                  * write MMIO send doorbell.
1916                  */
1917                 wmb();
1918                 mthca_write64(doorbell,
1919                               dev->kar + MTHCA_SEND_DOORBELL,
1920                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1921         }
1922
1923         spin_unlock_irqrestore(&qp->sq.lock, flags);
1924         return err;
1925 }
1926
1927 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1928                              struct ib_recv_wr **bad_wr)
1929 {
1930         struct mthca_dev *dev = to_mdev(ibqp->device);
1931         struct mthca_qp *qp = to_mqp(ibqp);
1932         unsigned long flags;
1933         int err = 0;
1934         int nreq;
1935         int ind;
1936         int i;
1937         void *wqe;
1938
1939         spin_lock_irqsave(&qp->rq.lock, flags);
1940
1941         /* XXX check that state is OK to post receive */
1942
1943         ind = qp->rq.head & (qp->rq.max - 1);
1944
1945         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1946                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1947                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1948                                         " %d max, %d nreq)\n", qp->qpn,
1949                                         qp->rq.head, qp->rq.tail,
1950                                         qp->rq.max, nreq);
1951                         err = -ENOMEM;
1952                         *bad_wr = wr;
1953                         goto out;
1954                 }
1955
1956                 wqe = get_recv_wqe(qp, ind);
1957
1958                 ((struct mthca_next_seg *) wqe)->flags = 0;
1959
1960                 wqe += sizeof (struct mthca_next_seg);
1961
1962                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1963                         err = -EINVAL;
1964                         *bad_wr = wr;
1965                         goto out;
1966                 }
1967
1968                 for (i = 0; i < wr->num_sge; ++i) {
1969                         ((struct mthca_data_seg *) wqe)->byte_count =
1970                                 cpu_to_be32(wr->sg_list[i].length);
1971                         ((struct mthca_data_seg *) wqe)->lkey =
1972                                 cpu_to_be32(wr->sg_list[i].lkey);
1973                         ((struct mthca_data_seg *) wqe)->addr =
1974                                 cpu_to_be64(wr->sg_list[i].addr);
1975                         wqe += sizeof (struct mthca_data_seg);
1976                 }
1977
1978                 if (i < qp->rq.max_gs) {
1979                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
1980                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1981                         ((struct mthca_data_seg *) wqe)->addr = 0;
1982                 }
1983
1984                 qp->wrid[ind] = wr->wr_id;
1985
1986                 ++ind;
1987                 if (unlikely(ind >= qp->rq.max))
1988                         ind -= qp->rq.max;
1989         }
1990 out:
1991         if (likely(nreq)) {
1992                 qp->rq.head += nreq;
1993
1994                 /*
1995                  * Make sure that descriptors are written before
1996                  * doorbell record.
1997                  */
1998                 wmb();
1999                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2000         }
2001
2002         spin_unlock_irqrestore(&qp->rq.lock, flags);
2003         return err;
2004 }
2005
2006 int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2007                        int index, int *dbd, __be32 *new_wqe)
2008 {
2009         struct mthca_next_seg *next;
2010
2011         if (is_send)
2012                 next = get_send_wqe(qp, index);
2013         else
2014                 next = get_recv_wqe(qp, index);
2015
2016         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2017         if (next->ee_nds & cpu_to_be32(0x3f))
2018                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2019                         (next->ee_nds & cpu_to_be32(0x3f));
2020         else
2021                 *new_wqe = 0;
2022
2023         return 0;
2024 }
2025
2026 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2027 {
2028         int err;
2029         u8 status;
2030         int i;
2031
2032         spin_lock_init(&dev->qp_table.lock);
2033
2034         /*
2035          * We reserve 2 extra QPs per port for the special QPs.  The
2036          * special QP for port 1 has to be even, so round up.
2037          */
2038         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2039         err = mthca_alloc_init(&dev->qp_table.alloc,
2040                                dev->limits.num_qps,
2041                                (1 << 24) - 1,
2042                                dev->qp_table.sqp_start +
2043                                MTHCA_MAX_PORTS * 2);
2044         if (err)
2045                 return err;
2046
2047         err = mthca_array_init(&dev->qp_table.qp,
2048                                dev->limits.num_qps);
2049         if (err) {
2050                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2051                 return err;
2052         }
2053
2054         for (i = 0; i < 2; ++i) {
2055                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2056                                             dev->qp_table.sqp_start + i * 2,
2057                                             &status);
2058                 if (err)
2059                         goto err_out;
2060                 if (status) {
2061                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2062                                    "status %02x, aborting.\n",
2063                                    status);
2064                         err = -EINVAL;
2065                         goto err_out;
2066                 }
2067         }
2068         return 0;
2069
2070  err_out:
2071         for (i = 0; i < 2; ++i)
2072                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2073
2074         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2075         mthca_alloc_cleanup(&dev->qp_table.alloc);
2076
2077         return err;
2078 }
2079
2080 void __devexit mthca_cleanup_qp_table(struct mthca_dev *dev)
2081 {
2082         int i;
2083         u8 status;
2084
2085         for (i = 0; i < 2; ++i)
2086                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2087
2088         mthca_alloc_cleanup(&dev->qp_table.alloc);
2089 }