drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/string.h>
  39 #include <linux/slab.h>
  40
  41 #include <asm/io.h>
  42
  43 #include <rdma/ib_verbs.h>
  44 #include <rdma/ib_cache.h>
  45 #include <rdma/ib_pack.h>
  46
  47 #include "mthca_dev.h"
  48 #include "mthca_cmd.h"
  49 #include "mthca_memfree.h"
  50 #include "mthca_wqe.h"
  51
  52 enum {
  53         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  54         MTHCA_ACK_REQ_FREQ       = 10,
  55         MTHCA_FLIGHT_LIMIT       = 9,
  56         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  57         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  58         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  59 };
  60
  61 enum {
  62         MTHCA_QP_STATE_RST  = 0,
  63         MTHCA_QP_STATE_INIT = 1,
  64         MTHCA_QP_STATE_RTR  = 2,
  65         MTHCA_QP_STATE_RTS  = 3,
  66         MTHCA_QP_STATE_SQE  = 4,
  67         MTHCA_QP_STATE_SQD  = 5,
  68         MTHCA_QP_STATE_ERR  = 6,
  69         MTHCA_QP_STATE_DRAINING = 7
  70 };
  71
  72 enum {
  73         MTHCA_QP_ST_RC  = 0x0,
  74         MTHCA_QP_ST_UC  = 0x1,
  75         MTHCA_QP_ST_RD  = 0x2,
  76         MTHCA_QP_ST_UD  = 0x3,
  77         MTHCA_QP_ST_MLX = 0x7
  78 };
  79
  80 enum {
  81         MTHCA_QP_PM_MIGRATED = 0x3,
  82         MTHCA_QP_PM_ARMED    = 0x0,
  83         MTHCA_QP_PM_REARM    = 0x1
  84 };
  85
  86 enum {
  87         /* qp_context flags */
  88         MTHCA_QP_BIT_DE  = 1 <<  8,
  89         /* params1 */
  90         MTHCA_QP_BIT_SRE = 1 << 15,
  91         MTHCA_QP_BIT_SWE = 1 << 14,
  92         MTHCA_QP_BIT_SAE = 1 << 13,
  93         MTHCA_QP_BIT_SIC = 1 <<  4,
  94         MTHCA_QP_BIT_SSC = 1 <<  3,
  95         /* params2 */
  96         MTHCA_QP_BIT_RRE = 1 << 15,
  97         MTHCA_QP_BIT_RWE = 1 << 14,
  98         MTHCA_QP_BIT_RAE = 1 << 13,
  99         MTHCA_QP_BIT_RIC = 1 <<  4,
 100         MTHCA_QP_BIT_RSC = 1 <<  3
 101 };
 102
 103 enum {
 104         MTHCA_SEND_DOORBELL_FENCE = 1 << 5
 105 };
 106
 107 struct mthca_qp_path {
 108         __be32 port_pkey;
 109         u8     rnr_retry;
 110         u8     g_mylmc;
 111         __be16 rlid;
 112         u8     ackto;
 113         u8     mgid_index;
 114         u8     static_rate;
 115         u8     hop_limit;
 116         __be32 sl_tclass_flowlabel;
 117         u8     rgid[16];
 118 } __attribute__((packed));
 119
 120 struct mthca_qp_context {
 121         __be32 flags;
 122         __be32 tavor_sched_queue; /* Reserved on Arbel */
 123         u8     mtu_msgmax;
 124         u8     rq_size_stride;  /* Reserved on Tavor */
 125         u8     sq_size_stride;  /* Reserved on Tavor */
 126         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 127         __be32 usr_page;
 128         __be32 local_qpn;
 129         __be32 remote_qpn;
 130         u32    reserved1[2];
 131         struct mthca_qp_path pri_path;
 132         struct mthca_qp_path alt_path;
 133         __be32 rdd;
 134         __be32 pd;
 135         __be32 wqe_base;
 136         __be32 wqe_lkey;
 137         __be32 params1;
 138         __be32 reserved2;
 139         __be32 next_send_psn;
 140         __be32 cqn_snd;
 141         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 142         __be32 snd_db_index;    /* (debugging only entries) */
 143         __be32 last_acked_psn;
 144         __be32 ssn;
 145         __be32 params2;
 146         __be32 rnr_nextrecvpsn;
 147         __be32 ra_buff_indx;
 148         __be32 cqn_rcv;
 149         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 150         __be32 rcv_db_index;    /* (debugging only entries) */
 151         __be32 qkey;
 152         __be32 srqn;
 153         __be32 rmsn;
 154         __be16 rq_wqe_counter;  /* reserved on Tavor */
 155         __be16 sq_wqe_counter;  /* reserved on Tavor */
 156         u32    reserved3[18];
 157 } __attribute__((packed));
 158
 159 struct mthca_qp_param {
 160         __be32 opt_param_mask;
 161         u32    reserved1;
 162         struct mthca_qp_context context;
 163         u32    reserved2[62];
 164 } __attribute__((packed));
 165
 166 enum {
 167         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 168         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 169         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 170         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 171         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 172         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 173         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 174         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 175         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 176         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 177         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 178         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 179         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 180         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 181         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 182         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 183         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 184 };
 185
 186 static const u8 mthca_opcode[] = {
 187         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 188         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 189         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 190         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 191         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 192         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 193         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 194 };
 195
 196 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 197 {
 198         return qp->qpn >= dev->qp_table.sqp_start &&
 199                 qp->qpn <= dev->qp_table.sqp_start + 3;
 200 }
 201
 202 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 203 {
 204         return qp->qpn >= dev->qp_table.sqp_start &&
 205                 qp->qpn <= dev->qp_table.sqp_start + 1;
 206 }
 207
 208 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 209 {
 210         if (qp->is_direct)
 211                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 212         else
 213                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 214                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 215 }
 216
 217 static void *get_send_wqe(struct mthca_qp *qp, int n)
 218 {
 219         if (qp->is_direct)
 220                 return qp->queue.direct.buf + qp->send_wqe_offset +
 221                         (n << qp->sq.wqe_shift);
 222         else
 223                 return qp->queue.page_list[(qp->send_wqe_offset +
 224                                             (n << qp->sq.wqe_shift)) >>
 225                                            PAGE_SHIFT].buf +
 226                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 227                          (PAGE_SIZE - 1));
 228 }
 229
 230 static void mthca_wq_reset(struct mthca_wq *wq)
 231 {
 232         wq->next_ind  = 0;
 233         wq->last_comp = wq->max - 1;
 234         wq->head      = 0;
 235         wq->tail      = 0;
 236 }
 237
 238 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 239                     enum ib_event_type event_type)
 240 {
 241         struct mthca_qp *qp;
 242         struct ib_event event;
 243
 244         spin_lock(&dev->qp_table.lock);
 245         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 246         if (qp)
 247                 ++qp->refcount;
 248         spin_unlock(&dev->qp_table.lock);
 249
 250         if (!qp) {
 251                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 252                 return;
 253         }
 254
 255         if (event_type == IB_EVENT_PATH_MIG)
 256                 qp->port = qp->alt_port;
 257
 258         event.device      = &dev->ib_dev;
 259         event.event       = event_type;
 260         event.element.qp  = &qp->ibqp;
 261         if (qp->ibqp.event_handler)
 262                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 263
 264         spin_lock(&dev->qp_table.lock);
 265         if (!--qp->refcount)
 266                 wake_up(&qp->wait);
 267         spin_unlock(&dev->qp_table.lock);
 268 }
 269
 270 static int to_mthca_state(enum ib_qp_state ib_state)
 271 {
 272         switch (ib_state) {
 273         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 274         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 275         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 276         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 277         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 278         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 279         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 280         default:                return -1;
 281         }
 282 }
 283
 284 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 285
 286 static int to_mthca_st(int transport)
 287 {
 288         switch (transport) {
 289         case RC:  return MTHCA_QP_ST_RC;
 290         case UC:  return MTHCA_QP_ST_UC;
 291         case UD:  return MTHCA_QP_ST_UD;
 292         case RD:  return MTHCA_QP_ST_RD;
 293         case MLX: return MTHCA_QP_ST_MLX;
 294         default:  return -1;
 295         }
 296 }
 297
 298 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 299                         int attr_mask)
 300 {
 301         if (attr_mask & IB_QP_PKEY_INDEX)
 302                 sqp->pkey_index = attr->pkey_index;
 303         if (attr_mask & IB_QP_QKEY)
 304                 sqp->qkey = attr->qkey;
 305         if (attr_mask & IB_QP_SQ_PSN)
 306                 sqp->send_psn = attr->sq_psn;
 307 }
 308
 309 static void init_port(struct mthca_dev *dev, int port)
 310 {
 311         int err;
 312         u8 status;
 313         struct mthca_init_ib_param param;
 314
 315         memset(&param, 0, sizeof param);
 316
 317         param.port_width = dev->limits.port_width_cap;
 318         param.vl_cap     = dev->limits.vl_cap;
 319         param.mtu_cap    = dev->limits.mtu_cap;
 320         param.gid_cap    = dev->limits.gid_table_len;
 321         param.pkey_cap   = dev->limits.pkey_table_len;
 322
 323         err = mthca_INIT_IB(dev, &param, port, &status);
 324         if (err)
 325                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 326         if (status)
 327                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 328 }
 329
 330 static __be32 get_hw_access_flags(struct mthca_qp *qp, struct ib_qp_attr *attr,
 331                                   int attr_mask)
 332 {
 333         u8 dest_rd_atomic;
 334         u32 access_flags;
 335         u32 hw_access_flags = 0;
 336
 337         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 338                 dest_rd_atomic = attr->max_dest_rd_atomic;
 339         else
 340                 dest_rd_atomic = qp->resp_depth;
 341
 342         if (attr_mask & IB_QP_ACCESS_FLAGS)
 343                 access_flags = attr->qp_access_flags;
 344         else
 345                 access_flags = qp->atomic_rd_en;
 346
 347         if (!dest_rd_atomic)
 348                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 349
 350         if (access_flags & IB_ACCESS_REMOTE_READ)
 351                 hw_access_flags |= MTHCA_QP_BIT_RRE;
 352         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 353                 hw_access_flags |= MTHCA_QP_BIT_RAE;
 354         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 355                 hw_access_flags |= MTHCA_QP_BIT_RWE;
 356
 357         return cpu_to_be32(hw_access_flags);
 358 }
 359
 360 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
 361 {
 362         switch (mthca_state) {
 363         case MTHCA_QP_STATE_RST:      return IB_QPS_RESET;
 364         case MTHCA_QP_STATE_INIT:     return IB_QPS_INIT;
 365         case MTHCA_QP_STATE_RTR:      return IB_QPS_RTR;
 366         case MTHCA_QP_STATE_RTS:      return IB_QPS_RTS;
 367         case MTHCA_QP_STATE_DRAINING:
 368         case MTHCA_QP_STATE_SQD:      return IB_QPS_SQD;
 369         case MTHCA_QP_STATE_SQE:      return IB_QPS_SQE;
 370         case MTHCA_QP_STATE_ERR:      return IB_QPS_ERR;
 371         default:                      return -1;
 372         }
 373 }
 374
 375 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
 376 {
 377         switch (mthca_mig_state) {
 378         case 0:  return IB_MIG_ARMED;
 379         case 1:  return IB_MIG_REARM;
 380         case 3:  return IB_MIG_MIGRATED;
 381         default: return -1;
 382         }
 383 }
 384
 385 static int to_ib_qp_access_flags(int mthca_flags)
 386 {
 387         int ib_flags = 0;
 388
 389         if (mthca_flags & MTHCA_QP_BIT_RRE)
 390                 ib_flags |= IB_ACCESS_REMOTE_READ;
 391         if (mthca_flags & MTHCA_QP_BIT_RWE)
 392                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
 393         if (mthca_flags & MTHCA_QP_BIT_RAE)
 394                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
 395
 396         return ib_flags;
 397 }
 398
 399 static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr,
 400                                 struct mthca_qp_path *path)
 401 {
 402         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
 403         ib_ah_attr->port_num      = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
 404
 405         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->limits.num_ports)
 406                 return;
 407
 408         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
 409         ib_ah_attr->sl            = be32_to_cpu(path->sl_tclass_flowlabel) >> 28;
 410         ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f;
 411         ib_ah_attr->static_rate   = mthca_rate_to_ib(dev,
 412                                                      path->static_rate & 0xf,
 413                                                      ib_ah_attr->port_num);
 414         ib_ah_attr->ah_flags      = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
 415         if (ib_ah_attr->ah_flags) {
 416                 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1);
 417                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
 418                 ib_ah_attr->grh.traffic_class =
 419                         (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff;
 420                 ib_ah_attr->grh.flow_label =
 421                         be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff;
 422                 memcpy(ib_ah_attr->grh.dgid.raw,
 423                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
 424         }
 425 }
 426
 427 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
 428                    struct ib_qp_init_attr *qp_init_attr)
 429 {
 430         struct mthca_dev *dev = to_mdev(ibqp->device);
 431         struct mthca_qp *qp = to_mqp(ibqp);
 432         int err = 0;
 433         struct mthca_mailbox *mailbox = NULL;
 434         struct mthca_qp_param *qp_param;
 435         struct mthca_qp_context *context;
 436         int mthca_state;
 437         u8 status;
 438
 439         if (qp->state == IB_QPS_RESET) {
 440                 qp_attr->qp_state = IB_QPS_RESET;
 441                 goto done;
 442         }
 443
 444         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 445         if (IS_ERR(mailbox))
 446                 return PTR_ERR(mailbox);
 447
 448         err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status);
 449         if (err)
 450                 goto out;
 451         if (status) {
 452                 mthca_warn(dev, "QUERY_QP returned status %02x\n", status);
 453                 err = -EINVAL;
 454                 goto out;
 455         }
 456
 457         qp_param    = mailbox->buf;
 458         context     = &qp_param->context;
 459         mthca_state = be32_to_cpu(context->flags) >> 28;
 460
 461         qp_attr->qp_state            = to_ib_qp_state(mthca_state);
 462         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
 463         qp_attr->path_mig_state      =
 464                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
 465         qp_attr->qkey                = be32_to_cpu(context->qkey);
 466         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
 467         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
 468         qp_attr->dest_qp_num         = be32_to_cpu(context->remote_qpn) & 0xffffff;
 469         qp_attr->qp_access_flags     =
 470                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
 471
 472         if (qp->transport == RC || qp->transport == UC) {
 473                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
 474                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
 475                 qp_attr->alt_pkey_index =
 476                         be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
 477                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
 478         }
 479
 480         qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
 481         qp_attr->port_num   =
 482                 (be32_to_cpu(context->pri_path.port_pkey) >> 24) & 0x3;
 483
 484         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
 485         qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
 486
 487         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
 488
 489         qp_attr->max_dest_rd_atomic =
 490                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
 491         qp_attr->min_rnr_timer      =
 492                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
 493         qp_attr->timeout            = context->pri_path.ackto >> 3;
 494         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
 495         qp_attr->rnr_retry          = context->pri_path.rnr_retry >> 5;
 496         qp_attr->alt_timeout        = context->alt_path.ackto >> 3;
 497
 498 done:
 499         qp_attr->cur_qp_state        = qp_attr->qp_state;
 500         qp_attr->cap.max_send_wr     = qp->sq.max;
 501         qp_attr->cap.max_recv_wr     = qp->rq.max;
 502         qp_attr->cap.max_send_sge    = qp->sq.max_gs;
 503         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
 504         qp_attr->cap.max_inline_data = qp->max_inline_data;
 505
 506         qp_init_attr->cap            = qp_attr->cap;
 507
 508 out:
 509         mthca_free_mailbox(dev, mailbox);
 510         return err;
 511 }
 512
 513 static int mthca_path_set(struct mthca_dev *dev, struct ib_ah_attr *ah,
 514                           struct mthca_qp_path *path, u8 port)
 515 {
 516         path->g_mylmc     = ah->src_path_bits & 0x7f;
 517         path->rlid        = cpu_to_be16(ah->dlid);
 518         path->static_rate = mthca_get_rate(dev, ah->static_rate, port);
 519
 520         if (ah->ah_flags & IB_AH_GRH) {
 521                 if (ah->grh.sgid_index >= dev->limits.gid_table_len) {
 522                         mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
 523                                   ah->grh.sgid_index, dev->limits.gid_table_len-1);
 524                         return -1;
 525                 }
 526
 527                 path->g_mylmc   |= 1 << 7;
 528                 path->mgid_index = ah->grh.sgid_index;
 529                 path->hop_limit  = ah->grh.hop_limit;
 530                 path->sl_tclass_flowlabel =
 531                         cpu_to_be32((ah->sl << 28)                |
 532                                     (ah->grh.traffic_class << 20) |
 533                                     (ah->grh.flow_label));
 534                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 535         } else
 536                 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28);
 537
 538         return 0;
 539 }
 540
 541 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
 542                     struct ib_udata *udata)
 543 {
 544         struct mthca_dev *dev = to_mdev(ibqp->device);
 545         struct mthca_qp *qp = to_mqp(ibqp);
 546         enum ib_qp_state cur_state, new_state;
 547         struct mthca_mailbox *mailbox;
 548         struct mthca_qp_param *qp_param;
 549         struct mthca_qp_context *qp_context;
 550         u32 sqd_event = 0;
 551         u8 status;
 552         int err = -EINVAL;
 553
 554         mutex_lock(&qp->mutex);
 555
 556         if (attr_mask & IB_QP_CUR_STATE) {
 557                 cur_state = attr->cur_qp_state;
 558         } else {
 559                 spin_lock_irq(&qp->sq.lock);
 560                 spin_lock(&qp->rq.lock);
 561                 cur_state = qp->state;
 562                 spin_unlock(&qp->rq.lock);
 563                 spin_unlock_irq(&qp->sq.lock);
 564         }
 565
 566         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
 567
 568         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
 569                 mthca_dbg(dev, "Bad QP transition (transport %d) "
 570                           "%d->%d with attr 0x%08x\n",
 571                           qp->transport, cur_state, new_state,
 572                           attr_mask);
 573                 goto out;
 574         }
 575
 576         if ((attr_mask & IB_QP_PKEY_INDEX) &&
 577              attr->pkey_index >= dev->limits.pkey_table_len) {
 578                 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
 579                           attr->pkey_index, dev->limits.pkey_table_len-1);
 580                 goto out;
 581         }
 582
 583         if ((attr_mask & IB_QP_PORT) &&
 584             (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
 585                 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
 586                 goto out;
 587         }
 588
 589         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
 590             attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
 591                 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
 592                           attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
 593                 goto out;
 594         }
 595
 596         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
 597             attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
 598                 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
 599                           attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
 600                 goto out;
 601         }
 602
 603         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 604         if (IS_ERR(mailbox)) {
 605                 err = PTR_ERR(mailbox);
 606                 goto out;
 607         }
 608         qp_param = mailbox->buf;
 609         qp_context = &qp_param->context;
 610         memset(qp_param, 0, sizeof *qp_param);
 611
 612         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 613                                              (to_mthca_st(qp->transport) << 16));
 614         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 615         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 616                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 617         else {
 618                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 619                 switch (attr->path_mig_state) {
 620                 case IB_MIG_MIGRATED:
 621                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 622                         break;
 623                 case IB_MIG_REARM:
 624                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 625                         break;
 626                 case IB_MIG_ARMED:
 627                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 628                         break;
 629                 }
 630         }
 631
 632         /* leave tavor_sched_queue as 0 */
 633
 634         if (qp->transport == MLX || qp->transport == UD)
 635                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 636         else if (attr_mask & IB_QP_PATH_MTU) {
 637                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
 638                         mthca_dbg(dev, "path MTU (%u) is invalid\n",
 639                                   attr->path_mtu);
 640                         goto out_mailbox;
 641                 }
 642                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 643         }
 644
 645         if (mthca_is_memfree(dev)) {
 646                 if (qp->rq.max)
 647                         qp_context->rq_size_stride = ilog2(qp->rq.max) << 3;
 648                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
 649
 650                 if (qp->sq.max)
 651                         qp_context->sq_size_stride = ilog2(qp->sq.max) << 3;
 652                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
 653         }
 654
 655         /* leave arbel_sched_queue as 0 */
 656
 657         if (qp->ibqp.uobject)
 658                 qp_context->usr_page =
 659                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 660         else
 661                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 662         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 663         if (attr_mask & IB_QP_DEST_QPN) {
 664                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 665         }
 666
 667         if (qp->transport == MLX)
 668                 qp_context->pri_path.port_pkey |=
 669                         cpu_to_be32(qp->port << 24);
 670         else {
 671                 if (attr_mask & IB_QP_PORT) {
 672                         qp_context->pri_path.port_pkey |=
 673                                 cpu_to_be32(attr->port_num << 24);
 674                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 675                 }
 676         }
 677
 678         if (attr_mask & IB_QP_PKEY_INDEX) {
 679                 qp_context->pri_path.port_pkey |=
 680                         cpu_to_be32(attr->pkey_index);
 681                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 682         }
 683
 684         if (attr_mask & IB_QP_RNR_RETRY) {
 685                 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
 686                         attr->rnr_retry << 5;
 687                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
 688                                                         MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
 689         }
 690
 691         if (attr_mask & IB_QP_AV) {
 692                 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
 693                                    attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
 694                         goto out_mailbox;
 695
 696                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 697         }
 698
 699         if (attr_mask & IB_QP_TIMEOUT) {
 700                 qp_context->pri_path.ackto = attr->timeout << 3;
 701                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 702         }
 703
 704         if (attr_mask & IB_QP_ALT_PATH) {
 705                 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
 706                         mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
 707                                   attr->alt_pkey_index, dev->limits.pkey_table_len-1);
 708                         goto out_mailbox;
 709                 }
 710
 711                 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
 712                         mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
 713                                 attr->alt_port_num);
 714                         goto out_mailbox;
 715                 }
 716
 717                 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
 718                                    attr->alt_ah_attr.port_num))
 719                         goto out_mailbox;
 720
 721                 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
 722                                                               attr->alt_port_num << 24);
 723                 qp_context->alt_path.ackto = attr->alt_timeout << 3;
 724                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
 725         }
 726
 727         /* leave rdd as 0 */
 728         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 729         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 730         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 731         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 732                                              (MTHCA_FLIGHT_LIMIT << 24) |
 733                                              MTHCA_QP_BIT_SWE);
 734         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 735                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 736         if (attr_mask & IB_QP_RETRY_CNT) {
 737                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 738                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 739         }
 740
 741         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 742                 if (attr->max_rd_atomic) {
 743                         qp_context->params1 |=
 744                                 cpu_to_be32(MTHCA_QP_BIT_SRE |
 745                                             MTHCA_QP_BIT_SAE);
 746                         qp_context->params1 |=
 747                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 748                 }
 749                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 750         }
 751
 752         if (attr_mask & IB_QP_SQ_PSN)
 753                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 754         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 755
 756         if (mthca_is_memfree(dev)) {
 757                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 758                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 759         }
 760
 761         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 762                 if (attr->max_dest_rd_atomic)
 763                         qp_context->params2 |=
 764                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 765
 766                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 767         }
 768
 769         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
 770                 qp_context->params2      |= get_hw_access_flags(qp, attr, attr_mask);
 771                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 772                                                         MTHCA_QP_OPTPAR_RRE |
 773                                                         MTHCA_QP_OPTPAR_RAE);
 774         }
 775
 776         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 777
 778         if (ibqp->srq)
 779                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
 780
 781         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 782                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 783                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 784         }
 785         if (attr_mask & IB_QP_RQ_PSN)
 786                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 787
 788         qp_context->ra_buff_indx =
 789                 cpu_to_be32(dev->qp_table.rdb_base +
 790                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 791                              dev->qp_table.rdb_shift));
 792
 793         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 794
 795         if (mthca_is_memfree(dev))
 796                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 797
 798         if (attr_mask & IB_QP_QKEY) {
 799                 qp_context->qkey = cpu_to_be32(attr->qkey);
 800                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 801         }
 802
 803         if (ibqp->srq)
 804                 qp_context->srqn = cpu_to_be32(1 << 24 |
 805                                                to_msrq(ibqp->srq)->srqn);
 806
 807         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
 808             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY               &&
 809             attr->en_sqd_async_notify)
 810                 sqd_event = 1 << 31;
 811
 812         err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
 813                               mailbox, sqd_event, &status);
 814         if (err)
 815                 goto out_mailbox;
 816         if (status) {
 817                 mthca_warn(dev, "modify QP %d->%d returned status %02x.\n",
 818                            cur_state, new_state, status);
 819                 err = -EINVAL;
 820                 goto out_mailbox;
 821         }
 822
 823         qp->state = new_state;
 824         if (attr_mask & IB_QP_ACCESS_FLAGS)
 825                 qp->atomic_rd_en = attr->qp_access_flags;
 826         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 827                 qp->resp_depth = attr->max_dest_rd_atomic;
 828         if (attr_mask & IB_QP_PORT)
 829                 qp->port = attr->port_num;
 830         if (attr_mask & IB_QP_ALT_PATH)
 831                 qp->alt_port = attr->alt_port_num;
 832
 833         if (is_sqp(dev, qp))
 834                 store_attrs(to_msqp(qp), attr, attr_mask);
 835
 836         /*
 837          * If we moved QP0 to RTR, bring the IB link up; if we moved
 838          * QP0 to RESET or ERROR, bring the link back down.
 839          */
 840         if (is_qp0(dev, qp)) {
 841                 if (cur_state != IB_QPS_RTR &&
 842                     new_state == IB_QPS_RTR)
 843                         init_port(dev, qp->port);
 844
 845                 if (cur_state != IB_QPS_RESET &&
 846                     cur_state != IB_QPS_ERR &&
 847                     (new_state == IB_QPS_RESET ||
 848                      new_state == IB_QPS_ERR))
 849                         mthca_CLOSE_IB(dev, qp->port, &status);
 850         }
 851
 852         /*
 853          * If we moved a kernel QP to RESET, clean up all old CQ
 854          * entries and reinitialize the QP.
 855          */
 856         if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
 857                 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
 858                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 859                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
 860                         mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn, NULL);
 861
 862                 mthca_wq_reset(&qp->sq);
 863                 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
 864
 865                 mthca_wq_reset(&qp->rq);
 866                 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
 867
 868                 if (mthca_is_memfree(dev)) {
 869                         *qp->sq.db = 0;
 870                         *qp->rq.db = 0;
 871                 }
 872         }
 873
 874 out_mailbox:
 875         mthca_free_mailbox(dev, mailbox);
 876
 877 out:
 878         mutex_unlock(&qp->mutex);
 879         return err;
 880 }
 881
 882 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
 883 {
 884         /*
 885          * Calculate the maximum size of WQE s/g segments, excluding
 886          * the next segment and other non-data segments.
 887          */
 888         int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
 889
 890         switch (qp->transport) {
 891         case MLX:
 892                 max_data_size -= 2 * sizeof (struct mthca_data_seg);
 893                 break;
 894
 895         case UD:
 896                 if (mthca_is_memfree(dev))
 897                         max_data_size -= sizeof (struct mthca_arbel_ud_seg);
 898                 else
 899                         max_data_size -= sizeof (struct mthca_tavor_ud_seg);
 900                 break;
 901
 902         default:
 903                 max_data_size -= sizeof (struct mthca_raddr_seg);
 904                 break;
 905         }
 906
 907         return max_data_size;
 908 }
 909
 910 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
 911 {
 912         /* We don't support inline data for kernel QPs (yet). */
 913         return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
 914 }
 915
 916 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
 917                                  struct mthca_pd *pd,
 918                                  struct mthca_qp *qp)
 919 {
 920         int max_data_size = mthca_max_data_size(dev, qp,
 921                                                 min(dev->limits.max_desc_sz,
 922                                                     1 << qp->sq.wqe_shift));
 923
 924         qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
 925
 926         qp->sq.max_gs = min_t(int, dev->limits.max_sg,
 927                               max_data_size / sizeof (struct mthca_data_seg));
 928         qp->rq.max_gs = min_t(int, dev->limits.max_sg,
 929                                (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
 930                                 sizeof (struct mthca_next_seg)) /
 931                                sizeof (struct mthca_data_seg));
 932 }
 933
 934 /*
 935  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 936  * rq.max_gs and sq.max_gs must all be assigned.
 937  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 938  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 939  * queue)
 940  */
 941 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 942                                struct mthca_pd *pd,
 943                                struct mthca_qp *qp)
 944 {
 945         int size;
 946         int err = -ENOMEM;
 947
 948         size = sizeof (struct mthca_next_seg) +
 949                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 950
 951         if (size > dev->limits.max_desc_sz)
 952                 return -EINVAL;
 953
 954         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 955              qp->rq.wqe_shift++)
 956                 ; /* nothing */
 957
 958         size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
 959         switch (qp->transport) {
 960         case MLX:
 961                 size += 2 * sizeof (struct mthca_data_seg);
 962                 break;
 963
 964         case UD:
 965                 size += mthca_is_memfree(dev) ?
 966                         sizeof (struct mthca_arbel_ud_seg) :
 967                         sizeof (struct mthca_tavor_ud_seg);
 968                 break;
 969
 970         case UC:
 971                 size += sizeof (struct mthca_raddr_seg);
 972                 break;
 973
 974         case RC:
 975                 size += sizeof (struct mthca_raddr_seg);
 976                 /*
 977                  * An atomic op will require an atomic segment, a
 978                  * remote address segment and one scatter entry.
 979                  */
 980                 size = max_t(int, size,
 981                              sizeof (struct mthca_atomic_seg) +
 982                              sizeof (struct mthca_raddr_seg) +
 983                              sizeof (struct mthca_data_seg));
 984                 break;
 985
 986         default:
 987                 break;
 988         }
 989
 990         /* Make sure that we have enough space for a bind request */
 991         size = max_t(int, size, sizeof (struct mthca_bind_seg));
 992
 993         size += sizeof (struct mthca_next_seg);
 994
 995         if (size > dev->limits.max_desc_sz)
 996                 return -EINVAL;
 997
 998         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
 999              qp->sq.wqe_shift++)
1000                 ; /* nothing */
1001
1002         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
1003                                     1 << qp->sq.wqe_shift);
1004
1005         /*
1006          * If this is a userspace QP, we don't actually have to
1007          * allocate anything.  All we need is to calculate the WQE
1008          * sizes and the send_wqe_offset, so we're done now.
1009          */
1010         if (pd->ibpd.uobject)
1011                 return 0;
1012
1013         size = PAGE_ALIGN(qp->send_wqe_offset +
1014                           (qp->sq.max << qp->sq.wqe_shift));
1015
1016         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1017                            GFP_KERNEL);
1018         if (!qp->wrid)
1019                 goto err_out;
1020
1021         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1022                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1023         if (err)
1024                 goto err_out;
1025
1026         return 0;
1027
1028 err_out:
1029         kfree(qp->wrid);
1030         return err;
1031 }
1032
1033 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1034                                struct mthca_qp *qp)
1035 {
1036         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1037                                        (qp->sq.max << qp->sq.wqe_shift)),
1038                        &qp->queue, qp->is_direct, &qp->mr);
1039         kfree(qp->wrid);
1040 }
1041
1042 static int mthca_map_memfree(struct mthca_dev *dev,
1043                              struct mthca_qp *qp)
1044 {
1045         int ret;
1046
1047         if (mthca_is_memfree(dev)) {
1048                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1049                 if (ret)
1050                         return ret;
1051
1052                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1053                 if (ret)
1054                         goto err_qpc;
1055
1056                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1057                                       qp->qpn << dev->qp_table.rdb_shift);
1058                 if (ret)
1059                         goto err_eqpc;
1060
1061         }
1062
1063         return 0;
1064
1065 err_eqpc:
1066         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1067
1068 err_qpc:
1069         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1070
1071         return ret;
1072 }
1073
1074 static void mthca_unmap_memfree(struct mthca_dev *dev,
1075                                 struct mthca_qp *qp)
1076 {
1077         mthca_table_put(dev, dev->qp_table.rdb_table,
1078                         qp->qpn << dev->qp_table.rdb_shift);
1079         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1080         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1081 }
1082
1083 static int mthca_alloc_memfree(struct mthca_dev *dev,
1084                                struct mthca_qp *qp)
1085 {
1086         int ret = 0;
1087
1088         if (mthca_is_memfree(dev)) {
1089                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1090                                                  qp->qpn, &qp->rq.db);
1091                 if (qp->rq.db_index < 0)
1092                         return ret;
1093
1094                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1095                                                  qp->qpn, &qp->sq.db);
1096                 if (qp->sq.db_index < 0)
1097                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1098         }
1099
1100         return ret;
1101 }
1102
1103 static void mthca_free_memfree(struct mthca_dev *dev,
1104                                struct mthca_qp *qp)
1105 {
1106         if (mthca_is_memfree(dev)) {
1107                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1108                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1109         }
1110 }
1111
1112 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1113                                  struct mthca_pd *pd,
1114                                  struct mthca_cq *send_cq,
1115                                  struct mthca_cq *recv_cq,
1116                                  enum ib_sig_type send_policy,
1117                                  struct mthca_qp *qp)
1118 {
1119         int ret;
1120         int i;
1121
1122         qp->refcount = 1;
1123         init_waitqueue_head(&qp->wait);
1124         mutex_init(&qp->mutex);
1125         qp->state        = IB_QPS_RESET;
1126         qp->atomic_rd_en = 0;
1127         qp->resp_depth   = 0;
1128         qp->sq_policy    = send_policy;
1129         mthca_wq_reset(&qp->sq);
1130         mthca_wq_reset(&qp->rq);
1131
1132         spin_lock_init(&qp->sq.lock);
1133         spin_lock_init(&qp->rq.lock);
1134
1135         ret = mthca_map_memfree(dev, qp);
1136         if (ret)
1137                 return ret;
1138
1139         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1140         if (ret) {
1141                 mthca_unmap_memfree(dev, qp);
1142                 return ret;
1143         }
1144
1145         mthca_adjust_qp_caps(dev, pd, qp);
1146
1147         /*
1148          * If this is a userspace QP, we're done now.  The doorbells
1149          * will be allocated and buffers will be initialized in
1150          * userspace.
1151          */
1152         if (pd->ibpd.uobject)
1153                 return 0;
1154
1155         ret = mthca_alloc_memfree(dev, qp);
1156         if (ret) {
1157                 mthca_free_wqe_buf(dev, qp);
1158                 mthca_unmap_memfree(dev, qp);
1159                 return ret;
1160         }
1161
1162         if (mthca_is_memfree(dev)) {
1163                 struct mthca_next_seg *next;
1164                 struct mthca_data_seg *scatter;
1165                 int size = (sizeof (struct mthca_next_seg) +
1166                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1167
1168                 for (i = 0; i < qp->rq.max; ++i) {
1169                         next = get_recv_wqe(qp, i);
1170                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1171                                                    qp->rq.wqe_shift);
1172                         next->ee_nds = cpu_to_be32(size);
1173
1174                         for (scatter = (void *) (next + 1);
1175                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1176                              ++scatter)
1177                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1178                 }
1179
1180                 for (i = 0; i < qp->sq.max; ++i) {
1181                         next = get_send_wqe(qp, i);
1182                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1183                                                     qp->sq.wqe_shift) +
1184                                                    qp->send_wqe_offset);
1185                 }
1186         }
1187
1188         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1189         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1190
1191         return 0;
1192 }
1193
1194 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1195                              struct mthca_pd *pd, struct mthca_qp *qp)
1196 {
1197         int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1198
1199         /* Sanity check QP size before proceeding */
1200         if (cap->max_send_wr     > dev->limits.max_wqes ||
1201             cap->max_recv_wr     > dev->limits.max_wqes ||
1202             cap->max_send_sge    > dev->limits.max_sg   ||
1203             cap->max_recv_sge    > dev->limits.max_sg   ||
1204             cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1205                 return -EINVAL;
1206
1207         /*
1208          * For MLX transport we need 2 extra S/G entries:
1209          * one for the header and one for the checksum at the end
1210          */
1211         if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg)
1212                 return -EINVAL;
1213
1214         if (mthca_is_memfree(dev)) {
1215                 qp->rq.max = cap->max_recv_wr ?
1216                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1217                 qp->sq.max = cap->max_send_wr ?
1218                         roundup_pow_of_two(cap->max_send_wr) : 0;
1219         } else {
1220                 qp->rq.max = cap->max_recv_wr;
1221                 qp->sq.max = cap->max_send_wr;
1222         }
1223
1224         qp->rq.max_gs = cap->max_recv_sge;
1225         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1226                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1227                                     MTHCA_INLINE_CHUNK_SIZE) /
1228                               sizeof (struct mthca_data_seg));
1229
1230         return 0;
1231 }
1232
1233 int mthca_alloc_qp(struct mthca_dev *dev,
1234                    struct mthca_pd *pd,
1235                    struct mthca_cq *send_cq,
1236                    struct mthca_cq *recv_cq,
1237                    enum ib_qp_type type,
1238                    enum ib_sig_type send_policy,
1239                    struct ib_qp_cap *cap,
1240                    struct mthca_qp *qp)
1241 {
1242         int err;
1243
1244         switch (type) {
1245         case IB_QPT_RC: qp->transport = RC; break;
1246         case IB_QPT_UC: qp->transport = UC; break;
1247         case IB_QPT_UD: qp->transport = UD; break;
1248         default: return -EINVAL;
1249         }
1250
1251         err = mthca_set_qp_size(dev, cap, pd, qp);
1252         if (err)
1253                 return err;
1254
1255         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1256         if (qp->qpn == -1)
1257                 return -ENOMEM;
1258
1259         /* initialize port to zero for error-catching. */
1260         qp->port = 0;
1261
1262         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1263                                     send_policy, qp);
1264         if (err) {
1265                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1266                 return err;
1267         }
1268
1269         spin_lock_irq(&dev->qp_table.lock);
1270         mthca_array_set(&dev->qp_table.qp,
1271                         qp->qpn & (dev->limits.num_qps - 1), qp);
1272         spin_unlock_irq(&dev->qp_table.lock);
1273
1274         return 0;
1275 }
1276
1277 static void mthca_lock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1278 {
1279         if (send_cq == recv_cq)
1280                 spin_lock_irq(&send_cq->lock);
1281         else if (send_cq->cqn < recv_cq->cqn) {
1282                 spin_lock_irq(&send_cq->lock);
1283                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1284         } else {
1285                 spin_lock_irq(&recv_cq->lock);
1286                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1287         }
1288 }
1289
1290 static void mthca_unlock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1291 {
1292         if (send_cq == recv_cq)
1293                 spin_unlock_irq(&send_cq->lock);
1294         else if (send_cq->cqn < recv_cq->cqn) {
1295                 spin_unlock(&recv_cq->lock);
1296                 spin_unlock_irq(&send_cq->lock);
1297         } else {
1298                 spin_unlock(&send_cq->lock);
1299                 spin_unlock_irq(&recv_cq->lock);
1300         }
1301 }
1302
1303 int mthca_alloc_sqp(struct mthca_dev *dev,
1304                     struct mthca_pd *pd,
1305                     struct mthca_cq *send_cq,
1306                     struct mthca_cq *recv_cq,
1307                     enum ib_sig_type send_policy,
1308                     struct ib_qp_cap *cap,
1309                     int qpn,
1310                     int port,
1311                     struct mthca_sqp *sqp)
1312 {
1313         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1314         int err;
1315
1316         sqp->qp.transport = MLX;
1317         err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1318         if (err)
1319                 return err;
1320
1321         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1322         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1323                                              &sqp->header_dma, GFP_KERNEL);
1324         if (!sqp->header_buf)
1325                 return -ENOMEM;
1326
1327         spin_lock_irq(&dev->qp_table.lock);
1328         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1329                 err = -EBUSY;
1330         else
1331                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1332         spin_unlock_irq(&dev->qp_table.lock);
1333
1334         if (err)
1335                 goto err_out;
1336
1337         sqp->qp.port      = port;
1338         sqp->qp.qpn       = mqpn;
1339         sqp->qp.transport = MLX;
1340
1341         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1342                                     send_policy, &sqp->qp);
1343         if (err)
1344                 goto err_out_free;
1345
1346         atomic_inc(&pd->sqp_count);
1347
1348         return 0;
1349
1350  err_out_free:
1351         /*
1352          * Lock CQs here, so that CQ polling code can do QP lookup
1353          * without taking a lock.
1354          */
1355         mthca_lock_cqs(send_cq, recv_cq);
1356
1357         spin_lock(&dev->qp_table.lock);
1358         mthca_array_clear(&dev->qp_table.qp, mqpn);
1359         spin_unlock(&dev->qp_table.lock);
1360
1361         mthca_unlock_cqs(send_cq, recv_cq);
1362
1363  err_out:
1364         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1365                           sqp->header_buf, sqp->header_dma);
1366
1367         return err;
1368 }
1369
1370 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp)
1371 {
1372         int c;
1373
1374         spin_lock_irq(&dev->qp_table.lock);
1375         c = qp->refcount;
1376         spin_unlock_irq(&dev->qp_table.lock);
1377
1378         return c;
1379 }
1380
1381 void mthca_free_qp(struct mthca_dev *dev,
1382                    struct mthca_qp *qp)
1383 {
1384         u8 status;
1385         struct mthca_cq *send_cq;
1386         struct mthca_cq *recv_cq;
1387
1388         send_cq = to_mcq(qp->ibqp.send_cq);
1389         recv_cq = to_mcq(qp->ibqp.recv_cq);
1390
1391         /*
1392          * Lock CQs here, so that CQ polling code can do QP lookup
1393          * without taking a lock.
1394          */
1395         mthca_lock_cqs(send_cq, recv_cq);
1396
1397         spin_lock(&dev->qp_table.lock);
1398         mthca_array_clear(&dev->qp_table.qp,
1399                           qp->qpn & (dev->limits.num_qps - 1));
1400         --qp->refcount;
1401         spin_unlock(&dev->qp_table.lock);
1402
1403         mthca_unlock_cqs(send_cq, recv_cq);
1404
1405         wait_event(qp->wait, !get_qp_refcount(dev, qp));
1406
1407         if (qp->state != IB_QPS_RESET)
1408                 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1409                                 NULL, 0, &status);
1410
1411         /*
1412          * If this is a userspace QP, the buffers, MR, CQs and so on
1413          * will be cleaned up in userspace, so all we have to do is
1414          * unref the mem-free tables and free the QPN in our table.
1415          */
1416         if (!qp->ibqp.uobject) {
1417                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn,
1418                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1419                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1420                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
1421                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1422
1423                 mthca_free_memfree(dev, qp);
1424                 mthca_free_wqe_buf(dev, qp);
1425         }
1426
1427         mthca_unmap_memfree(dev, qp);
1428
1429         if (is_sqp(dev, qp)) {
1430                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1431                 dma_free_coherent(&dev->pdev->dev,
1432                                   to_msqp(qp)->header_buf_size,
1433                                   to_msqp(qp)->header_buf,
1434                                   to_msqp(qp)->header_dma);
1435         } else
1436                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1437 }
1438
1439 /* Create UD header for an MLX send and build a data segment for it */
1440 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1441                             int ind, struct ib_send_wr *wr,
1442                             struct mthca_mlx_seg *mlx,
1443                             struct mthca_data_seg *data)
1444 {
1445         int header_size;
1446         int err;
1447         u16 pkey;
1448
1449         ib_ud_header_init(256, /* assume a MAD */
1450                           mthca_ah_grh_present(to_mah(wr->wr.ud.ah)),
1451                           &sqp->ud_header);
1452
1453         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1454         if (err)
1455                 return err;
1456         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1457         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1458                                   (sqp->ud_header.lrh.destination_lid ==
1459                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1460                                   (sqp->ud_header.lrh.service_level << 8));
1461         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1462         mlx->vcrc = 0;
1463
1464         switch (wr->opcode) {
1465         case IB_WR_SEND:
1466                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1467                 sqp->ud_header.immediate_present = 0;
1468                 break;
1469         case IB_WR_SEND_WITH_IMM:
1470                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1471                 sqp->ud_header.immediate_present = 1;
1472                 sqp->ud_header.immediate_data = wr->imm_data;
1473                 break;
1474         default:
1475                 return -EINVAL;
1476         }
1477
1478         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1479         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1480                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1481         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1482         if (!sqp->qp.ibqp.qp_num)
1483                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1484                                    sqp->pkey_index, &pkey);
1485         else
1486                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1487                                    wr->wr.ud.pkey_index, &pkey);
1488         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1489         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1490         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1491         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1492                                                sqp->qkey : wr->wr.ud.remote_qkey);
1493         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1494
1495         header_size = ib_ud_header_pack(&sqp->ud_header,
1496                                         sqp->header_buf +
1497                                         ind * MTHCA_UD_HEADER_SIZE);
1498
1499         data->byte_count = cpu_to_be32(header_size);
1500         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1501         data->addr       = cpu_to_be64(sqp->header_dma +
1502                                        ind * MTHCA_UD_HEADER_SIZE);
1503
1504         return 0;
1505 }
1506
1507 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1508                                     struct ib_cq *ib_cq)
1509 {
1510         unsigned cur;
1511         struct mthca_cq *cq;
1512
1513         cur = wq->head - wq->tail;
1514         if (likely(cur + nreq < wq->max))
1515                 return 0;
1516
1517         cq = to_mcq(ib_cq);
1518         spin_lock(&cq->lock);
1519         cur = wq->head - wq->tail;
1520         spin_unlock(&cq->lock);
1521
1522         return cur + nreq >= wq->max;
1523 }
1524
1525 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1526                           struct ib_send_wr **bad_wr)
1527 {
1528         struct mthca_dev *dev = to_mdev(ibqp->device);
1529         struct mthca_qp *qp = to_mqp(ibqp);
1530         void *wqe;
1531         void *prev_wqe;
1532         unsigned long flags;
1533         int err = 0;
1534         int nreq;
1535         int i;
1536         int size;
1537         int size0 = 0;
1538         u32 f0;
1539         int ind;
1540         u8 op0 = 0;
1541
1542         spin_lock_irqsave(&qp->sq.lock, flags);
1543
1544         /* XXX check that state is OK to post send */
1545
1546         ind = qp->sq.next_ind;
1547
1548         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1549                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1550                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1551                                         " %d max, %d nreq)\n", qp->qpn,
1552                                         qp->sq.head, qp->sq.tail,
1553                                         qp->sq.max, nreq);
1554                         err = -ENOMEM;
1555                         *bad_wr = wr;
1556                         goto out;
1557                 }
1558
1559                 wqe = get_send_wqe(qp, ind);
1560                 prev_wqe = qp->sq.last;
1561                 qp->sq.last = wqe;
1562
1563                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1564                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1565                 ((struct mthca_next_seg *) wqe)->flags =
1566                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1567                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1568                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1569                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1570                         cpu_to_be32(1);
1571                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1572                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1573                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1574
1575                 wqe += sizeof (struct mthca_next_seg);
1576                 size = sizeof (struct mthca_next_seg) / 16;
1577
1578                 switch (qp->transport) {
1579                 case RC:
1580                         switch (wr->opcode) {
1581                         case IB_WR_ATOMIC_CMP_AND_SWP:
1582                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1583                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1584                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1585                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1586                                         cpu_to_be32(wr->wr.atomic.rkey);
1587                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1588
1589                                 wqe += sizeof (struct mthca_raddr_seg);
1590
1591                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1592                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1593                                                 cpu_to_be64(wr->wr.atomic.swap);
1594                                         ((struct mthca_atomic_seg *) wqe)->compare =
1595                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1596                                 } else {
1597                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1598                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1599                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1600                                 }
1601
1602                                 wqe += sizeof (struct mthca_atomic_seg);
1603                                 size += (sizeof (struct mthca_raddr_seg) +
1604                                          sizeof (struct mthca_atomic_seg)) / 16;
1605                                 break;
1606
1607                         case IB_WR_RDMA_WRITE:
1608                         case IB_WR_RDMA_WRITE_WITH_IMM:
1609                         case IB_WR_RDMA_READ:
1610                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1611                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1612                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1613                                         cpu_to_be32(wr->wr.rdma.rkey);
1614                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1615                                 wqe += sizeof (struct mthca_raddr_seg);
1616                                 size += sizeof (struct mthca_raddr_seg) / 16;
1617                                 break;
1618
1619                         default:
1620                                 /* No extra segments required for sends */
1621                                 break;
1622                         }
1623
1624                         break;
1625
1626                 case UC:
1627                         switch (wr->opcode) {
1628                         case IB_WR_RDMA_WRITE:
1629                         case IB_WR_RDMA_WRITE_WITH_IMM:
1630                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1631                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1632                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1633                                         cpu_to_be32(wr->wr.rdma.rkey);
1634                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1635                                 wqe += sizeof (struct mthca_raddr_seg);
1636                                 size += sizeof (struct mthca_raddr_seg) / 16;
1637                                 break;
1638
1639                         default:
1640                                 /* No extra segments required for sends */
1641                                 break;
1642                         }
1643
1644                         break;
1645
1646                 case UD:
1647                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1648                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1649                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1650                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1651                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1652                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1653                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1654                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1655
1656                         wqe += sizeof (struct mthca_tavor_ud_seg);
1657                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1658                         break;
1659
1660                 case MLX:
1661                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1662                                                wqe - sizeof (struct mthca_next_seg),
1663                                                wqe);
1664                         if (err) {
1665                                 *bad_wr = wr;
1666                                 goto out;
1667                         }
1668                         wqe += sizeof (struct mthca_data_seg);
1669                         size += sizeof (struct mthca_data_seg) / 16;
1670                         break;
1671                 }
1672
1673                 if (wr->num_sge > qp->sq.max_gs) {
1674                         mthca_err(dev, "too many gathers\n");
1675                         err = -EINVAL;
1676                         *bad_wr = wr;
1677                         goto out;
1678                 }
1679
1680                 for (i = 0; i < wr->num_sge; ++i) {
1681                         ((struct mthca_data_seg *) wqe)->byte_count =
1682                                 cpu_to_be32(wr->sg_list[i].length);
1683                         ((struct mthca_data_seg *) wqe)->lkey =
1684                                 cpu_to_be32(wr->sg_list[i].lkey);
1685                         ((struct mthca_data_seg *) wqe)->addr =
1686                                 cpu_to_be64(wr->sg_list[i].addr);
1687                         wqe += sizeof (struct mthca_data_seg);
1688                         size += sizeof (struct mthca_data_seg) / 16;
1689                 }
1690
1691                 /* Add one more inline data segment for ICRC */
1692                 if (qp->transport == MLX) {
1693                         ((struct mthca_data_seg *) wqe)->byte_count =
1694                                 cpu_to_be32((1 << 31) | 4);
1695                         ((u32 *) wqe)[1] = 0;
1696                         wqe += sizeof (struct mthca_data_seg);
1697                         size += sizeof (struct mthca_data_seg) / 16;
1698                 }
1699
1700                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1701
1702                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1703                         mthca_err(dev, "opcode invalid\n");
1704                         err = -EINVAL;
1705                         *bad_wr = wr;
1706                         goto out;
1707                 }
1708
1709                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1710                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1711                                      qp->send_wqe_offset) |
1712                                     mthca_opcode[wr->opcode]);
1713                 wmb();
1714                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1715                         cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size |
1716                                     ((wr->send_flags & IB_SEND_FENCE) ?
1717                                     MTHCA_NEXT_FENCE : 0));
1718
1719                 if (!size0) {
1720                         size0 = size;
1721                         op0   = mthca_opcode[wr->opcode];
1722                         f0    = wr->send_flags & IB_SEND_FENCE ?
1723                                 MTHCA_SEND_DOORBELL_FENCE : 0;
1724                 }
1725
1726                 ++ind;
1727                 if (unlikely(ind >= qp->sq.max))
1728                         ind -= qp->sq.max;
1729         }
1730
1731 out:
1732         if (likely(nreq)) {
1733                 __be32 doorbell[2];
1734
1735                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1736                                            qp->send_wqe_offset) | f0 | op0);
1737                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1738
1739                 wmb();
1740
1741                 mthca_write64(doorbell,
1742                               dev->kar + MTHCA_SEND_DOORBELL,
1743                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1744                 /*
1745                  * Make sure doorbells don't leak out of SQ spinlock
1746                  * and reach the HCA out of order:
1747                  */
1748                 mmiowb();
1749         }
1750
1751         qp->sq.next_ind = ind;
1752         qp->sq.head    += nreq;
1753
1754         spin_unlock_irqrestore(&qp->sq.lock, flags);
1755         return err;
1756 }
1757
1758 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1759                              struct ib_recv_wr **bad_wr)
1760 {
1761         struct mthca_dev *dev = to_mdev(ibqp->device);
1762         struct mthca_qp *qp = to_mqp(ibqp);
1763         __be32 doorbell[2];
1764         unsigned long flags;
1765         int err = 0;
1766         int nreq;
1767         int i;
1768         int size;
1769         int size0 = 0;
1770         int ind;
1771         void *wqe;
1772         void *prev_wqe;
1773
1774         spin_lock_irqsave(&qp->rq.lock, flags);
1775
1776         /* XXX check that state is OK to post receive */
1777
1778         ind = qp->rq.next_ind;
1779
1780         for (nreq = 0; wr; wr = wr->next) {
1781                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1782                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1783                                         " %d max, %d nreq)\n", qp->qpn,
1784                                         qp->rq.head, qp->rq.tail,
1785                                         qp->rq.max, nreq);
1786                         err = -ENOMEM;
1787                         *bad_wr = wr;
1788                         goto out;
1789                 }
1790
1791                 wqe = get_recv_wqe(qp, ind);
1792                 prev_wqe = qp->rq.last;
1793                 qp->rq.last = wqe;
1794
1795                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1796                 ((struct mthca_next_seg *) wqe)->ee_nds =
1797                         cpu_to_be32(MTHCA_NEXT_DBD);
1798                 ((struct mthca_next_seg *) wqe)->flags = 0;
1799
1800                 wqe += sizeof (struct mthca_next_seg);
1801                 size = sizeof (struct mthca_next_seg) / 16;
1802
1803                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1804                         err = -EINVAL;
1805                         *bad_wr = wr;
1806                         goto out;
1807                 }
1808
1809                 for (i = 0; i < wr->num_sge; ++i) {
1810                         ((struct mthca_data_seg *) wqe)->byte_count =
1811                                 cpu_to_be32(wr->sg_list[i].length);
1812                         ((struct mthca_data_seg *) wqe)->lkey =
1813                                 cpu_to_be32(wr->sg_list[i].lkey);
1814                         ((struct mthca_data_seg *) wqe)->addr =
1815                                 cpu_to_be64(wr->sg_list[i].addr);
1816                         wqe += sizeof (struct mthca_data_seg);
1817                         size += sizeof (struct mthca_data_seg) / 16;
1818                 }
1819
1820                 qp->wrid[ind] = wr->wr_id;
1821
1822                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1823                         cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1824                 wmb();
1825                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1826                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1827
1828                 if (!size0)
1829                         size0 = size;
1830
1831                 ++ind;
1832                 if (unlikely(ind >= qp->rq.max))
1833                         ind -= qp->rq.max;
1834
1835                 ++nreq;
1836                 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1837                         nreq = 0;
1838
1839                         doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1840                         doorbell[1] = cpu_to_be32(qp->qpn << 8);
1841
1842                         wmb();
1843
1844                         mthca_write64(doorbell,
1845                                       dev->kar + MTHCA_RECEIVE_DOORBELL,
1846                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1847
1848                         qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1849                         size0 = 0;
1850                 }
1851         }
1852
1853 out:
1854         if (likely(nreq)) {
1855                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1856                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1857
1858                 wmb();
1859
1860                 mthca_write64(doorbell,
1861                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1862                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1863         }
1864
1865         qp->rq.next_ind = ind;
1866         qp->rq.head    += nreq;
1867
1868         /*
1869          * Make sure doorbells don't leak out of RQ spinlock and reach
1870          * the HCA out of order:
1871          */
1872         mmiowb();
1873
1874         spin_unlock_irqrestore(&qp->rq.lock, flags);
1875         return err;
1876 }
1877
1878 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1879                           struct ib_send_wr **bad_wr)
1880 {
1881         struct mthca_dev *dev = to_mdev(ibqp->device);
1882         struct mthca_qp *qp = to_mqp(ibqp);
1883         __be32 doorbell[2];
1884         void *wqe;
1885         void *prev_wqe;
1886         unsigned long flags;
1887         int err = 0;
1888         int nreq;
1889         int i;
1890         int size;
1891         int size0 = 0;
1892         u32 f0;
1893         int ind;
1894         u8 op0 = 0;
1895
1896         spin_lock_irqsave(&qp->sq.lock, flags);
1897
1898         /* XXX check that state is OK to post send */
1899
1900         ind = qp->sq.head & (qp->sq.max - 1);
1901
1902         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1903                 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1904                         nreq = 0;
1905
1906                         doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1907                                                   ((qp->sq.head & 0xffff) << 8) |
1908                                                   f0 | op0);
1909                         doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1910
1911                         qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1912                         size0 = 0;
1913
1914                         /*
1915                          * Make sure that descriptors are written before
1916                          * doorbell record.
1917                          */
1918                         wmb();
1919                         *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1920
1921                         /*
1922                          * Make sure doorbell record is written before we
1923                          * write MMIO send doorbell.
1924                          */
1925                         wmb();
1926                         mthca_write64(doorbell,
1927                                       dev->kar + MTHCA_SEND_DOORBELL,
1928                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1929                 }
1930
1931                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1932                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1933                                         " %d max, %d nreq)\n", qp->qpn,
1934                                         qp->sq.head, qp->sq.tail,
1935                                         qp->sq.max, nreq);
1936                         err = -ENOMEM;
1937                         *bad_wr = wr;
1938                         goto out;
1939                 }
1940
1941                 wqe = get_send_wqe(qp, ind);
1942                 prev_wqe = qp->sq.last;
1943                 qp->sq.last = wqe;
1944
1945                 ((struct mthca_next_seg *) wqe)->flags =
1946                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1947                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1948                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1949                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1950                         cpu_to_be32(1);
1951                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1952                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1953                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1954
1955                 wqe += sizeof (struct mthca_next_seg);
1956                 size = sizeof (struct mthca_next_seg) / 16;
1957
1958                 switch (qp->transport) {
1959                 case RC:
1960                         switch (wr->opcode) {
1961                         case IB_WR_ATOMIC_CMP_AND_SWP:
1962                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1963                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1964                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1965                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1966                                         cpu_to_be32(wr->wr.atomic.rkey);
1967                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1968
1969                                 wqe += sizeof (struct mthca_raddr_seg);
1970
1971                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1972                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1973                                                 cpu_to_be64(wr->wr.atomic.swap);
1974                                         ((struct mthca_atomic_seg *) wqe)->compare =
1975                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1976                                 } else {
1977                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1978                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1979                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1980                                 }
1981
1982                                 wqe += sizeof (struct mthca_atomic_seg);
1983                                 size += (sizeof (struct mthca_raddr_seg) +
1984                                          sizeof (struct mthca_atomic_seg)) / 16;
1985                                 break;
1986
1987                         case IB_WR_RDMA_READ:
1988                         case IB_WR_RDMA_WRITE:
1989                         case IB_WR_RDMA_WRITE_WITH_IMM:
1990                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1991                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1992                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1993                                         cpu_to_be32(wr->wr.rdma.rkey);
1994                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1995                                 wqe += sizeof (struct mthca_raddr_seg);
1996                                 size += sizeof (struct mthca_raddr_seg) / 16;
1997                                 break;
1998
1999                         default:
2000                                 /* No extra segments required for sends */
2001                                 break;
2002                         }
2003
2004                         break;
2005
2006                 case UC:
2007                         switch (wr->opcode) {
2008                         case IB_WR_RDMA_WRITE:
2009                         case IB_WR_RDMA_WRITE_WITH_IMM:
2010                                 ((struct mthca_raddr_seg *) wqe)->raddr =
2011                                         cpu_to_be64(wr->wr.rdma.remote_addr);
2012                                 ((struct mthca_raddr_seg *) wqe)->rkey =
2013                                         cpu_to_be32(wr->wr.rdma.rkey);
2014                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
2015                                 wqe += sizeof (struct mthca_raddr_seg);
2016                                 size += sizeof (struct mthca_raddr_seg) / 16;
2017                                 break;
2018
2019                         default:
2020                                 /* No extra segments required for sends */
2021                                 break;
2022                         }
2023
2024                         break;
2025
2026                 case UD:
2027                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
2028                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
2029                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
2030                                 cpu_to_be32(wr->wr.ud.remote_qpn);
2031                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
2032                                 cpu_to_be32(wr->wr.ud.remote_qkey);
2033
2034                         wqe += sizeof (struct mthca_arbel_ud_seg);
2035                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
2036                         break;
2037
2038                 case MLX:
2039                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
2040                                                wqe - sizeof (struct mthca_next_seg),
2041                                                wqe);
2042                         if (err) {
2043                                 *bad_wr = wr;
2044                                 goto out;
2045                         }
2046                         wqe += sizeof (struct mthca_data_seg);
2047                         size += sizeof (struct mthca_data_seg) / 16;
2048                         break;
2049                 }
2050
2051                 if (wr->num_sge > qp->sq.max_gs) {
2052                         mthca_err(dev, "too many gathers\n");
2053                         err = -EINVAL;
2054                         *bad_wr = wr;
2055                         goto out;
2056                 }
2057
2058                 for (i = 0; i < wr->num_sge; ++i) {
2059                         ((struct mthca_data_seg *) wqe)->byte_count =
2060                                 cpu_to_be32(wr->sg_list[i].length);
2061                         ((struct mthca_data_seg *) wqe)->lkey =
2062                                 cpu_to_be32(wr->sg_list[i].lkey);
2063                         ((struct mthca_data_seg *) wqe)->addr =
2064                                 cpu_to_be64(wr->sg_list[i].addr);
2065                         wqe += sizeof (struct mthca_data_seg);
2066                         size += sizeof (struct mthca_data_seg) / 16;
2067                 }
2068
2069                 /* Add one more inline data segment for ICRC */
2070                 if (qp->transport == MLX) {
2071                         ((struct mthca_data_seg *) wqe)->byte_count =
2072                                 cpu_to_be32((1 << 31) | 4);
2073                         ((u32 *) wqe)[1] = 0;
2074                         wqe += sizeof (struct mthca_data_seg);
2075                         size += sizeof (struct mthca_data_seg) / 16;
2076                 }
2077
2078                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2079
2080                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2081                         mthca_err(dev, "opcode invalid\n");
2082                         err = -EINVAL;
2083                         *bad_wr = wr;
2084                         goto out;
2085                 }
2086
2087                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2088                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
2089                                      qp->send_wqe_offset) |
2090                                     mthca_opcode[wr->opcode]);
2091                 wmb();
2092                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2093                         cpu_to_be32(MTHCA_NEXT_DBD | size |
2094                                     ((wr->send_flags & IB_SEND_FENCE) ?
2095                                      MTHCA_NEXT_FENCE : 0));
2096
2097                 if (!size0) {
2098                         size0 = size;
2099                         op0   = mthca_opcode[wr->opcode];
2100                         f0    = wr->send_flags & IB_SEND_FENCE ?
2101                                 MTHCA_SEND_DOORBELL_FENCE : 0;
2102                 }
2103
2104                 ++ind;
2105                 if (unlikely(ind >= qp->sq.max))
2106                         ind -= qp->sq.max;
2107         }
2108
2109 out:
2110         if (likely(nreq)) {
2111                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
2112                                           ((qp->sq.head & 0xffff) << 8) |
2113                                           f0 | op0);
2114                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2115
2116                 qp->sq.head += nreq;
2117
2118                 /*
2119                  * Make sure that descriptors are written before
2120                  * doorbell record.
2121                  */
2122                 wmb();
2123                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2124
2125                 /*
2126                  * Make sure doorbell record is written before we
2127                  * write MMIO send doorbell.
2128                  */
2129                 wmb();
2130                 mthca_write64(doorbell,
2131                               dev->kar + MTHCA_SEND_DOORBELL,
2132                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2133         }
2134
2135         /*
2136          * Make sure doorbells don't leak out of SQ spinlock and reach
2137          * the HCA out of order:
2138          */
2139         mmiowb();
2140
2141         spin_unlock_irqrestore(&qp->sq.lock, flags);
2142         return err;
2143 }
2144
2145 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2146                              struct ib_recv_wr **bad_wr)
2147 {
2148         struct mthca_dev *dev = to_mdev(ibqp->device);
2149         struct mthca_qp *qp = to_mqp(ibqp);
2150         unsigned long flags;
2151         int err = 0;
2152         int nreq;
2153         int ind;
2154         int i;
2155         void *wqe;
2156
2157         spin_lock_irqsave(&qp->rq.lock, flags);
2158
2159         /* XXX check that state is OK to post receive */
2160
2161         ind = qp->rq.head & (qp->rq.max - 1);
2162
2163         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2164                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2165                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2166                                         " %d max, %d nreq)\n", qp->qpn,
2167                                         qp->rq.head, qp->rq.tail,
2168                                         qp->rq.max, nreq);
2169                         err = -ENOMEM;
2170                         *bad_wr = wr;
2171                         goto out;
2172                 }
2173
2174                 wqe = get_recv_wqe(qp, ind);
2175
2176                 ((struct mthca_next_seg *) wqe)->flags = 0;
2177
2178                 wqe += sizeof (struct mthca_next_seg);
2179
2180                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2181                         err = -EINVAL;
2182                         *bad_wr = wr;
2183                         goto out;
2184                 }
2185
2186                 for (i = 0; i < wr->num_sge; ++i) {
2187                         ((struct mthca_data_seg *) wqe)->byte_count =
2188                                 cpu_to_be32(wr->sg_list[i].length);
2189                         ((struct mthca_data_seg *) wqe)->lkey =
2190                                 cpu_to_be32(wr->sg_list[i].lkey);
2191                         ((struct mthca_data_seg *) wqe)->addr =
2192                                 cpu_to_be64(wr->sg_list[i].addr);
2193                         wqe += sizeof (struct mthca_data_seg);
2194                 }
2195
2196                 if (i < qp->rq.max_gs) {
2197                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2198                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2199                         ((struct mthca_data_seg *) wqe)->addr = 0;
2200                 }
2201
2202                 qp->wrid[ind] = wr->wr_id;
2203
2204                 ++ind;
2205                 if (unlikely(ind >= qp->rq.max))
2206                         ind -= qp->rq.max;
2207         }
2208 out:
2209         if (likely(nreq)) {
2210                 qp->rq.head += nreq;
2211
2212                 /*
2213                  * Make sure that descriptors are written before
2214                  * doorbell record.
2215                  */
2216                 wmb();
2217                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2218         }
2219
2220         spin_unlock_irqrestore(&qp->rq.lock, flags);
2221         return err;
2222 }
2223
2224 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2225                         int index, int *dbd, __be32 *new_wqe)
2226 {
2227         struct mthca_next_seg *next;
2228
2229         /*
2230          * For SRQs, all WQEs generate a CQE, so we're always at the
2231          * end of the doorbell chain.
2232          */
2233         if (qp->ibqp.srq) {
2234                 *new_wqe = 0;
2235                 return;
2236         }
2237
2238         if (is_send)
2239                 next = get_send_wqe(qp, index);
2240         else
2241                 next = get_recv_wqe(qp, index);
2242
2243         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2244         if (next->ee_nds & cpu_to_be32(0x3f))
2245                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2246                         (next->ee_nds & cpu_to_be32(0x3f));
2247         else
2248                 *new_wqe = 0;
2249 }
2250
2251 int mthca_init_qp_table(struct mthca_dev *dev)
2252 {
2253         int err;
2254         u8 status;
2255         int i;
2256
2257         spin_lock_init(&dev->qp_table.lock);
2258
2259         /*
2260          * We reserve 2 extra QPs per port for the special QPs.  The
2261          * special QP for port 1 has to be even, so round up.
2262          */
2263         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2264         err = mthca_alloc_init(&dev->qp_table.alloc,
2265                                dev->limits.num_qps,
2266                                (1 << 24) - 1,
2267                                dev->qp_table.sqp_start +
2268                                MTHCA_MAX_PORTS * 2);
2269         if (err)
2270                 return err;
2271
2272         err = mthca_array_init(&dev->qp_table.qp,
2273                                dev->limits.num_qps);
2274         if (err) {
2275                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2276                 return err;
2277         }
2278
2279         for (i = 0; i < 2; ++i) {
2280                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2281                                             dev->qp_table.sqp_start + i * 2,
2282                                             &status);
2283                 if (err)
2284                         goto err_out;
2285                 if (status) {
2286                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2287                                    "status %02x, aborting.\n",
2288                                    status);
2289                         err = -EINVAL;
2290                         goto err_out;
2291                 }
2292         }
2293         return 0;
2294
2295  err_out:
2296         for (i = 0; i < 2; ++i)
2297                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2298
2299         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2300         mthca_alloc_cleanup(&dev->qp_table.alloc);
2301
2302         return err;
2303 }
2304
2305 void mthca_cleanup_qp_table(struct mthca_dev *dev)
2306 {
2307         int i;
2308         u8 status;
2309
2310         for (i = 0; i < 2; ++i)
2311                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2312
2313         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2314         mthca_alloc_cleanup(&dev->qp_table.alloc);
2315 }