drivers/infiniband/hw/mthca/mthca_cq.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006 Cisco Systems, Inc. All rights reserved.
   5  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   6  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   7  *
   8  * This software is available to you under a choice of one of two
   9  * licenses.  You may choose to be licensed under the terms of the GNU
  10  * General Public License (GPL) Version 2, available from the file
  11  * COPYING in the main directory of this source tree, or the
  12  * OpenIB.org BSD license below:
  13  *
  14  *     Redistribution and use in source and binary forms, with or
  15  *     without modification, are permitted provided that the following
  16  *     conditions are met:
  17  *
  18  *      - Redistributions of source code must retain the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer.
  21  *
  22  *      - Redistributions in binary form must reproduce the above
  23  *        copyright notice, this list of conditions and the following
  24  *        disclaimer in the documentation and/or other materials
  25  *        provided with the distribution.
  26  *
  27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  34  * SOFTWARE.
  35  *
  36  * $Id: mthca_cq.c 1369 2004-12-20 16:17:07Z roland $
  37  */
  38
  39 #include <linux/init.h>
  40 #include <linux/hardirq.h>
  41
  42 #include <asm/io.h>
  43
  44 #include <rdma/ib_pack.h>
  45
  46 #include "mthca_dev.h"
  47 #include "mthca_cmd.h"
  48 #include "mthca_memfree.h"
  49
  50 enum {
  51         MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE
  52 };
  53
  54 enum {
  55         MTHCA_CQ_ENTRY_SIZE = 0x20
  56 };
  57
  58 /*
  59  * Must be packed because start is 64 bits but only aligned to 32 bits.
  60  */
  61 struct mthca_cq_context {
  62         __be32 flags;
  63         __be64 start;
  64         __be32 logsize_usrpage;
  65         __be32 error_eqn;       /* Tavor only */
  66         __be32 comp_eqn;
  67         __be32 pd;
  68         __be32 lkey;
  69         __be32 last_notified_index;
  70         __be32 solicit_producer_index;
  71         __be32 consumer_index;
  72         __be32 producer_index;
  73         __be32 cqn;
  74         __be32 ci_db;           /* Arbel only */
  75         __be32 state_db;        /* Arbel only */
  76         u32    reserved;
  77 } __attribute__((packed));
  78
  79 #define MTHCA_CQ_STATUS_OK          ( 0 << 28)
  80 #define MTHCA_CQ_STATUS_OVERFLOW    ( 9 << 28)
  81 #define MTHCA_CQ_STATUS_WRITE_FAIL  (10 << 28)
  82 #define MTHCA_CQ_FLAG_TR            ( 1 << 18)
  83 #define MTHCA_CQ_FLAG_OI            ( 1 << 17)
  84 #define MTHCA_CQ_STATE_DISARMED     ( 0 <<  8)
  85 #define MTHCA_CQ_STATE_ARMED        ( 1 <<  8)
  86 #define MTHCA_CQ_STATE_ARMED_SOL    ( 4 <<  8)
  87 #define MTHCA_EQ_STATE_FIRED        (10 <<  8)
  88
  89 enum {
  90         MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe
  91 };
  92
  93 enum {
  94         SYNDROME_LOCAL_LENGTH_ERR        = 0x01,
  95         SYNDROME_LOCAL_QP_OP_ERR         = 0x02,
  96         SYNDROME_LOCAL_EEC_OP_ERR        = 0x03,
  97         SYNDROME_LOCAL_PROT_ERR          = 0x04,
  98         SYNDROME_WR_FLUSH_ERR            = 0x05,
  99         SYNDROME_MW_BIND_ERR             = 0x06,
 100         SYNDROME_BAD_RESP_ERR            = 0x10,
 101         SYNDROME_LOCAL_ACCESS_ERR        = 0x11,
 102         SYNDROME_REMOTE_INVAL_REQ_ERR    = 0x12,
 103         SYNDROME_REMOTE_ACCESS_ERR       = 0x13,
 104         SYNDROME_REMOTE_OP_ERR           = 0x14,
 105         SYNDROME_RETRY_EXC_ERR           = 0x15,
 106         SYNDROME_RNR_RETRY_EXC_ERR       = 0x16,
 107         SYNDROME_LOCAL_RDD_VIOL_ERR      = 0x20,
 108         SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21,
 109         SYNDROME_REMOTE_ABORTED_ERR      = 0x22,
 110         SYNDROME_INVAL_EECN_ERR          = 0x23,
 111         SYNDROME_INVAL_EEC_STATE_ERR     = 0x24
 112 };
 113
 114 struct mthca_cqe {
 115         __be32 my_qpn;
 116         __be32 my_ee;
 117         __be32 rqpn;
 118         __be16 sl_g_mlpath;
 119         __be16 rlid;
 120         __be32 imm_etype_pkey_eec;
 121         __be32 byte_cnt;
 122         __be32 wqe;
 123         u8     opcode;
 124         u8     is_send;
 125         u8     reserved;
 126         u8     owner;
 127 };
 128
 129 struct mthca_err_cqe {
 130         __be32 my_qpn;
 131         u32    reserved1[3];
 132         u8     syndrome;
 133         u8     vendor_err;
 134         __be16 db_cnt;
 135         u32    reserved2;
 136         __be32 wqe;
 137         u8     opcode;
 138         u8     reserved3[2];
 139         u8     owner;
 140 };
 141
 142 #define MTHCA_CQ_ENTRY_OWNER_SW      (0 << 7)
 143 #define MTHCA_CQ_ENTRY_OWNER_HW      (1 << 7)
 144
 145 #define MTHCA_TAVOR_CQ_DB_INC_CI       (1 << 24)
 146 #define MTHCA_TAVOR_CQ_DB_REQ_NOT      (2 << 24)
 147 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL  (3 << 24)
 148 #define MTHCA_TAVOR_CQ_DB_SET_CI       (4 << 24)
 149 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24)
 150
 151 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL  (1 << 24)
 152 #define MTHCA_ARBEL_CQ_DB_REQ_NOT      (2 << 24)
 153 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24)
 154
 155 static inline struct mthca_cqe *get_cqe_from_buf(struct mthca_cq_buf *buf,
 156                                                  int entry)
 157 {
 158         if (buf->is_direct)
 159                 return buf->queue.direct.buf + (entry * MTHCA_CQ_ENTRY_SIZE);
 160         else
 161                 return buf->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].buf
 162                         + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE;
 163 }
 164
 165 static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry)
 166 {
 167         return get_cqe_from_buf(&cq->buf, entry);
 168 }
 169
 170 static inline struct mthca_cqe *cqe_sw(struct mthca_cqe *cqe)
 171 {
 172         return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe;
 173 }
 174
 175 static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq)
 176 {
 177         return cqe_sw(get_cqe(cq, cq->cons_index & cq->ibcq.cqe));
 178 }
 179
 180 static inline void set_cqe_hw(struct mthca_cqe *cqe)
 181 {
 182         cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW;
 183 }
 184
 185 static void dump_cqe(struct mthca_dev *dev, void *cqe_ptr)
 186 {
 187         __be32 *cqe = cqe_ptr;
 188
 189         (void) cqe;     /* avoid warning if mthca_dbg compiled away... */
 190         mthca_dbg(dev, "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
 191                   be32_to_cpu(cqe[0]), be32_to_cpu(cqe[1]), be32_to_cpu(cqe[2]),
 192                   be32_to_cpu(cqe[3]), be32_to_cpu(cqe[4]), be32_to_cpu(cqe[5]),
 193                   be32_to_cpu(cqe[6]), be32_to_cpu(cqe[7]));
 194 }
 195
 196 /*
 197  * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index
 198  * should be correct before calling update_cons_index().
 199  */
 200 static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq,
 201                                      int incr)
 202 {
 203         __be32 doorbell[2];
 204
 205         if (mthca_is_memfree(dev)) {
 206                 *cq->set_ci_db = cpu_to_be32(cq->cons_index);
 207                 wmb();
 208         } else {
 209                 doorbell[0] = cpu_to_be32(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn);
 210                 doorbell[1] = cpu_to_be32(incr - 1);
 211
 212                 mthca_write64(doorbell,
 213                               dev->kar + MTHCA_CQ_DOORBELL,
 214                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
 215                 /*
 216                  * Make sure doorbells don't leak out of CQ spinlock
 217                  * and reach the HCA out of order:
 218                  */
 219                 mmiowb();
 220         }
 221 }
 222
 223 void mthca_cq_completion(struct mthca_dev *dev, u32 cqn)
 224 {
 225         struct mthca_cq *cq;
 226
 227         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
 228
 229         if (!cq) {
 230                 mthca_warn(dev, "Completion event for bogus CQ %08x\n", cqn);
 231                 return;
 232         }
 233
 234         ++cq->arm_sn;
 235
 236         cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
 237 }
 238
 239 void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
 240                     enum ib_event_type event_type)
 241 {
 242         struct mthca_cq *cq;
 243         struct ib_event event;
 244
 245         spin_lock(&dev->cq_table.lock);
 246
 247         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
 248         if (cq)
 249                 ++cq->refcount;
 250
 251         spin_unlock(&dev->cq_table.lock);
 252
 253         if (!cq) {
 254                 mthca_warn(dev, "Async event for bogus CQ %08x\n", cqn);
 255                 return;
 256         }
 257
 258         event.device      = &dev->ib_dev;
 259         event.event       = event_type;
 260         event.element.cq  = &cq->ibcq;
 261         if (cq->ibcq.event_handler)
 262                 cq->ibcq.event_handler(&event, cq->ibcq.cq_context);
 263
 264         spin_lock(&dev->cq_table.lock);
 265         if (!--cq->refcount)
 266                 wake_up(&cq->wait);
 267         spin_unlock(&dev->cq_table.lock);
 268 }
 269
 270 static inline int is_recv_cqe(struct mthca_cqe *cqe)
 271 {
 272         if ((cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
 273             MTHCA_ERROR_CQE_OPCODE_MASK)
 274                 return !(cqe->opcode & 0x01);
 275         else
 276                 return !(cqe->is_send & 0x80);
 277 }
 278
 279 void mthca_cq_clean(struct mthca_dev *dev, struct mthca_cq *cq, u32 qpn,
 280                     struct mthca_srq *srq)
 281 {
 282         struct mthca_cqe *cqe;
 283         u32 prod_index;
 284         int nfreed = 0;
 285
 286         spin_lock_irq(&cq->lock);
 287
 288         /*
 289          * First we need to find the current producer index, so we
 290          * know where to start cleaning from.  It doesn't matter if HW
 291          * adds new entries after this loop -- the QP we're worried
 292          * about is already in RESET, so the new entries won't come
 293          * from our QP and therefore don't need to be checked.
 294          */
 295         for (prod_index = cq->cons_index;
 296              cqe_sw(get_cqe(cq, prod_index & cq->ibcq.cqe));
 297              ++prod_index)
 298                 if (prod_index == cq->cons_index + cq->ibcq.cqe)
 299                         break;
 300
 301         if (0)
 302                 mthca_dbg(dev, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n",
 303                           qpn, cq->cqn, cq->cons_index, prod_index);
 304
 305         /*
 306          * Now sweep backwards through the CQ, removing CQ entries
 307          * that match our QP by copying older entries on top of them.
 308          */
 309         while ((int) --prod_index - (int) cq->cons_index >= 0) {
 310                 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
 311                 if (cqe->my_qpn == cpu_to_be32(qpn)) {
 312                         if (srq && is_recv_cqe(cqe))
 313                                 mthca_free_srq_wqe(srq, be32_to_cpu(cqe->wqe));
 314                         ++nfreed;
 315                 } else if (nfreed)
 316                         memcpy(get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe),
 317                                cqe, MTHCA_CQ_ENTRY_SIZE);
 318         }
 319
 320         if (nfreed) {
 321                 wmb();
 322                 cq->cons_index += nfreed;
 323                 update_cons_index(dev, cq, nfreed);
 324         }
 325
 326         spin_unlock_irq(&cq->lock);
 327 }
 328
 329 void mthca_cq_resize_copy_cqes(struct mthca_cq *cq)
 330 {
 331         int i;
 332
 333         /*
 334          * In Tavor mode, the hardware keeps the consumer and producer
 335          * indices mod the CQ size.  Since we might be making the CQ
 336          * bigger, we need to deal with the case where the producer
 337          * index wrapped around before the CQ was resized.
 338          */
 339         if (!mthca_is_memfree(to_mdev(cq->ibcq.device)) &&
 340             cq->ibcq.cqe < cq->resize_buf->cqe) {
 341                 cq->cons_index &= cq->ibcq.cqe;
 342                 if (cqe_sw(get_cqe(cq, cq->ibcq.cqe)))
 343                         cq->cons_index -= cq->ibcq.cqe + 1;
 344         }
 345
 346         for (i = cq->cons_index; cqe_sw(get_cqe(cq, i & cq->ibcq.cqe)); ++i)
 347                 memcpy(get_cqe_from_buf(&cq->resize_buf->buf,
 348                                         i & cq->resize_buf->cqe),
 349                        get_cqe(cq, i & cq->ibcq.cqe), MTHCA_CQ_ENTRY_SIZE);
 350 }
 351
 352 int mthca_alloc_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int nent)
 353 {
 354         int ret;
 355         int i;
 356
 357         ret = mthca_buf_alloc(dev, nent * MTHCA_CQ_ENTRY_SIZE,
 358                               MTHCA_MAX_DIRECT_CQ_SIZE,
 359                               &buf->queue, &buf->is_direct,
 360                               &dev->driver_pd, 1, &buf->mr);
 361         if (ret)
 362                 return ret;
 363
 364         for (i = 0; i < nent; ++i)
 365                 set_cqe_hw(get_cqe_from_buf(buf, i));
 366
 367         return 0;
 368 }
 369
 370 void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int cqe)
 371 {
 372         mthca_buf_free(dev, (cqe + 1) * MTHCA_CQ_ENTRY_SIZE, &buf->queue,
 373                        buf->is_direct, &buf->mr);
 374 }
 375
 376 static void handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
 377                              struct mthca_qp *qp, int wqe_index, int is_send,
 378                              struct mthca_err_cqe *cqe,
 379                              struct ib_wc *entry, int *free_cqe)
 380 {
 381         int dbd;
 382         __be32 new_wqe;
 383
 384         if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) {
 385                 mthca_dbg(dev, "local QP operation err "
 386                           "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n",
 387                           be32_to_cpu(cqe->my_qpn), be32_to_cpu(cqe->wqe),
 388                           cq->cqn, cq->cons_index);
 389                 dump_cqe(dev, cqe);
 390         }
 391
 392         /*
 393          * For completions in error, only work request ID, status, vendor error
 394          * (and freed resource count for RD) have to be set.
 395          */
 396         switch (cqe->syndrome) {
 397         case SYNDROME_LOCAL_LENGTH_ERR:
 398                 entry->status = IB_WC_LOC_LEN_ERR;
 399                 break;
 400         case SYNDROME_LOCAL_QP_OP_ERR:
 401                 entry->status = IB_WC_LOC_QP_OP_ERR;
 402                 break;
 403         case SYNDROME_LOCAL_EEC_OP_ERR:
 404                 entry->status = IB_WC_LOC_EEC_OP_ERR;
 405                 break;
 406         case SYNDROME_LOCAL_PROT_ERR:
 407                 entry->status = IB_WC_LOC_PROT_ERR;
 408                 break;
 409         case SYNDROME_WR_FLUSH_ERR:
 410                 entry->status = IB_WC_WR_FLUSH_ERR;
 411                 break;
 412         case SYNDROME_MW_BIND_ERR:
 413                 entry->status = IB_WC_MW_BIND_ERR;
 414                 break;
 415         case SYNDROME_BAD_RESP_ERR:
 416                 entry->status = IB_WC_BAD_RESP_ERR;
 417                 break;
 418         case SYNDROME_LOCAL_ACCESS_ERR:
 419                 entry->status = IB_WC_LOC_ACCESS_ERR;
 420                 break;
 421         case SYNDROME_REMOTE_INVAL_REQ_ERR:
 422                 entry->status = IB_WC_REM_INV_REQ_ERR;
 423                 break;
 424         case SYNDROME_REMOTE_ACCESS_ERR:
 425                 entry->status = IB_WC_REM_ACCESS_ERR;
 426                 break;
 427         case SYNDROME_REMOTE_OP_ERR:
 428                 entry->status = IB_WC_REM_OP_ERR;
 429                 break;
 430         case SYNDROME_RETRY_EXC_ERR:
 431                 entry->status = IB_WC_RETRY_EXC_ERR;
 432                 break;
 433         case SYNDROME_RNR_RETRY_EXC_ERR:
 434                 entry->status = IB_WC_RNR_RETRY_EXC_ERR;
 435                 break;
 436         case SYNDROME_LOCAL_RDD_VIOL_ERR:
 437                 entry->status = IB_WC_LOC_RDD_VIOL_ERR;
 438                 break;
 439         case SYNDROME_REMOTE_INVAL_RD_REQ_ERR:
 440                 entry->status = IB_WC_REM_INV_RD_REQ_ERR;
 441                 break;
 442         case SYNDROME_REMOTE_ABORTED_ERR:
 443                 entry->status = IB_WC_REM_ABORT_ERR;
 444                 break;
 445         case SYNDROME_INVAL_EECN_ERR:
 446                 entry->status = IB_WC_INV_EECN_ERR;
 447                 break;
 448         case SYNDROME_INVAL_EEC_STATE_ERR:
 449                 entry->status = IB_WC_INV_EEC_STATE_ERR;
 450                 break;
 451         default:
 452                 entry->status = IB_WC_GENERAL_ERR;
 453                 break;
 454         }
 455
 456         entry->vendor_err = cqe->vendor_err;
 457
 458         /*
 459          * Mem-free HCAs always generate one CQE per WQE, even in the
 460          * error case, so we don't have to check the doorbell count, etc.
 461          */
 462         if (mthca_is_memfree(dev))
 463                 return;
 464
 465         mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe);
 466
 467         /*
 468          * If we're at the end of the WQE chain, or we've used up our
 469          * doorbell count, free the CQE.  Otherwise just update it for
 470          * the next poll operation.
 471          */
 472         if (!(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd))
 473                 return;
 474
 475         cqe->db_cnt   = cpu_to_be16(be16_to_cpu(cqe->db_cnt) - dbd);
 476         cqe->wqe      = new_wqe;
 477         cqe->syndrome = SYNDROME_WR_FLUSH_ERR;
 478
 479         *free_cqe = 0;
 480 }
 481
 482 static inline int mthca_poll_one(struct mthca_dev *dev,
 483                                  struct mthca_cq *cq,
 484                                  struct mthca_qp **cur_qp,
 485                                  int *freed,
 486                                  struct ib_wc *entry)
 487 {
 488         struct mthca_wq *wq;
 489         struct mthca_cqe *cqe;
 490         int wqe_index;
 491         int is_error;
 492         int is_send;
 493         int free_cqe = 1;
 494         int err = 0;
 495
 496         cqe = next_cqe_sw(cq);
 497         if (!cqe)
 498                 return -EAGAIN;
 499
 500         /*
 501          * Make sure we read CQ entry contents after we've checked the
 502          * ownership bit.
 503          */
 504         rmb();
 505
 506         if (0) {
 507                 mthca_dbg(dev, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n",
 508                           cq->cqn, cq->cons_index, be32_to_cpu(cqe->my_qpn),
 509                           be32_to_cpu(cqe->wqe));
 510                 dump_cqe(dev, cqe);
 511         }
 512
 513         is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
 514                 MTHCA_ERROR_CQE_OPCODE_MASK;
 515         is_send  = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80;
 516
 517         if (!*cur_qp || be32_to_cpu(cqe->my_qpn) != (*cur_qp)->qpn) {
 518                 /*
 519                  * We do not have to take the QP table lock here,
 520                  * because CQs will be locked while QPs are removed
 521                  * from the table.
 522                  */
 523                 *cur_qp = mthca_array_get(&dev->qp_table.qp,
 524                                           be32_to_cpu(cqe->my_qpn) &
 525                                           (dev->limits.num_qps - 1));
 526                 if (!*cur_qp) {
 527                         mthca_warn(dev, "CQ entry for unknown QP %06x\n",
 528                                    be32_to_cpu(cqe->my_qpn) & 0xffffff);
 529                         err = -EINVAL;
 530                         goto out;
 531                 }
 532         }
 533
 534         entry->qp_num = (*cur_qp)->qpn;
 535
 536         if (is_send) {
 537                 wq = &(*cur_qp)->sq;
 538                 wqe_index = ((be32_to_cpu(cqe->wqe) - (*cur_qp)->send_wqe_offset)
 539                              >> wq->wqe_shift);
 540                 entry->wr_id = (*cur_qp)->wrid[wqe_index +
 541                                                (*cur_qp)->rq.max];
 542         } else if ((*cur_qp)->ibqp.srq) {
 543                 struct mthca_srq *srq = to_msrq((*cur_qp)->ibqp.srq);
 544                 u32 wqe = be32_to_cpu(cqe->wqe);
 545                 wq = NULL;
 546                 wqe_index = wqe >> srq->wqe_shift;
 547                 entry->wr_id = srq->wrid[wqe_index];
 548                 mthca_free_srq_wqe(srq, wqe);
 549         } else {
 550                 s32 wqe;
 551                 wq = &(*cur_qp)->rq;
 552                 wqe = be32_to_cpu(cqe->wqe);
 553                 wqe_index = wqe >> wq->wqe_shift;
 554                 /*
 555                  * WQE addr == base - 1 might be reported in receive completion
 556                  * with error instead of (rq size - 1) by Sinai FW 1.0.800 and
 557                  * Arbel FW 5.1.400.  This bug should be fixed in later FW revs.
 558                  */
 559                 if (unlikely(wqe_index < 0))
 560                         wqe_index = wq->max - 1;
 561                 entry->wr_id = (*cur_qp)->wrid[wqe_index];
 562         }
 563
 564         if (wq) {
 565                 if (wq->last_comp < wqe_index)
 566                         wq->tail += wqe_index - wq->last_comp;
 567                 else
 568                         wq->tail += wqe_index + wq->max - wq->last_comp;
 569
 570                 wq->last_comp = wqe_index;
 571         }
 572
 573         if (is_error) {
 574                 handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send,
 575                                  (struct mthca_err_cqe *) cqe,
 576                                  entry, &free_cqe);
 577                 goto out;
 578         }
 579
 580         if (is_send) {
 581                 entry->wc_flags = 0;
 582                 switch (cqe->opcode) {
 583                 case MTHCA_OPCODE_RDMA_WRITE:
 584                         entry->opcode    = IB_WC_RDMA_WRITE;
 585                         break;
 586                 case MTHCA_OPCODE_RDMA_WRITE_IMM:
 587                         entry->opcode    = IB_WC_RDMA_WRITE;
 588                         entry->wc_flags |= IB_WC_WITH_IMM;
 589                         break;
 590                 case MTHCA_OPCODE_SEND:
 591                         entry->opcode    = IB_WC_SEND;
 592                         break;
 593                 case MTHCA_OPCODE_SEND_IMM:
 594                         entry->opcode    = IB_WC_SEND;
 595                         entry->wc_flags |= IB_WC_WITH_IMM;
 596                         break;
 597                 case MTHCA_OPCODE_RDMA_READ:
 598                         entry->opcode    = IB_WC_RDMA_READ;
 599                         entry->byte_len  = be32_to_cpu(cqe->byte_cnt);
 600                         break;
 601                 case MTHCA_OPCODE_ATOMIC_CS:
 602                         entry->opcode    = IB_WC_COMP_SWAP;
 603                         entry->byte_len  = be32_to_cpu(cqe->byte_cnt);
 604                         break;
 605                 case MTHCA_OPCODE_ATOMIC_FA:
 606                         entry->opcode    = IB_WC_FETCH_ADD;
 607                         entry->byte_len  = be32_to_cpu(cqe->byte_cnt);
 608                         break;
 609                 case MTHCA_OPCODE_BIND_MW:
 610                         entry->opcode    = IB_WC_BIND_MW;
 611                         break;
 612                 default:
 613                         entry->opcode    = MTHCA_OPCODE_INVALID;
 614                         break;
 615                 }
 616         } else {
 617                 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
 618                 switch (cqe->opcode & 0x1f) {
 619                 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE:
 620                 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE:
 621                         entry->wc_flags = IB_WC_WITH_IMM;
 622                         entry->imm_data = cqe->imm_etype_pkey_eec;
 623                         entry->opcode = IB_WC_RECV;
 624                         break;
 625                 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE:
 626                 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE:
 627                         entry->wc_flags = IB_WC_WITH_IMM;
 628                         entry->imm_data = cqe->imm_etype_pkey_eec;
 629                         entry->opcode = IB_WC_RECV_RDMA_WITH_IMM;
 630                         break;
 631                 default:
 632                         entry->wc_flags = 0;
 633                         entry->opcode = IB_WC_RECV;
 634                         break;
 635                 }
 636                 entry->slid        = be16_to_cpu(cqe->rlid);
 637                 entry->sl          = be16_to_cpu(cqe->sl_g_mlpath) >> 12;
 638                 entry->src_qp      = be32_to_cpu(cqe->rqpn) & 0xffffff;
 639                 entry->dlid_path_bits = be16_to_cpu(cqe->sl_g_mlpath) & 0x7f;
 640                 entry->pkey_index  = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16;
 641                 entry->wc_flags   |= be16_to_cpu(cqe->sl_g_mlpath) & 0x80 ?
 642                                         IB_WC_GRH : 0;
 643         }
 644
 645         entry->status = IB_WC_SUCCESS;
 646
 647  out:
 648         if (likely(free_cqe)) {
 649                 set_cqe_hw(cqe);
 650                 ++(*freed);
 651                 ++cq->cons_index;
 652         }
 653
 654         return err;
 655 }
 656
 657 int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
 658                   struct ib_wc *entry)
 659 {
 660         struct mthca_dev *dev = to_mdev(ibcq->device);
 661         struct mthca_cq *cq = to_mcq(ibcq);
 662         struct mthca_qp *qp = NULL;
 663         unsigned long flags;
 664         int err = 0;
 665         int freed = 0;
 666         int npolled;
 667
 668         spin_lock_irqsave(&cq->lock, flags);
 669
 670         npolled = 0;
 671 repoll:
 672         while (npolled < num_entries) {
 673                 err = mthca_poll_one(dev, cq, &qp,
 674                                      &freed, entry + npolled);
 675                 if (err)
 676                         break;
 677                 ++npolled;
 678         }
 679
 680         if (freed) {
 681                 wmb();
 682                 update_cons_index(dev, cq, freed);
 683         }
 684
 685         /*
 686          * If a CQ resize is in progress and we discovered that the
 687          * old buffer is empty, then peek in the new buffer, and if
 688          * it's not empty, switch to the new buffer and continue
 689          * polling there.
 690          */
 691         if (unlikely(err == -EAGAIN && cq->resize_buf &&
 692                      cq->resize_buf->state == CQ_RESIZE_READY)) {
 693                 /*
 694                  * In Tavor mode, the hardware keeps the producer
 695                  * index modulo the CQ size.  Since we might be making
 696                  * the CQ bigger, we need to mask our consumer index
 697                  * using the size of the old CQ buffer before looking
 698                  * in the new CQ buffer.
 699                  */
 700                 if (!mthca_is_memfree(dev))
 701                         cq->cons_index &= cq->ibcq.cqe;
 702
 703                 if (cqe_sw(get_cqe_from_buf(&cq->resize_buf->buf,
 704                                             cq->cons_index & cq->resize_buf->cqe))) {
 705                         struct mthca_cq_buf tbuf;
 706                         int tcqe;
 707
 708                         tbuf         = cq->buf;
 709                         tcqe         = cq->ibcq.cqe;
 710                         cq->buf      = cq->resize_buf->buf;
 711                         cq->ibcq.cqe = cq->resize_buf->cqe;
 712
 713                         cq->resize_buf->buf   = tbuf;
 714                         cq->resize_buf->cqe   = tcqe;
 715                         cq->resize_buf->state = CQ_RESIZE_SWAPPED;
 716
 717                         goto repoll;
 718                 }
 719         }
 720
 721         spin_unlock_irqrestore(&cq->lock, flags);
 722
 723         return err == 0 || err == -EAGAIN ? npolled : err;
 724 }
 725
 726 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify)
 727 {
 728         __be32 doorbell[2];
 729
 730         doorbell[0] = cpu_to_be32((notify == IB_CQ_SOLICITED ?
 731                                    MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL :
 732                                    MTHCA_TAVOR_CQ_DB_REQ_NOT)      |
 733                                   to_mcq(cq)->cqn);
 734         doorbell[1] = (__force __be32) 0xffffffff;
 735
 736         mthca_write64(doorbell,
 737                       to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL,
 738                       MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock));
 739
 740         return 0;
 741 }
 742
 743 int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify notify)
 744 {
 745         struct mthca_cq *cq = to_mcq(ibcq);
 746         __be32 doorbell[2];
 747         u32 sn;
 748         __be32 ci;
 749
 750         sn = cq->arm_sn & 3;
 751         ci = cpu_to_be32(cq->cons_index);
 752
 753         doorbell[0] = ci;
 754         doorbell[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) |
 755                                   (notify == IB_CQ_SOLICITED ? 1 : 2));
 756
 757         mthca_write_db_rec(doorbell, cq->arm_db);
 758
 759         /*
 760          * Make sure that the doorbell record in host memory is
 761          * written before ringing the doorbell via PCI MMIO.
 762          */
 763         wmb();
 764
 765         doorbell[0] = cpu_to_be32((sn << 28)                       |
 766                                   (notify == IB_CQ_SOLICITED ?
 767                                    MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL :
 768                                    MTHCA_ARBEL_CQ_DB_REQ_NOT)      |
 769                                   cq->cqn);
 770         doorbell[1] = ci;
 771
 772         mthca_write64(doorbell,
 773                       to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL,
 774                       MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock));
 775
 776         return 0;
 777 }
 778
 779 int mthca_init_cq(struct mthca_dev *dev, int nent,
 780                   struct mthca_ucontext *ctx, u32 pdn,
 781                   struct mthca_cq *cq)
 782 {
 783         struct mthca_mailbox *mailbox;
 784         struct mthca_cq_context *cq_context;
 785         int err = -ENOMEM;
 786         u8 status;
 787
 788         cq->ibcq.cqe  = nent - 1;
 789         cq->is_kernel = !ctx;
 790
 791         cq->cqn = mthca_alloc(&dev->cq_table.alloc);
 792         if (cq->cqn == -1)
 793                 return -ENOMEM;
 794
 795         if (mthca_is_memfree(dev)) {
 796                 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn);
 797                 if (err)
 798                         goto err_out;
 799
 800                 if (cq->is_kernel) {
 801                         cq->arm_sn = 1;
 802
 803                         err = -ENOMEM;
 804
 805                         cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI,
 806                                                              cq->cqn, &cq->set_ci_db);
 807                         if (cq->set_ci_db_index < 0)
 808                                 goto err_out_icm;
 809
 810                         cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM,
 811                                                           cq->cqn, &cq->arm_db);
 812                         if (cq->arm_db_index < 0)
 813                                 goto err_out_ci;
 814                 }
 815         }
 816
 817         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 818         if (IS_ERR(mailbox))
 819                 goto err_out_arm;
 820
 821         cq_context = mailbox->buf;
 822
 823         if (cq->is_kernel) {
 824                 err = mthca_alloc_cq_buf(dev, &cq->buf, nent);
 825                 if (err)
 826                         goto err_out_mailbox;
 827         }
 828
 829         spin_lock_init(&cq->lock);
 830         cq->refcount = 1;
 831         init_waitqueue_head(&cq->wait);
 832         mutex_init(&cq->mutex);
 833
 834         memset(cq_context, 0, sizeof *cq_context);
 835         cq_context->flags           = cpu_to_be32(MTHCA_CQ_STATUS_OK      |
 836                                                   MTHCA_CQ_STATE_DISARMED |
 837                                                   MTHCA_CQ_FLAG_TR);
 838         cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24);
 839         if (ctx)
 840                 cq_context->logsize_usrpage |= cpu_to_be32(ctx->uar.index);
 841         else
 842                 cq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index);
 843         cq_context->error_eqn       = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn);
 844         cq_context->comp_eqn        = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn);
 845         cq_context->pd              = cpu_to_be32(pdn);
 846         cq_context->lkey            = cpu_to_be32(cq->buf.mr.ibmr.lkey);
 847         cq_context->cqn             = cpu_to_be32(cq->cqn);
 848
 849         if (mthca_is_memfree(dev)) {
 850                 cq_context->ci_db    = cpu_to_be32(cq->set_ci_db_index);
 851                 cq_context->state_db = cpu_to_be32(cq->arm_db_index);
 852         }
 853
 854         err = mthca_SW2HW_CQ(dev, mailbox, cq->cqn, &status);
 855         if (err) {
 856                 mthca_warn(dev, "SW2HW_CQ failed (%d)\n", err);
 857                 goto err_out_free_mr;
 858         }
 859
 860         if (status) {
 861                 mthca_warn(dev, "SW2HW_CQ returned status 0x%02x\n",
 862                            status);
 863                 err = -EINVAL;
 864                 goto err_out_free_mr;
 865         }
 866
 867         spin_lock_irq(&dev->cq_table.lock);
 868         if (mthca_array_set(&dev->cq_table.cq,
 869                             cq->cqn & (dev->limits.num_cqs - 1),
 870                             cq)) {
 871                 spin_unlock_irq(&dev->cq_table.lock);
 872                 goto err_out_free_mr;
 873         }
 874         spin_unlock_irq(&dev->cq_table.lock);
 875
 876         cq->cons_index = 0;
 877
 878         mthca_free_mailbox(dev, mailbox);
 879
 880         return 0;
 881
 882 err_out_free_mr:
 883         if (cq->is_kernel)
 884                 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
 885
 886 err_out_mailbox:
 887         mthca_free_mailbox(dev, mailbox);
 888
 889 err_out_arm:
 890         if (cq->is_kernel && mthca_is_memfree(dev))
 891                 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
 892
 893 err_out_ci:
 894         if (cq->is_kernel && mthca_is_memfree(dev))
 895                 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
 896
 897 err_out_icm:
 898         mthca_table_put(dev, dev->cq_table.table, cq->cqn);
 899
 900 err_out:
 901         mthca_free(&dev->cq_table.alloc, cq->cqn);
 902
 903         return err;
 904 }
 905
 906 static inline int get_cq_refcount(struct mthca_dev *dev, struct mthca_cq *cq)
 907 {
 908         int c;
 909
 910         spin_lock_irq(&dev->cq_table.lock);
 911         c = cq->refcount;
 912         spin_unlock_irq(&dev->cq_table.lock);
 913
 914         return c;
 915 }
 916
 917 void mthca_free_cq(struct mthca_dev *dev,
 918                    struct mthca_cq *cq)
 919 {
 920         struct mthca_mailbox *mailbox;
 921         int err;
 922         u8 status;
 923
 924         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 925         if (IS_ERR(mailbox)) {
 926                 mthca_warn(dev, "No memory for mailbox to free CQ.\n");
 927                 return;
 928         }
 929
 930         err = mthca_HW2SW_CQ(dev, mailbox, cq->cqn, &status);
 931         if (err)
 932                 mthca_warn(dev, "HW2SW_CQ failed (%d)\n", err);
 933         else if (status)
 934                 mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n", status);
 935
 936         if (0) {
 937                 __be32 *ctx = mailbox->buf;
 938                 int j;
 939
 940                 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n",
 941                        cq->cqn, cq->cons_index,
 942                        cq->is_kernel ? !!next_cqe_sw(cq) : 0);
 943                 for (j = 0; j < 16; ++j)
 944                         printk(KERN_ERR "[%2x] %08x\n", j * 4, be32_to_cpu(ctx[j]));
 945         }
 946
 947         spin_lock_irq(&dev->cq_table.lock);
 948         mthca_array_clear(&dev->cq_table.cq,
 949                           cq->cqn & (dev->limits.num_cqs - 1));
 950         --cq->refcount;
 951         spin_unlock_irq(&dev->cq_table.lock);
 952
 953         if (dev->mthca_flags & MTHCA_FLAG_MSI_X)
 954                 synchronize_irq(dev->eq_table.eq[MTHCA_EQ_COMP].msi_x_vector);
 955         else
 956                 synchronize_irq(dev->pdev->irq);
 957
 958         wait_event(cq->wait, !get_cq_refcount(dev, cq));
 959
 960         if (cq->is_kernel) {
 961                 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
 962                 if (mthca_is_memfree(dev)) {
 963                         mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM,    cq->arm_db_index);
 964                         mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
 965                 }
 966         }
 967
 968         mthca_table_put(dev, dev->cq_table.table, cq->cqn);
 969         mthca_free(&dev->cq_table.alloc, cq->cqn);
 970         mthca_free_mailbox(dev, mailbox);
 971 }
 972
 973 int __devinit mthca_init_cq_table(struct mthca_dev *dev)
 974 {
 975         int err;
 976
 977         spin_lock_init(&dev->cq_table.lock);
 978
 979         err = mthca_alloc_init(&dev->cq_table.alloc,
 980                                dev->limits.num_cqs,
 981                                (1 << 24) - 1,
 982                                dev->limits.reserved_cqs);
 983         if (err)
 984                 return err;
 985
 986         err = mthca_array_init(&dev->cq_table.cq,
 987                                dev->limits.num_cqs);
 988         if (err)
 989                 mthca_alloc_cleanup(&dev->cq_table.alloc);
 990
 991         return err;
 992 }
 993
 994 void mthca_cleanup_cq_table(struct mthca_dev *dev)
 995 {
 996         mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs);
 997         mthca_alloc_cleanup(&dev->cq_table.alloc);
 998 }