drivers/infiniband/hw/mthca/mthca_cmd.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  *
  34  * $Id: mthca_cmd.c 1349 2004-12-16 21:09:43Z roland $
  35  */
  36
  37 #include <linux/sched.h>
  38 #include <linux/pci.h>
  39 #include <linux/errno.h>
  40 #include <asm/io.h>
  41 #include <rdma/ib_mad.h>
  42
  43 #include "mthca_dev.h"
  44 #include "mthca_config_reg.h"
  45 #include "mthca_cmd.h"
  46 #include "mthca_memfree.h"
  47
  48 #define CMD_POLL_TOKEN 0xffff
  49
  50 enum {
  51         HCR_IN_PARAM_OFFSET    = 0x00,
  52         HCR_IN_MODIFIER_OFFSET = 0x08,
  53         HCR_OUT_PARAM_OFFSET   = 0x0c,
  54         HCR_TOKEN_OFFSET       = 0x14,
  55         HCR_STATUS_OFFSET      = 0x18,
  56
  57         HCR_OPMOD_SHIFT        = 12,
  58         HCA_E_BIT              = 22,
  59         HCR_GO_BIT             = 23
  60 };
  61
  62 enum {
  63         /* initialization and general commands */
  64         CMD_SYS_EN          = 0x1,
  65         CMD_SYS_DIS         = 0x2,
  66         CMD_MAP_FA          = 0xfff,
  67         CMD_UNMAP_FA        = 0xffe,
  68         CMD_RUN_FW          = 0xff6,
  69         CMD_MOD_STAT_CFG    = 0x34,
  70         CMD_QUERY_DEV_LIM   = 0x3,
  71         CMD_QUERY_FW        = 0x4,
  72         CMD_ENABLE_LAM      = 0xff8,
  73         CMD_DISABLE_LAM     = 0xff7,
  74         CMD_QUERY_DDR       = 0x5,
  75         CMD_QUERY_ADAPTER   = 0x6,
  76         CMD_INIT_HCA        = 0x7,
  77         CMD_CLOSE_HCA       = 0x8,
  78         CMD_INIT_IB         = 0x9,
  79         CMD_CLOSE_IB        = 0xa,
  80         CMD_QUERY_HCA       = 0xb,
  81         CMD_SET_IB          = 0xc,
  82         CMD_ACCESS_DDR      = 0x2e,
  83         CMD_MAP_ICM         = 0xffa,
  84         CMD_UNMAP_ICM       = 0xff9,
  85         CMD_MAP_ICM_AUX     = 0xffc,
  86         CMD_UNMAP_ICM_AUX   = 0xffb,
  87         CMD_SET_ICM_SIZE    = 0xffd,
  88
  89         /* TPT commands */
  90         CMD_SW2HW_MPT       = 0xd,
  91         CMD_QUERY_MPT       = 0xe,
  92         CMD_HW2SW_MPT       = 0xf,
  93         CMD_READ_MTT        = 0x10,
  94         CMD_WRITE_MTT       = 0x11,
  95         CMD_SYNC_TPT        = 0x2f,
  96
  97         /* EQ commands */
  98         CMD_MAP_EQ          = 0x12,
  99         CMD_SW2HW_EQ        = 0x13,
 100         CMD_HW2SW_EQ        = 0x14,
 101         CMD_QUERY_EQ        = 0x15,
 102
 103         /* CQ commands */
 104         CMD_SW2HW_CQ        = 0x16,
 105         CMD_HW2SW_CQ        = 0x17,
 106         CMD_QUERY_CQ        = 0x18,
 107         CMD_RESIZE_CQ       = 0x2c,
 108
 109         /* SRQ commands */
 110         CMD_SW2HW_SRQ       = 0x35,
 111         CMD_HW2SW_SRQ       = 0x36,
 112         CMD_QUERY_SRQ       = 0x37,
 113         CMD_ARM_SRQ         = 0x40,
 114
 115         /* QP/EE commands */
 116         CMD_RST2INIT_QPEE   = 0x19,
 117         CMD_INIT2RTR_QPEE   = 0x1a,
 118         CMD_RTR2RTS_QPEE    = 0x1b,
 119         CMD_RTS2RTS_QPEE    = 0x1c,
 120         CMD_SQERR2RTS_QPEE  = 0x1d,
 121         CMD_2ERR_QPEE       = 0x1e,
 122         CMD_RTS2SQD_QPEE    = 0x1f,
 123         CMD_SQD2SQD_QPEE    = 0x38,
 124         CMD_SQD2RTS_QPEE    = 0x20,
 125         CMD_ERR2RST_QPEE    = 0x21,
 126         CMD_QUERY_QPEE      = 0x22,
 127         CMD_INIT2INIT_QPEE  = 0x2d,
 128         CMD_SUSPEND_QPEE    = 0x32,
 129         CMD_UNSUSPEND_QPEE  = 0x33,
 130         /* special QPs and management commands */
 131         CMD_CONF_SPECIAL_QP = 0x23,
 132         CMD_MAD_IFC         = 0x24,
 133
 134         /* multicast commands */
 135         CMD_READ_MGM        = 0x25,
 136         CMD_WRITE_MGM       = 0x26,
 137         CMD_MGID_HASH       = 0x27,
 138
 139         /* miscellaneous commands */
 140         CMD_DIAG_RPRT       = 0x30,
 141         CMD_NOP             = 0x31,
 142
 143         /* debug commands */
 144         CMD_QUERY_DEBUG_MSG = 0x2a,
 145         CMD_SET_DEBUG_MSG   = 0x2b,
 146 };
 147
 148 /*
 149  * According to Mellanox code, FW may be starved and never complete
 150  * commands.  So we can't use strict timeouts described in PRM -- we
 151  * just arbitrarily select 60 seconds for now.
 152  */
 153 #if 0
 154 /*
 155  * Round up and add 1 to make sure we get the full wait time (since we
 156  * will be starting in the middle of a jiffy)
 157  */
 158 enum {
 159         CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1,
 160         CMD_TIME_CLASS_B = (HZ +  99) /  100 + 1,
 161         CMD_TIME_CLASS_C = (HZ +   9) /   10 + 1
 162 };
 163 #else
 164 enum {
 165         CMD_TIME_CLASS_A = 60 * HZ,
 166         CMD_TIME_CLASS_B = 60 * HZ,
 167         CMD_TIME_CLASS_C = 60 * HZ
 168 };
 169 #endif
 170
 171 enum {
 172         GO_BIT_TIMEOUT = HZ * 10
 173 };
 174
 175 struct mthca_cmd_context {
 176         struct completion done;
 177         struct timer_list timer;
 178         int               result;
 179         int               next;
 180         u64               out_param;
 181         u16               token;
 182         u8                status;
 183 };
 184
 185 static inline int go_bit(struct mthca_dev *dev)
 186 {
 187         return readl(dev->hcr + HCR_STATUS_OFFSET) &
 188                 swab32(1 << HCR_GO_BIT);
 189 }
 190
 191 static int mthca_cmd_post(struct mthca_dev *dev,
 192                           u64 in_param,
 193                           u64 out_param,
 194                           u32 in_modifier,
 195                           u8 op_modifier,
 196                           u16 op,
 197                           u16 token,
 198                           int event)
 199 {
 200         int err = 0;
 201
 202         mutex_lock(&dev->cmd.hcr_mutex);
 203
 204         if (event) {
 205                 unsigned long end = jiffies + GO_BIT_TIMEOUT;
 206
 207                 while (go_bit(dev) && time_before(jiffies, end)) {
 208                         set_current_state(TASK_RUNNING);
 209                         schedule();
 210                 }
 211         }
 212
 213         if (go_bit(dev)) {
 214                 err = -EAGAIN;
 215                 goto out;
 216         }
 217
 218         /*
 219          * We use writel (instead of something like memcpy_toio)
 220          * because writes of less than 32 bits to the HCR don't work
 221          * (and some architectures such as ia64 implement memcpy_toio
 222          * in terms of writeb).
 223          */
 224         __raw_writel((__force u32) cpu_to_be32(in_param >> 32),           dev->hcr + 0 * 4);
 225         __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful),  dev->hcr + 1 * 4);
 226         __raw_writel((__force u32) cpu_to_be32(in_modifier),              dev->hcr + 2 * 4);
 227         __raw_writel((__force u32) cpu_to_be32(out_param >> 32),          dev->hcr + 3 * 4);
 228         __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
 229         __raw_writel((__force u32) cpu_to_be32(token << 16),              dev->hcr + 5 * 4);
 230
 231         /* __raw_writel may not order writes. */
 232         wmb();
 233
 234         __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT)                |
 235                                                (event ? (1 << HCA_E_BIT) : 0)   |
 236                                                (op_modifier << HCR_OPMOD_SHIFT) |
 237                                                op),                       dev->hcr + 6 * 4);
 238
 239 out:
 240         mutex_unlock(&dev->cmd.hcr_mutex);
 241         return err;
 242 }
 243
 244 static int mthca_cmd_poll(struct mthca_dev *dev,
 245                           u64 in_param,
 246                           u64 *out_param,
 247                           int out_is_imm,
 248                           u32 in_modifier,
 249                           u8 op_modifier,
 250                           u16 op,
 251                           unsigned long timeout,
 252                           u8 *status)
 253 {
 254         int err = 0;
 255         unsigned long end;
 256
 257         down(&dev->cmd.poll_sem);
 258
 259         err = mthca_cmd_post(dev, in_param,
 260                              out_param ? *out_param : 0,
 261                              in_modifier, op_modifier,
 262                              op, CMD_POLL_TOKEN, 0);
 263         if (err)
 264                 goto out;
 265
 266         end = timeout + jiffies;
 267         while (go_bit(dev) && time_before(jiffies, end)) {
 268                 set_current_state(TASK_RUNNING);
 269                 schedule();
 270         }
 271
 272         if (go_bit(dev)) {
 273                 err = -EBUSY;
 274                 goto out;
 275         }
 276
 277         if (out_is_imm)
 278                 *out_param =
 279                         (u64) be32_to_cpu((__force __be32)
 280                                           __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
 281                         (u64) be32_to_cpu((__force __be32)
 282                                           __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4));
 283
 284         *status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
 285
 286 out:
 287         up(&dev->cmd.poll_sem);
 288         return err;
 289 }
 290
 291 void mthca_cmd_event(struct mthca_dev *dev,
 292                      u16 token,
 293                      u8  status,
 294                      u64 out_param)
 295 {
 296         struct mthca_cmd_context *context =
 297                 &dev->cmd.context[token & dev->cmd.token_mask];
 298
 299         /* previously timed out command completing at long last */
 300         if (token != context->token)
 301                 return;
 302
 303         context->result    = 0;
 304         context->status    = status;
 305         context->out_param = out_param;
 306
 307         context->token += dev->cmd.token_mask + 1;
 308
 309         complete(&context->done);
 310 }
 311
 312 static void event_timeout(unsigned long context_ptr)
 313 {
 314         struct mthca_cmd_context *context =
 315                 (struct mthca_cmd_context *) context_ptr;
 316
 317         context->result = -EBUSY;
 318         complete(&context->done);
 319 }
 320
 321 static int mthca_cmd_wait(struct mthca_dev *dev,
 322                           u64 in_param,
 323                           u64 *out_param,
 324                           int out_is_imm,
 325                           u32 in_modifier,
 326                           u8 op_modifier,
 327                           u16 op,
 328                           unsigned long timeout,
 329                           u8 *status)
 330 {
 331         int err = 0;
 332         struct mthca_cmd_context *context;
 333
 334         down(&dev->cmd.event_sem);
 335
 336         spin_lock(&dev->cmd.context_lock);
 337         BUG_ON(dev->cmd.free_head < 0);
 338         context = &dev->cmd.context[dev->cmd.free_head];
 339         dev->cmd.free_head = context->next;
 340         spin_unlock(&dev->cmd.context_lock);
 341
 342         init_completion(&context->done);
 343
 344         err = mthca_cmd_post(dev, in_param,
 345                              out_param ? *out_param : 0,
 346                              in_modifier, op_modifier,
 347                              op, context->token, 1);
 348         if (err)
 349                 goto out;
 350
 351         context->timer.expires  = jiffies + timeout;
 352         add_timer(&context->timer);
 353
 354         wait_for_completion(&context->done);
 355         del_timer_sync(&context->timer);
 356
 357         err = context->result;
 358         if (err)
 359                 goto out;
 360
 361         *status = context->status;
 362         if (*status)
 363                 mthca_dbg(dev, "Command %02x completed with status %02x\n",
 364                           op, *status);
 365
 366         if (out_is_imm)
 367                 *out_param = context->out_param;
 368
 369 out:
 370         spin_lock(&dev->cmd.context_lock);
 371         context->next = dev->cmd.free_head;
 372         dev->cmd.free_head = context - dev->cmd.context;
 373         spin_unlock(&dev->cmd.context_lock);
 374
 375         up(&dev->cmd.event_sem);
 376         return err;
 377 }
 378
 379 /* Invoke a command with an output mailbox */
 380 static int mthca_cmd_box(struct mthca_dev *dev,
 381                          u64 in_param,
 382                          u64 out_param,
 383                          u32 in_modifier,
 384                          u8 op_modifier,
 385                          u16 op,
 386                          unsigned long timeout,
 387                          u8 *status)
 388 {
 389         if (dev->cmd.use_events)
 390                 return mthca_cmd_wait(dev, in_param, &out_param, 0,
 391                                       in_modifier, op_modifier, op,
 392                                       timeout, status);
 393         else
 394                 return mthca_cmd_poll(dev, in_param, &out_param, 0,
 395                                       in_modifier, op_modifier, op,
 396                                       timeout, status);
 397 }
 398
 399 /* Invoke a command with no output parameter */
 400 static int mthca_cmd(struct mthca_dev *dev,
 401                      u64 in_param,
 402                      u32 in_modifier,
 403                      u8 op_modifier,
 404                      u16 op,
 405                      unsigned long timeout,
 406                      u8 *status)
 407 {
 408         return mthca_cmd_box(dev, in_param, 0, in_modifier,
 409                              op_modifier, op, timeout, status);
 410 }
 411
 412 /*
 413  * Invoke a command with an immediate output parameter (and copy the
 414  * output into the caller's out_param pointer after the command
 415  * executes).
 416  */
 417 static int mthca_cmd_imm(struct mthca_dev *dev,
 418                          u64 in_param,
 419                          u64 *out_param,
 420                          u32 in_modifier,
 421                          u8 op_modifier,
 422                          u16 op,
 423                          unsigned long timeout,
 424                          u8 *status)
 425 {
 426         if (dev->cmd.use_events)
 427                 return mthca_cmd_wait(dev, in_param, out_param, 1,
 428                                       in_modifier, op_modifier, op,
 429                                       timeout, status);
 430         else
 431                 return mthca_cmd_poll(dev, in_param, out_param, 1,
 432                                       in_modifier, op_modifier, op,
 433                                       timeout, status);
 434 }
 435
 436 int mthca_cmd_init(struct mthca_dev *dev)
 437 {
 438         mutex_init(&dev->cmd.hcr_mutex);
 439         sema_init(&dev->cmd.poll_sem, 1);
 440         dev->cmd.use_events = 0;
 441
 442         dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE,
 443                            MTHCA_HCR_SIZE);
 444         if (!dev->hcr) {
 445                 mthca_err(dev, "Couldn't map command register.");
 446                 return -ENOMEM;
 447         }
 448
 449         dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev,
 450                                         MTHCA_MAILBOX_SIZE,
 451                                         MTHCA_MAILBOX_SIZE, 0);
 452         if (!dev->cmd.pool) {
 453                 iounmap(dev->hcr);
 454                 return -ENOMEM;
 455         }
 456
 457         return 0;
 458 }
 459
 460 void mthca_cmd_cleanup(struct mthca_dev *dev)
 461 {
 462         pci_pool_destroy(dev->cmd.pool);
 463         iounmap(dev->hcr);
 464 }
 465
 466 /*
 467  * Switch to using events to issue FW commands (should be called after
 468  * event queue to command events has been initialized).
 469  */
 470 int mthca_cmd_use_events(struct mthca_dev *dev)
 471 {
 472         int i;
 473
 474         dev->cmd.context = kmalloc(dev->cmd.max_cmds *
 475                                    sizeof (struct mthca_cmd_context),
 476                                    GFP_KERNEL);
 477         if (!dev->cmd.context)
 478                 return -ENOMEM;
 479
 480         for (i = 0; i < dev->cmd.max_cmds; ++i) {
 481                 dev->cmd.context[i].token = i;
 482                 dev->cmd.context[i].next = i + 1;
 483                 init_timer(&dev->cmd.context[i].timer);
 484                 dev->cmd.context[i].timer.data     =
 485                         (unsigned long) &dev->cmd.context[i];
 486                 dev->cmd.context[i].timer.function = event_timeout;
 487         }
 488
 489         dev->cmd.context[dev->cmd.max_cmds - 1].next = -1;
 490         dev->cmd.free_head = 0;
 491
 492         sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds);
 493         spin_lock_init(&dev->cmd.context_lock);
 494
 495         for (dev->cmd.token_mask = 1;
 496              dev->cmd.token_mask < dev->cmd.max_cmds;
 497              dev->cmd.token_mask <<= 1)
 498                 ; /* nothing */
 499         --dev->cmd.token_mask;
 500
 501         dev->cmd.use_events = 1;
 502         down(&dev->cmd.poll_sem);
 503
 504         return 0;
 505 }
 506
 507 /*
 508  * Switch back to polling (used when shutting down the device)
 509  */
 510 void mthca_cmd_use_polling(struct mthca_dev *dev)
 511 {
 512         int i;
 513
 514         dev->cmd.use_events = 0;
 515
 516         for (i = 0; i < dev->cmd.max_cmds; ++i)
 517                 down(&dev->cmd.event_sem);
 518
 519         kfree(dev->cmd.context);
 520
 521         up(&dev->cmd.poll_sem);
 522 }
 523
 524 struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
 525                                           gfp_t gfp_mask)
 526 {
 527         struct mthca_mailbox *mailbox;
 528
 529         mailbox = kmalloc(sizeof *mailbox, gfp_mask);
 530         if (!mailbox)
 531                 return ERR_PTR(-ENOMEM);
 532
 533         mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma);
 534         if (!mailbox->buf) {
 535                 kfree(mailbox);
 536                 return ERR_PTR(-ENOMEM);
 537         }
 538
 539         return mailbox;
 540 }
 541
 542 void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox)
 543 {
 544         if (!mailbox)
 545                 return;
 546
 547         pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
 548         kfree(mailbox);
 549 }
 550
 551 int mthca_SYS_EN(struct mthca_dev *dev, u8 *status)
 552 {
 553         u64 out;
 554         int ret;
 555
 556         ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, HZ, status);
 557
 558         if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR)
 559                 mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, "
 560                            "sladdr=%d, SPD source=%s\n",
 561                            (int) (out >> 6) & 0xf, (int) (out >> 4) & 3,
 562                            (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM");
 563
 564         return ret;
 565 }
 566
 567 int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status)
 568 {
 569         return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, HZ, status);
 570 }
 571
 572 static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
 573                          u64 virt, u8 *status)
 574 {
 575         struct mthca_mailbox *mailbox;
 576         struct mthca_icm_iter iter;
 577         __be64 *pages;
 578         int lg;
 579         int nent = 0;
 580         int i;
 581         int err = 0;
 582         int ts = 0, tc = 0;
 583
 584         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 585         if (IS_ERR(mailbox))
 586                 return PTR_ERR(mailbox);
 587         memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE);
 588         pages = mailbox->buf;
 589
 590         for (mthca_icm_first(icm, &iter);
 591              !mthca_icm_last(&iter);
 592              mthca_icm_next(&iter)) {
 593                 /*
 594                  * We have to pass pages that are aligned to their
 595                  * size, so find the least significant 1 in the
 596                  * address or size and use that as our log2 size.
 597                  */
 598                 lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1;
 599                 if (lg < 12) {
 600                         mthca_warn(dev, "Got FW area not aligned to 4K (%llx/%lx).\n",
 601                                    (unsigned long long) mthca_icm_addr(&iter),
 602                                    mthca_icm_size(&iter));
 603                         err = -EINVAL;
 604                         goto out;
 605                 }
 606                 for (i = 0; i < mthca_icm_size(&iter) >> lg; ++i) {
 607                         if (virt != -1) {
 608                                 pages[nent * 2] = cpu_to_be64(virt);
 609                                 virt += 1 << lg;
 610                         }
 611
 612                         pages[nent * 2 + 1] = cpu_to_be64((mthca_icm_addr(&iter) +
 613                                                            (i << lg)) | (lg - 12));
 614                         ts += 1 << (lg - 10);
 615                         ++tc;
 616
 617                         if (++nent == MTHCA_MAILBOX_SIZE / 16) {
 618                                 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
 619                                                 CMD_TIME_CLASS_B, status);
 620                                 if (err || *status)
 621                                         goto out;
 622                                 nent = 0;
 623                         }
 624                 }
 625         }
 626
 627         if (nent)
 628                 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
 629                                 CMD_TIME_CLASS_B, status);
 630
 631         switch (op) {
 632         case CMD_MAP_FA:
 633                 mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
 634                 break;
 635         case CMD_MAP_ICM_AUX:
 636                 mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
 637                 break;
 638         case CMD_MAP_ICM:
 639                 mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
 640                           tc, ts, (unsigned long long) virt - (ts << 10));
 641                 break;
 642         }
 643
 644 out:
 645         mthca_free_mailbox(dev, mailbox);
 646         return err;
 647 }
 648
 649 int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
 650 {
 651         return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1, status);
 652 }
 653
 654 int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status)
 655 {
 656         return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B, status);
 657 }
 658
 659 int mthca_RUN_FW(struct mthca_dev *dev, u8 *status)
 660 {
 661         return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A, status);
 662 }
 663
 664 int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status)
 665 {
 666         struct mthca_mailbox *mailbox;
 667         u32 *outbox;
 668         int err = 0;
 669         u8 lg;
 670
 671 #define QUERY_FW_OUT_SIZE             0x100
 672 #define QUERY_FW_VER_OFFSET            0x00
 673 #define QUERY_FW_MAX_CMD_OFFSET        0x0f
 674 #define QUERY_FW_ERR_START_OFFSET      0x30
 675 #define QUERY_FW_ERR_SIZE_OFFSET       0x38
 676
 677 #define QUERY_FW_START_OFFSET          0x20
 678 #define QUERY_FW_END_OFFSET            0x28
 679
 680 #define QUERY_FW_SIZE_OFFSET           0x00
 681 #define QUERY_FW_CLR_INT_BASE_OFFSET   0x20
 682 #define QUERY_FW_EQ_ARM_BASE_OFFSET    0x40
 683 #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
 684
 685         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 686         if (IS_ERR(mailbox))
 687                 return PTR_ERR(mailbox);
 688         outbox = mailbox->buf;
 689
 690         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW,
 691                             CMD_TIME_CLASS_A, status);
 692
 693         if (err)
 694                 goto out;
 695
 696         MTHCA_GET(dev->fw_ver,   outbox, QUERY_FW_VER_OFFSET);
 697         /*
 698          * FW subminor version is at more signifant bits than minor
 699          * version, so swap here.
 700          */
 701         dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) |
 702                 ((dev->fw_ver & 0xffff0000ull) >> 16) |
 703                 ((dev->fw_ver & 0x0000ffffull) << 16);
 704
 705         MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
 706         dev->cmd.max_cmds = 1 << lg;
 707         MTHCA_GET(dev->catas_err.addr, outbox, QUERY_FW_ERR_START_OFFSET);
 708         MTHCA_GET(dev->catas_err.size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
 709
 710         mthca_dbg(dev, "FW version %012llx, max commands %d\n",
 711                   (unsigned long long) dev->fw_ver, dev->cmd.max_cmds);
 712         mthca_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x\n",
 713                   (unsigned long long) dev->catas_err.addr, dev->catas_err.size);
 714
 715         if (mthca_is_memfree(dev)) {
 716                 MTHCA_GET(dev->fw.arbel.fw_pages,       outbox, QUERY_FW_SIZE_OFFSET);
 717                 MTHCA_GET(dev->fw.arbel.clr_int_base,   outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
 718                 MTHCA_GET(dev->fw.arbel.eq_arm_base,    outbox, QUERY_FW_EQ_ARM_BASE_OFFSET);
 719                 MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET);
 720                 mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2);
 721
 722                 /*
 723                  * Arbel page size is always 4 KB; round up number of
 724                  * system pages needed.
 725                  */
 726                 dev->fw.arbel.fw_pages =
 727                         ALIGN(dev->fw.arbel.fw_pages, PAGE_SIZE >> 12) >>
 728                                 (PAGE_SHIFT - 12);
 729
 730                 mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n",
 731                           (unsigned long long) dev->fw.arbel.clr_int_base,
 732                           (unsigned long long) dev->fw.arbel.eq_arm_base,
 733                           (unsigned long long) dev->fw.arbel.eq_set_ci_base);
 734         } else {
 735                 MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET);
 736                 MTHCA_GET(dev->fw.tavor.fw_end,   outbox, QUERY_FW_END_OFFSET);
 737
 738                 mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n",
 739                           (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10),
 740                           (unsigned long long) dev->fw.tavor.fw_start,
 741                           (unsigned long long) dev->fw.tavor.fw_end);
 742         }
 743
 744 out:
 745         mthca_free_mailbox(dev, mailbox);
 746         return err;
 747 }
 748
 749 int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status)
 750 {
 751         struct mthca_mailbox *mailbox;
 752         u8 info;
 753         u32 *outbox;
 754         int err = 0;
 755
 756 #define ENABLE_LAM_OUT_SIZE         0x100
 757 #define ENABLE_LAM_START_OFFSET     0x00
 758 #define ENABLE_LAM_END_OFFSET       0x08
 759 #define ENABLE_LAM_INFO_OFFSET      0x13
 760
 761 #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
 762 #define ENABLE_LAM_INFO_ECC_MASK    0x3
 763
 764         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 765         if (IS_ERR(mailbox))
 766                 return PTR_ERR(mailbox);
 767         outbox = mailbox->buf;
 768
 769         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM,
 770                             CMD_TIME_CLASS_C, status);
 771
 772         if (err)
 773                 goto out;
 774
 775         if (*status == MTHCA_CMD_STAT_LAM_NOT_PRE)
 776                 goto out;
 777
 778         MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET);
 779         MTHCA_GET(dev->ddr_end,   outbox, ENABLE_LAM_END_OFFSET);
 780         MTHCA_GET(info,           outbox, ENABLE_LAM_INFO_OFFSET);
 781
 782         if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) !=
 783             !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
 784                 mthca_info(dev, "FW reports that HCA-attached memory "
 785                            "is %s hidden; does not match PCI config\n",
 786                            (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ?
 787                            "" : "not");
 788         }
 789         if (info & ENABLE_LAM_INFO_HIDDEN_FLAG)
 790                 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
 791
 792         mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
 793                   (int) ((dev->ddr_end - dev->ddr_start) >> 10),
 794                   (unsigned long long) dev->ddr_start,
 795                   (unsigned long long) dev->ddr_end);
 796
 797 out:
 798         mthca_free_mailbox(dev, mailbox);
 799         return err;
 800 }
 801
 802 int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status)
 803 {
 804         return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status);
 805 }
 806
 807 int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status)
 808 {
 809         struct mthca_mailbox *mailbox;
 810         u8 info;
 811         u32 *outbox;
 812         int err = 0;
 813
 814 #define QUERY_DDR_OUT_SIZE         0x100
 815 #define QUERY_DDR_START_OFFSET     0x00
 816 #define QUERY_DDR_END_OFFSET       0x08
 817 #define QUERY_DDR_INFO_OFFSET      0x13
 818
 819 #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
 820 #define QUERY_DDR_INFO_ECC_MASK    0x3
 821
 822         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 823         if (IS_ERR(mailbox))
 824                 return PTR_ERR(mailbox);
 825         outbox = mailbox->buf;
 826
 827         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR,
 828                             CMD_TIME_CLASS_A, status);
 829
 830         if (err)
 831                 goto out;
 832
 833         MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET);
 834         MTHCA_GET(dev->ddr_end,   outbox, QUERY_DDR_END_OFFSET);
 835         MTHCA_GET(info,           outbox, QUERY_DDR_INFO_OFFSET);
 836
 837         if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) !=
 838             !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
 839                 mthca_info(dev, "FW reports that HCA-attached memory "
 840                            "is %s hidden; does not match PCI config\n",
 841                            (info & QUERY_DDR_INFO_HIDDEN_FLAG) ?
 842                            "" : "not");
 843         }
 844         if (info & QUERY_DDR_INFO_HIDDEN_FLAG)
 845                 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
 846
 847         mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
 848                   (int) ((dev->ddr_end - dev->ddr_start) >> 10),
 849                   (unsigned long long) dev->ddr_start,
 850                   (unsigned long long) dev->ddr_end);
 851
 852 out:
 853         mthca_free_mailbox(dev, mailbox);
 854         return err;
 855 }
 856
 857 int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
 858                         struct mthca_dev_lim *dev_lim, u8 *status)
 859 {
 860         struct mthca_mailbox *mailbox;
 861         u32 *outbox;
 862         u8 field;
 863         u16 size;
 864         int err;
 865
 866 #define QUERY_DEV_LIM_OUT_SIZE             0x100
 867 #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET     0x10
 868 #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET      0x11
 869 #define QUERY_DEV_LIM_RSVD_QP_OFFSET        0x12
 870 #define QUERY_DEV_LIM_MAX_QP_OFFSET         0x13
 871 #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET       0x14
 872 #define QUERY_DEV_LIM_MAX_SRQ_OFFSET        0x15
 873 #define QUERY_DEV_LIM_RSVD_EEC_OFFSET       0x16
 874 #define QUERY_DEV_LIM_MAX_EEC_OFFSET        0x17
 875 #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET      0x19
 876 #define QUERY_DEV_LIM_RSVD_CQ_OFFSET        0x1a
 877 #define QUERY_DEV_LIM_MAX_CQ_OFFSET         0x1b
 878 #define QUERY_DEV_LIM_MAX_MPT_OFFSET        0x1d
 879 #define QUERY_DEV_LIM_RSVD_EQ_OFFSET        0x1e
 880 #define QUERY_DEV_LIM_MAX_EQ_OFFSET         0x1f
 881 #define QUERY_DEV_LIM_RSVD_MTT_OFFSET       0x20
 882 #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET     0x21
 883 #define QUERY_DEV_LIM_RSVD_MRW_OFFSET       0x22
 884 #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET    0x23
 885 #define QUERY_DEV_LIM_MAX_AV_OFFSET         0x27
 886 #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET     0x29
 887 #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET     0x2b
 888 #define QUERY_DEV_LIM_MAX_RDMA_OFFSET       0x2f
 889 #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET        0x33
 890 #define QUERY_DEV_LIM_ACK_DELAY_OFFSET      0x35
 891 #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET      0x36
 892 #define QUERY_DEV_LIM_VL_PORT_OFFSET        0x37
 893 #define QUERY_DEV_LIM_MAX_GID_OFFSET        0x3b
 894 #define QUERY_DEV_LIM_MAX_PKEY_OFFSET       0x3f
 895 #define QUERY_DEV_LIM_FLAGS_OFFSET          0x44
 896 #define QUERY_DEV_LIM_RSVD_UAR_OFFSET       0x48
 897 #define QUERY_DEV_LIM_UAR_SZ_OFFSET         0x49
 898 #define QUERY_DEV_LIM_PAGE_SZ_OFFSET        0x4b
 899 #define QUERY_DEV_LIM_MAX_SG_OFFSET         0x51
 900 #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET    0x52
 901 #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET      0x55
 902 #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
 903 #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET     0x61
 904 #define QUERY_DEV_LIM_RSVD_MCG_OFFSET       0x62
 905 #define QUERY_DEV_LIM_MAX_MCG_OFFSET        0x63
 906 #define QUERY_DEV_LIM_RSVD_PD_OFFSET        0x64
 907 #define QUERY_DEV_LIM_MAX_PD_OFFSET         0x65
 908 #define QUERY_DEV_LIM_RSVD_RDD_OFFSET       0x66
 909 #define QUERY_DEV_LIM_MAX_RDD_OFFSET        0x67
 910 #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET   0x80
 911 #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET   0x82
 912 #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET  0x84
 913 #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET  0x86
 914 #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET   0x88
 915 #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET   0x8a
 916 #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET   0x8c
 917 #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET   0x8e
 918 #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET   0x90
 919 #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET   0x92
 920 #define QUERY_DEV_LIM_PBL_SZ_OFFSET         0x96
 921 #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET     0x97
 922 #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET      0x98
 923 #define QUERY_DEV_LIM_LAMR_OFFSET           0x9f
 924 #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET     0xa0
 925
 926         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 927         if (IS_ERR(mailbox))
 928                 return PTR_ERR(mailbox);
 929         outbox = mailbox->buf;
 930
 931         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM,
 932                             CMD_TIME_CLASS_A, status);
 933
 934         if (err)
 935                 goto out;
 936
 937         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET);
 938         dev_lim->reserved_qps = 1 << (field & 0xf);
 939         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET);
 940         dev_lim->max_qps = 1 << (field & 0x1f);
 941         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET);
 942         dev_lim->reserved_srqs = 1 << (field >> 4);
 943         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET);
 944         dev_lim->max_srqs = 1 << (field & 0x1f);
 945         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);
 946         dev_lim->reserved_eecs = 1 << (field & 0xf);
 947         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);
 948         dev_lim->max_eecs = 1 << (field & 0x1f);
 949         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);
 950         dev_lim->max_cq_sz = 1 << field;
 951         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);
 952         dev_lim->reserved_cqs = 1 << (field & 0xf);
 953         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);
 954         dev_lim->max_cqs = 1 << (field & 0x1f);
 955         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);
 956         dev_lim->max_mpts = 1 << (field & 0x3f);
 957         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);
 958         dev_lim->reserved_eqs = 1 << (field & 0xf);
 959         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);
 960         dev_lim->max_eqs = 1 << (field & 0x7);
 961         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);
 962         dev_lim->reserved_mtts = 1 << (field >> 4);
 963         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);
 964         dev_lim->max_mrw_sz = 1 << field;
 965         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);
 966         dev_lim->reserved_mrws = 1 << (field & 0xf);
 967         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);
 968         dev_lim->max_mtt_seg = 1 << (field & 0x3f);
 969         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);
 970         dev_lim->max_requester_per_qp = 1 << (field & 0x3f);
 971         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);
 972         dev_lim->max_responder_per_qp = 1 << (field & 0x3f);
 973         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);
 974         dev_lim->max_rdma_global = 1 << (field & 0x3f);
 975         MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);
 976         dev_lim->local_ca_ack_delay = field & 0x1f;
 977         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);
 978         dev_lim->max_mtu        = field >> 4;
 979         dev_lim->max_port_width = field & 0xf;
 980         MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);
 981         dev_lim->max_vl    = field >> 4;
 982         dev_lim->num_ports = field & 0xf;
 983         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);
 984         dev_lim->max_gids = 1 << (field & 0xf);
 985         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);
 986         dev_lim->max_pkeys = 1 << (field & 0xf);
 987         MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);
 988         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);
 989         dev_lim->reserved_uars = field >> 4;
 990         MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);
 991         dev_lim->uar_size = 1 << ((field & 0x3f) + 20);
 992         MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);
 993         dev_lim->min_page_sz = 1 << field;
 994         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);
 995         dev_lim->max_sg = field;
 996
 997         MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);
 998         dev_lim->max_desc_sz = size;
 999
1000         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);
1001         dev_lim->max_qp_per_mcg = 1 << field;
1002         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);
1003         dev_lim->reserved_mgms = field & 0xf;
1004         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);
1005         dev_lim->max_mcgs = 1 << field;
1006         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);
1007         dev_lim->reserved_pds = field >> 4;
1008         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);
1009         dev_lim->max_pds = 1 << (field & 0x3f);
1010         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);
1011         dev_lim->reserved_rdds = field >> 4;
1012         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);
1013         dev_lim->max_rdds = 1 << (field & 0x3f);
1014
1015         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);
1016         dev_lim->eec_entry_sz = size;
1017         MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);
1018         dev_lim->qpc_entry_sz = size;
1019         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);
1020         dev_lim->eeec_entry_sz = size;
1021         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);
1022         dev_lim->eqpc_entry_sz = size;
1023         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);
1024         dev_lim->eqc_entry_sz = size;
1025         MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);
1026         dev_lim->cqc_entry_sz = size;
1027         MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);
1028         dev_lim->srq_entry_sz = size;
1029         MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);
1030         dev_lim->uar_scratch_entry_sz = size;
1031
1032         mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1033                   dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz);
1034         mthca_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
1035                   dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz);
1036         mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1037                   dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz);
1038         mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
1039                   dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz);
1040         mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
1041                   dev_lim->reserved_mrws, dev_lim->reserved_mtts);
1042         mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1043                   dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars);
1044         mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
1045                   dev_lim->max_pds, dev_lim->reserved_mgms);
1046         mthca_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
1047                   dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz);
1048
1049         mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags);
1050
1051         if (mthca_is_memfree(dev)) {
1052                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1053                 dev_lim->max_srq_sz = 1 << field;
1054                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1055                 dev_lim->max_qp_sz = 1 << field;
1056                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);
1057                 dev_lim->hca.arbel.resize_srq = field & 1;
1058                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET);
1059                 dev_lim->max_sg = min_t(int, field, dev_lim->max_sg);
1060                 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET);
1061                 dev_lim->max_desc_sz = min_t(int, size, dev_lim->max_desc_sz);
1062                 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);
1063                 dev_lim->mpt_entry_sz = size;
1064                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);
1065                 dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);
1066                 MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,
1067                           QUERY_DEV_LIM_BMME_FLAGS_OFFSET);
1068                 MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,
1069                           QUERY_DEV_LIM_RSVD_LKEY_OFFSET);
1070                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);
1071                 dev_lim->hca.arbel.lam_required = field & 1;
1072                 MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,
1073                           QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);
1074
1075                 if (dev_lim->hca.arbel.bmme_flags & 1)
1076                         mthca_dbg(dev, "Base MM extensions: yes "
1077                                   "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
1078                                   dev_lim->hca.arbel.bmme_flags,
1079                                   dev_lim->hca.arbel.max_pbl_sz,
1080                                   dev_lim->hca.arbel.reserved_lkey);
1081                 else
1082                         mthca_dbg(dev, "Base MM extensions: no\n");
1083
1084                 mthca_dbg(dev, "Max ICM size %lld MB\n",
1085                           (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20);
1086         } else {
1087                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1088                 dev_lim->max_srq_sz = (1 << field) - 1;
1089                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1090                 dev_lim->max_qp_sz = (1 << field) - 1;
1091                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);
1092                 dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);
1093                 dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;
1094         }
1095
1096 out:
1097         mthca_free_mailbox(dev, mailbox);
1098         return err;
1099 }
1100
1101 static void get_board_id(void *vsd, char *board_id)
1102 {
1103         int i;
1104
1105 #define VSD_OFFSET_SIG1         0x00
1106 #define VSD_OFFSET_SIG2         0xde
1107 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1108 #define VSD_OFFSET_TS_BOARD_ID  0x20
1109
1110 #define VSD_SIGNATURE_TOPSPIN   0x5ad
1111
1112         memset(board_id, 0, MTHCA_BOARD_ID_LEN);
1113
1114         if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1115             be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1116                 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN);
1117         } else {
1118                 /*
1119                  * The board ID is a string but the firmware byte
1120                  * swaps each 4-byte word before passing it back to
1121                  * us.  Therefore we need to swab it before printing.
1122                  */
1123                 for (i = 0; i < 4; ++i)
1124                         ((u32 *) board_id)[i] =
1125                                 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1126         }
1127 }
1128
1129 int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
1130                         struct mthca_adapter *adapter, u8 *status)
1131 {
1132         struct mthca_mailbox *mailbox;
1133         u32 *outbox;
1134         int err;
1135
1136 #define QUERY_ADAPTER_OUT_SIZE             0x100
1137 #define QUERY_ADAPTER_VENDOR_ID_OFFSET     0x00
1138 #define QUERY_ADAPTER_DEVICE_ID_OFFSET     0x04
1139 #define QUERY_ADAPTER_REVISION_ID_OFFSET   0x08
1140 #define QUERY_ADAPTER_INTA_PIN_OFFSET      0x10
1141 #define QUERY_ADAPTER_VSD_OFFSET           0x20
1142
1143         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1144         if (IS_ERR(mailbox))
1145                 return PTR_ERR(mailbox);
1146         outbox = mailbox->buf;
1147
1148         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER,
1149                             CMD_TIME_CLASS_A, status);
1150
1151         if (err)
1152                 goto out;
1153
1154         MTHCA_GET(adapter->vendor_id, outbox,   QUERY_ADAPTER_VENDOR_ID_OFFSET);
1155         MTHCA_GET(adapter->device_id, outbox,   QUERY_ADAPTER_DEVICE_ID_OFFSET);
1156         MTHCA_GET(adapter->revision_id, outbox, QUERY_ADAPTER_REVISION_ID_OFFSET);
1157         MTHCA_GET(adapter->inta_pin, outbox,    QUERY_ADAPTER_INTA_PIN_OFFSET);
1158
1159         get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1160                      adapter->board_id);
1161
1162 out:
1163         mthca_free_mailbox(dev, mailbox);
1164         return err;
1165 }
1166
1167 int mthca_INIT_HCA(struct mthca_dev *dev,
1168                    struct mthca_init_hca_param *param,
1169                    u8 *status)
1170 {
1171         struct mthca_mailbox *mailbox;
1172         __be32 *inbox;
1173         int err;
1174
1175 #define INIT_HCA_IN_SIZE                 0x200
1176 #define INIT_HCA_FLAGS_OFFSET            0x014
1177 #define INIT_HCA_QPC_OFFSET              0x020
1178 #define  INIT_HCA_QPC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x10)
1179 #define  INIT_HCA_LOG_QP_OFFSET          (INIT_HCA_QPC_OFFSET + 0x17)
1180 #define  INIT_HCA_EEC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x20)
1181 #define  INIT_HCA_LOG_EEC_OFFSET         (INIT_HCA_QPC_OFFSET + 0x27)
1182 #define  INIT_HCA_SRQC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x28)
1183 #define  INIT_HCA_LOG_SRQ_OFFSET         (INIT_HCA_QPC_OFFSET + 0x2f)
1184 #define  INIT_HCA_CQC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x30)
1185 #define  INIT_HCA_LOG_CQ_OFFSET          (INIT_HCA_QPC_OFFSET + 0x37)
1186 #define  INIT_HCA_EQPC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x40)
1187 #define  INIT_HCA_EEEC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x50)
1188 #define  INIT_HCA_EQC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x60)
1189 #define  INIT_HCA_LOG_EQ_OFFSET          (INIT_HCA_QPC_OFFSET + 0x67)
1190 #define  INIT_HCA_RDB_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x70)
1191 #define INIT_HCA_UDAV_OFFSET             0x0b0
1192 #define  INIT_HCA_UDAV_LKEY_OFFSET       (INIT_HCA_UDAV_OFFSET + 0x0)
1193 #define  INIT_HCA_UDAV_PD_OFFSET         (INIT_HCA_UDAV_OFFSET + 0x4)
1194 #define INIT_HCA_MCAST_OFFSET            0x0c0
1195 #define  INIT_HCA_MC_BASE_OFFSET         (INIT_HCA_MCAST_OFFSET + 0x00)
1196 #define  INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1197 #define  INIT_HCA_MC_HASH_SZ_OFFSET      (INIT_HCA_MCAST_OFFSET + 0x16)
1198 #define  INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1199 #define INIT_HCA_TPT_OFFSET              0x0f0
1200 #define  INIT_HCA_MPT_BASE_OFFSET        (INIT_HCA_TPT_OFFSET + 0x00)
1201 #define  INIT_HCA_MTT_SEG_SZ_OFFSET      (INIT_HCA_TPT_OFFSET + 0x09)
1202 #define  INIT_HCA_LOG_MPT_SZ_OFFSET      (INIT_HCA_TPT_OFFSET + 0x0b)
1203 #define  INIT_HCA_MTT_BASE_OFFSET        (INIT_HCA_TPT_OFFSET + 0x10)
1204 #define INIT_HCA_UAR_OFFSET              0x120
1205 #define  INIT_HCA_UAR_BASE_OFFSET        (INIT_HCA_UAR_OFFSET + 0x00)
1206 #define  INIT_HCA_UARC_SZ_OFFSET         (INIT_HCA_UAR_OFFSET + 0x09)
1207 #define  INIT_HCA_LOG_UAR_SZ_OFFSET      (INIT_HCA_UAR_OFFSET + 0x0a)
1208 #define  INIT_HCA_UAR_PAGE_SZ_OFFSET     (INIT_HCA_UAR_OFFSET + 0x0b)
1209 #define  INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
1210 #define  INIT_HCA_UAR_CTX_BASE_OFFSET    (INIT_HCA_UAR_OFFSET + 0x18)
1211
1212         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1213         if (IS_ERR(mailbox))
1214                 return PTR_ERR(mailbox);
1215         inbox = mailbox->buf;
1216
1217         memset(inbox, 0, INIT_HCA_IN_SIZE);
1218
1219 #if defined(__LITTLE_ENDIAN)
1220         *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1221 #elif defined(__BIG_ENDIAN)
1222         *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1223 #else
1224 #error Host endianness not defined
1225 #endif
1226         /* Check port for UD address vector: */
1227         *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1228
1229         /* We leave wqe_quota, responder_exu, etc as 0 (default) */
1230
1231         /* QPC/EEC/CQC/EQC/RDB attributes */
1232
1233         MTHCA_PUT(inbox, param->qpc_base,     INIT_HCA_QPC_BASE_OFFSET);
1234         MTHCA_PUT(inbox, param->log_num_qps,  INIT_HCA_LOG_QP_OFFSET);
1235         MTHCA_PUT(inbox, param->eec_base,     INIT_HCA_EEC_BASE_OFFSET);
1236         MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET);
1237         MTHCA_PUT(inbox, param->srqc_base,    INIT_HCA_SRQC_BASE_OFFSET);
1238         MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1239         MTHCA_PUT(inbox, param->cqc_base,     INIT_HCA_CQC_BASE_OFFSET);
1240         MTHCA_PUT(inbox, param->log_num_cqs,  INIT_HCA_LOG_CQ_OFFSET);
1241         MTHCA_PUT(inbox, param->eqpc_base,    INIT_HCA_EQPC_BASE_OFFSET);
1242         MTHCA_PUT(inbox, param->eeec_base,    INIT_HCA_EEEC_BASE_OFFSET);
1243         MTHCA_PUT(inbox, param->eqc_base,     INIT_HCA_EQC_BASE_OFFSET);
1244         MTHCA_PUT(inbox, param->log_num_eqs,  INIT_HCA_LOG_EQ_OFFSET);
1245         MTHCA_PUT(inbox, param->rdb_base,     INIT_HCA_RDB_BASE_OFFSET);
1246
1247         /* UD AV attributes */
1248
1249         /* multicast attributes */
1250
1251         MTHCA_PUT(inbox, param->mc_base,         INIT_HCA_MC_BASE_OFFSET);
1252         MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1253         MTHCA_PUT(inbox, param->mc_hash_sz,      INIT_HCA_MC_HASH_SZ_OFFSET);
1254         MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1255
1256         /* TPT attributes */
1257
1258         MTHCA_PUT(inbox, param->mpt_base,   INIT_HCA_MPT_BASE_OFFSET);
1259         if (!mthca_is_memfree(dev))
1260                 MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET);
1261         MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1262         MTHCA_PUT(inbox, param->mtt_base,   INIT_HCA_MTT_BASE_OFFSET);
1263
1264         /* UAR attributes */
1265         {
1266                 u8 uar_page_sz = PAGE_SHIFT - 12;
1267                 MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1268         }
1269
1270         MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET);
1271
1272         if (mthca_is_memfree(dev)) {
1273                 MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET);
1274                 MTHCA_PUT(inbox, param->log_uar_sz,  INIT_HCA_LOG_UAR_SZ_OFFSET);
1275                 MTHCA_PUT(inbox, param->uarc_base,   INIT_HCA_UAR_CTX_BASE_OFFSET);
1276         }
1277
1278         err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, HZ, status);
1279
1280         mthca_free_mailbox(dev, mailbox);
1281         return err;
1282 }
1283
1284 int mthca_INIT_IB(struct mthca_dev *dev,
1285                   struct mthca_init_ib_param *param,
1286                   int port, u8 *status)
1287 {
1288         struct mthca_mailbox *mailbox;
1289         u32 *inbox;
1290         int err;
1291         u32 flags;
1292
1293 #define INIT_IB_IN_SIZE          56
1294 #define INIT_IB_FLAGS_OFFSET     0x00
1295 #define INIT_IB_FLAG_SIG         (1 << 18)
1296 #define INIT_IB_FLAG_NG          (1 << 17)
1297 #define INIT_IB_FLAG_G0          (1 << 16)
1298 #define INIT_IB_VL_SHIFT         4
1299 #define INIT_IB_PORT_WIDTH_SHIFT 8
1300 #define INIT_IB_MTU_SHIFT        12
1301 #define INIT_IB_MAX_GID_OFFSET   0x06
1302 #define INIT_IB_MAX_PKEY_OFFSET  0x0a
1303 #define INIT_IB_GUID0_OFFSET     0x10
1304 #define INIT_IB_NODE_GUID_OFFSET 0x18
1305 #define INIT_IB_SI_GUID_OFFSET   0x20
1306
1307         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1308         if (IS_ERR(mailbox))
1309                 return PTR_ERR(mailbox);
1310         inbox = mailbox->buf;
1311
1312         memset(inbox, 0, INIT_IB_IN_SIZE);
1313
1314         flags = 0;
1315         flags |= param->set_guid0     ? INIT_IB_FLAG_G0  : 0;
1316         flags |= param->set_node_guid ? INIT_IB_FLAG_NG  : 0;
1317         flags |= param->set_si_guid   ? INIT_IB_FLAG_SIG : 0;
1318         flags |= param->vl_cap << INIT_IB_VL_SHIFT;
1319         flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT;
1320         flags |= param->mtu_cap << INIT_IB_MTU_SHIFT;
1321         MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET);
1322
1323         MTHCA_PUT(inbox, param->gid_cap,   INIT_IB_MAX_GID_OFFSET);
1324         MTHCA_PUT(inbox, param->pkey_cap,  INIT_IB_MAX_PKEY_OFFSET);
1325         MTHCA_PUT(inbox, param->guid0,     INIT_IB_GUID0_OFFSET);
1326         MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET);
1327         MTHCA_PUT(inbox, param->si_guid,   INIT_IB_SI_GUID_OFFSET);
1328
1329         err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB,
1330                         CMD_TIME_CLASS_A, status);
1331
1332         mthca_free_mailbox(dev, mailbox);
1333         return err;
1334 }
1335
1336 int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status)
1337 {
1338         return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, HZ, status);
1339 }
1340
1341 int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status)
1342 {
1343         return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, HZ, status);
1344 }
1345
1346 int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
1347                  int port, u8 *status)
1348 {
1349         struct mthca_mailbox *mailbox;
1350         u32 *inbox;
1351         int err;
1352         u32 flags = 0;
1353
1354 #define SET_IB_IN_SIZE         0x40
1355 #define SET_IB_FLAGS_OFFSET    0x00
1356 #define SET_IB_FLAG_SIG        (1 << 18)
1357 #define SET_IB_FLAG_RQK        (1 <<  0)
1358 #define SET_IB_CAP_MASK_OFFSET 0x04
1359 #define SET_IB_SI_GUID_OFFSET  0x08
1360
1361         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1362         if (IS_ERR(mailbox))
1363                 return PTR_ERR(mailbox);
1364         inbox = mailbox->buf;
1365
1366         memset(inbox, 0, SET_IB_IN_SIZE);
1367
1368         flags |= param->set_si_guid     ? SET_IB_FLAG_SIG : 0;
1369         flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0;
1370         MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET);
1371
1372         MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET);
1373         MTHCA_PUT(inbox, param->si_guid,  SET_IB_SI_GUID_OFFSET);
1374
1375         err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB,
1376                         CMD_TIME_CLASS_B, status);
1377
1378         mthca_free_mailbox(dev, mailbox);
1379         return err;
1380 }
1381
1382 int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status)
1383 {
1384         return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt, status);
1385 }
1386
1387 int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status)
1388 {
1389         struct mthca_mailbox *mailbox;
1390         __be64 *inbox;
1391         int err;
1392
1393         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1394         if (IS_ERR(mailbox))
1395                 return PTR_ERR(mailbox);
1396         inbox = mailbox->buf;
1397
1398         inbox[0] = cpu_to_be64(virt);
1399         inbox[1] = cpu_to_be64(dma_addr);
1400
1401         err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM,
1402                         CMD_TIME_CLASS_B, status);
1403
1404         mthca_free_mailbox(dev, mailbox);
1405
1406         if (!err)
1407                 mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
1408                           (unsigned long long) dma_addr, (unsigned long long) virt);
1409
1410         return err;
1411 }
1412
1413 int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status)
1414 {
1415         mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n",
1416                   page_count, (unsigned long long) virt);
1417
1418         return mthca_cmd(dev, virt, page_count, 0, CMD_UNMAP_ICM, CMD_TIME_CLASS_B, status);
1419 }
1420
1421 int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
1422 {
1423         return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1, status);
1424 }
1425
1426 int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status)
1427 {
1428         return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B, status);
1429 }
1430
1431 int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages,
1432                        u8 *status)
1433 {
1434         int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, 0, CMD_SET_ICM_SIZE,
1435                                 CMD_TIME_CLASS_A, status);
1436
1437         if (ret || status)
1438                 return ret;
1439
1440         /*
1441          * Arbel page size is always 4 KB; round up number of system
1442          * pages needed.
1443          */
1444         *aux_pages = (*aux_pages + (1 << (PAGE_SHIFT - 12)) - 1) >> (PAGE_SHIFT - 12);
1445         *aux_pages = ALIGN(*aux_pages, PAGE_SIZE >> 12) >> (PAGE_SHIFT - 12);
1446
1447         return 0;
1448 }
1449
1450 int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1451                     int mpt_index, u8 *status)
1452 {
1453         return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT,
1454                          CMD_TIME_CLASS_B, status);
1455 }
1456
1457 int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1458                     int mpt_index, u8 *status)
1459 {
1460         return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
1461                              !mailbox, CMD_HW2SW_MPT,
1462                              CMD_TIME_CLASS_B, status);
1463 }
1464
1465 int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1466                     int num_mtt, u8 *status)
1467 {
1468         return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT,
1469                          CMD_TIME_CLASS_B, status);
1470 }
1471
1472 int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status)
1473 {
1474         return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B, status);
1475 }
1476
1477 int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
1478                  int eq_num, u8 *status)
1479 {
1480         mthca_dbg(dev, "%s mask %016llx for eqn %d\n",
1481                   unmap ? "Clearing" : "Setting",
1482                   (unsigned long long) event_mask, eq_num);
1483         return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num,
1484                          0, CMD_MAP_EQ, CMD_TIME_CLASS_B, status);
1485 }
1486
1487 int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1488                    int eq_num, u8 *status)
1489 {
1490         return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ,
1491                          CMD_TIME_CLASS_A, status);
1492 }
1493
1494 int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1495                    int eq_num, u8 *status)
1496 {
1497         return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0,
1498                              CMD_HW2SW_EQ,
1499                              CMD_TIME_CLASS_A, status);
1500 }
1501
1502 int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1503                    int cq_num, u8 *status)
1504 {
1505         return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ,
1506                         CMD_TIME_CLASS_A, status);
1507 }
1508
1509 int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1510                    int cq_num, u8 *status)
1511 {
1512         return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0,
1513                              CMD_HW2SW_CQ,
1514                              CMD_TIME_CLASS_A, status);
1515 }
1516
1517 int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1518                     int srq_num, u8 *status)
1519 {
1520         return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ,
1521                         CMD_TIME_CLASS_A, status);
1522 }
1523
1524 int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1525                     int srq_num, u8 *status)
1526 {
1527         return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0,
1528                              CMD_HW2SW_SRQ,
1529                              CMD_TIME_CLASS_A, status);
1530 }
1531
1532 int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit, u8 *status)
1533 {
1534         return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ,
1535                          CMD_TIME_CLASS_B, status);
1536 }
1537
1538 int mthca_MODIFY_QP(struct mthca_dev *dev, int trans, u32 num,
1539                     int is_ee, struct mthca_mailbox *mailbox, u32 optmask,
1540                     u8 *status)
1541 {
1542         static const u16 op[] = {
1543                 [MTHCA_TRANS_RST2INIT]  = CMD_RST2INIT_QPEE,
1544                 [MTHCA_TRANS_INIT2INIT] = CMD_INIT2INIT_QPEE,
1545                 [MTHCA_TRANS_INIT2RTR]  = CMD_INIT2RTR_QPEE,
1546                 [MTHCA_TRANS_RTR2RTS]   = CMD_RTR2RTS_QPEE,
1547                 [MTHCA_TRANS_RTS2RTS]   = CMD_RTS2RTS_QPEE,
1548                 [MTHCA_TRANS_SQERR2RTS] = CMD_SQERR2RTS_QPEE,
1549                 [MTHCA_TRANS_ANY2ERR]   = CMD_2ERR_QPEE,
1550                 [MTHCA_TRANS_RTS2SQD]   = CMD_RTS2SQD_QPEE,
1551                 [MTHCA_TRANS_SQD2SQD]   = CMD_SQD2SQD_QPEE,
1552                 [MTHCA_TRANS_SQD2RTS]   = CMD_SQD2RTS_QPEE,
1553                 [MTHCA_TRANS_ANY2RST]   = CMD_ERR2RST_QPEE
1554         };
1555         u8 op_mod = 0;
1556         int my_mailbox = 0;
1557         int err;
1558
1559         if (trans < 0 || trans >= ARRAY_SIZE(op))
1560                 return -EINVAL;
1561
1562         if (trans == MTHCA_TRANS_ANY2RST) {
1563                 op_mod = 3;     /* don't write outbox, any->reset */
1564
1565                 /* For debugging */
1566                 if (!mailbox) {
1567                         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1568                         if (!IS_ERR(mailbox)) {
1569                                 my_mailbox = 1;
1570                                 op_mod     = 2; /* write outbox, any->reset */
1571                         } else
1572                                 mailbox = NULL;
1573                 }
1574         } else {
1575                 if (0) {
1576                         int i;
1577                         mthca_dbg(dev, "Dumping QP context:\n");
1578                         printk("  opt param mask: %08x\n", be32_to_cpup(mailbox->buf));
1579                         for (i = 0; i < 0x100 / 4; ++i) {
1580                                 if (i % 8 == 0)
1581                                         printk("  [%02x] ", i * 4);
1582                                 printk(" %08x",
1583                                        be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1584                                 if ((i + 1) % 8 == 0)
1585                                         printk("\n");
1586                         }
1587                 }
1588         }
1589
1590         if (trans == MTHCA_TRANS_ANY2RST) {
1591                 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
1592                                     (!!is_ee << 24) | num, op_mod,
1593                                     op[trans], CMD_TIME_CLASS_C, status);
1594
1595                 if (0 && mailbox) {
1596                         int i;
1597                         mthca_dbg(dev, "Dumping QP context:\n");
1598                         printk(" %08x\n", be32_to_cpup(mailbox->buf));
1599                         for (i = 0; i < 0x100 / 4; ++i) {
1600                                 if (i % 8 == 0)
1601                                         printk("[%02x] ", i * 4);
1602                                 printk(" %08x",
1603                                        be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1604                                 if ((i + 1) % 8 == 0)
1605                                         printk("\n");
1606                         }
1607                 }
1608
1609         } else
1610                 err = mthca_cmd(dev, mailbox->dma, (!!is_ee << 24) | num,
1611                                 op_mod, op[trans], CMD_TIME_CLASS_C, status);
1612
1613         if (my_mailbox)
1614                 mthca_free_mailbox(dev, mailbox);
1615
1616         return err;
1617 }
1618
1619 int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
1620                    struct mthca_mailbox *mailbox, u8 *status)
1621 {
1622         return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0,
1623                              CMD_QUERY_QPEE, CMD_TIME_CLASS_A, status);
1624 }
1625
1626 int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn,
1627                           u8 *status)
1628 {
1629         u8 op_mod;
1630
1631         switch (type) {
1632         case IB_QPT_SMI:
1633                 op_mod = 0;
1634                 break;
1635         case IB_QPT_GSI:
1636                 op_mod = 1;
1637                 break;
1638         case IB_QPT_RAW_IPV6:
1639                 op_mod = 2;
1640                 break;
1641         case IB_QPT_RAW_ETY:
1642                 op_mod = 3;
1643                 break;
1644         default:
1645                 return -EINVAL;
1646         }
1647
1648         return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP,
1649                          CMD_TIME_CLASS_B, status);
1650 }
1651
1652 int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
1653                   int port, struct ib_wc *in_wc, struct ib_grh *in_grh,
1654                   void *in_mad, void *response_mad, u8 *status)
1655 {
1656         struct mthca_mailbox *inmailbox, *outmailbox;
1657         void *inbox;
1658         int err;
1659         u32 in_modifier = port;
1660         u8 op_modifier = 0;
1661
1662 #define MAD_IFC_BOX_SIZE      0x400
1663 #define MAD_IFC_MY_QPN_OFFSET 0x100
1664 #define MAD_IFC_RQPN_OFFSET   0x104
1665 #define MAD_IFC_SL_OFFSET     0x108
1666 #define MAD_IFC_G_PATH_OFFSET 0x109
1667 #define MAD_IFC_RLID_OFFSET   0x10a
1668 #define MAD_IFC_PKEY_OFFSET   0x10e
1669 #define MAD_IFC_GRH_OFFSET    0x140
1670
1671         inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1672         if (IS_ERR(inmailbox))
1673                 return PTR_ERR(inmailbox);
1674         inbox = inmailbox->buf;
1675
1676         outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1677         if (IS_ERR(outmailbox)) {
1678                 mthca_free_mailbox(dev, inmailbox);
1679                 return PTR_ERR(outmailbox);
1680         }
1681
1682         memcpy(inbox, in_mad, 256);
1683
1684         /*
1685          * Key check traps can't be generated unless we have in_wc to
1686          * tell us where to send the trap.
1687          */
1688         if (ignore_mkey || !in_wc)
1689                 op_modifier |= 0x1;
1690         if (ignore_bkey || !in_wc)
1691                 op_modifier |= 0x2;
1692
1693         if (in_wc) {
1694                 u8 val;
1695
1696                 memset(inbox + 256, 0, 256);
1697
1698                 MTHCA_PUT(inbox, in_wc->qp_num,     MAD_IFC_MY_QPN_OFFSET);
1699                 MTHCA_PUT(inbox, in_wc->src_qp,     MAD_IFC_RQPN_OFFSET);
1700
1701                 val = in_wc->sl << 4;
1702                 MTHCA_PUT(inbox, val,               MAD_IFC_SL_OFFSET);
1703
1704                 val = in_wc->dlid_path_bits |
1705                         (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
1706                 MTHCA_PUT(inbox, val,               MAD_IFC_GRH_OFFSET);
1707
1708                 MTHCA_PUT(inbox, in_wc->slid,       MAD_IFC_RLID_OFFSET);
1709                 MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET);
1710
1711                 if (in_grh)
1712                         memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40);
1713
1714                 op_modifier |= 0x10;
1715
1716                 in_modifier |= in_wc->slid << 16;
1717         }
1718
1719         err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma,
1720                             in_modifier, op_modifier,
1721                             CMD_MAD_IFC, CMD_TIME_CLASS_C, status);
1722
1723         if (!err && !*status)
1724                 memcpy(response_mad, outmailbox->buf, 256);
1725
1726         mthca_free_mailbox(dev, inmailbox);
1727         mthca_free_mailbox(dev, outmailbox);
1728         return err;
1729 }
1730
1731 int mthca_READ_MGM(struct mthca_dev *dev, int index,
1732                    struct mthca_mailbox *mailbox, u8 *status)
1733 {
1734         return mthca_cmd_box(dev, 0, mailbox->dma, index, 0,
1735                              CMD_READ_MGM, CMD_TIME_CLASS_A, status);
1736 }
1737
1738 int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
1739                     struct mthca_mailbox *mailbox, u8 *status)
1740 {
1741         return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM,
1742                          CMD_TIME_CLASS_A, status);
1743 }
1744
1745 int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1746                     u16 *hash, u8 *status)
1747 {
1748         u64 imm;
1749         int err;
1750
1751         err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH,
1752                             CMD_TIME_CLASS_A, status);
1753
1754         *hash = imm;
1755         return err;
1756 }
1757
1758 int mthca_NOP(struct mthca_dev *dev, u8 *status)
1759 {
1760         return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100), status);
1761 }