drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <rdma/ib_cache.h>
  34 #include <rdma/ib_pack.h>
  35
  36 #include <linux/mlx4/qp.h>
  37
  38 #include "mlx4_ib.h"
  39 #include "user.h"
  40
  41 enum {
  42         MLX4_IB_ACK_REQ_FREQ    = 8,
  43 };
  44
  45 enum {
  46         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  47         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f
  48 };
  49
  50 enum {
  51         /*
  52          * Largest possible UD header: send with GRH and immediate data.
  53          */
  54         MLX4_IB_UD_HEADER_SIZE          = 72
  55 };
  56
  57 struct mlx4_ib_sqp {
  58         struct mlx4_ib_qp       qp;
  59         int                     pkey_index;
  60         u32                     qkey;
  61         u32                     send_psn;
  62         struct ib_ud_header     ud_header;
  63         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  64 };
  65
  66 enum {
  67         MLX4_IB_MIN_SQ_STRIDE = 6
  68 };
  69
  70 static const __be32 mlx4_ib_opcode[] = {
  71         [IB_WR_SEND]                    = __constant_cpu_to_be32(MLX4_OPCODE_SEND),
  72         [IB_WR_SEND_WITH_IMM]           = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM),
  73         [IB_WR_RDMA_WRITE]              = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
  74         [IB_WR_RDMA_WRITE_WITH_IMM]     = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
  75         [IB_WR_RDMA_READ]               = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_READ),
  76         [IB_WR_ATOMIC_CMP_AND_SWP]      = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
  77         [IB_WR_ATOMIC_FETCH_AND_ADD]    = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
  78 };
  79
  80 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
  81 {
  82         return container_of(mqp, struct mlx4_ib_sqp, qp);
  83 }
  84
  85 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
  86 {
  87         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
  88                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
  89 }
  90
  91 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
  92 {
  93         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
  94                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
  95 }
  96
  97 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
  98 {
  99         if (qp->buf.nbufs == 1)
 100                 return qp->buf.u.direct.buf + offset;
 101         else
 102                 return qp->buf.u.page_list[offset >> PAGE_SHIFT].buf +
 103                         (offset & (PAGE_SIZE - 1));
 104 }
 105
 106 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 107 {
 108         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 109 }
 110
 111 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 112 {
 113         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 114 }
 115
 116 /*
 117  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 118  * first four bytes of every 64 byte chunk with 0xffffffff, except for
 119  * the very first chunk of the WQE.
 120  */
 121 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n)
 122 {
 123         u32 *wqe = get_send_wqe(qp, n);
 124         int i;
 125
 126         for (i = 16; i < 1 << (qp->sq.wqe_shift - 2); i += 16)
 127                 wqe[i] = 0xffffffff;
 128 }
 129
 130 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 131 {
 132         struct ib_event event;
 133         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 134
 135         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 136                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 137
 138         if (ibqp->event_handler) {
 139                 event.device     = ibqp->device;
 140                 event.element.qp = ibqp;
 141                 switch (type) {
 142                 case MLX4_EVENT_TYPE_PATH_MIG:
 143                         event.event = IB_EVENT_PATH_MIG;
 144                         break;
 145                 case MLX4_EVENT_TYPE_COMM_EST:
 146                         event.event = IB_EVENT_COMM_EST;
 147                         break;
 148                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 149                         event.event = IB_EVENT_SQ_DRAINED;
 150                         break;
 151                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 152                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 153                         break;
 154                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 155                         event.event = IB_EVENT_QP_FATAL;
 156                         break;
 157                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 158                         event.event = IB_EVENT_PATH_MIG_ERR;
 159                         break;
 160                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 161                         event.event = IB_EVENT_QP_REQ_ERR;
 162                         break;
 163                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 164                         event.event = IB_EVENT_QP_ACCESS_ERR;
 165                         break;
 166                 default:
 167                         printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
 168                                "on QP %06x\n", type, qp->qpn);
 169                         return;
 170                 }
 171
 172                 ibqp->event_handler(&event, ibqp->qp_context);
 173         }
 174 }
 175
 176 static int send_wqe_overhead(enum ib_qp_type type)
 177 {
 178         /*
 179          * UD WQEs must have a datagram segment.
 180          * RC and UC WQEs might have a remote address segment.
 181          * MLX WQEs need two extra inline data segments (for the UD
 182          * header and space for the ICRC).
 183          */
 184         switch (type) {
 185         case IB_QPT_UD:
 186                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 187                         sizeof (struct mlx4_wqe_datagram_seg);
 188         case IB_QPT_UC:
 189                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 190                         sizeof (struct mlx4_wqe_raddr_seg);
 191         case IB_QPT_RC:
 192                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 193                         sizeof (struct mlx4_wqe_atomic_seg) +
 194                         sizeof (struct mlx4_wqe_raddr_seg);
 195         case IB_QPT_SMI:
 196         case IB_QPT_GSI:
 197                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 198                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 199                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 200                                            MLX4_INLINE_ALIGN) *
 201                               sizeof (struct mlx4_wqe_inline_seg),
 202                               sizeof (struct mlx4_wqe_data_seg)) +
 203                         ALIGN(4 +
 204                               sizeof (struct mlx4_wqe_inline_seg),
 205                               sizeof (struct mlx4_wqe_data_seg));
 206         default:
 207                 return sizeof (struct mlx4_wqe_ctrl_seg);
 208         }
 209 }
 210
 211 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 212                        int is_user, int has_srq, struct mlx4_ib_qp *qp)
 213 {
 214         /* Sanity check RQ size before proceeding */
 215         if (cap->max_recv_wr  > dev->dev->caps.max_wqes  ||
 216             cap->max_recv_sge > dev->dev->caps.max_rq_sg)
 217                 return -EINVAL;
 218
 219         if (has_srq) {
 220                 /* QPs attached to an SRQ should have no RQ */
 221                 if (cap->max_recv_wr)
 222                         return -EINVAL;
 223
 224                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 225         } else {
 226                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 227                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 228                         return -EINVAL;
 229
 230                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 231                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 232                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 233         }
 234
 235         cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 236         cap->max_recv_sge = qp->rq.max_gs;
 237
 238         return 0;
 239 }
 240
 241 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 242                               enum ib_qp_type type, struct mlx4_ib_qp *qp)
 243 {
 244         /* Sanity check SQ size before proceeding */
 245         if (cap->max_send_wr     > dev->dev->caps.max_wqes  ||
 246             cap->max_send_sge    > dev->dev->caps.max_sq_sg ||
 247             cap->max_inline_data + send_wqe_overhead(type) +
 248             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 249                 return -EINVAL;
 250
 251         /*
 252          * For MLX transport we need 2 extra S/G entries:
 253          * one for the header and one for the checksum at the end
 254          */
 255         if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
 256             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 257                 return -EINVAL;
 258
 259         qp->sq.wqe_shift = ilog2(roundup_pow_of_two(max(cap->max_send_sge *
 260                                                         sizeof (struct mlx4_wqe_data_seg),
 261                                                         cap->max_inline_data +
 262                                                         sizeof (struct mlx4_wqe_inline_seg)) +
 263                                                     send_wqe_overhead(type)));
 264         qp->sq.max_gs    = ((1 << qp->sq.wqe_shift) - send_wqe_overhead(type)) /
 265                 sizeof (struct mlx4_wqe_data_seg);
 266
 267         /*
 268          * We need to leave 2 KB + 1 WQE of headroom in the SQ to
 269          * allow HW to prefetch.
 270          */
 271         qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + 1;
 272         qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr + qp->sq_spare_wqes);
 273
 274         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 275                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 276         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 277                 qp->rq.offset = 0;
 278                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 279         } else {
 280                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 281                 qp->sq.offset = 0;
 282         }
 283
 284         cap->max_send_wr  = qp->sq.max_post = qp->sq.wqe_cnt - qp->sq_spare_wqes;
 285         cap->max_send_sge = qp->sq.max_gs;
 286         /* We don't support inline sends for kernel QPs (yet) */
 287         cap->max_inline_data = 0;
 288
 289         return 0;
 290 }
 291
 292 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 293                             struct mlx4_ib_qp *qp,
 294                             struct mlx4_ib_create_qp *ucmd)
 295 {
 296         /* Sanity check SQ size before proceeding */
 297         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 298             ucmd->log_sq_stride >
 299                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 300             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 301                 return -EINVAL;
 302
 303         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 304         qp->sq.wqe_shift = ucmd->log_sq_stride;
 305
 306         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 307                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 308
 309         return 0;
 310 }
 311
 312 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 313                             struct ib_qp_init_attr *init_attr,
 314                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
 315 {
 316         int err;
 317
 318         mutex_init(&qp->mutex);
 319         spin_lock_init(&qp->sq.lock);
 320         spin_lock_init(&qp->rq.lock);
 321
 322         qp->state        = IB_QPS_RESET;
 323         qp->atomic_rd_en = 0;
 324         qp->resp_depth   = 0;
 325
 326         qp->rq.head         = 0;
 327         qp->rq.tail         = 0;
 328         qp->sq.head         = 0;
 329         qp->sq.tail         = 0;
 330
 331         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp);
 332         if (err)
 333                 goto err;
 334
 335         if (pd->uobject) {
 336                 struct mlx4_ib_create_qp ucmd;
 337
 338                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 339                         err = -EFAULT;
 340                         goto err;
 341                 }
 342
 343                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 344
 345                 err = set_user_sq_size(dev, qp, &ucmd);
 346                 if (err)
 347                         goto err;
 348
 349                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 350                                        qp->buf_size, 0);
 351                 if (IS_ERR(qp->umem)) {
 352                         err = PTR_ERR(qp->umem);
 353                         goto err;
 354                 }
 355
 356                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 357                                     ilog2(qp->umem->page_size), &qp->mtt);
 358                 if (err)
 359                         goto err_buf;
 360
 361                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 362                 if (err)
 363                         goto err_mtt;
 364
 365                 if (!init_attr->srq) {
 366                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 367                                                   ucmd.db_addr, &qp->db);
 368                         if (err)
 369                                 goto err_mtt;
 370                 }
 371         } else {
 372                 qp->sq_no_prefetch = 0;
 373
 374                 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
 375                 if (err)
 376                         goto err;
 377
 378                 if (!init_attr->srq) {
 379                         err = mlx4_ib_db_alloc(dev, &qp->db, 0);
 380                         if (err)
 381                                 goto err;
 382
 383                         *qp->db.db = 0;
 384                 }
 385
 386                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
 387                         err = -ENOMEM;
 388                         goto err_db;
 389                 }
 390
 391                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 392                                     &qp->mtt);
 393                 if (err)
 394                         goto err_buf;
 395
 396                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
 397                 if (err)
 398                         goto err_mtt;
 399
 400                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 401                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 402
 403                 if (!qp->sq.wrid || !qp->rq.wrid) {
 404                         err = -ENOMEM;
 405                         goto err_wrid;
 406                 }
 407         }
 408
 409         err = mlx4_qp_alloc(dev->dev, sqpn, &qp->mqp);
 410         if (err)
 411                 goto err_wrid;
 412
 413         /*
 414          * Hardware wants QPN written in big-endian order (after
 415          * shifting) for send doorbell.  Precompute this value to save
 416          * a little bit when posting sends.
 417          */
 418         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 419
 420         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 421                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 422         else
 423                 qp->sq_signal_bits = 0;
 424
 425         qp->mqp.event = mlx4_ib_qp_event;
 426
 427         return 0;
 428
 429 err_wrid:
 430         if (pd->uobject) {
 431                 if (!init_attr->srq)
 432                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context),
 433                                               &qp->db);
 434         } else {
 435                 kfree(qp->sq.wrid);
 436                 kfree(qp->rq.wrid);
 437         }
 438
 439 err_mtt:
 440         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 441
 442 err_buf:
 443         if (pd->uobject)
 444                 ib_umem_release(qp->umem);
 445         else
 446                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 447
 448 err_db:
 449         if (!pd->uobject && !init_attr->srq)
 450                 mlx4_ib_db_free(dev, &qp->db);
 451
 452 err:
 453         return err;
 454 }
 455
 456 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 457 {
 458         switch (state) {
 459         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 460         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 461         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 462         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 463         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 464         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 465         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 466         default:                return -1;
 467         }
 468 }
 469
 470 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 471 {
 472         if (send_cq == recv_cq)
 473                 spin_lock_irq(&send_cq->lock);
 474         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 475                 spin_lock_irq(&send_cq->lock);
 476                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 477         } else {
 478                 spin_lock_irq(&recv_cq->lock);
 479                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 480         }
 481 }
 482
 483 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 484 {
 485         if (send_cq == recv_cq)
 486                 spin_unlock_irq(&send_cq->lock);
 487         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 488                 spin_unlock(&recv_cq->lock);
 489                 spin_unlock_irq(&send_cq->lock);
 490         } else {
 491                 spin_unlock(&send_cq->lock);
 492                 spin_unlock_irq(&recv_cq->lock);
 493         }
 494 }
 495
 496 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 497                               int is_user)
 498 {
 499         struct mlx4_ib_cq *send_cq, *recv_cq;
 500
 501         if (qp->state != IB_QPS_RESET)
 502                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
 503                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
 504                         printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
 505                                qp->mqp.qpn);
 506
 507         send_cq = to_mcq(qp->ibqp.send_cq);
 508         recv_cq = to_mcq(qp->ibqp.recv_cq);
 509
 510         mlx4_ib_lock_cqs(send_cq, recv_cq);
 511
 512         if (!is_user) {
 513                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
 514                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
 515                 if (send_cq != recv_cq)
 516                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
 517         }
 518
 519         mlx4_qp_remove(dev->dev, &qp->mqp);
 520
 521         mlx4_ib_unlock_cqs(send_cq, recv_cq);
 522
 523         mlx4_qp_free(dev->dev, &qp->mqp);
 524         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 525
 526         if (is_user) {
 527                 if (!qp->ibqp.srq)
 528                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
 529                                               &qp->db);
 530                 ib_umem_release(qp->umem);
 531         } else {
 532                 kfree(qp->sq.wrid);
 533                 kfree(qp->rq.wrid);
 534                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 535                 if (!qp->ibqp.srq)
 536                         mlx4_ib_db_free(dev, &qp->db);
 537         }
 538 }
 539
 540 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
 541                                 struct ib_qp_init_attr *init_attr,
 542                                 struct ib_udata *udata)
 543 {
 544         struct mlx4_ib_dev *dev = to_mdev(pd->device);
 545         struct mlx4_ib_sqp *sqp;
 546         struct mlx4_ib_qp *qp;
 547         int err;
 548
 549         switch (init_attr->qp_type) {
 550         case IB_QPT_RC:
 551         case IB_QPT_UC:
 552         case IB_QPT_UD:
 553         {
 554                 qp = kmalloc(sizeof *qp, GFP_KERNEL);
 555                 if (!qp)
 556                         return ERR_PTR(-ENOMEM);
 557
 558                 err = create_qp_common(dev, pd, init_attr, udata, 0, qp);
 559                 if (err) {
 560                         kfree(qp);
 561                         return ERR_PTR(err);
 562                 }
 563
 564                 qp->ibqp.qp_num = qp->mqp.qpn;
 565
 566                 break;
 567         }
 568         case IB_QPT_SMI:
 569         case IB_QPT_GSI:
 570         {
 571                 /* Userspace is not allowed to create special QPs: */
 572                 if (pd->uobject)
 573                         return ERR_PTR(-EINVAL);
 574
 575                 sqp = kmalloc(sizeof *sqp, GFP_KERNEL);
 576                 if (!sqp)
 577                         return ERR_PTR(-ENOMEM);
 578
 579                 qp = &sqp->qp;
 580
 581                 err = create_qp_common(dev, pd, init_attr, udata,
 582                                        dev->dev->caps.sqp_start +
 583                                        (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
 584                                        init_attr->port_num - 1,
 585                                        qp);
 586                 if (err) {
 587                         kfree(sqp);
 588                         return ERR_PTR(err);
 589                 }
 590
 591                 qp->port        = init_attr->port_num;
 592                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
 593
 594                 break;
 595         }
 596         default:
 597                 /* Don't support raw QPs */
 598                 return ERR_PTR(-EINVAL);
 599         }
 600
 601         return &qp->ibqp;
 602 }
 603
 604 int mlx4_ib_destroy_qp(struct ib_qp *qp)
 605 {
 606         struct mlx4_ib_dev *dev = to_mdev(qp->device);
 607         struct mlx4_ib_qp *mqp = to_mqp(qp);
 608
 609         if (is_qp0(dev, mqp))
 610                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
 611
 612         destroy_qp_common(dev, mqp, !!qp->pd->uobject);
 613
 614         if (is_sqp(dev, mqp))
 615                 kfree(to_msqp(mqp));
 616         else
 617                 kfree(mqp);
 618
 619         return 0;
 620 }
 621
 622 static int to_mlx4_st(enum ib_qp_type type)
 623 {
 624         switch (type) {
 625         case IB_QPT_RC:         return MLX4_QP_ST_RC;
 626         case IB_QPT_UC:         return MLX4_QP_ST_UC;
 627         case IB_QPT_UD:         return MLX4_QP_ST_UD;
 628         case IB_QPT_SMI:
 629         case IB_QPT_GSI:        return MLX4_QP_ST_MLX;
 630         default:                return -1;
 631         }
 632 }
 633
 634 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
 635                                    int attr_mask)
 636 {
 637         u8 dest_rd_atomic;
 638         u32 access_flags;
 639         u32 hw_access_flags = 0;
 640
 641         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 642                 dest_rd_atomic = attr->max_dest_rd_atomic;
 643         else
 644                 dest_rd_atomic = qp->resp_depth;
 645
 646         if (attr_mask & IB_QP_ACCESS_FLAGS)
 647                 access_flags = attr->qp_access_flags;
 648         else
 649                 access_flags = qp->atomic_rd_en;
 650
 651         if (!dest_rd_atomic)
 652                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 653
 654         if (access_flags & IB_ACCESS_REMOTE_READ)
 655                 hw_access_flags |= MLX4_QP_BIT_RRE;
 656         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 657                 hw_access_flags |= MLX4_QP_BIT_RAE;
 658         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 659                 hw_access_flags |= MLX4_QP_BIT_RWE;
 660
 661         return cpu_to_be32(hw_access_flags);
 662 }
 663
 664 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
 665                             int attr_mask)
 666 {
 667         if (attr_mask & IB_QP_PKEY_INDEX)
 668                 sqp->pkey_index = attr->pkey_index;
 669         if (attr_mask & IB_QP_QKEY)
 670                 sqp->qkey = attr->qkey;
 671         if (attr_mask & IB_QP_SQ_PSN)
 672                 sqp->send_psn = attr->sq_psn;
 673 }
 674
 675 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
 676 {
 677         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
 678 }
 679
 680 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
 681                          struct mlx4_qp_path *path, u8 port)
 682 {
 683         path->grh_mylmc     = ah->src_path_bits & 0x7f;
 684         path->rlid          = cpu_to_be16(ah->dlid);
 685         if (ah->static_rate) {
 686                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
 687                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
 688                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
 689                         --path->static_rate;
 690         } else
 691                 path->static_rate = 0;
 692         path->counter_index = 0xff;
 693
 694         if (ah->ah_flags & IB_AH_GRH) {
 695                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
 696                         printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
 697                                ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
 698                         return -1;
 699                 }
 700
 701                 path->grh_mylmc |= 1 << 7;
 702                 path->mgid_index = ah->grh.sgid_index;
 703                 path->hop_limit  = ah->grh.hop_limit;
 704                 path->tclass_flowlabel =
 705                         cpu_to_be32((ah->grh.traffic_class << 20) |
 706                                     (ah->grh.flow_label));
 707                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 708         }
 709
 710         path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
 711                 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
 712
 713         return 0;
 714 }
 715
 716 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
 717                                const struct ib_qp_attr *attr, int attr_mask,
 718                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
 719 {
 720         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
 721         struct mlx4_ib_qp *qp = to_mqp(ibqp);
 722         struct mlx4_qp_context *context;
 723         enum mlx4_qp_optpar optpar = 0;
 724         int sqd_event;
 725         int err = -EINVAL;
 726
 727         context = kzalloc(sizeof *context, GFP_KERNEL);
 728         if (!context)
 729                 return -ENOMEM;
 730
 731         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
 732                                      (to_mlx4_st(ibqp->qp_type) << 16));
 733         context->flags     |= cpu_to_be32(1 << 8); /* DE? */
 734
 735         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 736                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
 737         else {
 738                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
 739                 switch (attr->path_mig_state) {
 740                 case IB_MIG_MIGRATED:
 741                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
 742                         break;
 743                 case IB_MIG_REARM:
 744                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
 745                         break;
 746                 case IB_MIG_ARMED:
 747                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
 748                         break;
 749                 }
 750         }
 751
 752         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
 753             ibqp->qp_type == IB_QPT_UD)
 754                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
 755         else if (attr_mask & IB_QP_PATH_MTU) {
 756                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
 757                         printk(KERN_ERR "path MTU (%u) is invalid\n",
 758                                attr->path_mtu);
 759                         goto out;
 760                 }
 761                 context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 762         }
 763
 764         if (qp->rq.wqe_cnt)
 765                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
 766         context->rq_size_stride |= qp->rq.wqe_shift - 4;
 767
 768         if (qp->sq.wqe_cnt)
 769                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
 770         context->sq_size_stride |= qp->sq.wqe_shift - 4;
 771
 772         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
 773                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
 774
 775         if (qp->ibqp.uobject)
 776                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
 777         else
 778                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
 779
 780         if (attr_mask & IB_QP_DEST_QPN)
 781                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 782
 783         if (attr_mask & IB_QP_PORT) {
 784                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
 785                     !(attr_mask & IB_QP_AV)) {
 786                         mlx4_set_sched(&context->pri_path, attr->port_num);
 787                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
 788                 }
 789         }
 790
 791         if (attr_mask & IB_QP_PKEY_INDEX) {
 792                 context->pri_path.pkey_index = attr->pkey_index;
 793                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
 794         }
 795
 796         if (attr_mask & IB_QP_AV) {
 797                 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
 798                                   attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
 799                         goto out;
 800
 801                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
 802                            MLX4_QP_OPTPAR_SCHED_QUEUE);
 803         }
 804
 805         if (attr_mask & IB_QP_TIMEOUT) {
 806                 context->pri_path.ackto = attr->timeout << 3;
 807                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
 808         }
 809
 810         if (attr_mask & IB_QP_ALT_PATH) {
 811                 if (attr->alt_port_num == 0 ||
 812                     attr->alt_port_num > dev->dev->caps.num_ports)
 813                         goto out;
 814
 815                 if (attr->alt_pkey_index >=
 816                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
 817                         goto out;
 818
 819                 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
 820                                   attr->alt_port_num))
 821                         goto out;
 822
 823                 context->alt_path.pkey_index = attr->alt_pkey_index;
 824                 context->alt_path.ackto = attr->alt_timeout << 3;
 825                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
 826         }
 827
 828         context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
 829         context->params1    = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
 830
 831         if (attr_mask & IB_QP_RNR_RETRY) {
 832                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
 833                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
 834         }
 835
 836         if (attr_mask & IB_QP_RETRY_CNT) {
 837                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 838                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
 839         }
 840
 841         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 842                 if (attr->max_rd_atomic)
 843                         context->params1 |=
 844                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 845                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
 846         }
 847
 848         if (attr_mask & IB_QP_SQ_PSN)
 849                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
 850
 851         context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn);
 852
 853         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 854                 if (attr->max_dest_rd_atomic)
 855                         context->params2 |=
 856                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 857                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
 858         }
 859
 860         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
 861                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
 862                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
 863         }
 864
 865         if (ibqp->srq)
 866                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
 867
 868         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 869                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 870                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
 871         }
 872         if (attr_mask & IB_QP_RQ_PSN)
 873                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 874
 875         context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn);
 876
 877         if (attr_mask & IB_QP_QKEY) {
 878                 context->qkey = cpu_to_be32(attr->qkey);
 879                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
 880         }
 881
 882         if (ibqp->srq)
 883                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
 884
 885         if (!ibqp->srq && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
 886                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
 887
 888         if (cur_state == IB_QPS_INIT &&
 889             new_state == IB_QPS_RTR  &&
 890             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
 891              ibqp->qp_type == IB_QPT_UD)) {
 892                 context->pri_path.sched_queue = (qp->port - 1) << 6;
 893                 if (is_qp0(dev, qp))
 894                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
 895                 else
 896                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
 897         }
 898
 899         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
 900             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
 901                 sqd_event = 1;
 902         else
 903                 sqd_event = 0;
 904
 905         /*
 906          * Before passing a kernel QP to the HW, make sure that the
 907          * ownership bits of the send queue are set and the SQ
 908          * headroom is stamped so that the hardware doesn't start
 909          * processing stale work requests.
 910          */
 911         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
 912                 struct mlx4_wqe_ctrl_seg *ctrl;
 913                 int i;
 914
 915                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
 916                         ctrl = get_send_wqe(qp, i);
 917                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
 918
 919                         stamp_send_wqe(qp, i);
 920                 }
 921         }
 922
 923         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
 924                              to_mlx4_state(new_state), context, optpar,
 925                              sqd_event, &qp->mqp);
 926         if (err)
 927                 goto out;
 928
 929         qp->state = new_state;
 930
 931         if (attr_mask & IB_QP_ACCESS_FLAGS)
 932                 qp->atomic_rd_en = attr->qp_access_flags;
 933         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 934                 qp->resp_depth = attr->max_dest_rd_atomic;
 935         if (attr_mask & IB_QP_PORT)
 936                 qp->port = attr->port_num;
 937         if (attr_mask & IB_QP_ALT_PATH)
 938                 qp->alt_port = attr->alt_port_num;
 939
 940         if (is_sqp(dev, qp))
 941                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
 942
 943         /*
 944          * If we moved QP0 to RTR, bring the IB link up; if we moved
 945          * QP0 to RESET or ERROR, bring the link back down.
 946          */
 947         if (is_qp0(dev, qp)) {
 948                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
 949                         if (mlx4_INIT_PORT(dev->dev, qp->port))
 950                                 printk(KERN_WARNING "INIT_PORT failed for port %d\n",
 951                                        qp->port);
 952
 953                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
 954                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
 955                         mlx4_CLOSE_PORT(dev->dev, qp->port);
 956         }
 957
 958         /*
 959          * If we moved a kernel QP to RESET, clean up all old CQ
 960          * entries and reinitialize the QP.
 961          */
 962         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
 963                 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn,
 964                                  ibqp->srq ? to_msrq(ibqp->srq): NULL);
 965                 if (ibqp->send_cq != ibqp->recv_cq)
 966                         mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL);
 967
 968                 qp->rq.head = 0;
 969                 qp->rq.tail = 0;
 970                 qp->sq.head = 0;
 971                 qp->sq.tail = 0;
 972                 if (!ibqp->srq)
 973                         *qp->db.db  = 0;
 974         }
 975
 976 out:
 977         kfree(context);
 978         return err;
 979 }
 980
 981 static const struct ib_qp_attr mlx4_ib_qp_attr = { .port_num = 1 };
 982 static const int mlx4_ib_qp_attr_mask_table[IB_QPT_UD + 1] = {
 983                 [IB_QPT_UD]  = (IB_QP_PKEY_INDEX                |
 984                                 IB_QP_PORT                      |
 985                                 IB_QP_QKEY),
 986                 [IB_QPT_UC]  = (IB_QP_PKEY_INDEX                |
 987                                 IB_QP_PORT                      |
 988                                 IB_QP_ACCESS_FLAGS),
 989                 [IB_QPT_RC]  = (IB_QP_PKEY_INDEX                |
 990                                 IB_QP_PORT                      |
 991                                 IB_QP_ACCESS_FLAGS),
 992                 [IB_QPT_SMI] = (IB_QP_PKEY_INDEX                |
 993                                 IB_QP_QKEY),
 994                 [IB_QPT_GSI] = (IB_QP_PKEY_INDEX                |
 995                                 IB_QP_QKEY),
 996 };
 997
 998 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
 999                       int attr_mask, struct ib_udata *udata)
1000 {
1001         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1002         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1003         enum ib_qp_state cur_state, new_state;
1004         int err = -EINVAL;
1005
1006         mutex_lock(&qp->mutex);
1007
1008         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1009         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1010
1011         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1012                 goto out;
1013
1014         if ((attr_mask & IB_QP_PORT) &&
1015             (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
1016                 goto out;
1017         }
1018
1019         if (attr_mask & IB_QP_PKEY_INDEX) {
1020                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1021                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p])
1022                         goto out;
1023         }
1024
1025         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1026             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1027                 goto out;
1028         }
1029
1030         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1031             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1032                 goto out;
1033         }
1034
1035         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1036                 err = 0;
1037                 goto out;
1038         }
1039
1040         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_ERR) {
1041                 err = __mlx4_ib_modify_qp(ibqp, &mlx4_ib_qp_attr,
1042                                           mlx4_ib_qp_attr_mask_table[ibqp->qp_type],
1043                                           IB_QPS_RESET, IB_QPS_INIT);
1044                 if (err)
1045                         goto out;
1046                 cur_state = IB_QPS_INIT;
1047         }
1048
1049         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1050
1051 out:
1052         mutex_unlock(&qp->mutex);
1053         return err;
1054 }
1055
1056 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1057                             void *wqe)
1058 {
1059         struct ib_device *ib_dev = &to_mdev(sqp->qp.ibqp.device)->ib_dev;
1060         struct mlx4_wqe_mlx_seg *mlx = wqe;
1061         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1062         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1063         u16 pkey;
1064         int send_size;
1065         int header_size;
1066         int spc;
1067         int i;
1068
1069         send_size = 0;
1070         for (i = 0; i < wr->num_sge; ++i)
1071                 send_size += wr->sg_list[i].length;
1072
1073         ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), &sqp->ud_header);
1074
1075         sqp->ud_header.lrh.service_level   =
1076                 be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28;
1077         sqp->ud_header.lrh.destination_lid = ah->av.dlid;
1078         sqp->ud_header.lrh.source_lid      = cpu_to_be16(ah->av.g_slid & 0x7f);
1079         if (mlx4_ib_ah_grh_present(ah)) {
1080                 sqp->ud_header.grh.traffic_class =
1081                         (be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff;
1082                 sqp->ud_header.grh.flow_label    =
1083                         ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1084                 sqp->ud_header.grh.hop_limit     = ah->av.hop_limit;
1085                 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.port_pd) >> 24,
1086                                   ah->av.gid_index, &sqp->ud_header.grh.source_gid);
1087                 memcpy(sqp->ud_header.grh.destination_gid.raw,
1088                        ah->av.dgid, 16);
1089         }
1090
1091         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1092         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1093                                   (sqp->ud_header.lrh.destination_lid ==
1094                                    IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1095                                   (sqp->ud_header.lrh.service_level << 8));
1096         mlx->rlid   = sqp->ud_header.lrh.destination_lid;
1097
1098         switch (wr->opcode) {
1099         case IB_WR_SEND:
1100                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
1101                 sqp->ud_header.immediate_present = 0;
1102                 break;
1103         case IB_WR_SEND_WITH_IMM:
1104                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1105                 sqp->ud_header.immediate_present = 1;
1106                 sqp->ud_header.immediate_data    = wr->imm_data;
1107                 break;
1108         default:
1109                 return -EINVAL;
1110         }
1111
1112         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1113         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1114                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1115         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1116         if (!sqp->qp.ibqp.qp_num)
1117                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1118         else
1119                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1120         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1121         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1122         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1123         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1124                                                sqp->qkey : wr->wr.ud.remote_qkey);
1125         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1126
1127         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1128
1129         if (0) {
1130                 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1131                 for (i = 0; i < header_size / 4; ++i) {
1132                         if (i % 8 == 0)
1133                                 printk("  [%02x] ", i * 4);
1134                         printk(" %08x",
1135                                be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1136                         if ((i + 1) % 8 == 0)
1137                                 printk("\n");
1138                 }
1139                 printk("\n");
1140         }
1141
1142         /*
1143          * Inline data segments may not cross a 64 byte boundary.  If
1144          * our UD header is bigger than the space available up to the
1145          * next 64 byte boundary in the WQE, use two inline data
1146          * segments to hold the UD header.
1147          */
1148         spc = MLX4_INLINE_ALIGN -
1149                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1150         if (header_size <= spc) {
1151                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1152                 memcpy(inl + 1, sqp->header_buf, header_size);
1153                 i = 1;
1154         } else {
1155                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1156                 memcpy(inl + 1, sqp->header_buf, spc);
1157
1158                 inl = (void *) (inl + 1) + spc;
1159                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1160                 /*
1161                  * Need a barrier here to make sure all the data is
1162                  * visible before the byte_count field is set.
1163                  * Otherwise the HCA prefetcher could grab the 64-byte
1164                  * chunk with this inline segment and get a valid (!=
1165                  * 0xffffffff) byte count but stale data, and end up
1166                  * generating a packet with bad headers.
1167                  *
1168                  * The first inline segment's byte_count field doesn't
1169                  * need a barrier, because it comes after a
1170                  * control/MLX segment and therefore is at an offset
1171                  * of 16 mod 64.
1172                  */
1173                 wmb();
1174                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1175                 i = 2;
1176         }
1177
1178         return ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1179 }
1180
1181 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1182 {
1183         unsigned cur;
1184         struct mlx4_ib_cq *cq;
1185
1186         cur = wq->head - wq->tail;
1187         if (likely(cur + nreq < wq->max_post))
1188                 return 0;
1189
1190         cq = to_mcq(ib_cq);
1191         spin_lock(&cq->lock);
1192         cur = wq->head - wq->tail;
1193         spin_unlock(&cq->lock);
1194
1195         return cur + nreq >= wq->max_post;
1196 }
1197
1198 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
1199                                           u64 remote_addr, u32 rkey)
1200 {
1201         rseg->raddr    = cpu_to_be64(remote_addr);
1202         rseg->rkey     = cpu_to_be32(rkey);
1203         rseg->reserved = 0;
1204 }
1205
1206 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
1207 {
1208         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1209                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1210                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add);
1211         } else {
1212                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1213                 aseg->compare  = 0;
1214         }
1215
1216 }
1217
1218 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
1219                              struct ib_send_wr *wr)
1220 {
1221         memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1222         dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1223         dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1224 }
1225
1226 static void set_mlx_icrc_seg(void *dseg)
1227 {
1228         u32 *t = dseg;
1229         struct mlx4_wqe_inline_seg *iseg = dseg;
1230
1231         t[1] = 0;
1232
1233         /*
1234          * Need a barrier here before writing the byte_count field to
1235          * make sure that all the data is visible before the
1236          * byte_count field is set.  Otherwise, if the segment begins
1237          * a new cacheline, the HCA prefetcher could grab the 64-byte
1238          * chunk and get a valid (!= * 0xffffffff) byte count but
1239          * stale data, and end up sending the wrong data.
1240          */
1241         wmb();
1242
1243         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
1244 }
1245
1246 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1247 {
1248         dseg->lkey       = cpu_to_be32(sg->lkey);
1249         dseg->addr       = cpu_to_be64(sg->addr);
1250
1251         /*
1252          * Need a barrier here before writing the byte_count field to
1253          * make sure that all the data is visible before the
1254          * byte_count field is set.  Otherwise, if the segment begins
1255          * a new cacheline, the HCA prefetcher could grab the 64-byte
1256          * chunk and get a valid (!= * 0xffffffff) byte count but
1257          * stale data, and end up sending the wrong data.
1258          */
1259         wmb();
1260
1261         dseg->byte_count = cpu_to_be32(sg->length);
1262 }
1263
1264 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1265 {
1266         dseg->byte_count = cpu_to_be32(sg->length);
1267         dseg->lkey       = cpu_to_be32(sg->lkey);
1268         dseg->addr       = cpu_to_be64(sg->addr);
1269 }
1270
1271 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1272                       struct ib_send_wr **bad_wr)
1273 {
1274         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1275         void *wqe;
1276         struct mlx4_wqe_ctrl_seg *ctrl;
1277         struct mlx4_wqe_data_seg *dseg;
1278         unsigned long flags;
1279         int nreq;
1280         int err = 0;
1281         int ind;
1282         int size;
1283         int i;
1284
1285         spin_lock_irqsave(&qp->rq.lock, flags);
1286
1287         ind = qp->sq.head;
1288
1289         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1290                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1291                         err = -ENOMEM;
1292                         *bad_wr = wr;
1293                         goto out;
1294                 }
1295
1296                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1297                         err = -EINVAL;
1298                         *bad_wr = wr;
1299                         goto out;
1300                 }
1301
1302                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
1303                 qp->sq.wrid[ind & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
1304
1305                 ctrl->srcrb_flags =
1306                         (wr->send_flags & IB_SEND_SIGNALED ?
1307                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1308                         (wr->send_flags & IB_SEND_SOLICITED ?
1309                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
1310                         qp->sq_signal_bits;
1311
1312                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1313                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1314                         ctrl->imm = wr->imm_data;
1315                 else
1316                         ctrl->imm = 0;
1317
1318                 wqe += sizeof *ctrl;
1319                 size = sizeof *ctrl / 16;
1320
1321                 switch (ibqp->qp_type) {
1322                 case IB_QPT_RC:
1323                 case IB_QPT_UC:
1324                         switch (wr->opcode) {
1325                         case IB_WR_ATOMIC_CMP_AND_SWP:
1326                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1327                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1328                                               wr->wr.atomic.rkey);
1329                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1330
1331                                 set_atomic_seg(wqe, wr);
1332                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
1333
1334                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1335                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1336
1337                                 break;
1338
1339                         case IB_WR_RDMA_READ:
1340                         case IB_WR_RDMA_WRITE:
1341                         case IB_WR_RDMA_WRITE_WITH_IMM:
1342                                 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1343                                               wr->wr.rdma.rkey);
1344                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1345                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
1346                                 break;
1347
1348                         default:
1349                                 /* No extra segments required for sends */
1350                                 break;
1351                         }
1352                         break;
1353
1354                 case IB_QPT_UD:
1355                         set_datagram_seg(wqe, wr);
1356                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
1357                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
1358                         break;
1359
1360                 case IB_QPT_SMI:
1361                 case IB_QPT_GSI:
1362                         err = build_mlx_header(to_msqp(qp), wr, ctrl);
1363                         if (err < 0) {
1364                                 *bad_wr = wr;
1365                                 goto out;
1366                         }
1367                         wqe  += err;
1368                         size += err / 16;
1369
1370                         err = 0;
1371                         break;
1372
1373                 default:
1374                         break;
1375                 }
1376
1377                 /*
1378                  * Write data segments in reverse order, so as to
1379                  * overwrite cacheline stamp last within each
1380                  * cacheline.  This avoids issues with WQE
1381                  * prefetching.
1382                  */
1383
1384                 dseg = wqe;
1385                 dseg += wr->num_sge - 1;
1386                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
1387
1388                 /* Add one more inline data segment for ICRC for MLX sends */
1389                 if (unlikely(qp->ibqp.qp_type == IB_QPT_SMI ||
1390                              qp->ibqp.qp_type == IB_QPT_GSI)) {
1391                         set_mlx_icrc_seg(dseg + 1);
1392                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
1393                 }
1394
1395                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
1396                         set_data_seg(dseg, wr->sg_list + i);
1397
1398                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1399                                     MLX4_WQE_CTRL_FENCE : 0) | size;
1400
1401                 /*
1402                  * Make sure descriptor is fully written before
1403                  * setting ownership bit (because HW can start
1404                  * executing as soon as we do).
1405                  */
1406                 wmb();
1407
1408                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
1409                         err = -EINVAL;
1410                         goto out;
1411                 }
1412
1413                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
1414                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
1415
1416                 /*
1417                  * We can improve latency by not stamping the last
1418                  * send queue WQE until after ringing the doorbell, so
1419                  * only stamp here if there are still more WQEs to post.
1420                  */
1421                 if (wr->next)
1422                         stamp_send_wqe(qp, (ind + qp->sq_spare_wqes) &
1423                                        (qp->sq.wqe_cnt - 1));
1424
1425                 ++ind;
1426         }
1427
1428 out:
1429         if (likely(nreq)) {
1430                 qp->sq.head += nreq;
1431
1432                 /*
1433                  * Make sure that descriptors are written before
1434                  * doorbell record.
1435                  */
1436                 wmb();
1437
1438                 writel(qp->doorbell_qpn,
1439                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1440
1441                 /*
1442                  * Make sure doorbells don't leak out of SQ spinlock
1443                  * and reach the HCA out of order.
1444                  */
1445                 mmiowb();
1446
1447                 stamp_send_wqe(qp, (ind + qp->sq_spare_wqes - 1) &
1448                                (qp->sq.wqe_cnt - 1));
1449         }
1450
1451         spin_unlock_irqrestore(&qp->rq.lock, flags);
1452
1453         return err;
1454 }
1455
1456 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1457                       struct ib_recv_wr **bad_wr)
1458 {
1459         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1460         struct mlx4_wqe_data_seg *scat;
1461         unsigned long flags;
1462         int err = 0;
1463         int nreq;
1464         int ind;
1465         int i;
1466
1467         spin_lock_irqsave(&qp->rq.lock, flags);
1468
1469         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
1470
1471         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1472                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.send_cq)) {
1473                         err = -ENOMEM;
1474                         *bad_wr = wr;
1475                         goto out;
1476                 }
1477
1478                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1479                         err = -EINVAL;
1480                         *bad_wr = wr;
1481                         goto out;
1482                 }
1483
1484                 scat = get_recv_wqe(qp, ind);
1485
1486                 for (i = 0; i < wr->num_sge; ++i)
1487                         __set_data_seg(scat + i, wr->sg_list + i);
1488
1489                 if (i < qp->rq.max_gs) {
1490                         scat[i].byte_count = 0;
1491                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
1492                         scat[i].addr       = 0;
1493                 }
1494
1495                 qp->rq.wrid[ind] = wr->wr_id;
1496
1497                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
1498         }
1499
1500 out:
1501         if (likely(nreq)) {
1502                 qp->rq.head += nreq;
1503
1504                 /*
1505                  * Make sure that descriptors are written before
1506                  * doorbell record.
1507                  */
1508                 wmb();
1509
1510                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1511         }
1512
1513         spin_unlock_irqrestore(&qp->rq.lock, flags);
1514
1515         return err;
1516 }
1517
1518 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
1519 {
1520         switch (mlx4_state) {
1521         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
1522         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
1523         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
1524         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
1525         case MLX4_QP_STATE_SQ_DRAINING:
1526         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
1527         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
1528         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
1529         default:                     return -1;
1530         }
1531 }
1532
1533 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
1534 {
1535         switch (mlx4_mig_state) {
1536         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
1537         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
1538         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
1539         default: return -1;
1540         }
1541 }
1542
1543 static int to_ib_qp_access_flags(int mlx4_flags)
1544 {
1545         int ib_flags = 0;
1546
1547         if (mlx4_flags & MLX4_QP_BIT_RRE)
1548                 ib_flags |= IB_ACCESS_REMOTE_READ;
1549         if (mlx4_flags & MLX4_QP_BIT_RWE)
1550                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
1551         if (mlx4_flags & MLX4_QP_BIT_RAE)
1552                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
1553
1554         return ib_flags;
1555 }
1556
1557 static void to_ib_ah_attr(struct mlx4_dev *dev, struct ib_ah_attr *ib_ah_attr,
1558                                 struct mlx4_qp_path *path)
1559 {
1560         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
1561         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
1562
1563         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
1564                 return;
1565
1566         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
1567         ib_ah_attr->sl            = (path->sched_queue >> 2) & 0xf;
1568         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
1569         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
1570         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
1571         if (ib_ah_attr->ah_flags) {
1572                 ib_ah_attr->grh.sgid_index = path->mgid_index;
1573                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
1574                 ib_ah_attr->grh.traffic_class =
1575                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
1576                 ib_ah_attr->grh.flow_label =
1577                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
1578                 memcpy(ib_ah_attr->grh.dgid.raw,
1579                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
1580         }
1581 }
1582
1583 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1584                      struct ib_qp_init_attr *qp_init_attr)
1585 {
1586         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1587         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1588         struct mlx4_qp_context context;
1589         int mlx4_state;
1590         int err;
1591
1592         if (qp->state == IB_QPS_RESET) {
1593                 qp_attr->qp_state = IB_QPS_RESET;
1594                 goto done;
1595         }
1596
1597         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
1598         if (err)
1599                 return -EINVAL;
1600
1601         mlx4_state = be32_to_cpu(context.flags) >> 28;
1602
1603         qp_attr->qp_state            = to_ib_qp_state(mlx4_state);
1604         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
1605         qp_attr->path_mig_state      =
1606                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
1607         qp_attr->qkey                = be32_to_cpu(context.qkey);
1608         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
1609         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
1610         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
1611         qp_attr->qp_access_flags     =
1612                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
1613
1614         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
1615                 to_ib_ah_attr(dev->dev, &qp_attr->ah_attr, &context.pri_path);
1616                 to_ib_ah_attr(dev->dev, &qp_attr->alt_ah_attr, &context.alt_path);
1617                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
1618                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
1619         }
1620
1621         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1622         if (qp_attr->qp_state == IB_QPS_INIT)
1623                 qp_attr->port_num = qp->port;
1624         else
1625                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
1626
1627         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
1628         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
1629
1630         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
1631
1632         qp_attr->max_dest_rd_atomic =
1633                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
1634         qp_attr->min_rnr_timer      =
1635                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
1636         qp_attr->timeout            = context.pri_path.ackto >> 3;
1637         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
1638         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
1639         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
1640
1641 done:
1642         qp_attr->cur_qp_state        = qp_attr->qp_state;
1643         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
1644         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
1645
1646         if (!ibqp->uobject) {
1647                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
1648                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
1649         } else {
1650                 qp_attr->cap.max_send_wr  = 0;
1651                 qp_attr->cap.max_send_sge = 0;
1652         }
1653
1654         /*
1655          * We don't support inline sends for kernel QPs (yet), and we
1656          * don't know what userspace's value should be.
1657          */
1658         qp_attr->cap.max_inline_data = 0;
1659
1660         qp_init_attr->cap            = qp_attr->cap;
1661
1662         return 0;
1663 }
1664