drivers/infiniband/hw/ipath/ipath_ht400.c

   1 /*
   2  * Copyright (c) 2006 QLogic, Inc. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 /*
  35  * This file contains all of the code that is specific to the InfiniPath
  36  * HT-400 chip.
  37  */
  38
  39 #include <linux/pci.h>
  40 #include <linux/delay.h>
  41
  42 #include "ipath_kernel.h"
  43 #include "ipath_registers.h"
  44
  45 /*
  46  * This lists the InfiniPath HT400 registers, in the actual chip layout.
  47  * This structure should never be directly accessed.
  48  *
  49  * The names are in InterCap form because they're taken straight from
  50  * the chip specification.  Since they're only used in this file, they
  51  * don't pollute the rest of the source.
  52 */
  53
  54 struct _infinipath_do_not_use_kernel_regs {
  55         unsigned long long Revision;
  56         unsigned long long Control;
  57         unsigned long long PageAlign;
  58         unsigned long long PortCnt;
  59         unsigned long long DebugPortSelect;
  60         unsigned long long DebugPort;
  61         unsigned long long SendRegBase;
  62         unsigned long long UserRegBase;
  63         unsigned long long CounterRegBase;
  64         unsigned long long Scratch;
  65         unsigned long long ReservedMisc1;
  66         unsigned long long InterruptConfig;
  67         unsigned long long IntBlocked;
  68         unsigned long long IntMask;
  69         unsigned long long IntStatus;
  70         unsigned long long IntClear;
  71         unsigned long long ErrorMask;
  72         unsigned long long ErrorStatus;
  73         unsigned long long ErrorClear;
  74         unsigned long long HwErrMask;
  75         unsigned long long HwErrStatus;
  76         unsigned long long HwErrClear;
  77         unsigned long long HwDiagCtrl;
  78         unsigned long long MDIO;
  79         unsigned long long IBCStatus;
  80         unsigned long long IBCCtrl;
  81         unsigned long long ExtStatus;
  82         unsigned long long ExtCtrl;
  83         unsigned long long GPIOOut;
  84         unsigned long long GPIOMask;
  85         unsigned long long GPIOStatus;
  86         unsigned long long GPIOClear;
  87         unsigned long long RcvCtrl;
  88         unsigned long long RcvBTHQP;
  89         unsigned long long RcvHdrSize;
  90         unsigned long long RcvHdrCnt;
  91         unsigned long long RcvHdrEntSize;
  92         unsigned long long RcvTIDBase;
  93         unsigned long long RcvTIDCnt;
  94         unsigned long long RcvEgrBase;
  95         unsigned long long RcvEgrCnt;
  96         unsigned long long RcvBufBase;
  97         unsigned long long RcvBufSize;
  98         unsigned long long RxIntMemBase;
  99         unsigned long long RxIntMemSize;
 100         unsigned long long RcvPartitionKey;
 101         unsigned long long ReservedRcv[10];
 102         unsigned long long SendCtrl;
 103         unsigned long long SendPIOBufBase;
 104         unsigned long long SendPIOSize;
 105         unsigned long long SendPIOBufCnt;
 106         unsigned long long SendPIOAvailAddr;
 107         unsigned long long TxIntMemBase;
 108         unsigned long long TxIntMemSize;
 109         unsigned long long ReservedSend[9];
 110         unsigned long long SendBufferError;
 111         unsigned long long SendBufferErrorCONT1;
 112         unsigned long long SendBufferErrorCONT2;
 113         unsigned long long SendBufferErrorCONT3;
 114         unsigned long long ReservedSBE[4];
 115         unsigned long long RcvHdrAddr0;
 116         unsigned long long RcvHdrAddr1;
 117         unsigned long long RcvHdrAddr2;
 118         unsigned long long RcvHdrAddr3;
 119         unsigned long long RcvHdrAddr4;
 120         unsigned long long RcvHdrAddr5;
 121         unsigned long long RcvHdrAddr6;
 122         unsigned long long RcvHdrAddr7;
 123         unsigned long long RcvHdrAddr8;
 124         unsigned long long ReservedRHA[7];
 125         unsigned long long RcvHdrTailAddr0;
 126         unsigned long long RcvHdrTailAddr1;
 127         unsigned long long RcvHdrTailAddr2;
 128         unsigned long long RcvHdrTailAddr3;
 129         unsigned long long RcvHdrTailAddr4;
 130         unsigned long long RcvHdrTailAddr5;
 131         unsigned long long RcvHdrTailAddr6;
 132         unsigned long long RcvHdrTailAddr7;
 133         unsigned long long RcvHdrTailAddr8;
 134         unsigned long long ReservedRHTA[7];
 135         unsigned long long Sync;        /* Software only */
 136         unsigned long long Dump;        /* Software only */
 137         unsigned long long SimVer;      /* Software only */
 138         unsigned long long ReservedSW[5];
 139         unsigned long long SerdesConfig0;
 140         unsigned long long SerdesConfig1;
 141         unsigned long long SerdesStatus;
 142         unsigned long long XGXSConfig;
 143         unsigned long long ReservedSW2[4];
 144 };
 145
 146 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
 147     _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
 148 #define IPATH_CREG_OFFSET(field) (offsetof( \
 149     struct infinipath_counters, field) / sizeof(u64))
 150
 151 static const struct ipath_kregs ipath_ht_kregs = {
 152         .kr_control = IPATH_KREG_OFFSET(Control),
 153         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
 154         .kr_debugport = IPATH_KREG_OFFSET(DebugPort),
 155         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
 156         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
 157         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
 158         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
 159         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
 160         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
 161         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
 162         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
 163         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
 164         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
 165         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
 166         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
 167         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
 168         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
 169         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
 170         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
 171         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
 172         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
 173         .kr_interruptconfig = IPATH_KREG_OFFSET(InterruptConfig),
 174         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
 175         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
 176         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
 177         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
 178         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
 179         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
 180         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
 181         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
 182         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
 183         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
 184         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
 185         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
 186         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
 187         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
 188         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
 189         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
 190         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
 191         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
 192         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
 193         .kr_revision = IPATH_KREG_OFFSET(Revision),
 194         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
 195         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
 196         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
 197         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
 198         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
 199         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
 200         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
 201         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
 202         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
 203         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
 204         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
 205         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
 206         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
 207         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
 208         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
 209         /*
 210          * These should not be used directly via ipath_read_kreg64(),
 211          * use them with ipath_read_kreg64_port(),
 212          */
 213         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
 214         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0)
 215 };
 216
 217 static const struct ipath_cregs ipath_ht_cregs = {
 218         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
 219         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
 220         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
 221         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
 222         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
 223         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
 224         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
 225         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
 226         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
 227         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
 228         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
 229         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
 230         /* calc from Reg_CounterRegBase + offset */
 231         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
 232         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
 233         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
 234         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
 235         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
 236         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
 237         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
 238         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
 239         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
 240         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
 241         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
 242         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
 243         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
 244         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
 245         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
 246         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
 247         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
 248         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
 249         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
 250         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
 251         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
 252 };
 253
 254 /* kr_intstatus, kr_intclear, kr_intmask bits */
 255 #define INFINIPATH_I_RCVURG_MASK 0x1FF
 256 #define INFINIPATH_I_RCVAVAIL_MASK 0x1FF
 257
 258 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
 259 #define INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT 0
 260 #define INFINIPATH_HWE_HTCMEMPARITYERR_MASK 0x3FFFFFULL
 261 #define INFINIPATH_HWE_HTCLNKABYTE0CRCERR   0x0000000000800000ULL
 262 #define INFINIPATH_HWE_HTCLNKABYTE1CRCERR   0x0000000001000000ULL
 263 #define INFINIPATH_HWE_HTCLNKBBYTE0CRCERR   0x0000000002000000ULL
 264 #define INFINIPATH_HWE_HTCLNKBBYTE1CRCERR   0x0000000004000000ULL
 265 #define INFINIPATH_HWE_HTCMISCERR4          0x0000000008000000ULL
 266 #define INFINIPATH_HWE_HTCMISCERR5          0x0000000010000000ULL
 267 #define INFINIPATH_HWE_HTCMISCERR6          0x0000000020000000ULL
 268 #define INFINIPATH_HWE_HTCMISCERR7          0x0000000040000000ULL
 269 #define INFINIPATH_HWE_HTCBUSTREQPARITYERR  0x0000000080000000ULL
 270 #define INFINIPATH_HWE_HTCBUSTRESPPARITYERR 0x0000000100000000ULL
 271 #define INFINIPATH_HWE_HTCBUSIREQPARITYERR  0x0000000200000000ULL
 272 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
 273 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
 274 #define INFINIPATH_HWE_HTBPLL_FBSLIP        0x0200000000000000ULL
 275 #define INFINIPATH_HWE_HTBPLL_RFSLIP        0x0400000000000000ULL
 276 #define INFINIPATH_HWE_HTAPLL_FBSLIP        0x0800000000000000ULL
 277 #define INFINIPATH_HWE_HTAPLL_RFSLIP        0x1000000000000000ULL
 278 #define INFINIPATH_HWE_SERDESPLLFAILED      0x2000000000000000ULL
 279
 280 /* kr_extstatus bits */
 281 #define INFINIPATH_EXTS_FREQSEL 0x2
 282 #define INFINIPATH_EXTS_SERDESSEL 0x4
 283 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
 284 #define INFINIPATH_EXTS_MEMBIST_CORRECT     0x0000000000008000
 285
 286 /*
 287  * masks and bits that are different in different chips, or present only
 288  * in one
 289  */
 290 static const ipath_err_t infinipath_hwe_htcmemparityerr_mask =
 291     INFINIPATH_HWE_HTCMEMPARITYERR_MASK;
 292 static const ipath_err_t infinipath_hwe_htcmemparityerr_shift =
 293     INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT;
 294
 295 static const ipath_err_t infinipath_hwe_htclnkabyte0crcerr =
 296     INFINIPATH_HWE_HTCLNKABYTE0CRCERR;
 297 static const ipath_err_t infinipath_hwe_htclnkabyte1crcerr =
 298     INFINIPATH_HWE_HTCLNKABYTE1CRCERR;
 299 static const ipath_err_t infinipath_hwe_htclnkbbyte0crcerr =
 300     INFINIPATH_HWE_HTCLNKBBYTE0CRCERR;
 301 static const ipath_err_t infinipath_hwe_htclnkbbyte1crcerr =
 302     INFINIPATH_HWE_HTCLNKBBYTE1CRCERR;
 303
 304 #define _IPATH_GPIO_SDA_NUM 1
 305 #define _IPATH_GPIO_SCL_NUM 0
 306
 307 #define IPATH_GPIO_SDA \
 308         (1ULL << (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 309 #define IPATH_GPIO_SCL \
 310         (1ULL << (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 311
 312 /* keep the code below somewhat more readonable; not used elsewhere */
 313 #define _IPATH_HTLINK0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
 314                                 infinipath_hwe_htclnkabyte1crcerr)
 315 #define _IPATH_HTLINK1_CRCBITS (infinipath_hwe_htclnkbbyte0crcerr |     \
 316                                 infinipath_hwe_htclnkbbyte1crcerr)
 317 #define _IPATH_HTLANE0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
 318                                 infinipath_hwe_htclnkbbyte0crcerr)
 319 #define _IPATH_HTLANE1_CRCBITS (infinipath_hwe_htclnkabyte1crcerr |     \
 320                                 infinipath_hwe_htclnkbbyte1crcerr)
 321
 322 static void hwerr_crcbits(struct ipath_devdata *dd, ipath_err_t hwerrs,
 323                           char *msg, size_t msgl)
 324 {
 325         char bitsmsg[64];
 326         ipath_err_t crcbits = hwerrs &
 327                 (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS);
 328         /* don't check if 8bit HT */
 329         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
 330                 crcbits &= ~infinipath_hwe_htclnkabyte1crcerr;
 331         /* don't check if 8bit HT */
 332         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
 333                 crcbits &= ~infinipath_hwe_htclnkbbyte1crcerr;
 334         /*
 335          * we'll want to ignore link errors on link that is
 336          * not in use, if any.  For now, complain about both
 337          */
 338         if (crcbits) {
 339                 u16 ctrl0, ctrl1;
 340                 snprintf(bitsmsg, sizeof bitsmsg,
 341                          "[HT%s lane %s CRC (%llx); ignore till reload]",
 342                          !(crcbits & _IPATH_HTLINK1_CRCBITS) ?
 343                          "0 (A)" : (!(crcbits & _IPATH_HTLINK0_CRCBITS)
 344                                     ? "1 (B)" : "0+1 (A+B)"),
 345                          !(crcbits & _IPATH_HTLANE1_CRCBITS) ? "0"
 346                          : (!(crcbits & _IPATH_HTLANE0_CRCBITS) ? "1" :
 347                             "0+1"), (unsigned long long) crcbits);
 348                 strlcat(msg, bitsmsg, msgl);
 349
 350                 /*
 351                  * print extra info for debugging.  slave/primary
 352                  * config word 4, 8 (link control 0, 1)
 353                  */
 354
 355                 if (pci_read_config_word(dd->pcidev,
 356                                          dd->ipath_ht_slave_off + 0x4,
 357                                          &ctrl0))
 358                         dev_info(&dd->pcidev->dev, "Couldn't read "
 359                                  "linkctrl0 of slave/primary "
 360                                  "config block\n");
 361                 else if (!(ctrl0 & 1 << 6))
 362                         /* not if EOC bit set */
 363                         ipath_dbg("HT linkctrl0 0x%x%s%s\n", ctrl0,
 364                                   ((ctrl0 >> 8) & 7) ? " CRC" : "",
 365                                   ((ctrl0 >> 4) & 1) ? "linkfail" :
 366                                   "");
 367                 if (pci_read_config_word(dd->pcidev,
 368                                          dd->ipath_ht_slave_off + 0x8,
 369                                          &ctrl1))
 370                         dev_info(&dd->pcidev->dev, "Couldn't read "
 371                                  "linkctrl1 of slave/primary "
 372                                  "config block\n");
 373                 else if (!(ctrl1 & 1 << 6))
 374                         /* not if EOC bit set */
 375                         ipath_dbg("HT linkctrl1 0x%x%s%s\n", ctrl1,
 376                                   ((ctrl1 >> 8) & 7) ? " CRC" : "",
 377                                   ((ctrl1 >> 4) & 1) ? "linkfail" :
 378                                   "");
 379
 380                 /* disable until driver reloaded */
 381                 dd->ipath_hwerrmask &= ~crcbits;
 382                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 383                                  dd->ipath_hwerrmask);
 384                 ipath_dbg("HT crc errs: %s\n", msg);
 385         } else
 386                 ipath_dbg("ignoring HT crc errors 0x%llx, "
 387                           "not in use\n", (unsigned long long)
 388                           (hwerrs & (_IPATH_HTLINK0_CRCBITS |
 389                                      _IPATH_HTLINK1_CRCBITS)));
 390 }
 391
 392 /**
 393  * ipath_ht_handle_hwerrors - display hardware errors
 394  * @dd: the infinipath device
 395  * @msg: the output buffer
 396  * @msgl: the size of the output buffer
 397  *
 398  * Use same msg buffer as regular errors to avoid
 399  * excessive stack use.  Most hardware errors are catastrophic, but for
 400  * right now, we'll print them and continue.
 401  * We reuse the same message buffer as ipath_handle_errors() to avoid
 402  * excessive stack usage.
 403  */
 404 static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
 405                                      size_t msgl)
 406 {
 407         ipath_err_t hwerrs;
 408         u32 bits, ctrl;
 409         int isfatal = 0;
 410         char bitsmsg[64];
 411
 412         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
 413
 414         if (!hwerrs) {
 415                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
 416                 /*
 417                  * better than printing cofusing messages
 418                  * This seems to be related to clearing the crc error, or
 419                  * the pll error during init.
 420                  */
 421                 goto bail;
 422         } else if (hwerrs == -1LL) {
 423                 ipath_dev_err(dd, "Read of hardware error status failed "
 424                               "(all bits set); ignoring\n");
 425                 goto bail;
 426         }
 427         ipath_stats.sps_hwerrs++;
 428
 429         /* Always clear the error status register, except MEMBISTFAIL,
 430          * regardless of whether we continue or stop using the chip.
 431          * We want that set so we know it failed, even across driver reload.
 432          * We'll still ignore it in the hwerrmask.  We do this partly for
 433          * diagnostics, but also for support */
 434         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 435                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
 436
 437         hwerrs &= dd->ipath_hwerrmask;
 438
 439         /*
 440          * make sure we get this much out, unless told to be quiet,
 441          * or it's occurred within the last 5 seconds
 442          */
 443         if ((hwerrs & ~dd->ipath_lasthwerror) ||
 444             (ipath_debug & __IPATH_VERBDBG))
 445                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
 446                          "(cleared)\n", (unsigned long long) hwerrs);
 447         dd->ipath_lasthwerror |= hwerrs;
 448
 449         if (hwerrs & ~infinipath_hwe_bitsextant)
 450                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
 451                               "%llx set\n", (unsigned long long)
 452                               (hwerrs & ~infinipath_hwe_bitsextant));
 453
 454         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
 455         if (ctrl & INFINIPATH_C_FREEZEMODE) {
 456                 if (hwerrs) {
 457                         /*
 458                          * if any set that we aren't ignoring; only
 459                          * make the complaint once, in case it's stuck
 460                          * or recurring, and we get here multiple
 461                          * times.
 462                          */
 463                         if (dd->ipath_flags & IPATH_INITTED) {
 464                                 ipath_dev_err(dd, "Fatal Error (freeze "
 465                                               "mode), no longer usable\n");
 466                                 isfatal = 1;
 467                         }
 468                         *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
 469                         /* mark as having had error */
 470                         *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 471                         /*
 472                          * mark as not usable, at a minimum until driver
 473                          * is reloaded, probably until reboot, since no
 474                          * other reset is possible.
 475                          */
 476                         dd->ipath_flags &= ~IPATH_INITTED;
 477                 } else {
 478                         ipath_dbg("Clearing freezemode on ignored hardware "
 479                                   "error\n");
 480                         ctrl &= ~INFINIPATH_C_FREEZEMODE;
 481                         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 482                                          ctrl);
 483                 }
 484         }
 485
 486         *msg = '\0';
 487
 488         /*
 489          * may someday want to decode into which bits are which
 490          * functional area for parity errors, etc.
 491          */
 492         if (hwerrs & (infinipath_hwe_htcmemparityerr_mask
 493                       << INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT)) {
 494                 bits = (u32) ((hwerrs >>
 495                                INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) &
 496                               INFINIPATH_HWE_HTCMEMPARITYERR_MASK);
 497                 snprintf(bitsmsg, sizeof bitsmsg, "[HTC Parity Errs %x] ",
 498                          bits);
 499                 strlcat(msg, bitsmsg, msgl);
 500         }
 501         if (hwerrs & (INFINIPATH_HWE_RXEMEMPARITYERR_MASK
 502                       << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)) {
 503                 bits = (u32) ((hwerrs >>
 504                                INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) &
 505                               INFINIPATH_HWE_RXEMEMPARITYERR_MASK);
 506                 snprintf(bitsmsg, sizeof bitsmsg, "[RXE Parity Errs %x] ",
 507                          bits);
 508                 strlcat(msg, bitsmsg, msgl);
 509         }
 510         if (hwerrs & (INFINIPATH_HWE_TXEMEMPARITYERR_MASK
 511                       << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)) {
 512                 bits = (u32) ((hwerrs >>
 513                                INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) &
 514                               INFINIPATH_HWE_TXEMEMPARITYERR_MASK);
 515                 snprintf(bitsmsg, sizeof bitsmsg, "[TXE Parity Errs %x] ",
 516                          bits);
 517                 strlcat(msg, bitsmsg, msgl);
 518         }
 519         if (hwerrs & INFINIPATH_HWE_IBCBUSTOSPCPARITYERR)
 520                 strlcat(msg, "[IB2IPATH Parity]", msgl);
 521         if (hwerrs & INFINIPATH_HWE_IBCBUSFRSPCPARITYERR)
 522                 strlcat(msg, "[IPATH2IB Parity]", msgl);
 523         if (hwerrs & INFINIPATH_HWE_HTCBUSIREQPARITYERR)
 524                 strlcat(msg, "[HTC Ireq Parity]", msgl);
 525         if (hwerrs & INFINIPATH_HWE_HTCBUSTREQPARITYERR)
 526                 strlcat(msg, "[HTC Treq Parity]", msgl);
 527         if (hwerrs & INFINIPATH_HWE_HTCBUSTRESPPARITYERR)
 528                 strlcat(msg, "[HTC Tresp Parity]", msgl);
 529
 530         if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS))
 531                 hwerr_crcbits(dd, hwerrs, msg, msgl);
 532
 533         if (hwerrs & INFINIPATH_HWE_HTCMISCERR5)
 534                 strlcat(msg, "[HT core Misc5]", msgl);
 535         if (hwerrs & INFINIPATH_HWE_HTCMISCERR6)
 536                 strlcat(msg, "[HT core Misc6]", msgl);
 537         if (hwerrs & INFINIPATH_HWE_HTCMISCERR7)
 538                 strlcat(msg, "[HT core Misc7]", msgl);
 539         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
 540                 strlcat(msg, "[Memory BIST test failed, HT-400 unusable]",
 541                         msgl);
 542                 /* ignore from now on, so disable until driver reloaded */
 543                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
 544                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 545                                  dd->ipath_hwerrmask);
 546         }
 547 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
 548                          INFINIPATH_HWE_COREPLL_RFSLIP |        \
 549                          INFINIPATH_HWE_HTBPLL_FBSLIP |         \
 550                          INFINIPATH_HWE_HTBPLL_RFSLIP |         \
 551                          INFINIPATH_HWE_HTAPLL_FBSLIP |         \
 552                          INFINIPATH_HWE_HTAPLL_RFSLIP)
 553
 554         if (hwerrs & _IPATH_PLL_FAIL) {
 555                 snprintf(bitsmsg, sizeof bitsmsg,
 556                          "[PLL failed (%llx), HT-400 unusable]",
 557                          (unsigned long long) (hwerrs & _IPATH_PLL_FAIL));
 558                 strlcat(msg, bitsmsg, msgl);
 559                 /* ignore from now on, so disable until driver reloaded */
 560                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
 561                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 562                                  dd->ipath_hwerrmask);
 563         }
 564
 565         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
 566                 /*
 567                  * If it occurs, it is left masked since the eternal
 568                  * interface is unused
 569                  */
 570                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 571                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 572                                  dd->ipath_hwerrmask);
 573         }
 574
 575         if (hwerrs & INFINIPATH_HWE_RXDSYNCMEMPARITYERR)
 576                 strlcat(msg, "[Rx Dsync]", msgl);
 577         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED)
 578                 strlcat(msg, "[SerDes PLL]", msgl);
 579
 580         ipath_dev_err(dd, "%s hardware error\n", msg);
 581         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
 582                 /*
 583                  * for status file; if no trailing brace is copied,
 584                  * we'll know it was truncated.
 585                  */
 586                 snprintf(dd->ipath_freezemsg,
 587                          dd->ipath_freezelen, "{%s}", msg);
 588
 589 bail:;
 590 }
 591
 592 /**
 593  * ipath_ht_boardname - fill in the board name
 594  * @dd: the infinipath device
 595  * @name: the output buffer
 596  * @namelen: the size of the output buffer
 597  *
 598  * fill in the board name, based on the board revision register
 599  */
 600 static int ipath_ht_boardname(struct ipath_devdata *dd, char *name,
 601                               size_t namelen)
 602 {
 603         char *n = NULL;
 604         u8 boardrev = dd->ipath_boardrev;
 605         int ret;
 606
 607         switch (boardrev) {
 608         case 4:         /* Ponderosa is one of the bringup boards */
 609                 n = "Ponderosa";
 610                 break;
 611         case 5:
 612                 /*
 613                  * HT-460 original production board; two production levels, with
 614                  * different serial number ranges.   See ipath_ht_early_init() for
 615                  * case where we enable IPATH_GPIO_INTR for later serial # range.
 616                  */
 617                 n = "InfiniPath_HT-460";
 618                 break;
 619         case 6:
 620                 n = "OEM_Board_3";
 621                 break;
 622         case 7:
 623                 /* HT-460 small form factor production board */
 624                 n = "InfiniPath_HT-465";
 625                 break;
 626         case 8:
 627                 n = "LS/X-1";
 628                 break;
 629         case 9:         /* Comstock bringup test board */
 630                 n = "Comstock";
 631                 break;
 632         case 10:
 633                 n = "OEM_Board_2";
 634                 break;
 635         case 11:
 636                 n = "InfiniPath_HT-470";
 637                 break;
 638         case 12:
 639                 n = "OEM_Board_4";
 640                 break;
 641         default:                /* don't know, just print the number */
 642                 ipath_dev_err(dd, "Don't yet know about board "
 643                               "with ID %u\n", boardrev);
 644                 snprintf(name, namelen, "Unknown_InfiniPath_HT-4xx_%u",
 645                          boardrev);
 646                 break;
 647         }
 648         if (n)
 649                 snprintf(name, namelen, "%s", n);
 650
 651         if (dd->ipath_majrev != 3 || (dd->ipath_minrev < 2 || dd->ipath_minrev > 3)) {
 652                 /*
 653                  * This version of the driver only supports the HT-400
 654                  * Rev 3.2
 655                  */
 656                 ipath_dev_err(dd,
 657                               "Unsupported HT-400 revision %u.%u!\n",
 658                               dd->ipath_majrev, dd->ipath_minrev);
 659                 ret = 1;
 660                 goto bail;
 661         }
 662         /*
 663          * pkt/word counters are 32 bit, and therefore wrap fast enough
 664          * that we snapshot them from a timer, and maintain 64 bit shadow
 665          * copies
 666          */
 667         dd->ipath_flags |= IPATH_32BITCOUNTERS;
 668         if (dd->ipath_htspeed != 800)
 669                 ipath_dev_err(dd,
 670                               "Incorrectly configured for HT @ %uMHz\n",
 671                               dd->ipath_htspeed);
 672         if (dd->ipath_boardrev == 7 || dd->ipath_boardrev == 11 ||
 673             dd->ipath_boardrev == 6)
 674                 dd->ipath_flags |= IPATH_GPIO_INTR;
 675         else
 676                 dd->ipath_flags |= IPATH_POLL_RX_INTR;
 677         if (dd->ipath_boardrev == 8) {  /* LS/X-1 */
 678                 u64 val;
 679                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
 680                 if (val & INFINIPATH_EXTS_SERDESSEL) {
 681                         /*
 682                          * hardware disabled
 683                          *
 684                          * This means that the chip is hardware disabled,
 685                          * and will not be able to bring up the link,
 686                          * in any case.  We special case this and abort
 687                          * early, to avoid later messages.  We also set
 688                          * the DISABLED status bit
 689                          */
 690                         ipath_dbg("Unit %u is hardware-disabled\n",
 691                                   dd->ipath_unit);
 692                         *dd->ipath_statusp |= IPATH_STATUS_DISABLED;
 693                         /* this value is handled differently */
 694                         ret = 2;
 695                         goto bail;
 696                 }
 697         }
 698         ret = 0;
 699
 700 bail:
 701         return ret;
 702 }
 703
 704 static void ipath_check_htlink(struct ipath_devdata *dd)
 705 {
 706         u8 linkerr, link_off, i;
 707
 708         for (i = 0; i < 2; i++) {
 709                 link_off = dd->ipath_ht_slave_off + i * 4 + 0xd;
 710                 if (pci_read_config_byte(dd->pcidev, link_off, &linkerr))
 711                         dev_info(&dd->pcidev->dev, "Couldn't read "
 712                                  "linkerror%d of HT slave/primary block\n",
 713                                  i);
 714                 else if (linkerr & 0xf0) {
 715                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
 716                                    "clearing\n", linkerr >> 4, i);
 717                         /*
 718                          * writing the linkerr bits that are set should
 719                          * clear them
 720                          */
 721                         if (pci_write_config_byte(dd->pcidev, link_off,
 722                                                   linkerr))
 723                                 ipath_dbg("Failed write to clear HT "
 724                                           "linkerror%d\n", i);
 725                         if (pci_read_config_byte(dd->pcidev, link_off,
 726                                                  &linkerr))
 727                                 dev_info(&dd->pcidev->dev,
 728                                          "Couldn't reread linkerror%d of "
 729                                          "HT slave/primary block\n", i);
 730                         else if (linkerr & 0xf0)
 731                                 dev_info(&dd->pcidev->dev,
 732                                          "HT linkerror%d bits 0x%x "
 733                                          "couldn't be cleared\n",
 734                                          i, linkerr >> 4);
 735                 }
 736         }
 737 }
 738
 739 static int ipath_setup_ht_reset(struct ipath_devdata *dd)
 740 {
 741         ipath_dbg("No reset possible for HT-400\n");
 742         return 0;
 743 }
 744
 745 #define HT_CAPABILITY_ID   0x08 /* HT capabilities not defined in kernel */
 746 #define HT_INTR_DISC_CONFIG  0x80       /* HT interrupt and discovery cap */
 747 #define HT_INTR_REG_INDEX    2  /* intconfig requires indirect accesses */
 748
 749 /*
 750  * Bits 13-15 of command==0 is slave/primary block.  Clear any HT CRC
 751  * errors.  We only bother to do this at load time, because it's OK if
 752  * it happened before we were loaded (first time after boot/reset),
 753  * but any time after that, it's fatal anyway.  Also need to not check
 754  * for for upper byte errors if we are in 8 bit mode, so figure out
 755  * our width.  For now, at least, also complain if it's 8 bit.
 756  */
 757 static void slave_or_pri_blk(struct ipath_devdata *dd, struct pci_dev *pdev,
 758                              int pos, u8 cap_type)
 759 {
 760         u8 linkwidth = 0, linkerr, link_a_b_off, link_off;
 761         u16 linkctrl = 0;
 762         int i;
 763
 764         dd->ipath_ht_slave_off = pos;
 765         /* command word, master_host bit */
 766         /* master host || slave */
 767         if ((cap_type >> 2) & 1)
 768                 link_a_b_off = 4;
 769         else
 770                 link_a_b_off = 0;
 771         ipath_cdbg(VERBOSE, "HT%u (Link %c) connected to processor\n",
 772                    link_a_b_off ? 1 : 0,
 773                    link_a_b_off ? 'B' : 'A');
 774
 775         link_a_b_off += pos;
 776
 777         /*
 778          * check both link control registers; clear both HT CRC sets if
 779          * necessary.
 780          */
 781         for (i = 0; i < 2; i++) {
 782                 link_off = pos + i * 4 + 0x4;
 783                 if (pci_read_config_word(pdev, link_off, &linkctrl))
 784                         ipath_dev_err(dd, "Couldn't read HT link control%d "
 785                                       "register\n", i);
 786                 else if (linkctrl & (0xf << 8)) {
 787                         ipath_cdbg(VERBOSE, "Clear linkctrl%d CRC Error "
 788                                    "bits %x\n", i, linkctrl & (0xf << 8));
 789                         /*
 790                          * now write them back to clear the error.
 791                          */
 792                         pci_write_config_byte(pdev, link_off,
 793                                               linkctrl & (0xf << 8));
 794                 }
 795         }
 796
 797         /*
 798          * As with HT CRC bits, same for protocol errors that might occur
 799          * during boot.
 800          */
 801         for (i = 0; i < 2; i++) {
 802                 link_off = pos + i * 4 + 0xd;
 803                 if (pci_read_config_byte(pdev, link_off, &linkerr))
 804                         dev_info(&pdev->dev, "Couldn't read linkerror%d "
 805                                  "of HT slave/primary block\n", i);
 806                 else if (linkerr & 0xf0) {
 807                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
 808                                    "clearing\n", linkerr >> 4, i);
 809                         /*
 810                          * writing the linkerr bits that are set will clear
 811                          * them
 812                          */
 813                         if (pci_write_config_byte
 814                             (pdev, link_off, linkerr))
 815                                 ipath_dbg("Failed write to clear HT "
 816                                           "linkerror%d\n", i);
 817                         if (pci_read_config_byte(pdev, link_off, &linkerr))
 818                                 dev_info(&pdev->dev, "Couldn't reread "
 819                                          "linkerror%d of HT slave/primary "
 820                                          "block\n", i);
 821                         else if (linkerr & 0xf0)
 822                                 dev_info(&pdev->dev, "HT linkerror%d bits "
 823                                          "0x%x couldn't be cleared\n",
 824                                          i, linkerr >> 4);
 825                 }
 826         }
 827
 828         /*
 829          * this is just for our link to the host, not devices connected
 830          * through tunnel.
 831          */
 832
 833         if (pci_read_config_byte(pdev, link_a_b_off + 7, &linkwidth))
 834                 ipath_dev_err(dd, "Couldn't read HT link width "
 835                               "config register\n");
 836         else {
 837                 u32 width;
 838                 switch (linkwidth & 7) {
 839                 case 5:
 840                         width = 4;
 841                         break;
 842                 case 4:
 843                         width = 2;
 844                         break;
 845                 case 3:
 846                         width = 32;
 847                         break;
 848                 case 1:
 849                         width = 16;
 850                         break;
 851                 case 0:
 852                 default:        /* if wrong, assume 8 bit */
 853                         width = 8;
 854                         break;
 855                 }
 856
 857                 dd->ipath_htwidth = width;
 858
 859                 if (linkwidth != 0x11) {
 860                         ipath_dev_err(dd, "Not configured for 16 bit HT "
 861                                       "(%x)\n", linkwidth);
 862                         if (!(linkwidth & 0xf)) {
 863                                 ipath_dbg("Will ignore HT lane1 errors\n");
 864                                 dd->ipath_flags |= IPATH_8BIT_IN_HT0;
 865                         }
 866                 }
 867         }
 868
 869         /*
 870          * this is just for our link to the host, not devices connected
 871          * through tunnel.
 872          */
 873         if (pci_read_config_byte(pdev, link_a_b_off + 0xd, &linkwidth))
 874                 ipath_dev_err(dd, "Couldn't read HT link frequency "
 875                               "config register\n");
 876         else {
 877                 u32 speed;
 878                 switch (linkwidth & 0xf) {
 879                 case 6:
 880                         speed = 1000;
 881                         break;
 882                 case 5:
 883                         speed = 800;
 884                         break;
 885                 case 4:
 886                         speed = 600;
 887                         break;
 888                 case 3:
 889                         speed = 500;
 890                         break;
 891                 case 2:
 892                         speed = 400;
 893                         break;
 894                 case 1:
 895                         speed = 300;
 896                         break;
 897                 default:
 898                         /*
 899                          * assume reserved and vendor-specific are 200...
 900                          */
 901                 case 0:
 902                         speed = 200;
 903                         break;
 904                 }
 905                 dd->ipath_htspeed = speed;
 906         }
 907 }
 908
 909 static int set_int_handler(struct ipath_devdata *dd, struct pci_dev *pdev,
 910                             int pos)
 911 {
 912         u32 int_handler_addr_lower;
 913         u32 int_handler_addr_upper;
 914         u64 ihandler;
 915         u32 intvec;
 916
 917         /* use indirection register to get the intr handler */
 918         pci_write_config_byte(pdev, pos + HT_INTR_REG_INDEX, 0x10);
 919         pci_read_config_dword(pdev, pos + 4, &int_handler_addr_lower);
 920         pci_write_config_byte(pdev, pos + HT_INTR_REG_INDEX, 0x11);
 921         pci_read_config_dword(pdev, pos + 4, &int_handler_addr_upper);
 922
 923         ihandler = (u64) int_handler_addr_lower |
 924                 ((u64) int_handler_addr_upper << 32);
 925
 926         /*
 927          * kernels with CONFIG_PCI_MSI set the vector in the irq field of
 928          * struct pci_device, so we use that to program the HT-400 internal
 929          * interrupt register (not config space) with that value. The BIOS
 930          * must still have done the basic MSI setup.
 931          */
 932         intvec = pdev->irq;
 933         /*
 934          * clear any vector bits there; normally not set but we'll overload
 935          * this for some debug purposes (setting the HTC debug register
 936          * value from software, rather than GPIOs), so it might be set on a
 937          * driver reload.
 938          */
 939         ihandler &= ~0xff0000;
 940         /* x86 vector goes in intrinfo[23:16] */
 941         ihandler |= intvec << 16;
 942         ipath_cdbg(VERBOSE, "ihandler lower %x, upper %x, intvec %x, "
 943                    "interruptconfig %llx\n", int_handler_addr_lower,
 944                    int_handler_addr_upper, intvec,
 945                    (unsigned long long) ihandler);
 946
 947         /* can't program yet, so save for interrupt setup */
 948         dd->ipath_intconfig = ihandler;
 949         /* keep going, so we find link control stuff also */
 950
 951         return ihandler != 0;
 952 }
 953
 954 /**
 955  * ipath_setup_ht_config - setup the interruptconfig register
 956  * @dd: the infinipath device
 957  * @pdev: the PCI device
 958  *
 959  * setup the interruptconfig register from the HT config info.
 960  * Also clear CRC errors in HT linkcontrol, if necessary.
 961  * This is done only for the real hardware.  It is done before
 962  * chip address space is initted, so can't touch infinipath registers
 963  */
 964 static int ipath_setup_ht_config(struct ipath_devdata *dd,
 965                                  struct pci_dev *pdev)
 966 {
 967         int pos, ret = 0;
 968         int ihandler = 0;
 969
 970         /*
 971          * Read the capability info to find the interrupt info, and also
 972          * handle clearing CRC errors in linkctrl register if necessary.  We
 973          * do this early, before we ever enable errors or hardware errors,
 974          * mostly to avoid causing the chip to enter freeze mode.
 975          */
 976         pos = pci_find_capability(pdev, HT_CAPABILITY_ID);
 977         if (!pos) {
 978                 ipath_dev_err(dd, "Couldn't find HyperTransport "
 979                               "capability; no interrupts\n");
 980                 ret = -ENODEV;
 981                 goto bail;
 982         }
 983         do {
 984                 u8 cap_type;
 985
 986                 /* the HT capability type byte is 3 bytes after the
 987                  * capability byte.
 988                  */
 989                 if (pci_read_config_byte(pdev, pos + 3, &cap_type)) {
 990                         dev_info(&pdev->dev, "Couldn't read config "
 991                                  "command @ %d\n", pos);
 992                         continue;
 993                 }
 994                 if (!(cap_type & 0xE0))
 995                         slave_or_pri_blk(dd, pdev, pos, cap_type);
 996                 else if (cap_type == HT_INTR_DISC_CONFIG)
 997                         ihandler = set_int_handler(dd, pdev, pos);
 998         } while ((pos = pci_find_next_capability(pdev, pos,
 999                                                  HT_CAPABILITY_ID)));
1000
1001         if (!ihandler) {
1002                 ipath_dev_err(dd, "Couldn't find interrupt handler in "
1003                               "config space\n");
1004                 ret = -ENODEV;
1005         }
1006
1007 bail:
1008         return ret;
1009 }
1010
1011 /**
1012  * ipath_setup_ht_cleanup - clean up any per-chip chip-specific stuff
1013  * @dd: the infinipath device
1014  *
1015  * Called during driver unload.
1016  * This is currently a nop for the HT-400, not for all chips
1017  */
1018 static void ipath_setup_ht_cleanup(struct ipath_devdata *dd)
1019 {
1020 }
1021
1022 /**
1023  * ipath_setup_ht_setextled - set the state of the two external LEDs
1024  * @dd: the infinipath device
1025  * @lst: the L state
1026  * @ltst: the LT state
1027  *
1028  * Set the state of the two external LEDs, to indicate physical and
1029  * logical state of IB link.   For this chip (at least with recommended
1030  * board pinouts), LED1 is Green (physical state), and LED2 is Yellow
1031  * (logical state)
1032  *
1033  * Note:  We try to match the Mellanox HCA LED behavior as best
1034  * we can.  Green indicates physical link state is OK (something is
1035  * plugged in, and we can train).
1036  * Amber indicates the link is logically up (ACTIVE).
1037  * Mellanox further blinks the amber LED to indicate data packet
1038  * activity, but we have no hardware support for that, so it would
1039  * require waking up every 10-20 msecs and checking the counters
1040  * on the chip, and then turning the LED off if appropriate.  That's
1041  * visible overhead, so not something we will do.
1042  *
1043  */
1044 static void ipath_setup_ht_setextled(struct ipath_devdata *dd,
1045                                      u64 lst, u64 ltst)
1046 {
1047         u64 extctl;
1048
1049         /* the diags use the LED to indicate diag info, so we leave
1050          * the external LED alone when the diags are running */
1051         if (ipath_diag_inuse)
1052                 return;
1053
1054         /*
1055          * start by setting both LED control bits to off, then turn
1056          * on the appropriate bit(s).
1057          */
1058         if (dd->ipath_boardrev == 8) { /* LS/X-1 uses different pins */
1059                 /*
1060                  * major difference is that INFINIPATH_EXTC_LEDGBLERR_OFF
1061                  * is inverted,  because it is normally used to indicate
1062                  * a hardware fault at reset, if there were errors
1063                  */
1064                 extctl = (dd->ipath_extctrl & ~INFINIPATH_EXTC_LEDGBLOK_ON)
1065                         | INFINIPATH_EXTC_LEDGBLERR_OFF;
1066                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1067                         extctl &= ~INFINIPATH_EXTC_LEDGBLERR_OFF;
1068                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1069                         extctl |= INFINIPATH_EXTC_LEDGBLOK_ON;
1070         }
1071         else {
1072                 extctl = dd->ipath_extctrl &
1073                         ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1074                           INFINIPATH_EXTC_LED2PRIPORT_ON);
1075                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1076                         extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1077                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1078                         extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1079         }
1080         dd->ipath_extctrl = extctl;
1081         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1082 }
1083
1084 static void ipath_init_ht_variables(void)
1085 {
1086         ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1087         ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1088         ipath_gpio_sda = IPATH_GPIO_SDA;
1089         ipath_gpio_scl = IPATH_GPIO_SCL;
1090
1091         infinipath_i_bitsextant =
1092                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1093                 (INFINIPATH_I_RCVAVAIL_MASK <<
1094                  INFINIPATH_I_RCVAVAIL_SHIFT) |
1095                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1096                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1097
1098         infinipath_e_bitsextant =
1099                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1100                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1101                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1102                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1103                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1104                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1105                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1106                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1107                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1108                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1109                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1110                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1111                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1112                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1113                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1114                 INFINIPATH_E_HARDWARE;
1115
1116         infinipath_hwe_bitsextant =
1117                 (INFINIPATH_HWE_HTCMEMPARITYERR_MASK <<
1118                  INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) |
1119                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1120                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1121                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1122                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1123                 INFINIPATH_HWE_HTCLNKABYTE0CRCERR |
1124                 INFINIPATH_HWE_HTCLNKABYTE1CRCERR |
1125                 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR |
1126                 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR |
1127                 INFINIPATH_HWE_HTCMISCERR4 |
1128                 INFINIPATH_HWE_HTCMISCERR5 | INFINIPATH_HWE_HTCMISCERR6 |
1129                 INFINIPATH_HWE_HTCMISCERR7 |
1130                 INFINIPATH_HWE_HTCBUSTREQPARITYERR |
1131                 INFINIPATH_HWE_HTCBUSTRESPPARITYERR |
1132                 INFINIPATH_HWE_HTCBUSIREQPARITYERR |
1133                 INFINIPATH_HWE_RXDSYNCMEMPARITYERR |
1134                 INFINIPATH_HWE_MEMBISTFAILED |
1135                 INFINIPATH_HWE_COREPLL_FBSLIP |
1136                 INFINIPATH_HWE_COREPLL_RFSLIP |
1137                 INFINIPATH_HWE_HTBPLL_FBSLIP |
1138                 INFINIPATH_HWE_HTBPLL_RFSLIP |
1139                 INFINIPATH_HWE_HTAPLL_FBSLIP |
1140                 INFINIPATH_HWE_HTAPLL_RFSLIP |
1141                 INFINIPATH_HWE_SERDESPLLFAILED |
1142                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1143                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1144
1145         infinipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1146         infinipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1147 }
1148
1149 /**
1150  * ipath_ht_init_hwerrors - enable hardware errors
1151  * @dd: the infinipath device
1152  *
1153  * now that we have finished initializing everything that might reasonably
1154  * cause a hardware error, and cleared those errors bits as they occur,
1155  * we can enable hardware errors in the mask (potentially enabling
1156  * freeze mode), and enable hardware errors as errors (along with
1157  * everything else) in errormask
1158  */
1159 static void ipath_ht_init_hwerrors(struct ipath_devdata *dd)
1160 {
1161         ipath_err_t val;
1162         u64 extsval;
1163
1164         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
1165
1166         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
1167                 ipath_dev_err(dd, "MemBIST did not complete!\n");
1168
1169         ipath_check_htlink(dd);
1170
1171         /* barring bugs, all hwerrors become interrupts, which can */
1172         val = -1LL;
1173         /* don't look at crc lane1 if 8 bit */
1174         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
1175                 val &= ~infinipath_hwe_htclnkabyte1crcerr;
1176         /* don't look at crc lane1 if 8 bit */
1177         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
1178                 val &= ~infinipath_hwe_htclnkbbyte1crcerr;
1179
1180         /*
1181          * disable RXDSYNCMEMPARITY because external serdes is unused,
1182          * and therefore the logic will never be used or initialized,
1183          * and uninitialized state will normally result in this error
1184          * being asserted.  Similarly for the external serdess pll
1185          * lock signal.
1186          */
1187         val &= ~(INFINIPATH_HWE_SERDESPLLFAILED |
1188                  INFINIPATH_HWE_RXDSYNCMEMPARITYERR);
1189
1190         /*
1191          * Disable MISCERR4 because of an inversion in the HT core
1192          * logic checking for errors that cause this bit to be set.
1193          * The errata can also cause the protocol error bit to be set
1194          * in the HT config space linkerror register(s).
1195          */
1196         val &= ~INFINIPATH_HWE_HTCMISCERR4;
1197
1198         /*
1199          * PLL ignored because MDIO interface has a logic problem
1200          * for reads, on Comstock and Ponderosa.  BRINGUP
1201          */
1202         if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9)
1203                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
1204         dd->ipath_hwerrmask = val;
1205 }
1206
1207 /**
1208  * ipath_ht_bringup_serdes - bring up the serdes
1209  * @dd: the infinipath device
1210  */
1211 static int ipath_ht_bringup_serdes(struct ipath_devdata *dd)
1212 {
1213         u64 val, config1;
1214         int ret = 0, change = 0;
1215
1216         ipath_dbg("Trying to bringup serdes\n");
1217
1218         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
1219             INFINIPATH_HWE_SERDESPLLFAILED)
1220         {
1221                 ipath_dbg("At start, serdes PLL failed bit set in "
1222                           "hwerrstatus, clearing and continuing\n");
1223                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1224                                  INFINIPATH_HWE_SERDESPLLFAILED);
1225         }
1226
1227         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1228         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
1229
1230         ipath_cdbg(VERBOSE, "Initial serdes status is config0=%llx "
1231                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1232                    (unsigned long long) val, (unsigned long long) config1,
1233                    (unsigned long long)
1234                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1235                    (unsigned long long)
1236                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1237
1238         /* force reset on */
1239         val |= INFINIPATH_SERDC0_RESET_PLL
1240                 /* | INFINIPATH_SERDC0_RESET_MASK */
1241                 ;
1242         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1243         udelay(15);             /* need pll reset set at least for a bit */
1244
1245         if (val & INFINIPATH_SERDC0_RESET_PLL) {
1246                 u64 val2 = val &= ~INFINIPATH_SERDC0_RESET_PLL;
1247                 /* set lane resets, and tx idle, during pll reset */
1248                 val2 |= INFINIPATH_SERDC0_RESET_MASK |
1249                         INFINIPATH_SERDC0_TXIDLE;
1250                 ipath_cdbg(VERBOSE, "Clearing serdes PLL reset (writing "
1251                            "%llx)\n", (unsigned long long) val2);
1252                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1253                                  val2);
1254                 /*
1255                  * be sure chip saw it
1256                  */
1257                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1258                 /*
1259                  * need pll reset clear at least 11 usec before lane
1260                  * resets cleared; give it a few more
1261                  */
1262                 udelay(15);
1263                 val = val2;     /* for check below */
1264         }
1265
1266         if (val & (INFINIPATH_SERDC0_RESET_PLL |
1267                    INFINIPATH_SERDC0_RESET_MASK |
1268                    INFINIPATH_SERDC0_TXIDLE)) {
1269                 val &= ~(INFINIPATH_SERDC0_RESET_PLL |
1270                          INFINIPATH_SERDC0_RESET_MASK |
1271                          INFINIPATH_SERDC0_TXIDLE);
1272                 /* clear them */
1273                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1274                                  val);
1275         }
1276
1277         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1278         if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
1279              INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
1280                 val &= ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
1281                          INFINIPATH_XGXS_MDIOADDR_SHIFT);
1282                 /*
1283                  * we use address 3
1284                  */
1285                 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
1286                 change = 1;
1287         }
1288         if (val & INFINIPATH_XGXS_RESET) {
1289                 /* normally true after boot */
1290                 val &= ~INFINIPATH_XGXS_RESET;
1291                 change = 1;
1292         }
1293         if (change)
1294                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1295
1296         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1297
1298         /* clear current and de-emphasis bits */
1299         config1 &= ~0x0ffffffff00ULL;
1300         /* set current to 20ma */
1301         config1 |= 0x00000000000ULL;
1302         /* set de-emphasis to -5.68dB */
1303         config1 |= 0x0cccc000000ULL;
1304         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
1305
1306         ipath_cdbg(VERBOSE, "After setup: serdes status is config0=%llx "
1307                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1308                    (unsigned long long) val, (unsigned long long) config1,
1309                    (unsigned long long)
1310                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1311                    (unsigned long long)
1312                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1313
1314         if (!ipath_waitfor_mdio_cmdready(dd)) {
1315                 ipath_write_kreg(dd, dd->ipath_kregs->kr_mdio,
1316                                  ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
1317                                                 IPATH_MDIO_CTRL_XGXS_REG_8,
1318                                                 0));
1319                 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
1320                                            IPATH_MDIO_DATAVALID, &val))
1321                         ipath_dbg("Never got MDIO data for XGXS status "
1322                                   "read\n");
1323                 else
1324                         ipath_cdbg(VERBOSE, "MDIO Read reg8, "
1325                                    "'bank' 31 %x\n", (u32) val);
1326         } else
1327                 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
1328
1329         return ret;             /* for now, say we always succeeded */
1330 }
1331
1332 /**
1333  * ipath_ht_quiet_serdes - set serdes to txidle
1334  * @dd: the infinipath device
1335  * driver is being unloaded
1336  */
1337 static void ipath_ht_quiet_serdes(struct ipath_devdata *dd)
1338 {
1339         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1340
1341         val |= INFINIPATH_SERDC0_TXIDLE;
1342         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
1343                   (unsigned long long) val);
1344         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1345 }
1346
1347 static int ipath_ht_intconfig(struct ipath_devdata *dd)
1348 {
1349         int ret;
1350
1351         if (!dd->ipath_intconfig) {
1352                 ipath_dev_err(dd, "No interrupts enabled, couldn't setup "
1353                               "interrupt address\n");
1354                 ret = 1;
1355                 goto bail;
1356         }
1357
1358         ipath_write_kreg(dd, dd->ipath_kregs->kr_interruptconfig,
1359                          dd->ipath_intconfig);  /* interrupt address */
1360         ret = 0;
1361
1362 bail:
1363         return ret;
1364 }
1365
1366 /**
1367  * ipath_pe_put_tid - write a TID in chip
1368  * @dd: the infinipath device
1369  * @tidptr: pointer to the expected TID (in chip) to udpate
1370  * @tidtype: 0 for eager, 1 for expected
1371  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1372  *
1373  * This exists as a separate routine to allow for special locking etc.
1374  * It's used for both the full cleanup on exit, as well as the normal
1375  * setup and teardown.
1376  */
1377 static void ipath_ht_put_tid(struct ipath_devdata *dd,
1378                              u64 __iomem *tidptr, u32 type,
1379                              unsigned long pa)
1380 {
1381         if (pa != dd->ipath_tidinvalid) {
1382                 if (unlikely((pa & ~INFINIPATH_RT_ADDR_MASK))) {
1383                         dev_info(&dd->pcidev->dev,
1384                                  "physaddr %lx has more than "
1385                                  "40 bits, using only 40!!!\n", pa);
1386                         pa &= INFINIPATH_RT_ADDR_MASK;
1387                 }
1388                 if (type == 0)
1389                         pa |= dd->ipath_tidtemplate;
1390                 else {
1391                         /* in words (fixed, full page).  */
1392                         u64 lenvalid = PAGE_SIZE >> 2;
1393                         lenvalid <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1394                         pa |= lenvalid | INFINIPATH_RT_VALID;
1395                 }
1396         }
1397         if (dd->ipath_kregbase)
1398                 writeq(pa, tidptr);
1399 }
1400
1401 /**
1402  * ipath_ht_clear_tid - clear all TID entries for a port, expected and eager
1403  * @dd: the infinipath device
1404  * @port: the port
1405  *
1406  * Used from ipath_close(), and at chip initialization.
1407  */
1408 static void ipath_ht_clear_tids(struct ipath_devdata *dd, unsigned port)
1409 {
1410         u64 __iomem *tidbase;
1411         int i;
1412
1413         if (!dd->ipath_kregbase)
1414                 return;
1415
1416         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1417
1418         /*
1419          * need to invalidate all of the expected TID entries for this
1420          * port, so we don't have valid entries that might somehow get
1421          * used (early in next use of this port, or through some bug)
1422          */
1423         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1424                                    dd->ipath_rcvtidbase +
1425                                    port * dd->ipath_rcvtidcnt *
1426                                    sizeof(*tidbase));
1427         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1428                 ipath_ht_put_tid(dd, &tidbase[i], 1, dd->ipath_tidinvalid);
1429
1430         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1431                                    dd->ipath_rcvegrbase +
1432                                    port * dd->ipath_rcvegrcnt *
1433                                    sizeof(*tidbase));
1434
1435         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1436                 ipath_ht_put_tid(dd, &tidbase[i], 0, dd->ipath_tidinvalid);
1437 }
1438
1439 /**
1440  * ipath_ht_tidtemplate - setup constants for TID updates
1441  * @dd: the infinipath device
1442  *
1443  * We setup stuff that we use a lot, to avoid calculating each time
1444  */
1445 static void ipath_ht_tidtemplate(struct ipath_devdata *dd)
1446 {
1447         dd->ipath_tidtemplate = dd->ipath_ibmaxlen >> 2;
1448         dd->ipath_tidtemplate <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1449         dd->ipath_tidtemplate |= INFINIPATH_RT_VALID;
1450
1451         /*
1452          * work around chip errata bug 7358, by marking invalid tids
1453          * as having max length
1454          */
1455         dd->ipath_tidinvalid = (-1LL & INFINIPATH_RT_BUFSIZE_MASK) <<
1456                 INFINIPATH_RT_BUFSIZE_SHIFT;
1457 }
1458
1459 static int ipath_ht_early_init(struct ipath_devdata *dd)
1460 {
1461         u32 __iomem *piobuf;
1462         u32 pioincr, val32, egrsize;
1463         int i;
1464
1465         /*
1466          * one cache line; long IB headers will spill over into received
1467          * buffer
1468          */
1469         dd->ipath_rcvhdrentsize = 16;
1470         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1471
1472         /*
1473          * For HT-400, we allocate a somewhat overly large eager buffer,
1474          * such that we can guarantee that we can receive the largest
1475          * packet that we can send out.  To truly support a 4KB MTU,
1476          * we need to bump this to a large value.  To date, other than
1477          * testing, we have never encountered an HCA that can really
1478          * send 4KB MTU packets, so we do not handle that (we'll get
1479          * errors interrupts if we ever see one).
1480          */
1481         dd->ipath_rcvegrbufsize = dd->ipath_piosize2k;
1482         egrsize = dd->ipath_rcvegrbufsize;
1483
1484         /*
1485          * the min() check here is currently a nop, but it may not
1486          * always be, depending on just how we do ipath_rcvegrbufsize
1487          */
1488         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1489                                  dd->ipath_rcvegrbufsize);
1490         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1491         ipath_ht_tidtemplate(dd);
1492
1493         /*
1494          * zero all the TID entries at startup.  We do this for sanity,
1495          * in case of a previous driver crash of some kind, and also
1496          * because the chip powers up with these memories in an unknown
1497          * state.  Use portcnt, not cfgports, since this is for the
1498          * full chip, not for current (possibly different) configuration
1499          * value.
1500          * Chip Errata bug 6447
1501          */
1502         for (val32 = 0; val32 < dd->ipath_portcnt; val32++)
1503                 ipath_ht_clear_tids(dd, val32);
1504
1505         /*
1506          * write the pbc of each buffer, to be sure it's initialized, then
1507          * cancel all the buffers, and also abort any packets that might
1508          * have been in flight for some reason (the latter is for driver
1509          * unload/reload, but isn't a bad idea at first init).  PIO send
1510          * isn't enabled at this point, so there is no danger of sending
1511          * these out on the wire.
1512          * Chip Errata bug 6610
1513          */
1514         piobuf = (u32 __iomem *) (((char __iomem *)(dd->ipath_kregbase)) +
1515                                   dd->ipath_piobufbase);
1516         pioincr = dd->ipath_palign / sizeof(*piobuf);
1517         for (i = 0; i < dd->ipath_piobcnt2k; i++) {
1518                 /*
1519                  * reasonable word count, just to init pbc
1520                  */
1521                 writel(16, piobuf);
1522                 piobuf += pioincr;
1523         }
1524         /*
1525          * self-clearing
1526          */
1527         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1528                          INFINIPATH_S_ABORT);
1529
1530         ipath_get_eeprom_info(dd);
1531         if(dd->ipath_boardrev == 5 && dd->ipath_serial[0] == '1' &&
1532                 dd->ipath_serial[1] == '2' && dd->ipath_serial[2] == '8') {
1533                 /*
1534                  * Later production HT-460 has same changes as HT-465, so
1535                  * can use GPIO interrupts.  They have serial #'s starting
1536                  * with 128, rather than 112.
1537                  */
1538                 dd->ipath_flags |= IPATH_GPIO_INTR;
1539                 dd->ipath_flags &= ~IPATH_POLL_RX_INTR;
1540         }
1541         return 0;
1542 }
1543
1544 /**
1545  * ipath_init_ht_get_base_info - set chip-specific flags for user code
1546  * @dd: the infinipath device
1547  * @kbase: ipath_base_info pointer
1548  *
1549  * We set the PCIE flag because the lower bandwidth on PCIe vs
1550  * HyperTransport can affect some user packet algorithims.
1551  */
1552 static int ipath_ht_get_base_info(struct ipath_portdata *pd, void *kbase)
1553 {
1554         struct ipath_base_info *kinfo = kbase;
1555
1556         kinfo->spi_runtime_flags |= IPATH_RUNTIME_HT |
1557                 IPATH_RUNTIME_RCVHDR_COPY;
1558
1559         return 0;
1560 }
1561
1562 /**
1563  * ipath_init_ht400_funcs - set up the chip-specific function pointers
1564  * @dd: the infinipath device
1565  *
1566  * This is global, and is called directly at init to set up the
1567  * chip-specific function pointers for later use.
1568  */
1569 void ipath_init_ht400_funcs(struct ipath_devdata *dd)
1570 {
1571         dd->ipath_f_intrsetup = ipath_ht_intconfig;
1572         dd->ipath_f_bus = ipath_setup_ht_config;
1573         dd->ipath_f_reset = ipath_setup_ht_reset;
1574         dd->ipath_f_get_boardname = ipath_ht_boardname;
1575         dd->ipath_f_init_hwerrors = ipath_ht_init_hwerrors;
1576         dd->ipath_f_early_init = ipath_ht_early_init;
1577         dd->ipath_f_handle_hwerrors = ipath_ht_handle_hwerrors;
1578         dd->ipath_f_quiet_serdes = ipath_ht_quiet_serdes;
1579         dd->ipath_f_bringup_serdes = ipath_ht_bringup_serdes;
1580         dd->ipath_f_clear_tids = ipath_ht_clear_tids;
1581         dd->ipath_f_put_tid = ipath_ht_put_tid;
1582         dd->ipath_f_cleanup = ipath_setup_ht_cleanup;
1583         dd->ipath_f_setextled = ipath_setup_ht_setextled;
1584         dd->ipath_f_get_base_info = ipath_ht_get_base_info;
1585
1586         /*
1587          * initialize chip-specific variables
1588          */
1589         dd->ipath_f_tidtemplate = ipath_ht_tidtemplate;
1590
1591         /*
1592          * setup the register offsets, since they are different for each
1593          * chip
1594          */
1595         dd->ipath_kregs = &ipath_ht_kregs;
1596         dd->ipath_cregs = &ipath_ht_cregs;
1597
1598         /*
1599          * do very early init that is needed before ipath_f_bus is
1600          * called
1601          */
1602         ipath_init_ht_variables();
1603 }