drivers/infiniband/hw/cxgb3/cxio_hal.c

   1 /*
   2  * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include <asm/delay.h>
  33
  34 #include <linux/mutex.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/sched.h>
  37 #include <linux/spinlock.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-mapping.h>
  40 #include <net/net_namespace.h>
  41
  42 #include "cxio_resource.h"
  43 #include "cxio_hal.h"
  44 #include "cxgb3_offload.h"
  45 #include "sge_defs.h"
  46
  47 static LIST_HEAD(rdev_list);
  48 static cxio_hal_ev_callback_func_t cxio_ev_cb = NULL;
  49
  50 static struct cxio_rdev *cxio_hal_find_rdev_by_name(char *dev_name)
  51 {
  52         struct cxio_rdev *rdev;
  53
  54         list_for_each_entry(rdev, &rdev_list, entry)
  55                 if (!strcmp(rdev->dev_name, dev_name))
  56                         return rdev;
  57         return NULL;
  58 }
  59
  60 static struct cxio_rdev *cxio_hal_find_rdev_by_t3cdev(struct t3cdev *tdev)
  61 {
  62         struct cxio_rdev *rdev;
  63
  64         list_for_each_entry(rdev, &rdev_list, entry)
  65                 if (rdev->t3cdev_p == tdev)
  66                         return rdev;
  67         return NULL;
  68 }
  69
  70 int cxio_hal_cq_op(struct cxio_rdev *rdev_p, struct t3_cq *cq,
  71                    enum t3_cq_opcode op, u32 credit)
  72 {
  73         int ret;
  74         struct t3_cqe *cqe;
  75         u32 rptr;
  76
  77         struct rdma_cq_op setup;
  78         setup.id = cq->cqid;
  79         setup.credits = (op == CQ_CREDIT_UPDATE) ? credit : 0;
  80         setup.op = op;
  81         ret = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_OP, &setup);
  82
  83         if ((ret < 0) || (op == CQ_CREDIT_UPDATE))
  84                 return ret;
  85
  86         /*
  87          * If the rearm returned an index other than our current index,
  88          * then there might be CQE's in flight (being DMA'd).  We must wait
  89          * here for them to complete or the consumer can miss a notification.
  90          */
  91         if (Q_PTR2IDX((cq->rptr), cq->size_log2) != ret) {
  92                 int i=0;
  93
  94                 rptr = cq->rptr;
  95
  96                 /*
  97                  * Keep the generation correct by bumping rptr until it
  98                  * matches the index returned by the rearm - 1.
  99                  */
 100                 while (Q_PTR2IDX((rptr+1), cq->size_log2) != ret)
 101                         rptr++;
 102
 103                 /*
 104                  * Now rptr is the index for the (last) cqe that was
 105                  * in-flight at the time the HW rearmed the CQ.  We
 106                  * spin until that CQE is valid.
 107                  */
 108                 cqe = cq->queue + Q_PTR2IDX(rptr, cq->size_log2);
 109                 while (!CQ_VLD_ENTRY(rptr, cq->size_log2, cqe)) {
 110                         udelay(1);
 111                         if (i++ > 1000000) {
 112                                 printk(KERN_ERR "%s: stalled rnic\n",
 113                                        rdev_p->dev_name);
 114                                 return -EIO;
 115                         }
 116                 }
 117
 118                 return 1;
 119         }
 120
 121         return 0;
 122 }
 123
 124 static int cxio_hal_clear_cq_ctx(struct cxio_rdev *rdev_p, u32 cqid)
 125 {
 126         struct rdma_cq_setup setup;
 127         setup.id = cqid;
 128         setup.base_addr = 0;    /* NULL address */
 129         setup.size = 0;         /* disaable the CQ */
 130         setup.credits = 0;
 131         setup.credit_thres = 0;
 132         setup.ovfl_mode = 0;
 133         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 134 }
 135
 136 static int cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid)
 137 {
 138         u64 sge_cmd;
 139         struct t3_modify_qp_wr *wqe;
 140         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
 141         if (!skb) {
 142                 PDBG("%s alloc_skb failed\n", __func__);
 143                 return -ENOMEM;
 144         }
 145         wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
 146         memset(wqe, 0, sizeof(*wqe));
 147         build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD,
 148                        T3_COMPLETION_FLAG | T3_NOTIFY_FLAG, 0, qpid, 7,
 149                        T3_SOPEOP);
 150         wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
 151         sge_cmd = qpid << 8 | 3;
 152         wqe->sge_cmd = cpu_to_be64(sge_cmd);
 153         skb->priority = CPL_PRIORITY_CONTROL;
 154         return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
 155 }
 156
 157 int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq, int kernel)
 158 {
 159         struct rdma_cq_setup setup;
 160         int size = (1UL << (cq->size_log2)) * sizeof(struct t3_cqe);
 161
 162         cq->cqid = cxio_hal_get_cqid(rdev_p->rscp);
 163         if (!cq->cqid)
 164                 return -ENOMEM;
 165         if (kernel) {
 166                 cq->sw_queue = kzalloc(size, GFP_KERNEL);
 167                 if (!cq->sw_queue)
 168                         return -ENOMEM;
 169         }
 170         cq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev), size,
 171                                              &(cq->dma_addr), GFP_KERNEL);
 172         if (!cq->queue) {
 173                 kfree(cq->sw_queue);
 174                 return -ENOMEM;
 175         }
 176         pci_unmap_addr_set(cq, mapping, cq->dma_addr);
 177         memset(cq->queue, 0, size);
 178         setup.id = cq->cqid;
 179         setup.base_addr = (u64) (cq->dma_addr);
 180         setup.size = 1UL << cq->size_log2;
 181         setup.credits = 65535;
 182         setup.credit_thres = 1;
 183         if (rdev_p->t3cdev_p->type != T3A)
 184                 setup.ovfl_mode = 0;
 185         else
 186                 setup.ovfl_mode = 1;
 187         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 188 }
 189
 190 int cxio_resize_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
 191 {
 192         struct rdma_cq_setup setup;
 193         setup.id = cq->cqid;
 194         setup.base_addr = (u64) (cq->dma_addr);
 195         setup.size = 1UL << cq->size_log2;
 196         setup.credits = setup.size;
 197         setup.credit_thres = setup.size;        /* TBD: overflow recovery */
 198         setup.ovfl_mode = 1;
 199         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 200 }
 201
 202 static u32 get_qpid(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
 203 {
 204         struct cxio_qpid_list *entry;
 205         u32 qpid;
 206         int i;
 207
 208         mutex_lock(&uctx->lock);
 209         if (!list_empty(&uctx->qpids)) {
 210                 entry = list_entry(uctx->qpids.next, struct cxio_qpid_list,
 211                                    entry);
 212                 list_del(&entry->entry);
 213                 qpid = entry->qpid;
 214                 kfree(entry);
 215         } else {
 216                 qpid = cxio_hal_get_qpid(rdev_p->rscp);
 217                 if (!qpid)
 218                         goto out;
 219                 for (i = qpid+1; i & rdev_p->qpmask; i++) {
 220                         entry = kmalloc(sizeof *entry, GFP_KERNEL);
 221                         if (!entry)
 222                                 break;
 223                         entry->qpid = i;
 224                         list_add_tail(&entry->entry, &uctx->qpids);
 225                 }
 226         }
 227 out:
 228         mutex_unlock(&uctx->lock);
 229         PDBG("%s qpid 0x%x\n", __func__, qpid);
 230         return qpid;
 231 }
 232
 233 static void put_qpid(struct cxio_rdev *rdev_p, u32 qpid,
 234                      struct cxio_ucontext *uctx)
 235 {
 236         struct cxio_qpid_list *entry;
 237
 238         entry = kmalloc(sizeof *entry, GFP_KERNEL);
 239         if (!entry)
 240                 return;
 241         PDBG("%s qpid 0x%x\n", __func__, qpid);
 242         entry->qpid = qpid;
 243         mutex_lock(&uctx->lock);
 244         list_add_tail(&entry->entry, &uctx->qpids);
 245         mutex_unlock(&uctx->lock);
 246 }
 247
 248 void cxio_release_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
 249 {
 250         struct list_head *pos, *nxt;
 251         struct cxio_qpid_list *entry;
 252
 253         mutex_lock(&uctx->lock);
 254         list_for_each_safe(pos, nxt, &uctx->qpids) {
 255                 entry = list_entry(pos, struct cxio_qpid_list, entry);
 256                 list_del_init(&entry->entry);
 257                 if (!(entry->qpid & rdev_p->qpmask))
 258                         cxio_hal_put_qpid(rdev_p->rscp, entry->qpid);
 259                 kfree(entry);
 260         }
 261         mutex_unlock(&uctx->lock);
 262 }
 263
 264 void cxio_init_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
 265 {
 266         INIT_LIST_HEAD(&uctx->qpids);
 267         mutex_init(&uctx->lock);
 268 }
 269
 270 int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
 271                    struct t3_wq *wq, struct cxio_ucontext *uctx)
 272 {
 273         int depth = 1UL << wq->size_log2;
 274         int rqsize = 1UL << wq->rq_size_log2;
 275
 276         wq->qpid = get_qpid(rdev_p, uctx);
 277         if (!wq->qpid)
 278                 return -ENOMEM;
 279
 280         wq->rq = kzalloc(depth * sizeof(struct t3_swrq), GFP_KERNEL);
 281         if (!wq->rq)
 282                 goto err1;
 283
 284         wq->rq_addr = cxio_hal_rqtpool_alloc(rdev_p, rqsize);
 285         if (!wq->rq_addr)
 286                 goto err2;
 287
 288         wq->sq = kzalloc(depth * sizeof(struct t3_swsq), GFP_KERNEL);
 289         if (!wq->sq)
 290                 goto err3;
 291
 292         wq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
 293                                              depth * sizeof(union t3_wr),
 294                                              &(wq->dma_addr), GFP_KERNEL);
 295         if (!wq->queue)
 296                 goto err4;
 297
 298         memset(wq->queue, 0, depth * sizeof(union t3_wr));
 299         pci_unmap_addr_set(wq, mapping, wq->dma_addr);
 300         wq->doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
 301         if (!kernel_domain)
 302                 wq->udb = (u64)rdev_p->rnic_info.udbell_physbase +
 303                                         (wq->qpid << rdev_p->qpshift);
 304         wq->rdev = rdev_p;
 305         PDBG("%s qpid 0x%x doorbell 0x%p udb 0x%llx\n", __func__,
 306              wq->qpid, wq->doorbell, (unsigned long long) wq->udb);
 307         return 0;
 308 err4:
 309         kfree(wq->sq);
 310 err3:
 311         cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, rqsize);
 312 err2:
 313         kfree(wq->rq);
 314 err1:
 315         put_qpid(rdev_p, wq->qpid, uctx);
 316         return -ENOMEM;
 317 }
 318
 319 int cxio_destroy_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
 320 {
 321         int err;
 322         err = cxio_hal_clear_cq_ctx(rdev_p, cq->cqid);
 323         kfree(cq->sw_queue);
 324         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
 325                           (1UL << (cq->size_log2))
 326                           * sizeof(struct t3_cqe), cq->queue,
 327                           pci_unmap_addr(cq, mapping));
 328         cxio_hal_put_cqid(rdev_p->rscp, cq->cqid);
 329         return err;
 330 }
 331
 332 int cxio_destroy_qp(struct cxio_rdev *rdev_p, struct t3_wq *wq,
 333                     struct cxio_ucontext *uctx)
 334 {
 335         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
 336                           (1UL << (wq->size_log2))
 337                           * sizeof(union t3_wr), wq->queue,
 338                           pci_unmap_addr(wq, mapping));
 339         kfree(wq->sq);
 340         cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, (1UL << wq->rq_size_log2));
 341         kfree(wq->rq);
 342         put_qpid(rdev_p, wq->qpid, uctx);
 343         return 0;
 344 }
 345
 346 static void insert_recv_cqe(struct t3_wq *wq, struct t3_cq *cq)
 347 {
 348         struct t3_cqe cqe;
 349
 350         PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__,
 351              wq, cq, cq->sw_rptr, cq->sw_wptr);
 352         memset(&cqe, 0, sizeof(cqe));
 353         cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
 354                                  V_CQE_OPCODE(T3_SEND) |
 355                                  V_CQE_TYPE(0) |
 356                                  V_CQE_SWCQE(1) |
 357                                  V_CQE_QPID(wq->qpid) |
 358                                  V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
 359                                                        cq->size_log2)));
 360         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
 361         cq->sw_wptr++;
 362 }
 363
 364 int cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count)
 365 {
 366         u32 ptr;
 367         int flushed = 0;
 368
 369         PDBG("%s wq %p cq %p\n", __func__, wq, cq);
 370
 371         /* flush RQ */
 372         PDBG("%s rq_rptr %u rq_wptr %u skip count %u\n", __func__,
 373             wq->rq_rptr, wq->rq_wptr, count);
 374         ptr = wq->rq_rptr + count;
 375         while (ptr++ != wq->rq_wptr) {
 376                 insert_recv_cqe(wq, cq);
 377                 flushed++;
 378         }
 379         return flushed;
 380 }
 381
 382 static void insert_sq_cqe(struct t3_wq *wq, struct t3_cq *cq,
 383                           struct t3_swsq *sqp)
 384 {
 385         struct t3_cqe cqe;
 386
 387         PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__,
 388              wq, cq, cq->sw_rptr, cq->sw_wptr);
 389         memset(&cqe, 0, sizeof(cqe));
 390         cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
 391                                  V_CQE_OPCODE(sqp->opcode) |
 392                                  V_CQE_TYPE(1) |
 393                                  V_CQE_SWCQE(1) |
 394                                  V_CQE_QPID(wq->qpid) |
 395                                  V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
 396                                                        cq->size_log2)));
 397         cqe.u.scqe.wrid_hi = sqp->sq_wptr;
 398
 399         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
 400         cq->sw_wptr++;
 401 }
 402
 403 int cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count)
 404 {
 405         __u32 ptr;
 406         int flushed = 0;
 407         struct t3_swsq *sqp = wq->sq + Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2);
 408
 409         ptr = wq->sq_rptr + count;
 410         sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
 411         while (ptr != wq->sq_wptr) {
 412                 sqp->signaled = 0;
 413                 insert_sq_cqe(wq, cq, sqp);
 414                 ptr++;
 415                 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
 416                 flushed++;
 417         }
 418         return flushed;
 419 }
 420
 421 /*
 422  * Move all CQEs from the HWCQ into the SWCQ.
 423  */
 424 void cxio_flush_hw_cq(struct t3_cq *cq)
 425 {
 426         struct t3_cqe *cqe, *swcqe;
 427
 428         PDBG("%s cq %p cqid 0x%x\n", __func__, cq, cq->cqid);
 429         cqe = cxio_next_hw_cqe(cq);
 430         while (cqe) {
 431                 PDBG("%s flushing hwcq rptr 0x%x to swcq wptr 0x%x\n",
 432                      __func__, cq->rptr, cq->sw_wptr);
 433                 swcqe = cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2);
 434                 *swcqe = *cqe;
 435                 swcqe->header |= cpu_to_be32(V_CQE_SWCQE(1));
 436                 cq->sw_wptr++;
 437                 cq->rptr++;
 438                 cqe = cxio_next_hw_cqe(cq);
 439         }
 440 }
 441
 442 static int cqe_completes_wr(struct t3_cqe *cqe, struct t3_wq *wq)
 443 {
 444         if (CQE_OPCODE(*cqe) == T3_TERMINATE)
 445                 return 0;
 446
 447         if ((CQE_OPCODE(*cqe) == T3_RDMA_WRITE) && RQ_TYPE(*cqe))
 448                 return 0;
 449
 450         if ((CQE_OPCODE(*cqe) == T3_READ_RESP) && SQ_TYPE(*cqe))
 451                 return 0;
 452
 453         if (CQE_SEND_OPCODE(*cqe) && RQ_TYPE(*cqe) &&
 454             Q_EMPTY(wq->rq_rptr, wq->rq_wptr))
 455                 return 0;
 456
 457         return 1;
 458 }
 459
 460 void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
 461 {
 462         struct t3_cqe *cqe;
 463         u32 ptr;
 464
 465         *count = 0;
 466         ptr = cq->sw_rptr;
 467         while (!Q_EMPTY(ptr, cq->sw_wptr)) {
 468                 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
 469                 if ((SQ_TYPE(*cqe) ||
 470                      ((CQE_OPCODE(*cqe) == T3_READ_RESP) && wq->oldest_read)) &&
 471                     (CQE_QPID(*cqe) == wq->qpid))
 472                         (*count)++;
 473                 ptr++;
 474         }
 475         PDBG("%s cq %p count %d\n", __func__, cq, *count);
 476 }
 477
 478 void cxio_count_rcqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
 479 {
 480         struct t3_cqe *cqe;
 481         u32 ptr;
 482
 483         *count = 0;
 484         PDBG("%s count zero %d\n", __func__, *count);
 485         ptr = cq->sw_rptr;
 486         while (!Q_EMPTY(ptr, cq->sw_wptr)) {
 487                 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
 488                 if (RQ_TYPE(*cqe) && (CQE_OPCODE(*cqe) != T3_READ_RESP) &&
 489                     (CQE_QPID(*cqe) == wq->qpid) && cqe_completes_wr(cqe, wq))
 490                         (*count)++;
 491                 ptr++;
 492         }
 493         PDBG("%s cq %p count %d\n", __func__, cq, *count);
 494 }
 495
 496 static int cxio_hal_init_ctrl_cq(struct cxio_rdev *rdev_p)
 497 {
 498         struct rdma_cq_setup setup;
 499         setup.id = 0;
 500         setup.base_addr = 0;    /* NULL address */
 501         setup.size = 1;         /* enable the CQ */
 502         setup.credits = 0;
 503
 504         /* force SGE to redirect to RspQ and interrupt */
 505         setup.credit_thres = 0;
 506         setup.ovfl_mode = 1;
 507         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 508 }
 509
 510 static int cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p)
 511 {
 512         int err;
 513         u64 sge_cmd, ctx0, ctx1;
 514         u64 base_addr;
 515         struct t3_modify_qp_wr *wqe;
 516         struct sk_buff *skb;
 517
 518         skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
 519         if (!skb) {
 520                 PDBG("%s alloc_skb failed\n", __func__);
 521                 return -ENOMEM;
 522         }
 523         err = cxio_hal_init_ctrl_cq(rdev_p);
 524         if (err) {
 525                 PDBG("%s err %d initializing ctrl_cq\n", __func__, err);
 526                 goto err;
 527         }
 528         rdev_p->ctrl_qp.workq = dma_alloc_coherent(
 529                                         &(rdev_p->rnic_info.pdev->dev),
 530                                         (1 << T3_CTRL_QP_SIZE_LOG2) *
 531                                         sizeof(union t3_wr),
 532                                         &(rdev_p->ctrl_qp.dma_addr),
 533                                         GFP_KERNEL);
 534         if (!rdev_p->ctrl_qp.workq) {
 535                 PDBG("%s dma_alloc_coherent failed\n", __func__);
 536                 err = -ENOMEM;
 537                 goto err;
 538         }
 539         pci_unmap_addr_set(&rdev_p->ctrl_qp, mapping,
 540                            rdev_p->ctrl_qp.dma_addr);
 541         rdev_p->ctrl_qp.doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
 542         memset(rdev_p->ctrl_qp.workq, 0,
 543                (1 << T3_CTRL_QP_SIZE_LOG2) * sizeof(union t3_wr));
 544
 545         mutex_init(&rdev_p->ctrl_qp.lock);
 546         init_waitqueue_head(&rdev_p->ctrl_qp.waitq);
 547
 548         /* update HW Ctrl QP context */
 549         base_addr = rdev_p->ctrl_qp.dma_addr;
 550         base_addr >>= 12;
 551         ctx0 = (V_EC_SIZE((1 << T3_CTRL_QP_SIZE_LOG2)) |
 552                 V_EC_BASE_LO((u32) base_addr & 0xffff));
 553         ctx0 <<= 32;
 554         ctx0 |= V_EC_CREDITS(FW_WR_NUM);
 555         base_addr >>= 16;
 556         ctx1 = (u32) base_addr;
 557         base_addr >>= 32;
 558         ctx1 |= ((u64) (V_EC_BASE_HI((u32) base_addr & 0xf) | V_EC_RESPQ(0) |
 559                         V_EC_TYPE(0) | V_EC_GEN(1) |
 560                         V_EC_UP_TOKEN(T3_CTL_QP_TID) | F_EC_VALID)) << 32;
 561         wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
 562         memset(wqe, 0, sizeof(*wqe));
 563         build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 0, 0,
 564                        T3_CTL_QP_TID, 7, T3_SOPEOP);
 565         wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
 566         sge_cmd = (3ULL << 56) | FW_RI_SGEEC_START << 8 | 3;
 567         wqe->sge_cmd = cpu_to_be64(sge_cmd);
 568         wqe->ctx1 = cpu_to_be64(ctx1);
 569         wqe->ctx0 = cpu_to_be64(ctx0);
 570         PDBG("CtrlQP dma_addr 0x%llx workq %p size %d\n",
 571              (unsigned long long) rdev_p->ctrl_qp.dma_addr,
 572              rdev_p->ctrl_qp.workq, 1 << T3_CTRL_QP_SIZE_LOG2);
 573         skb->priority = CPL_PRIORITY_CONTROL;
 574         return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
 575 err:
 576         kfree_skb(skb);
 577         return err;
 578 }
 579
 580 static int cxio_hal_destroy_ctrl_qp(struct cxio_rdev *rdev_p)
 581 {
 582         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
 583                           (1UL << T3_CTRL_QP_SIZE_LOG2)
 584                           * sizeof(union t3_wr), rdev_p->ctrl_qp.workq,
 585                           pci_unmap_addr(&rdev_p->ctrl_qp, mapping));
 586         return cxio_hal_clear_qp_ctx(rdev_p, T3_CTRL_QP_ID);
 587 }
 588
 589 /* write len bytes of data into addr (32B aligned address)
 590  * If data is NULL, clear len byte of memory to zero.
 591  * caller acquires the ctrl_qp lock before the call
 592  */
 593 static int cxio_hal_ctrl_qp_write_mem(struct cxio_rdev *rdev_p, u32 addr,
 594                                       u32 len, void *data)
 595 {
 596         u32 i, nr_wqe, copy_len;
 597         u8 *copy_data;
 598         u8 wr_len, utx_len;     /* length in 8 byte flit */
 599         enum t3_wr_flags flag;
 600         __be64 *wqe;
 601         u64 utx_cmd;
 602         addr &= 0x7FFFFFF;
 603         nr_wqe = len % 96 ? len / 96 + 1 : len / 96;    /* 96B max per WQE */
 604         PDBG("%s wptr 0x%x rptr 0x%x len %d, nr_wqe %d data %p addr 0x%0x\n",
 605              __func__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len,
 606              nr_wqe, data, addr);
 607         utx_len = 3;            /* in 32B unit */
 608         for (i = 0; i < nr_wqe; i++) {
 609                 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr,
 610                            T3_CTRL_QP_SIZE_LOG2)) {
 611                         PDBG("%s ctrl_qp full wtpr 0x%0x rptr 0x%0x, "
 612                              "wait for more space i %d\n", __func__,
 613                              rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i);
 614                         if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
 615                                              !Q_FULL(rdev_p->ctrl_qp.rptr,
 616                                                      rdev_p->ctrl_qp.wptr,
 617                                                      T3_CTRL_QP_SIZE_LOG2))) {
 618                                 PDBG("%s ctrl_qp workq interrupted\n",
 619                                      __func__);
 620                                 return -ERESTARTSYS;
 621                         }
 622                         PDBG("%s ctrl_qp wakeup, continue posting work request "
 623                              "i %d\n", __func__, i);
 624                 }
 625                 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
 626                                                 (1 << T3_CTRL_QP_SIZE_LOG2)));
 627                 flag = 0;
 628                 if (i == (nr_wqe - 1)) {
 629                         /* last WQE */
 630                         flag = T3_COMPLETION_FLAG;
 631                         if (len % 32)
 632                                 utx_len = len / 32 + 1;
 633                         else
 634                                 utx_len = len / 32;
 635                 }
 636
 637                 /*
 638                  * Force a CQE to return the credit to the workq in case
 639                  * we posted more than half the max QP size of WRs
 640                  */
 641                 if ((i != 0) &&
 642                     (i % (((1 << T3_CTRL_QP_SIZE_LOG2)) >> 1) == 0)) {
 643                         flag = T3_COMPLETION_FLAG;
 644                         PDBG("%s force completion at i %d\n", __func__, i);
 645                 }
 646
 647                 /* build the utx mem command */
 648                 wqe += (sizeof(struct t3_bypass_wr) >> 3);
 649                 utx_cmd = (T3_UTX_MEM_WRITE << 28) | (addr + i * 3);
 650                 utx_cmd <<= 32;
 651                 utx_cmd |= (utx_len << 28) | ((utx_len << 2) + 1);
 652                 *wqe = cpu_to_be64(utx_cmd);
 653                 wqe++;
 654                 copy_data = (u8 *) data + i * 96;
 655                 copy_len = len > 96 ? 96 : len;
 656
 657                 /* clear memory content if data is NULL */
 658                 if (data)
 659                         memcpy(wqe, copy_data, copy_len);
 660                 else
 661                         memset(wqe, 0, copy_len);
 662                 if (copy_len % 32)
 663                         memset(((u8 *) wqe) + copy_len, 0,
 664                                32 - (copy_len % 32));
 665                 wr_len = ((sizeof(struct t3_bypass_wr)) >> 3) + 1 +
 666                          (utx_len << 2);
 667                 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
 668                               (1 << T3_CTRL_QP_SIZE_LOG2)));
 669
 670                 /* wptr in the WRID[31:0] */
 671                 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr;
 672
 673                 /*
 674                  * This must be the last write with a memory barrier
 675                  * for the genbit
 676                  */
 677                 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_BP, flag,
 678                                Q_GENBIT(rdev_p->ctrl_qp.wptr,
 679                                         T3_CTRL_QP_SIZE_LOG2), T3_CTRL_QP_ID,
 680                                wr_len, T3_SOPEOP);
 681                 if (flag == T3_COMPLETION_FLAG)
 682                         ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID);
 683                 len -= 96;
 684                 rdev_p->ctrl_qp.wptr++;
 685         }
 686         return 0;
 687 }
 688
 689 /* IN: stag key, pdid, perm, zbva, to, len, page_size, pbl_size and pbl_addr
 690  * OUT: stag index
 691  * TBD: shared memory region support
 692  */
 693 static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry,
 694                          u32 *stag, u8 stag_state, u32 pdid,
 695                          enum tpt_mem_type type, enum tpt_mem_perm perm,
 696                          u32 zbva, u64 to, u32 len, u8 page_size,
 697                          u32 pbl_size, u32 pbl_addr)
 698 {
 699         int err;
 700         struct tpt_entry tpt;
 701         u32 stag_idx;
 702         u32 wptr;
 703
 704         if (cxio_fatal_error(rdev_p))
 705                 return -EIO;
 706
 707         stag_state = stag_state > 0;
 708         stag_idx = (*stag) >> 8;
 709
 710         if ((!reset_tpt_entry) && !(*stag != T3_STAG_UNSET)) {
 711                 stag_idx = cxio_hal_get_stag(rdev_p->rscp);
 712                 if (!stag_idx)
 713                         return -ENOMEM;
 714                 *stag = (stag_idx << 8) | ((*stag) & 0xFF);
 715         }
 716         PDBG("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
 717              __func__, stag_state, type, pdid, stag_idx);
 718
 719         mutex_lock(&rdev_p->ctrl_qp.lock);
 720
 721         /* write TPT entry */
 722         if (reset_tpt_entry)
 723                 memset(&tpt, 0, sizeof(tpt));
 724         else {
 725                 tpt.valid_stag_pdid = cpu_to_be32(F_TPT_VALID |
 726                                 V_TPT_STAG_KEY((*stag) & M_TPT_STAG_KEY) |
 727                                 V_TPT_STAG_STATE(stag_state) |
 728                                 V_TPT_STAG_TYPE(type) | V_TPT_PDID(pdid));
 729                 BUG_ON(page_size >= 28);
 730                 tpt.flags_pagesize_qpid = cpu_to_be32(V_TPT_PERM(perm) |
 731                         ((perm & TPT_MW_BIND) ? F_TPT_MW_BIND_ENABLE : 0) |
 732                         V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) |
 733                         V_TPT_PAGE_SIZE(page_size));
 734                 tpt.rsvd_pbl_addr = reset_tpt_entry ? 0 :
 735                                     cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, pbl_addr)>>3));
 736                 tpt.len = cpu_to_be32(len);
 737                 tpt.va_hi = cpu_to_be32((u32) (to >> 32));
 738                 tpt.va_low_or_fbo = cpu_to_be32((u32) (to & 0xFFFFFFFFULL));
 739                 tpt.rsvd_bind_cnt_or_pstag = 0;
 740                 tpt.rsvd_pbl_size = reset_tpt_entry ? 0 :
 741                                   cpu_to_be32(V_TPT_PBL_SIZE(pbl_size >> 2));
 742         }
 743         err = cxio_hal_ctrl_qp_write_mem(rdev_p,
 744                                        stag_idx +
 745                                        (rdev_p->rnic_info.tpt_base >> 5),
 746                                        sizeof(tpt), &tpt);
 747
 748         /* release the stag index to free pool */
 749         if (reset_tpt_entry)
 750                 cxio_hal_put_stag(rdev_p->rscp, stag_idx);
 751
 752         wptr = rdev_p->ctrl_qp.wptr;
 753         mutex_unlock(&rdev_p->ctrl_qp.lock);
 754         if (!err)
 755                 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
 756                                              SEQ32_GE(rdev_p->ctrl_qp.rptr,
 757                                                       wptr)))
 758                         return -ERESTARTSYS;
 759         return err;
 760 }
 761
 762 int cxio_write_pbl(struct cxio_rdev *rdev_p, __be64 *pbl,
 763                    u32 pbl_addr, u32 pbl_size)
 764 {
 765         u32 wptr;
 766         int err;
 767
 768         PDBG("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
 769              __func__, pbl_addr, rdev_p->rnic_info.pbl_base,
 770              pbl_size);
 771
 772         mutex_lock(&rdev_p->ctrl_qp.lock);
 773         err = cxio_hal_ctrl_qp_write_mem(rdev_p, pbl_addr >> 5, pbl_size << 3,
 774                                          pbl);
 775         wptr = rdev_p->ctrl_qp.wptr;
 776         mutex_unlock(&rdev_p->ctrl_qp.lock);
 777         if (err)
 778                 return err;
 779
 780         if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
 781                                      SEQ32_GE(rdev_p->ctrl_qp.rptr,
 782                                               wptr)))
 783                 return -ERESTARTSYS;
 784
 785         return 0;
 786 }
 787
 788 int cxio_register_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
 789                            enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
 790                            u8 page_size, u32 pbl_size, u32 pbl_addr)
 791 {
 792         *stag = T3_STAG_UNSET;
 793         return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
 794                              zbva, to, len, page_size, pbl_size, pbl_addr);
 795 }
 796
 797 int cxio_reregister_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
 798                            enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
 799                            u8 page_size, u32 pbl_size, u32 pbl_addr)
 800 {
 801         return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
 802                              zbva, to, len, page_size, pbl_size, pbl_addr);
 803 }
 804
 805 int cxio_dereg_mem(struct cxio_rdev *rdev_p, u32 stag, u32 pbl_size,
 806                    u32 pbl_addr)
 807 {
 808         return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
 809                              pbl_size, pbl_addr);
 810 }
 811
 812 int cxio_allocate_window(struct cxio_rdev *rdev_p, u32 * stag, u32 pdid)
 813 {
 814         *stag = T3_STAG_UNSET;
 815         return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_MW, 0, 0, 0ULL, 0, 0,
 816                              0, 0);
 817 }
 818
 819 int cxio_deallocate_window(struct cxio_rdev *rdev_p, u32 stag)
 820 {
 821         return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
 822                              0, 0);
 823 }
 824
 825 int cxio_allocate_stag(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid, u32 pbl_size, u32 pbl_addr)
 826 {
 827         *stag = T3_STAG_UNSET;
 828         return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_NON_SHARED_MR,
 829                              0, 0, 0ULL, 0, 0, pbl_size, pbl_addr);
 830 }
 831
 832 int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr)
 833 {
 834         struct t3_rdma_init_wr *wqe;
 835         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_ATOMIC);
 836         if (!skb)
 837                 return -ENOMEM;
 838         PDBG("%s rdev_p %p\n", __func__, rdev_p);
 839         wqe = (struct t3_rdma_init_wr *) __skb_put(skb, sizeof(*wqe));
 840         wqe->wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_INIT));
 841         wqe->wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(attr->tid) |
 842                                            V_FW_RIWR_LEN(sizeof(*wqe) >> 3));
 843         wqe->wrid.id1 = 0;
 844         wqe->qpid = cpu_to_be32(attr->qpid);
 845         wqe->pdid = cpu_to_be32(attr->pdid);
 846         wqe->scqid = cpu_to_be32(attr->scqid);
 847         wqe->rcqid = cpu_to_be32(attr->rcqid);
 848         wqe->rq_addr = cpu_to_be32(attr->rq_addr - rdev_p->rnic_info.rqt_base);
 849         wqe->rq_size = cpu_to_be32(attr->rq_size);
 850         wqe->mpaattrs = attr->mpaattrs;
 851         wqe->qpcaps = attr->qpcaps;
 852         wqe->ulpdu_size = cpu_to_be16(attr->tcp_emss);
 853         wqe->rqe_count = cpu_to_be16(attr->rqe_count);
 854         wqe->flags_rtr_type = cpu_to_be16(attr->flags |
 855                                           V_RTR_TYPE(attr->rtr_type) |
 856                                           V_CHAN(attr->chan));
 857         wqe->ord = cpu_to_be32(attr->ord);
 858         wqe->ird = cpu_to_be32(attr->ird);
 859         wqe->qp_dma_addr = cpu_to_be64(attr->qp_dma_addr);
 860         wqe->qp_dma_size = cpu_to_be32(attr->qp_dma_size);
 861         wqe->irs = cpu_to_be32(attr->irs);
 862         skb->priority = 0;      /* 0=>ToeQ; 1=>CtrlQ */
 863         return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
 864 }
 865
 866 void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
 867 {
 868         cxio_ev_cb = ev_cb;
 869 }
 870
 871 void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
 872 {
 873         cxio_ev_cb = NULL;
 874 }
 875
 876 static int cxio_hal_ev_handler(struct t3cdev *t3cdev_p, struct sk_buff *skb)
 877 {
 878         static int cnt;
 879         struct cxio_rdev *rdev_p = NULL;
 880         struct respQ_msg_t *rsp_msg = (struct respQ_msg_t *) skb->data;
 881         PDBG("%d: %s cq_id 0x%x cq_ptr 0x%x genbit %0x overflow %0x an %0x"
 882              " se %0x notify %0x cqbranch %0x creditth %0x\n",
 883              cnt, __func__, RSPQ_CQID(rsp_msg), RSPQ_CQPTR(rsp_msg),
 884              RSPQ_GENBIT(rsp_msg), RSPQ_OVERFLOW(rsp_msg), RSPQ_AN(rsp_msg),
 885              RSPQ_SE(rsp_msg), RSPQ_NOTIFY(rsp_msg), RSPQ_CQBRANCH(rsp_msg),
 886              RSPQ_CREDIT_THRESH(rsp_msg));
 887         PDBG("CQE: QPID 0x%0x genbit %0x type 0x%0x status 0x%0x opcode %d "
 888              "len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
 889              CQE_QPID(rsp_msg->cqe), CQE_GENBIT(rsp_msg->cqe),
 890              CQE_TYPE(rsp_msg->cqe), CQE_STATUS(rsp_msg->cqe),
 891              CQE_OPCODE(rsp_msg->cqe), CQE_LEN(rsp_msg->cqe),
 892              CQE_WRID_HI(rsp_msg->cqe), CQE_WRID_LOW(rsp_msg->cqe));
 893         rdev_p = (struct cxio_rdev *)t3cdev_p->ulp;
 894         if (!rdev_p) {
 895                 PDBG("%s called by t3cdev %p with null ulp\n", __func__,
 896                      t3cdev_p);
 897                 return 0;
 898         }
 899         if (CQE_QPID(rsp_msg->cqe) == T3_CTRL_QP_ID) {
 900                 rdev_p->ctrl_qp.rptr = CQE_WRID_LOW(rsp_msg->cqe) + 1;
 901                 wake_up_interruptible(&rdev_p->ctrl_qp.waitq);
 902                 dev_kfree_skb_irq(skb);
 903         } else if (CQE_QPID(rsp_msg->cqe) == 0xfff8)
 904                 dev_kfree_skb_irq(skb);
 905         else if (cxio_ev_cb)
 906                 (*cxio_ev_cb) (rdev_p, skb);
 907         else
 908                 dev_kfree_skb_irq(skb);
 909         cnt++;
 910         return 0;
 911 }
 912
 913 /* Caller takes care of locking if needed */
 914 int cxio_rdev_open(struct cxio_rdev *rdev_p)
 915 {
 916         struct net_device *netdev_p = NULL;
 917         int err = 0;
 918         if (strlen(rdev_p->dev_name)) {
 919                 if (cxio_hal_find_rdev_by_name(rdev_p->dev_name)) {
 920                         return -EBUSY;
 921                 }
 922                 netdev_p = dev_get_by_name(&init_net, rdev_p->dev_name);
 923                 if (!netdev_p) {
 924                         return -EINVAL;
 925                 }
 926                 dev_put(netdev_p);
 927         } else if (rdev_p->t3cdev_p) {
 928                 if (cxio_hal_find_rdev_by_t3cdev(rdev_p->t3cdev_p)) {
 929                         return -EBUSY;
 930                 }
 931                 netdev_p = rdev_p->t3cdev_p->lldev;
 932                 strncpy(rdev_p->dev_name, rdev_p->t3cdev_p->name,
 933                         T3_MAX_DEV_NAME_LEN);
 934         } else {
 935                 PDBG("%s t3cdev_p or dev_name must be set\n", __func__);
 936                 return -EINVAL;
 937         }
 938
 939         list_add_tail(&rdev_p->entry, &rdev_list);
 940
 941         PDBG("%s opening rnic dev %s\n", __func__, rdev_p->dev_name);
 942         memset(&rdev_p->ctrl_qp, 0, sizeof(rdev_p->ctrl_qp));
 943         if (!rdev_p->t3cdev_p)
 944                 rdev_p->t3cdev_p = dev2t3cdev(netdev_p);
 945         rdev_p->t3cdev_p->ulp = (void *) rdev_p;
 946
 947         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_EMBEDDED_INFO,
 948                                          &(rdev_p->fw_info));
 949         if (err) {
 950                 printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n",
 951                      __func__, rdev_p->t3cdev_p, err);
 952                 goto err1;
 953         }
 954         if (G_FW_VERSION_MAJOR(rdev_p->fw_info.fw_vers) != CXIO_FW_MAJ) {
 955                 printk(KERN_ERR MOD "fatal firmware version mismatch: "
 956                        "need version %u but adapter has version %u\n",
 957                        CXIO_FW_MAJ,
 958                        G_FW_VERSION_MAJOR(rdev_p->fw_info.fw_vers));
 959                 err = -EINVAL;
 960                 goto err1;
 961         }
 962
 963         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_GET_PARAMS,
 964                                          &(rdev_p->rnic_info));
 965         if (err) {
 966                 printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n",
 967                      __func__, rdev_p->t3cdev_p, err);
 968                 goto err1;
 969         }
 970         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_PORTS,
 971                                     &(rdev_p->port_info));
 972         if (err) {
 973                 printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n",
 974                      __func__, rdev_p->t3cdev_p, err);
 975                 goto err1;
 976         }
 977
 978         /*
 979          * qpshift is the number of bits to shift the qpid left in order
 980          * to get the correct address of the doorbell for that qp.
 981          */
 982         cxio_init_ucontext(rdev_p, &rdev_p->uctx);
 983         rdev_p->qpshift = PAGE_SHIFT -
 984                           ilog2(65536 >>
 985                                     ilog2(rdev_p->rnic_info.udbell_len >>
 986                                               PAGE_SHIFT));
 987         rdev_p->qpnr = rdev_p->rnic_info.udbell_len >> PAGE_SHIFT;
 988         rdev_p->qpmask = (65536 >> ilog2(rdev_p->qpnr)) - 1;
 989         PDBG("%s rnic %s info: tpt_base 0x%0x tpt_top 0x%0x num stags %d "
 990              "pbl_base 0x%0x pbl_top 0x%0x rqt_base 0x%0x, rqt_top 0x%0x\n",
 991              __func__, rdev_p->dev_name, rdev_p->rnic_info.tpt_base,
 992              rdev_p->rnic_info.tpt_top, cxio_num_stags(rdev_p),
 993              rdev_p->rnic_info.pbl_base,
 994              rdev_p->rnic_info.pbl_top, rdev_p->rnic_info.rqt_base,
 995              rdev_p->rnic_info.rqt_top);
 996         PDBG("udbell_len 0x%0x udbell_physbase 0x%lx kdb_addr %p qpshift %lu "
 997              "qpnr %d qpmask 0x%x\n",
 998              rdev_p->rnic_info.udbell_len,
 999              rdev_p->rnic_info.udbell_physbase, rdev_p->rnic_info.kdb_addr,
1000              rdev_p->qpshift, rdev_p->qpnr, rdev_p->qpmask);
1001
1002         err = cxio_hal_init_ctrl_qp(rdev_p);
1003         if (err) {
1004                 printk(KERN_ERR "%s error %d initializing ctrl_qp.\n",
1005                        __func__, err);
1006                 goto err1;
1007         }
1008         err = cxio_hal_init_resource(rdev_p, cxio_num_stags(rdev_p), 0,
1009                                      0, T3_MAX_NUM_QP, T3_MAX_NUM_CQ,
1010                                      T3_MAX_NUM_PD);
1011         if (err) {
1012                 printk(KERN_ERR "%s error %d initializing hal resources.\n",
1013                        __func__, err);
1014                 goto err2;
1015         }
1016         err = cxio_hal_pblpool_create(rdev_p);
1017         if (err) {
1018                 printk(KERN_ERR "%s error %d initializing pbl mem pool.\n",
1019                        __func__, err);
1020                 goto err3;
1021         }
1022         err = cxio_hal_rqtpool_create(rdev_p);
1023         if (err) {
1024                 printk(KERN_ERR "%s error %d initializing rqt mem pool.\n",
1025                        __func__, err);
1026                 goto err4;
1027         }
1028         return 0;
1029 err4:
1030         cxio_hal_pblpool_destroy(rdev_p);
1031 err3:
1032         cxio_hal_destroy_resource(rdev_p->rscp);
1033 err2:
1034         cxio_hal_destroy_ctrl_qp(rdev_p);
1035 err1:
1036         rdev_p->t3cdev_p->ulp = NULL;
1037         list_del(&rdev_p->entry);
1038         return err;
1039 }
1040
1041 void cxio_rdev_close(struct cxio_rdev *rdev_p)
1042 {
1043         if (rdev_p) {
1044                 cxio_hal_pblpool_destroy(rdev_p);
1045                 cxio_hal_rqtpool_destroy(rdev_p);
1046                 list_del(&rdev_p->entry);
1047                 cxio_hal_destroy_ctrl_qp(rdev_p);
1048                 cxio_hal_destroy_resource(rdev_p->rscp);
1049                 rdev_p->t3cdev_p->ulp = NULL;
1050         }
1051 }
1052
1053 int __init cxio_hal_init(void)
1054 {
1055         if (cxio_hal_init_rhdl_resource(T3_MAX_NUM_RI))
1056                 return -ENOMEM;
1057         t3_register_cpl_handler(CPL_ASYNC_NOTIF, cxio_hal_ev_handler);
1058         return 0;
1059 }
1060
1061 void __exit cxio_hal_exit(void)
1062 {
1063         struct cxio_rdev *rdev, *tmp;
1064
1065         t3_register_cpl_handler(CPL_ASYNC_NOTIF, NULL);
1066         list_for_each_entry_safe(rdev, tmp, &rdev_list, entry)
1067                 cxio_rdev_close(rdev);
1068         cxio_hal_destroy_rhdl_resource();
1069 }
1070
1071 static void flush_completed_wrs(struct t3_wq *wq, struct t3_cq *cq)
1072 {
1073         struct t3_swsq *sqp;
1074         __u32 ptr = wq->sq_rptr;
1075         int count = Q_COUNT(wq->sq_rptr, wq->sq_wptr);
1076
1077         sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
1078         while (count--)
1079                 if (!sqp->signaled) {
1080                         ptr++;
1081                         sqp = wq->sq + Q_PTR2IDX(ptr,  wq->sq_size_log2);
1082                 } else if (sqp->complete) {
1083
1084                         /*
1085                          * Insert this completed cqe into the swcq.
1086                          */
1087                         PDBG("%s moving cqe into swcq sq idx %ld cq idx %ld\n",
1088                              __func__, Q_PTR2IDX(ptr,  wq->sq_size_log2),
1089                              Q_PTR2IDX(cq->sw_wptr, cq->size_log2));
1090                         sqp->cqe.header |= htonl(V_CQE_SWCQE(1));
1091                         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2))
1092                                 = sqp->cqe;
1093                         cq->sw_wptr++;
1094                         sqp->signaled = 0;
1095                         break;
1096                 } else
1097                         break;
1098 }
1099
1100 static void create_read_req_cqe(struct t3_wq *wq, struct t3_cqe *hw_cqe,
1101                                 struct t3_cqe *read_cqe)
1102 {
1103         read_cqe->u.scqe.wrid_hi = wq->oldest_read->sq_wptr;
1104         read_cqe->len = wq->oldest_read->read_len;
1105         read_cqe->header = htonl(V_CQE_QPID(CQE_QPID(*hw_cqe)) |
1106                                  V_CQE_SWCQE(SW_CQE(*hw_cqe)) |
1107                                  V_CQE_OPCODE(T3_READ_REQ) |
1108                                  V_CQE_TYPE(1));
1109 }
1110
1111 /*
1112  * Return a ptr to the next read wr in the SWSQ or NULL.
1113  */
1114 static void advance_oldest_read(struct t3_wq *wq)
1115 {
1116
1117         u32 rptr = wq->oldest_read - wq->sq + 1;
1118         u32 wptr = Q_PTR2IDX(wq->sq_wptr, wq->sq_size_log2);
1119
1120         while (Q_PTR2IDX(rptr, wq->sq_size_log2) != wptr) {
1121                 wq->oldest_read = wq->sq + Q_PTR2IDX(rptr, wq->sq_size_log2);
1122
1123                 if (wq->oldest_read->opcode == T3_READ_REQ)
1124                         return;
1125                 rptr++;
1126         }
1127         wq->oldest_read = NULL;
1128 }
1129
1130 /*
1131  * cxio_poll_cq
1132  *
1133  * Caller must:
1134  *     check the validity of the first CQE,
1135  *     supply the wq assicated with the qpid.
1136  *
1137  * credit: cq credit to return to sge.
1138  * cqe_flushed: 1 iff the CQE is flushed.
1139  * cqe: copy of the polled CQE.
1140  *
1141  * return value:
1142  *     0       CQE returned,
1143  *    -1       CQE skipped, try again.
1144  */
1145 int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
1146                      u8 *cqe_flushed, u64 *cookie, u32 *credit)
1147 {
1148         int ret = 0;
1149         struct t3_cqe *hw_cqe, read_cqe;
1150
1151         *cqe_flushed = 0;
1152         *credit = 0;
1153         hw_cqe = cxio_next_cqe(cq);
1154
1155         PDBG("%s CQE OOO %d qpid 0x%0x genbit %d type %d status 0x%0x"
1156              " opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
1157              __func__, CQE_OOO(*hw_cqe), CQE_QPID(*hw_cqe),
1158              CQE_GENBIT(*hw_cqe), CQE_TYPE(*hw_cqe), CQE_STATUS(*hw_cqe),
1159              CQE_OPCODE(*hw_cqe), CQE_LEN(*hw_cqe), CQE_WRID_HI(*hw_cqe),
1160              CQE_WRID_LOW(*hw_cqe));
1161
1162         /*
1163          * skip cqe's not affiliated with a QP.
1164          */
1165         if (wq == NULL) {
1166                 ret = -1;
1167                 goto skip_cqe;
1168         }
1169
1170         /*
1171          * Gotta tweak READ completions:
1172          *      1) the cqe doesn't contain the sq_wptr from the wr.
1173          *      2) opcode not reflected from the wr.
1174          *      3) read_len not reflected from the wr.
1175          *      4) cq_type is RQ_TYPE not SQ_TYPE.
1176          */
1177         if (RQ_TYPE(*hw_cqe) && (CQE_OPCODE(*hw_cqe) == T3_READ_RESP)) {
1178
1179                 /*
1180                  * If this is an unsolicited read response, then the read
1181                  * was generated by the kernel driver as part of peer-2-peer
1182                  * connection setup.  So ignore the completion.
1183                  */
1184                 if (!wq->oldest_read) {
1185                         if (CQE_STATUS(*hw_cqe))
1186                                 wq->error = 1;
1187                         ret = -1;
1188                         goto skip_cqe;
1189                 }
1190
1191                 /*
1192                  * Don't write to the HWCQ, so create a new read req CQE
1193                  * in local memory.
1194                  */
1195                 create_read_req_cqe(wq, hw_cqe, &read_cqe);
1196                 hw_cqe = &read_cqe;
1197                 advance_oldest_read(wq);
1198         }
1199
1200         /*
1201          * T3A: Discard TERMINATE CQEs.
1202          */
1203         if (CQE_OPCODE(*hw_cqe) == T3_TERMINATE) {
1204                 ret = -1;
1205                 wq->error = 1;
1206                 goto skip_cqe;
1207         }
1208
1209         if (CQE_STATUS(*hw_cqe) || wq->error) {
1210                 *cqe_flushed = wq->error;
1211                 wq->error = 1;
1212
1213                 /*
1214                  * T3A inserts errors into the CQE.  We cannot return
1215                  * these as work completions.
1216                  */
1217                 /* incoming write failures */
1218                 if ((CQE_OPCODE(*hw_cqe) == T3_RDMA_WRITE)
1219                      && RQ_TYPE(*hw_cqe)) {
1220                         ret = -1;
1221                         goto skip_cqe;
1222                 }
1223                 /* incoming read request failures */
1224                 if ((CQE_OPCODE(*hw_cqe) == T3_READ_RESP) && SQ_TYPE(*hw_cqe)) {
1225                         ret = -1;
1226                         goto skip_cqe;
1227                 }
1228
1229                 /* incoming SEND with no receive posted failures */
1230                 if (CQE_SEND_OPCODE(*hw_cqe) && RQ_TYPE(*hw_cqe) &&
1231                     Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1232                         ret = -1;
1233                         goto skip_cqe;
1234                 }
1235                 BUG_ON((*cqe_flushed == 0) && !SW_CQE(*hw_cqe));
1236                 goto proc_cqe;
1237         }
1238
1239         /*
1240          * RECV completion.
1241          */
1242         if (RQ_TYPE(*hw_cqe)) {
1243
1244                 /*
1245                  * HW only validates 4 bits of MSN.  So we must validate that
1246                  * the MSN in the SEND is the next expected MSN.  If its not,
1247                  * then we complete this with TPT_ERR_MSN and mark the wq in
1248                  * error.
1249                  */
1250
1251                 if (Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1252                         wq->error = 1;
1253                         ret = -1;
1254                         goto skip_cqe;
1255                 }
1256
1257                 if (unlikely((CQE_WRID_MSN(*hw_cqe) != (wq->rq_rptr + 1)))) {
1258                         wq->error = 1;
1259                         hw_cqe->header |= htonl(V_CQE_STATUS(TPT_ERR_MSN));
1260                         goto proc_cqe;
1261                 }
1262                 goto proc_cqe;
1263         }
1264
1265         /*
1266          * If we get here its a send completion.
1267          *
1268          * Handle out of order completion. These get stuffed
1269          * in the SW SQ. Then the SW SQ is walked to move any
1270          * now in-order completions into the SW CQ.  This handles
1271          * 2 cases:
1272          *      1) reaping unsignaled WRs when the first subsequent
1273          *         signaled WR is completed.
1274          *      2) out of order read completions.
1275          */
1276         if (!SW_CQE(*hw_cqe) && (CQE_WRID_SQ_WPTR(*hw_cqe) != wq->sq_rptr)) {
1277                 struct t3_swsq *sqp;
1278
1279                 PDBG("%s out of order completion going in swsq at idx %ld\n",
1280                      __func__,
1281                      Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2));
1282                 sqp = wq->sq +
1283                       Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2);
1284                 sqp->cqe = *hw_cqe;
1285                 sqp->complete = 1;
1286                 ret = -1;
1287                 goto flush_wq;
1288         }
1289
1290 proc_cqe:
1291         *cqe = *hw_cqe;
1292
1293         /*
1294          * Reap the associated WR(s) that are freed up with this
1295          * completion.
1296          */
1297         if (SQ_TYPE(*hw_cqe)) {
1298                 wq->sq_rptr = CQE_WRID_SQ_WPTR(*hw_cqe);
1299                 PDBG("%s completing sq idx %ld\n", __func__,
1300                      Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2));
1301                 *cookie = wq->sq[Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2)].wr_id;
1302                 wq->sq_rptr++;
1303         } else {
1304                 PDBG("%s completing rq idx %ld\n", __func__,
1305                      Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
1306                 *cookie = wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].wr_id;
1307                 if (wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].pbl_addr)
1308                         cxio_hal_pblpool_free(wq->rdev,
1309                                 wq->rq[Q_PTR2IDX(wq->rq_rptr,
1310                                 wq->rq_size_log2)].pbl_addr, T3_STAG0_PBL_SIZE);
1311                 BUG_ON(Q_EMPTY(wq->rq_rptr, wq->rq_wptr));
1312                 wq->rq_rptr++;
1313         }
1314
1315 flush_wq:
1316         /*
1317          * Flush any completed cqes that are now in-order.
1318          */
1319         flush_completed_wrs(wq, cq);
1320
1321 skip_cqe:
1322         if (SW_CQE(*hw_cqe)) {
1323                 PDBG("%s cq %p cqid 0x%x skip sw cqe sw_rptr 0x%x\n",
1324                      __func__, cq, cq->cqid, cq->sw_rptr);
1325                 ++cq->sw_rptr;
1326         } else {
1327                 PDBG("%s cq %p cqid 0x%x skip hw cqe rptr 0x%x\n",
1328                      __func__, cq, cq->cqid, cq->rptr);
1329                 ++cq->rptr;
1330
1331                 /*
1332                  * T3A: compute credits.
1333                  */
1334                 if (((cq->rptr - cq->wptr) > (1 << (cq->size_log2 - 1)))
1335                     || ((cq->rptr - cq->wptr) >= 128)) {
1336                         *credit = cq->rptr - cq->wptr;
1337                         cq->wptr = cq->rptr;
1338                 }
1339         }
1340         return ret;
1341 }