2 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2006-2007, 2009 MontaVista Software, Inc.
4 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6 * Portions Copyright (C) 1999 Promise Technology, Inc.
7 * Author: Frank Tiernan (frankt@promise.com)
8 * Released under terms of General Public License
11 #include <linux/types.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/delay.h>
15 #include <linux/blkdev.h>
16 #include <linux/pci.h>
17 #include <linux/init.h>
18 #include <linux/ide.h>
22 #define DRV_NAME "pdc202xx_old"
24 #define PDC202XX_DEBUG_DRIVE_INFO 0
26 static const char *pdc_quirk_drives[] = {
27 "QUANTUM FIREBALLlct08 08",
28 "QUANTUM FIREBALLP KA6.4",
29 "QUANTUM FIREBALLP KA9.1",
30 "QUANTUM FIREBALLP LM20.4",
31 "QUANTUM FIREBALLP KX13.6",
32 "QUANTUM FIREBALLP KX20.5",
33 "QUANTUM FIREBALLP KX27.3",
34 "QUANTUM FIREBALLP LM20.5",
38 static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
40 static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
42 ide_hwif_t *hwif = drive->hwif;
43 struct pci_dev *dev = to_pci_dev(hwif->dev);
44 u8 drive_pci = 0x60 + (drive->dn << 2);
46 u8 AP = 0, BP = 0, CP = 0;
47 u8 TA = 0, TB = 0, TC = 0;
49 #if PDC202XX_DEBUG_DRIVE_INFO
51 pci_read_config_dword(dev, drive_pci, &drive_conf);
55 * TODO: do this once per channel
57 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
58 pdc_old_disable_66MHz_clock(hwif);
60 pci_read_config_byte(dev, drive_pci, &AP);
61 pci_read_config_byte(dev, drive_pci + 1, &BP);
62 pci_read_config_byte(dev, drive_pci + 2, &CP);
66 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
67 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
69 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
71 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
72 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
73 case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
74 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
75 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
76 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
77 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
79 default: TA = 0x09; TB = 0x13; break;
82 if (speed < XFER_SW_DMA_0) {
84 * preserve SYNC_INT / ERDDY_EN bits while clearing
85 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
88 if (ata_id_iordy_disable(drive->id))
89 AP |= 0x20; /* set IORDY_EN bit */
90 if (drive->media == ide_disk)
91 AP |= 0x10; /* set Prefetch_EN bit */
92 /* clear PB[4:0] bits of register B */
94 pci_write_config_byte(dev, drive_pci, AP | TA);
95 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
97 /* clear MB[2:0] bits of register B */
99 /* clear MC[3:0] bits of register C */
101 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
102 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
105 #if PDC202XX_DEBUG_DRIVE_INFO
106 printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
107 drive->name, ide_xfer_verbose(speed),
108 drive->dn, drive_conf);
109 pci_read_config_dword(dev, drive_pci, &drive_conf);
110 printk("0x%08x\n", drive_conf);
114 static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
116 pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
119 static u8 pdc2026x_cable_detect(ide_hwif_t *hwif)
121 struct pci_dev *dev = to_pci_dev(hwif->dev);
122 u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
124 pci_read_config_word(dev, 0x50, &CIS);
126 return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
130 * Set the control register to use the 66MHz system
131 * clock for UDMA 3/4/5 mode operation when necessary.
133 * FIXME: this register is shared by both channels, some locking is needed
135 * It may also be possible to leave the 66MHz clock on
136 * and readjust the timing parameters.
138 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
140 unsigned long clock_reg = hwif->extra_base + 0x01;
141 u8 clock = inb(clock_reg);
143 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
146 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
148 unsigned long clock_reg = hwif->extra_base + 0x01;
149 u8 clock = inb(clock_reg);
151 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
154 static void pdc202xx_quirkproc(ide_drive_t *drive)
156 const char **list, *m = (char *)&drive->id[ATA_ID_PROD];
158 for (list = pdc_quirk_drives; *list != NULL; list++)
159 if (strstr(m, *list) != NULL) {
160 drive->quirk_list = 2;
164 drive->quirk_list = 0;
167 static void pdc202xx_dma_start(ide_drive_t *drive)
169 if (drive->current_speed > XFER_UDMA_2)
170 pdc_old_enable_66MHz_clock(drive->hwif);
171 if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
172 ide_hwif_t *hwif = drive->hwif;
173 struct request *rq = hwif->rq;
174 unsigned long high_16 = hwif->extra_base - 16;
175 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
177 u8 clock = inb(high_16 + 0x11);
179 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
180 word_count = (rq->nr_sectors << 8);
181 word_count = (rq_data_dir(rq) == READ) ?
182 word_count | 0x05000000 :
183 word_count | 0x06000000;
184 outl(word_count, atapi_reg);
186 ide_dma_start(drive);
189 static int pdc202xx_dma_end(ide_drive_t *drive)
191 if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
192 ide_hwif_t *hwif = drive->hwif;
193 unsigned long high_16 = hwif->extra_base - 16;
194 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
197 outl(0, atapi_reg); /* zero out extra */
198 clock = inb(high_16 + 0x11);
199 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
201 if (drive->current_speed > XFER_UDMA_2)
202 pdc_old_disable_66MHz_clock(drive->hwif);
203 return ide_dma_end(drive);
206 static void pdc202xx_reset(ide_drive_t *drive)
208 ide_hwif_t *hwif = drive->hwif;
209 unsigned long high_16 = hwif->extra_base - 16;
210 u8 udma_speed_flag = inb(high_16 | 0x001f);
212 printk(KERN_WARNING "PDC202xx: software reset...\n");
214 outb(udma_speed_flag | 0x10, high_16 | 0x001f);
216 outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
217 mdelay(2000); /* 2 seconds ?! */
219 ide_set_max_pio(drive);
222 static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
224 pdc202xx_reset(drive);
225 ide_dma_lost_irq(drive);
228 static int init_chipset_pdc202xx(struct pci_dev *dev)
230 unsigned long dmabase = pci_resource_start(dev, 4);
231 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
236 udma_speed_flag = inb(dmabase | 0x1f);
237 primary_mode = inb(dmabase | 0x1a);
238 secondary_mode = inb(dmabase | 0x1b);
239 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
241 "Secondary %s Mode.\n", pci_name(dev),
242 (udma_speed_flag & 1) ? "EN" : "DIS",
243 (primary_mode & 1) ? "MASTER" : "PCI",
244 (secondary_mode & 1) ? "MASTER" : "PCI" );
246 if (!(udma_speed_flag & 1)) {
247 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
248 pci_name(dev), udma_speed_flag,
249 (udma_speed_flag|1));
250 outb(udma_speed_flag | 1, dmabase | 0x1f);
251 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
257 static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
260 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
261 u8 irq = 0, irq2 = 0;
262 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
264 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
266 pci_write_config_byte(dev,
267 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
268 printk(KERN_INFO "%s %s: PCI config space interrupt "
269 "mirror fixed\n", name, pci_name(dev));
274 #define IDE_HFLAGS_PDC202XX \
275 (IDE_HFLAG_ERROR_STOPS_FIFO | \
278 static const struct ide_port_ops pdc20246_port_ops = {
279 .set_pio_mode = pdc202xx_set_pio_mode,
280 .set_dma_mode = pdc202xx_set_mode,
281 .quirkproc = pdc202xx_quirkproc,
284 static const struct ide_port_ops pdc2026x_port_ops = {
285 .set_pio_mode = pdc202xx_set_pio_mode,
286 .set_dma_mode = pdc202xx_set_mode,
287 .quirkproc = pdc202xx_quirkproc,
288 .resetproc = pdc202xx_reset,
289 .cable_detect = pdc2026x_cable_detect,
292 static const struct ide_dma_ops pdc2026x_dma_ops = {
293 .dma_host_set = ide_dma_host_set,
294 .dma_setup = ide_dma_setup,
295 .dma_start = pdc202xx_dma_start,
296 .dma_end = pdc202xx_dma_end,
297 .dma_test_irq = ide_dma_test_irq,
298 .dma_lost_irq = pdc202xx_dma_lost_irq,
299 .dma_timer_expiry = ide_dma_sff_timer_expiry,
300 .dma_clear = pdc202xx_reset,
301 .dma_sff_read_status = ide_dma_sff_read_status,
304 #define DECLARE_PDC2026X_DEV(udma, sectors) \
307 .init_chipset = init_chipset_pdc202xx, \
308 .port_ops = &pdc2026x_port_ops, \
309 .dma_ops = &pdc2026x_dma_ops, \
310 .host_flags = IDE_HFLAGS_PDC202XX, \
311 .pio_mask = ATA_PIO4, \
312 .mwdma_mask = ATA_MWDMA2, \
314 .max_sectors = sectors, \
317 static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
320 .init_chipset = init_chipset_pdc202xx,
321 .port_ops = &pdc20246_port_ops,
322 .dma_ops = &sff_dma_ops,
323 .host_flags = IDE_HFLAGS_PDC202XX,
324 .pio_mask = ATA_PIO4,
325 .mwdma_mask = ATA_MWDMA2,
326 .udma_mask = ATA_UDMA2,
329 /* 1: PDC2026{2,3} */
330 DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
331 /* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */
332 DECLARE_PDC2026X_DEV(ATA_UDMA5, 256),
336 * pdc202xx_init_one - called when a PDC202xx is found
337 * @dev: the pdc202xx device
338 * @id: the matching pci id
340 * Called when the PCI registration layer (or the IDE initialization)
341 * finds a device matching our IDE device tables.
344 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
346 const struct ide_port_info *d;
347 u8 idx = id->driver_data;
349 d = &pdc202xx_chipsets[idx];
352 pdc202ata4_fixup_irq(dev, d->name);
354 if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
355 struct pci_dev *bridge = dev->bus->self;
358 bridge->vendor == PCI_VENDOR_ID_INTEL &&
359 (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
360 bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
361 printk(KERN_INFO DRV_NAME " %s: skipping Promise "
362 "PDC20265 attached to I2O RAID controller\n",
368 return ide_pci_init_one(dev, d, NULL);
371 static const struct pci_device_id pdc202xx_pci_tbl[] = {
372 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
373 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
374 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
375 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
376 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
379 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
381 static struct pci_driver pdc202xx_pci_driver = {
382 .name = "Promise_Old_IDE",
383 .id_table = pdc202xx_pci_tbl,
384 .probe = pdc202xx_init_one,
385 .remove = ide_pci_remove,
386 .suspend = ide_pci_suspend,
387 .resume = ide_pci_resume,
390 static int __init pdc202xx_ide_init(void)
392 return ide_pci_register_driver(&pdc202xx_pci_driver);
395 static void __exit pdc202xx_ide_exit(void)
397 pci_unregister_driver(&pdc202xx_pci_driver);
400 module_init(pdc202xx_ide_init);
401 module_exit(pdc202xx_ide_exit);
403 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
404 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
405 MODULE_LICENSE("GPL");