drivers/ide/pci/sis5513.c

   1 /*
   2  * linux/drivers/ide/pci/sis5513.c      Version 0.31    Aug 9, 2007
   3  *
   4  * Copyright (C) 1999-2000      Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2002           Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
   6  * Copyright (C) 2003           Vojtech Pavlik <vojtech@suse.cz>
   7  * Copyright (C) 2007           Bartlomiej Zolnierkiewicz
   8  *
   9  * May be copied or modified under the terms of the GNU General Public License
  10  *
  11  *
  12  * Thanks :
  13  *
  14  * SiS Taiwan           : for direct support and hardware.
  15  * Daniela Engert       : for initial ATA100 advices and numerous others.
  16  * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt        :
  17  *                        for checking code correctness, providing patches.
  18  *
  19  *
  20  * Original tests and design on the SiS620 chipset.
  21  * ATA100 tests and design on the SiS735 chipset.
  22  * ATA16/33 support from specs
  23  * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
  24  * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
  25  *
  26  * Documentation:
  27  *      SiS chipset documentation available under NDA to companies only
  28  *      (not to individuals).
  29  */
  30
  31 /*
  32  * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
  33  * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
  34  * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
  35  *
  36  * Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
  37  * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
  38  * can figure out that we have a more modern and more capable 5513 by looking
  39  * for the respective NorthBridge IDs.
  40  *
  41  * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
  42  * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
  43  * ID, while the now ATA-133 capable 5513 still has the same PCI ID.
  44  * Fortunately the 5513 can be 'unmasked' by fiddling with some config space
  45  * bits, changing its device id to the true one - 5517 for 961 and 5518 for
  46  * 962/963.
  47  */
  48
  49 #include <linux/types.h>
  50 #include <linux/module.h>
  51 #include <linux/kernel.h>
  52 #include <linux/delay.h>
  53 #include <linux/timer.h>
  54 #include <linux/mm.h>
  55 #include <linux/ioport.h>
  56 #include <linux/blkdev.h>
  57 #include <linux/hdreg.h>
  58
  59 #include <linux/interrupt.h>
  60 #include <linux/pci.h>
  61 #include <linux/init.h>
  62 #include <linux/ide.h>
  63
  64 #include <asm/irq.h>
  65
  66 #include "ide-timing.h"
  67
  68 /* registers layout and init values are chipset family dependant */
  69
  70 #define ATA_16          0x01
  71 #define ATA_33          0x02
  72 #define ATA_66          0x03
  73 #define ATA_100a        0x04 // SiS730/SiS550 is ATA100 with ATA66 layout
  74 #define ATA_100         0x05
  75 #define ATA_133a        0x06 // SiS961b with 133 support
  76 #define ATA_133         0x07 // SiS962/963
  77
  78 static u8 chipset_family;
  79
  80 /*
  81  * Devices supported
  82  */
  83 static const struct {
  84         const char *name;
  85         u16 host_id;
  86         u8 chipset_family;
  87         u8 flags;
  88 } SiSHostChipInfo[] = {
  89         { "SiS968",     PCI_DEVICE_ID_SI_968,   ATA_133  },
  90         { "SiS966",     PCI_DEVICE_ID_SI_966,   ATA_133  },
  91         { "SiS965",     PCI_DEVICE_ID_SI_965,   ATA_133  },
  92         { "SiS745",     PCI_DEVICE_ID_SI_745,   ATA_100  },
  93         { "SiS735",     PCI_DEVICE_ID_SI_735,   ATA_100  },
  94         { "SiS733",     PCI_DEVICE_ID_SI_733,   ATA_100  },
  95         { "SiS635",     PCI_DEVICE_ID_SI_635,   ATA_100  },
  96         { "SiS633",     PCI_DEVICE_ID_SI_633,   ATA_100  },
  97
  98         { "SiS730",     PCI_DEVICE_ID_SI_730,   ATA_100a },
  99         { "SiS550",     PCI_DEVICE_ID_SI_550,   ATA_100a },
 100
 101         { "SiS640",     PCI_DEVICE_ID_SI_640,   ATA_66   },
 102         { "SiS630",     PCI_DEVICE_ID_SI_630,   ATA_66   },
 103         { "SiS620",     PCI_DEVICE_ID_SI_620,   ATA_66   },
 104         { "SiS540",     PCI_DEVICE_ID_SI_540,   ATA_66   },
 105         { "SiS530",     PCI_DEVICE_ID_SI_530,   ATA_66   },
 106
 107         { "SiS5600",    PCI_DEVICE_ID_SI_5600,  ATA_33   },
 108         { "SiS5598",    PCI_DEVICE_ID_SI_5598,  ATA_33   },
 109         { "SiS5597",    PCI_DEVICE_ID_SI_5597,  ATA_33   },
 110         { "SiS5591/2",  PCI_DEVICE_ID_SI_5591,  ATA_33   },
 111         { "SiS5582",    PCI_DEVICE_ID_SI_5582,  ATA_33   },
 112         { "SiS5581",    PCI_DEVICE_ID_SI_5581,  ATA_33   },
 113
 114         { "SiS5596",    PCI_DEVICE_ID_SI_5596,  ATA_16   },
 115         { "SiS5571",    PCI_DEVICE_ID_SI_5571,  ATA_16   },
 116         { "SiS5517",    PCI_DEVICE_ID_SI_5517,  ATA_16   },
 117         { "SiS551x",    PCI_DEVICE_ID_SI_5511,  ATA_16   },
 118 };
 119
 120 /* Cycle time bits and values vary across chip dma capabilities
 121    These three arrays hold the register layout and the values to set.
 122    Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
 123
 124 /* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
 125 static u8 cycle_time_offset[] = {0,0,5,4,4,0,0};
 126 static u8 cycle_time_range[] = {0,0,2,3,3,4,4};
 127 static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
 128         {0,0,0,0,0,0,0}, /* no udma */
 129         {0,0,0,0,0,0,0}, /* no udma */
 130         {3,2,1,0,0,0,0}, /* ATA_33 */
 131         {7,5,3,2,1,0,0}, /* ATA_66 */
 132         {7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */
 133         {11,7,5,4,2,1,0}, /* ATA_100 */
 134         {15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */
 135         {15,10,7,5,3,2,1}, /* ATA_133 */
 136 };
 137 /* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
 138    See SiS962 data sheet for more detail */
 139 static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
 140         {0,0,0,0,0,0,0}, /* no udma */
 141         {0,0,0,0,0,0,0}, /* no udma */
 142         {2,1,1,0,0,0,0},
 143         {4,3,2,1,0,0,0},
 144         {4,3,2,1,0,0,0},
 145         {6,4,3,1,1,1,0},
 146         {9,6,4,2,2,2,2},
 147         {9,6,4,2,2,2,2},
 148 };
 149 /* Initialize time, Active time, Recovery time vary across
 150    IDE clock settings. These 3 arrays hold the register value
 151    for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
 152 static u8 ini_time_value[][8] = {
 153         {0,0,0,0,0,0,0,0},
 154         {0,0,0,0,0,0,0,0},
 155         {2,1,0,0,0,1,0,0},
 156         {4,3,1,1,1,3,1,1},
 157         {4,3,1,1,1,3,1,1},
 158         {6,4,2,2,2,4,2,2},
 159         {9,6,3,3,3,6,3,3},
 160         {9,6,3,3,3,6,3,3},
 161 };
 162 static u8 act_time_value[][8] = {
 163         {0,0,0,0,0,0,0,0},
 164         {0,0,0,0,0,0,0,0},
 165         {9,9,9,2,2,7,2,2},
 166         {19,19,19,5,4,14,5,4},
 167         {19,19,19,5,4,14,5,4},
 168         {28,28,28,7,6,21,7,6},
 169         {38,38,38,10,9,28,10,9},
 170         {38,38,38,10,9,28,10,9},
 171 };
 172 static u8 rco_time_value[][8] = {
 173         {0,0,0,0,0,0,0,0},
 174         {0,0,0,0,0,0,0,0},
 175         {9,2,0,2,0,7,1,1},
 176         {19,5,1,5,2,16,3,2},
 177         {19,5,1,5,2,16,3,2},
 178         {30,9,3,9,4,25,6,4},
 179         {40,12,4,12,5,34,12,5},
 180         {40,12,4,12,5,34,12,5},
 181 };
 182
 183 /*
 184  * Printing configuration
 185  */
 186 /* Used for chipset type printing at boot time */
 187 static char* chipset_capability[] = {
 188         "ATA", "ATA 16",
 189         "ATA 33", "ATA 66",
 190         "ATA 100 (1st gen)", "ATA 100 (2nd gen)",
 191         "ATA 133 (1st gen)", "ATA 133 (2nd gen)"
 192 };
 193
 194 /*
 195  * Configuration functions
 196  */
 197
 198 static u8 sis_ata133_get_base(ide_drive_t *drive)
 199 {
 200         struct pci_dev *dev = drive->hwif->pci_dev;
 201         u32 reg54 = 0;
 202
 203         pci_read_config_dword(dev, 0x54, &reg54);
 204
 205         return ((reg54 & 0x40000000) ? 0x70 : 0x40) + drive->dn * 4;
 206 }
 207
 208 static void sis_ata16_program_timings(ide_drive_t *drive, const u8 mode)
 209 {
 210         struct pci_dev *dev = drive->hwif->pci_dev;
 211         u16 t1 = 0;
 212         u8 drive_pci = 0x40 + drive->dn * 2;
 213
 214         const u16 pio_timings[]   = { 0x000, 0x607, 0x404, 0x303, 0x301 };
 215         const u16 mwdma_timings[] = { 0x008, 0x302, 0x301 };
 216
 217         pci_read_config_word(dev, drive_pci, &t1);
 218
 219         /* clear active/recovery timings */
 220         t1 &= ~0x070f;
 221         if (mode >= XFER_MW_DMA_0) {
 222                 if (chipset_family > ATA_16)
 223                         t1 &= ~0x8000;  /* disable UDMA */
 224                 t1 |= mwdma_timings[mode - XFER_MW_DMA_0];
 225         } else
 226                 t1 |= pio_timings[mode - XFER_PIO_0];
 227
 228         pci_write_config_word(dev, drive_pci, t1);
 229 }
 230
 231 static void sis_ata100_program_timings(ide_drive_t *drive, const u8 mode)
 232 {
 233         struct pci_dev *dev = drive->hwif->pci_dev;
 234         u8 t1, drive_pci = 0x40 + drive->dn * 2;
 235
 236         /* timing bits: 7:4 active 3:0 recovery */
 237         const u8 pio_timings[]   = { 0x00, 0x67, 0x44, 0x33, 0x31 };
 238         const u8 mwdma_timings[] = { 0x08, 0x32, 0x31 };
 239
 240         if (mode >= XFER_MW_DMA_0) {
 241                 u8 t2 = 0;
 242
 243                 pci_read_config_byte(dev, drive_pci, &t2);
 244                 t2 &= ~0x80;    /* disable UDMA */
 245                 pci_write_config_byte(dev, drive_pci, t2);
 246
 247                 t1 = mwdma_timings[mode - XFER_MW_DMA_0];
 248         } else
 249                 t1 = pio_timings[mode - XFER_PIO_0];
 250
 251         pci_write_config_byte(dev, drive_pci + 1, t1);
 252 }
 253
 254 static void sis_ata133_program_timings(ide_drive_t *drive, const u8 mode)
 255 {
 256         struct pci_dev *dev = drive->hwif->pci_dev;
 257         u32 t1 = 0;
 258         u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
 259
 260         pci_read_config_dword(dev, drive_pci, &t1);
 261
 262         t1 &= 0xc0c00fff;
 263         clk = (t1 & 0x08) ? ATA_133 : ATA_100;
 264         if (mode >= XFER_MW_DMA_0) {
 265                 t1 &= ~0x04;    /* disable UDMA */
 266                 idx = mode - XFER_MW_DMA_0 + 5;
 267         } else
 268                 idx = mode - XFER_PIO_0;
 269         t1 |= ini_time_value[clk][idx] << 12;
 270         t1 |= act_time_value[clk][idx] << 16;
 271         t1 |= rco_time_value[clk][idx] << 24;
 272
 273         pci_write_config_dword(dev, drive_pci, t1);
 274 }
 275
 276 static void sis_program_timings(ide_drive_t *drive, const u8 mode)
 277 {
 278         if (chipset_family < ATA_100)           /* ATA_16/33/66/100a */
 279                 sis_ata16_program_timings(drive, mode);
 280         else if (chipset_family < ATA_133)      /* ATA_100/133a */
 281                 sis_ata100_program_timings(drive, mode);
 282         else                                    /* ATA_133 */
 283                 sis_ata133_program_timings(drive, mode);
 284 }
 285
 286 static void config_drive_art_rwp (ide_drive_t *drive)
 287 {
 288         ide_hwif_t *hwif        = HWIF(drive);
 289         struct pci_dev *dev     = hwif->pci_dev;
 290         u8 reg4bh               = 0;
 291         u8 rw_prefetch          = 0;
 292
 293         pci_read_config_byte(dev, 0x4b, &reg4bh);
 294
 295         if (drive->media == ide_disk)
 296                 rw_prefetch = 0x11 << drive->dn;
 297
 298         if ((reg4bh & (0x11 << drive->dn)) != rw_prefetch)
 299                 pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
 300 }
 301
 302 static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio)
 303 {
 304         config_drive_art_rwp(drive);
 305         sis_program_timings(drive, XFER_PIO_0 + pio);
 306 }
 307
 308 static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
 309 {
 310         ide_hwif_t *hwif        = HWIF(drive);
 311         struct pci_dev *dev     = hwif->pci_dev;
 312
 313         /* Config chip for mode */
 314         switch(speed) {
 315                 case XFER_UDMA_6:
 316                 case XFER_UDMA_5:
 317                 case XFER_UDMA_4:
 318                 case XFER_UDMA_3:
 319                 case XFER_UDMA_2:
 320                 case XFER_UDMA_1:
 321                 case XFER_UDMA_0:
 322                         if (chipset_family >= ATA_133) {
 323                                 u32 regdw = 0;
 324                                 u8 drive_pci = sis_ata133_get_base(drive);
 325
 326                                 pci_read_config_dword(dev, drive_pci, &regdw);
 327                                 regdw |= 0x04;
 328                                 regdw &= 0xfffff00f;
 329                                 /* check if ATA133 enable */
 330                                 if (regdw & 0x08) {
 331                                         regdw |= (unsigned long)cycle_time_value[ATA_133][speed-XFER_UDMA_0] << 4;
 332                                         regdw |= (unsigned long)cvs_time_value[ATA_133][speed-XFER_UDMA_0] << 8;
 333                                 } else {
 334                                         regdw |= (unsigned long)cycle_time_value[ATA_100][speed-XFER_UDMA_0] << 4;
 335                                         regdw |= (unsigned long)cvs_time_value[ATA_100][speed-XFER_UDMA_0] << 8;
 336                                 }
 337                                 pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
 338                         } else {
 339                                 u8 drive_pci = 0x40 + drive->dn * 2, reg = 0;
 340
 341                                 pci_read_config_byte(dev, drive_pci+1, &reg);
 342                                 /* Force the UDMA bit on if we want to use UDMA */
 343                                 reg |= 0x80;
 344                                 /* clean reg cycle time bits */
 345                                 reg &= ~((0xFF >> (8 - cycle_time_range[chipset_family]))
 346                                          << cycle_time_offset[chipset_family]);
 347                                 /* set reg cycle time bits */
 348                                 reg |= cycle_time_value[chipset_family][speed-XFER_UDMA_0]
 349                                         << cycle_time_offset[chipset_family];
 350                                 pci_write_config_byte(dev, drive_pci+1, reg);
 351                         }
 352                         break;
 353                 case XFER_MW_DMA_2:
 354                 case XFER_MW_DMA_1:
 355                 case XFER_MW_DMA_0:
 356                         sis_program_timings(drive, speed);
 357                         break;
 358                 default:
 359                         break;
 360         }
 361 }
 362
 363 static u8 sis5513_ata133_udma_filter(ide_drive_t *drive)
 364 {
 365         struct pci_dev *dev = drive->hwif->pci_dev;
 366         u32 regdw = 0;
 367         u8 drive_pci = sis_ata133_get_base(drive);
 368
 369         pci_read_config_dword(dev, drive_pci, &regdw);
 370
 371         /* if ATA133 disable, we should not set speed above UDMA5 */
 372         return (regdw & 0x08) ? ATA_UDMA6 : ATA_UDMA5;
 373 }
 374
 375 /* Chip detection and general config */
 376 static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const char *name)
 377 {
 378         struct pci_dev *host;
 379         int i = 0;
 380
 381         chipset_family = 0;
 382
 383         for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {
 384
 385                 host = pci_get_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);
 386
 387                 if (!host)
 388                         continue;
 389
 390                 chipset_family = SiSHostChipInfo[i].chipset_family;
 391
 392                 /* Special case for SiS630 : 630S/ET is ATA_100a */
 393                 if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
 394                         if (host->revision >= 0x30)
 395                                 chipset_family = ATA_100a;
 396                 }
 397                 pci_dev_put(host);
 398
 399                 printk(KERN_INFO "SIS5513: %s %s controller\n",
 400                          SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
 401         }
 402
 403         if (!chipset_family) { /* Belongs to pci-quirks */
 404
 405                         u32 idemisc;
 406                         u16 trueid;
 407
 408                         /* Disable ID masking and register remapping */
 409                         pci_read_config_dword(dev, 0x54, &idemisc);
 410                         pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
 411                         pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
 412                         pci_write_config_dword(dev, 0x54, idemisc);
 413
 414                         if (trueid == 0x5518) {
 415                                 printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n");
 416                                 chipset_family = ATA_133;
 417
 418                                 /* Check for 5513 compability mapping
 419                                  * We must use this, else the port enabled code will fail,
 420                                  * as it expects the enablebits at 0x4a.
 421                                  */
 422                                 if ((idemisc & 0x40000000) == 0) {
 423                                         pci_write_config_dword(dev, 0x54, idemisc | 0x40000000);
 424                                         printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
 425                                 }
 426                         }
 427         }
 428
 429         if (!chipset_family) { /* Belongs to pci-quirks */
 430
 431                         struct pci_dev *lpc_bridge;
 432                         u16 trueid;
 433                         u8 prefctl;
 434                         u8 idecfg;
 435
 436                         pci_read_config_byte(dev, 0x4a, &idecfg);
 437                         pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
 438                         pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
 439                         pci_write_config_byte(dev, 0x4a, idecfg);
 440
 441                         if (trueid == 0x5517) { /* SiS 961/961B */
 442
 443                                 lpc_bridge = pci_get_slot(dev->bus, 0x10); /* Bus 0, Dev 2, Fn 0 */
 444                                 pci_read_config_byte(dev, 0x49, &prefctl);
 445                                 pci_dev_put(lpc_bridge);
 446
 447                                 if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
 448                                         printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
 449                                         chipset_family = ATA_133a;
 450                                 } else {
 451                                         printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n");
 452                                         chipset_family = ATA_100;
 453                                 }
 454                         }
 455         }
 456
 457         if (!chipset_family)
 458                 return -1;
 459
 460         /* Make general config ops here
 461            1/ tell IDE channels to operate in Compatibility mode only
 462            2/ tell old chips to allow per drive IDE timings */
 463
 464         {
 465                 u8 reg;
 466                 u16 regw;
 467
 468                 switch(chipset_family) {
 469                         case ATA_133:
 470                                 /* SiS962 operation mode */
 471                                 pci_read_config_word(dev, 0x50, &regw);
 472                                 if (regw & 0x08)
 473                                         pci_write_config_word(dev, 0x50, regw&0xfff7);
 474                                 pci_read_config_word(dev, 0x52, &regw);
 475                                 if (regw & 0x08)
 476                                         pci_write_config_word(dev, 0x52, regw&0xfff7);
 477                                 break;
 478                         case ATA_133a:
 479                         case ATA_100:
 480                                 /* Fixup latency */
 481                                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
 482                                 /* Set compatibility bit */
 483                                 pci_read_config_byte(dev, 0x49, &reg);
 484                                 if (!(reg & 0x01)) {
 485                                         pci_write_config_byte(dev, 0x49, reg|0x01);
 486                                 }
 487                                 break;
 488                         case ATA_100a:
 489                         case ATA_66:
 490                                 /* Fixup latency */
 491                                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
 492
 493                                 /* On ATA_66 chips the bit was elsewhere */
 494                                 pci_read_config_byte(dev, 0x52, &reg);
 495                                 if (!(reg & 0x04)) {
 496                                         pci_write_config_byte(dev, 0x52, reg|0x04);
 497                                 }
 498                                 break;
 499                         case ATA_33:
 500                                 /* On ATA_33 we didn't have a single bit to set */
 501                                 pci_read_config_byte(dev, 0x09, &reg);
 502                                 if ((reg & 0x0f) != 0x00) {
 503                                         pci_write_config_byte(dev, 0x09, reg&0xf0);
 504                                 }
 505                         case ATA_16:
 506                                 /* force per drive recovery and active timings
 507                                    needed on ATA_33 and below chips */
 508                                 pci_read_config_byte(dev, 0x52, &reg);
 509                                 if (!(reg & 0x08)) {
 510                                         pci_write_config_byte(dev, 0x52, reg|0x08);
 511                                 }
 512                                 break;
 513                 }
 514         }
 515
 516         return 0;
 517 }
 518
 519 struct sis_laptop {
 520         u16 device;
 521         u16 subvendor;
 522         u16 subdevice;
 523 };
 524
 525 static const struct sis_laptop sis_laptop[] = {
 526         /* devid, subvendor, subdev */
 527         { 0x5513, 0x1043, 0x1107 },     /* ASUS A6K */
 528         { 0x5513, 0x1734, 0x105f },     /* FSC Amilo A1630 */
 529         /* end marker */
 530         { 0, }
 531 };
 532
 533 static u8 __devinit ata66_sis5513(ide_hwif_t *hwif)
 534 {
 535         struct pci_dev *pdev = hwif->pci_dev;
 536         const struct sis_laptop *lap = &sis_laptop[0];
 537         u8 ata66 = 0;
 538
 539         while (lap->device) {
 540                 if (lap->device == pdev->device &&
 541                     lap->subvendor == pdev->subsystem_vendor &&
 542                     lap->subdevice == pdev->subsystem_device)
 543                         return ATA_CBL_PATA40_SHORT;
 544                 lap++;
 545         }
 546
 547         if (chipset_family >= ATA_133) {
 548                 u16 regw = 0;
 549                 u16 reg_addr = hwif->channel ? 0x52: 0x50;
 550                 pci_read_config_word(hwif->pci_dev, reg_addr, &regw);
 551                 ata66 = (regw & 0x8000) ? 0 : 1;
 552         } else if (chipset_family >= ATA_66) {
 553                 u8 reg48h = 0;
 554                 u8 mask = hwif->channel ? 0x20 : 0x10;
 555                 pci_read_config_byte(hwif->pci_dev, 0x48, &reg48h);
 556                 ata66 = (reg48h & mask) ? 0 : 1;
 557         }
 558
 559         return ata66 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 560 }
 561
 562 static void __devinit init_hwif_sis5513 (ide_hwif_t *hwif)
 563 {
 564         u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f };
 565
 566         hwif->set_pio_mode = &sis_set_pio_mode;
 567         hwif->set_dma_mode = &sis_set_dma_mode;
 568
 569         if (chipset_family >= ATA_133)
 570                 hwif->udma_filter = sis5513_ata133_udma_filter;
 571
 572         if (hwif->dma_base == 0)
 573                 return;
 574
 575         hwif->ultra_mask = udma_rates[chipset_family];
 576
 577         if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 578                 hwif->cbl = ata66_sis5513(hwif);
 579 }
 580
 581 static const struct ide_port_info sis5513_chipset __devinitdata = {
 582         .name           = "SIS5513",
 583         .init_chipset   = init_chipset_sis5513,
 584         .init_hwif      = init_hwif_sis5513,
 585         .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 586         .host_flags     = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_NO_AUTODMA |
 587                           IDE_HFLAG_BOOTABLE,
 588         .pio_mask       = ATA_PIO4,
 589         .mwdma_mask     = ATA_MWDMA2,
 590 };
 591
 592 static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 593 {
 594         return ide_setup_pci_device(dev, &sis5513_chipset);
 595 }
 596
 597 static const struct pci_device_id sis5513_pci_tbl[] = {
 598         { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5513), 0 },
 599         { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5518), 0 },
 600         { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_1180), 0 },
 601         { 0, },
 602 };
 603 MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
 604
 605 static struct pci_driver driver = {
 606         .name           = "SIS_IDE",
 607         .id_table       = sis5513_pci_tbl,
 608         .probe          = sis5513_init_one,
 609 };
 610
 611 static int __init sis5513_ide_init(void)
 612 {
 613         return ide_pci_register_driver(&driver);
 614 }
 615
 616 module_init(sis5513_ide_init);
 617
 618 MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
 619 MODULE_DESCRIPTION("PCI driver module for SIS IDE");
 620 MODULE_LICENSE("GPL");
 621
 622 /*
 623  * TODO:
 624  *      - CLEANUP
 625  *      - Use drivers/ide/ide-timing.h !
 626  *      - More checks in the config registers (force values instead of
 627  *        relying on the BIOS setting them correctly).
 628  *      - Further optimisations ?
 629  *        . for example ATA66+ regs 0x48 & 0x4A
 630  */