2 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2003 Red Hat <alan@redhat.com>
4 * Copyright (C) 2007 MontaVista Software, Inc.
5 * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
7 * May be copied or modified under the terms of the GNU General Public License
9 * Documentation for CMD680:
10 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
12 * Documentation for SiI 3112:
13 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
15 * Errata and other documentation only available under NDA.
19 * If you are using Marvell SATA-IDE adapters with Maxtor drives
20 * ensure the system is set up for ATA100/UDMA5 not UDMA6.
22 * If you are using WD drives with SATA bridges you must set the
23 * drive to "Single". "Master" will hang
25 * If you have strange problems with nVidia chipset systems please
26 * see the SI support documentation and update your system BIOS
29 * The Dell DRAC4 has some interesting features including effectively hot
30 * unplugging/replugging the virtual CD interface when the DRAC is reset.
31 * This often causes drivers/ide/siimage to panic but is ok with the rather
32 * smarter code in libata.
39 #include <linux/types.h>
40 #include <linux/module.h>
41 #include <linux/pci.h>
42 #include <linux/hdreg.h>
43 #include <linux/ide.h>
44 #include <linux/init.h>
49 * pdev_is_sata - check if device is SATA
50 * @pdev: PCI device to check
52 * Returns true if this is a SATA controller
55 static int pdev_is_sata(struct pci_dev *pdev)
57 #ifdef CONFIG_BLK_DEV_IDE_SATA
58 switch(pdev->device) {
59 case PCI_DEVICE_ID_SII_3112:
60 case PCI_DEVICE_ID_SII_1210SA:
62 case PCI_DEVICE_ID_SII_680:
71 * is_sata - check if hwif is SATA
72 * @hwif: interface to check
74 * Returns true if this is a SATA controller
77 static inline int is_sata(ide_hwif_t *hwif)
79 return pdev_is_sata(to_pci_dev(hwif->dev));
83 * siimage_selreg - return register base
87 * Turn a config register offset into the right address in either
88 * PCI space or MMIO space to access the control register in question
89 * Thankfully this is a configuration operation so isnt performance
93 static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
95 unsigned long base = (unsigned long)hwif->hwif_data;
98 base += (hwif->channel << 6);
100 base += (hwif->channel << 4);
105 * siimage_seldev - return register base
109 * Turn a config register offset into the right address in either
110 * PCI space or MMIO space to access the control register in question
111 * including accounting for the unit shift.
114 static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
116 ide_hwif_t *hwif = HWIF(drive);
117 unsigned long base = (unsigned long)hwif->hwif_data;
120 base += (hwif->channel << 6);
122 base += (hwif->channel << 4);
123 base |= drive->select.b.unit << drive->select.b.unit;
127 static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr)
131 if (pci_get_drvdata(dev))
132 tmp = readb((void __iomem *)addr);
134 pci_read_config_byte(dev, addr, &tmp);
139 static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr)
143 if (pci_get_drvdata(dev))
144 tmp = readw((void __iomem *)addr);
146 pci_read_config_word(dev, addr, &tmp);
151 static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr)
153 if (pci_get_drvdata(dev))
154 writeb(val, (void __iomem *)addr);
156 pci_write_config_byte(dev, addr, val);
159 static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr)
161 if (pci_get_drvdata(dev))
162 writew(val, (void __iomem *)addr);
164 pci_write_config_word(dev, addr, val);
167 static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr)
169 if (pci_get_drvdata(dev))
170 writel(val, (void __iomem *)addr);
172 pci_write_config_dword(dev, addr, val);
176 * sil_udma_filter - compute UDMA mask
179 * Compute the available UDMA speeds for the device on the interface.
181 * For the CMD680 this depends on the clocking mode (scsc), for the
182 * SI3112 SATA controller life is a bit simpler.
185 static u8 sil_pata_udma_filter(ide_drive_t *drive)
187 ide_hwif_t *hwif = drive->hwif;
188 struct pci_dev *dev = to_pci_dev(hwif->dev);
189 unsigned long base = (unsigned long) hwif->hwif_data;
192 scsc = sil_ioread8(dev, base + (hwif->mmio ? 0x4A : 0x8A));
194 if ((scsc & 0x30) == 0x10) /* 133 */
196 else if ((scsc & 0x30) == 0x20) /* 2xPCI */
198 else if ((scsc & 0x30) == 0x00) /* 100 */
200 else /* Disabled ? */
206 static u8 sil_sata_udma_filter(ide_drive_t *drive)
208 return strstr(drive->id->model, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6;
212 * sil_set_pio_mode - set host controller for PIO mode
214 * @pio: PIO mode number
216 * Load the timing settings for this device mode into the
217 * controller. If we are in PIO mode 3 or 4 turn on IORDY
218 * monitoring (bit 9). The TF timing is bits 31:16
221 static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
223 const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
224 const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
226 ide_hwif_t *hwif = HWIF(drive);
227 struct pci_dev *dev = to_pci_dev(hwif->dev);
228 ide_drive_t *pair = ide_get_paired_drive(drive);
231 unsigned long addr = siimage_seldev(drive, 0x04);
232 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
233 unsigned long base = (unsigned long)hwif->hwif_data;
235 u8 addr_mask = hwif->channel ? (hwif->mmio ? 0xF4 : 0x84)
236 : (hwif->mmio ? 0xB4 : 0x80);
238 u8 unit = drive->select.b.unit;
240 /* trim *taskfile* PIO to the slowest of the master/slave */
242 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
244 if (pair_pio < tf_pio)
248 /* cheat for now and use the docs */
249 speedp = data_speed[pio];
250 speedt = tf_speed[tf_pio];
252 sil_iowrite16(dev, speedp, addr);
253 sil_iowrite16(dev, speedt, tfaddr);
255 /* now set up IORDY */
256 speedp = sil_ioread16(dev, tfaddr - 2);
260 sil_iowrite16(dev, speedp, tfaddr - 2);
262 mode = sil_ioread8(dev, base + addr_mask);
263 mode &= ~(unit ? 0x30 : 0x03);
264 mode |= (unit ? 0x10 : 0x01);
265 sil_iowrite8(dev, mode, base + addr_mask);
269 * sil_set_dma_mode - set host controller for DMA mode
273 * Tune the SiI chipset for the desired DMA mode.
276 static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed)
278 u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
279 u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
280 u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
282 ide_hwif_t *hwif = HWIF(drive);
283 struct pci_dev *dev = to_pci_dev(hwif->dev);
284 u16 ultra = 0, multi = 0;
285 u8 mode = 0, unit = drive->select.b.unit;
286 unsigned long base = (unsigned long)hwif->hwif_data;
287 u8 scsc = 0, addr_mask = ((hwif->channel) ?
288 ((hwif->mmio) ? 0xF4 : 0x84) :
289 ((hwif->mmio) ? 0xB4 : 0x80));
291 unsigned long ma = siimage_seldev(drive, 0x08);
292 unsigned long ua = siimage_seldev(drive, 0x0C);
294 scsc = sil_ioread8(dev, base + (hwif->mmio ? 0x4A : 0x8A));
295 mode = sil_ioread8(dev, base + addr_mask);
296 multi = sil_ioread16(dev, ma);
297 ultra = sil_ioread16(dev, ua);
299 mode &= ~((unit) ? 0x30 : 0x03);
301 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
303 scsc = is_sata(hwif) ? 1 : scsc;
305 if (speed >= XFER_UDMA_0) {
307 ultra |= (scsc ? ultra6[speed - XFER_UDMA_0] :
308 ultra5[speed - XFER_UDMA_0]);
309 mode |= (unit ? 0x30 : 0x03);
311 multi = dma[speed - XFER_MW_DMA_0];
312 mode |= (unit ? 0x20 : 0x02);
315 sil_iowrite8(dev, mode, base + addr_mask);
316 sil_iowrite16(dev, multi, ma);
317 sil_iowrite16(dev, ultra, ua);
320 /* returns 1 if dma irq issued, 0 otherwise */
321 static int siimage_io_dma_test_irq(ide_drive_t *drive)
323 ide_hwif_t *hwif = HWIF(drive);
324 struct pci_dev *dev = to_pci_dev(hwif->dev);
326 unsigned long addr = siimage_selreg(hwif, 1);
328 /* return 1 if INTR asserted */
329 if ((hwif->INB(hwif->dma_status) & 4) == 4)
332 /* return 1 if Device INTR asserted */
333 pci_read_config_byte(dev, addr, &dma_altstat);
335 return 0; //return 1;
340 * siimage_mmio_dma_test_irq - check we caused an IRQ
341 * @drive: drive we are testing
343 * Check if we caused an IDE DMA interrupt. We may also have caused
344 * SATA status interrupts, if so we clean them up and continue.
347 static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
349 ide_hwif_t *hwif = HWIF(drive);
350 unsigned long addr = siimage_selreg(hwif, 0x1);
351 void __iomem *sata_error_addr
352 = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET];
354 if (sata_error_addr) {
355 unsigned long base = (unsigned long)hwif->hwif_data;
356 u32 ext_stat = readl((void __iomem *)(base + 0x10));
359 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
360 u32 sata_error = readl(sata_error_addr);
362 writel(sata_error, sata_error_addr);
363 watchdog = (sata_error & 0x00680000) ? 1 : 0;
364 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
365 "watchdog = %d, %s\n",
366 drive->name, sata_error, watchdog,
370 watchdog = (ext_stat & 0x8000) ? 1 : 0;
374 if (!(ext_stat & 0x0404) && !watchdog)
378 /* return 1 if INTR asserted */
379 if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04)
382 /* return 1 if Device INTR asserted */
383 if ((readb((void __iomem *)addr) & 8) == 8)
384 return 0; //return 1;
389 static int siimage_dma_test_irq(ide_drive_t *drive)
391 if (drive->hwif->mmio)
392 return siimage_mmio_dma_test_irq(drive);
394 return siimage_io_dma_test_irq(drive);
398 * sil_sata_reset_poll - wait for SATA reset
399 * @drive: drive we are resetting
401 * Poll the SATA phy and see whether it has come back from the dead
405 static int sil_sata_reset_poll(ide_drive_t *drive)
407 ide_hwif_t *hwif = drive->hwif;
408 void __iomem *sata_status_addr
409 = (void __iomem *)hwif->sata_scr[SATA_STATUS_OFFSET];
411 if (sata_status_addr) {
412 /* SATA Status is available only when in MMIO mode */
413 u32 sata_stat = readl(sata_status_addr);
415 if ((sata_stat & 0x03) != 0x03) {
416 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
417 hwif->name, sata_stat);
418 HWGROUP(drive)->polling = 0;
427 * sil_sata_pre_reset - reset hook
428 * @drive: IDE device being reset
430 * For the SATA devices we need to handle recalibration/geometry
434 static void sil_sata_pre_reset(ide_drive_t *drive)
436 if (drive->media == ide_disk) {
437 drive->special.b.set_geometry = 0;
438 drive->special.b.recalibrate = 0;
443 * proc_reports_siimage - add siimage controller to proc
445 * @clocking: SCSC value
446 * @name: controller name
448 * Report the clocking mode of the controller and add it to
449 * the /proc interface layer
452 static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
454 if (!pdev_is_sata(dev)) {
455 printk(KERN_INFO "%s: BASE CLOCK ", name);
458 case 0x03: printk("DISABLED!\n"); break;
459 case 0x02: printk("== 2X PCI\n"); break;
460 case 0x01: printk("== 133\n"); break;
461 case 0x00: printk("== 100\n"); break;
467 * setup_mmio_siimage - switch an SI controller into MMIO
468 * @dev: PCI device we are configuring
471 * Attempt to put the device into mmio mode. There are some slight
472 * complications here with certain systems where the mmio bar isnt
473 * mapped so we have to be sure we can fall back to I/O.
476 static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
478 resource_size_t bar5 = pci_resource_start(dev, 5);
479 unsigned long barsize = pci_resource_len(dev, 5);
480 void __iomem *ioaddr;
483 * Drop back to PIO if we can't map the mmio. Some
484 * systems seem to get terminally confused in the PCI
487 if (!request_mem_region(bar5, barsize, name)) {
488 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
492 ioaddr = ioremap(bar5, barsize);
494 if (ioaddr == NULL) {
495 release_mem_region(bar5, barsize);
500 pci_set_drvdata(dev, (void *) ioaddr);
506 * init_chipset_siimage - set up an SI device
510 * Perform the initial PCI set up for this device. Attempt to switch
511 * to 133MHz clocking if the system isn't already set up to do it.
514 static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
516 unsigned long base, scsc_addr;
517 void __iomem *ioaddr = NULL;
518 u8 rev = dev->revision, tmp = 0, BA5_EN = 0;
520 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
522 pci_read_config_byte(dev, 0x8A, &BA5_EN);
524 if ((BA5_EN & 0x01) || pci_resource_start(dev, 5)) {
525 if (setup_mmio_siimage(dev, name))
526 ioaddr = pci_get_drvdata(dev);
529 base = (unsigned long)ioaddr;
531 if (ioaddr && pdev_is_sata(dev)) {
534 /* make sure IDE0/1 interrupts are not masked */
535 irq_mask = (1 << 22) | (1 << 23);
536 tmp32 = readl(ioaddr + 0x48);
537 if (tmp32 & irq_mask) {
539 writel(tmp32, ioaddr + 0x48);
540 readl(ioaddr + 0x48); /* flush */
542 writel(0, ioaddr + 0x148);
543 writel(0, ioaddr + 0x1C8);
546 sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);
547 sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);
549 scsc_addr = base ? (base + 0x4A) : 0x8A;
550 tmp = sil_ioread8(dev, scsc_addr);
552 switch (tmp & 0x30) {
554 /* On 100MHz clocking, try and switch to 133MHz */
555 sil_iowrite8(dev, tmp | 0x10, scsc_addr);
558 /* Clocking is disabled, attempt to force 133MHz clocking. */
559 sil_iowrite8(dev, tmp & ~0x20, scsc_addr);
561 /* On 133Mhz clocking. */
564 /* On PCIx2 clocking. */
568 tmp = sil_ioread8(dev, scsc_addr);
570 sil_iowrite8(dev, 0x72, base + 0xA1);
571 sil_iowrite16(dev, 0x328A, base + 0xA2);
572 sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
573 sil_iowrite32(dev, 0x43924392, base + 0xA8);
574 sil_iowrite32(dev, 0x40094009, base + 0xAC);
575 sil_iowrite8(dev, 0x72, base ? (base + 0xE1) : 0xB1);
576 sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2);
577 sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
578 sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
579 sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);
581 if (base && pdev_is_sata(dev)) {
582 writel(0xFFFF0000, ioaddr + 0x108);
583 writel(0xFFFF0000, ioaddr + 0x188);
584 writel(0x00680000, ioaddr + 0x148);
585 writel(0x00680000, ioaddr + 0x1C8);
588 proc_reports_siimage(dev, tmp >> 4, name);
594 * init_mmio_iops_siimage - set up the iops for MMIO
595 * @hwif: interface to set up
597 * The basic setup here is fairly simple, we can use standard MMIO
598 * operations. However we do have to set the taskfile register offsets
599 * by hand as there isnt a standard defined layout for them this
602 * The hardware supports buffered taskfiles and also some rather nice
603 * extended PRD tables. For better SI3112 support use the libata driver
606 static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
608 struct pci_dev *dev = to_pci_dev(hwif->dev);
609 void *addr = pci_get_drvdata(dev);
610 u8 ch = hwif->channel;
613 struct ide_io_ports *io_ports = &hwif->io_ports;
616 * Fill in the basic HWIF bits
619 hwif->host_flags |= IDE_HFLAG_MMIO;
620 default_hwif_mmiops(hwif);
621 hwif->hwif_data = addr;
624 * Now set up the hw. We have to do this ourselves as
625 * the MMIO layout isnt the same as the standard port
629 memset(io_ports, 0, sizeof(*io_ports));
631 base = (unsigned long)addr;
638 * The buffered task file doesn't have status/control
639 * so we can't currently use it sanely since we want to
642 io_ports->data_addr = base;
643 io_ports->error_addr = base + 1;
644 io_ports->nsect_addr = base + 2;
645 io_ports->lbal_addr = base + 3;
646 io_ports->lbam_addr = base + 4;
647 io_ports->lbah_addr = base + 5;
648 io_ports->device_addr = base + 6;
649 io_ports->status_addr = base + 7;
650 io_ports->ctl_addr = base + 10;
652 if (pdev_is_sata(dev)) {
653 base = (unsigned long)addr;
656 hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
657 hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
658 hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
661 hwif->irq = dev->irq;
663 hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
668 static int is_dev_seagate_sata(ide_drive_t *drive)
670 const char *s = &drive->id->model[0];
673 len = strnlen(s, sizeof(drive->id->model));
675 if ((len > 4) && (!memcmp(s, "ST", 2))) {
676 if ((!memcmp(s + len - 2, "AS", 2)) ||
677 (!memcmp(s + len - 3, "ASL", 3))) {
678 printk(KERN_INFO "%s: applying pessimistic Seagate "
679 "errata fix\n", drive->name);
687 * sil_quirkproc - post probe fixups
690 * Called after drive probe we use this to decide whether the
691 * Seagate fixup must be applied. This used to be in init_iops but
692 * that can occur before we know what drives are present.
695 static void __devinit sil_quirkproc(ide_drive_t *drive)
697 ide_hwif_t *hwif = drive->hwif;
699 /* Try and raise the rqsize */
700 if (!is_sata(hwif) || !is_dev_seagate_sata(drive))
705 * init_iops_siimage - set up iops
706 * @hwif: interface to set up
708 * Do the basic setup for the SIIMAGE hardware interface
709 * and then do the MMIO setup if we can. This is the first
710 * look in we get for setting up the hwif so that we
711 * can get the iops right before using them.
714 static void __devinit init_iops_siimage(ide_hwif_t *hwif)
716 struct pci_dev *dev = to_pci_dev(hwif->dev);
718 hwif->hwif_data = NULL;
720 /* Pessimal until we finish probing */
723 if (pci_get_drvdata(dev) == NULL)
726 init_mmio_iops_siimage(hwif);
730 * sil_cable_detect - cable detection
731 * @hwif: interface to check
733 * Check for the presence of an ATA66 capable cable on the
737 static u8 __devinit sil_cable_detect(ide_hwif_t *hwif)
739 struct pci_dev *dev = to_pci_dev(hwif->dev);
740 unsigned long addr = siimage_selreg(hwif, 0);
741 u8 ata66 = sil_ioread8(dev, addr);
743 return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
746 static const struct ide_port_ops sil_pata_port_ops = {
747 .set_pio_mode = sil_set_pio_mode,
748 .set_dma_mode = sil_set_dma_mode,
749 .quirkproc = sil_quirkproc,
750 .udma_filter = sil_pata_udma_filter,
751 .cable_detect = sil_cable_detect,
754 static const struct ide_port_ops sil_sata_port_ops = {
755 .set_pio_mode = sil_set_pio_mode,
756 .set_dma_mode = sil_set_dma_mode,
757 .reset_poll = sil_sata_reset_poll,
758 .pre_reset = sil_sata_pre_reset,
759 .quirkproc = sil_quirkproc,
760 .udma_filter = sil_sata_udma_filter,
761 .cable_detect = sil_cable_detect,
764 static struct ide_dma_ops sil_dma_ops = {
765 .dma_test_irq = siimage_dma_test_irq,
768 #define DECLARE_SII_DEV(name_str, p_ops) \
771 .init_chipset = init_chipset_siimage, \
772 .init_iops = init_iops_siimage, \
774 .dma_ops = &sil_dma_ops, \
775 .pio_mask = ATA_PIO4, \
776 .mwdma_mask = ATA_MWDMA2, \
777 .udma_mask = ATA_UDMA6, \
780 static const struct ide_port_info siimage_chipsets[] __devinitdata = {
781 /* 0 */ DECLARE_SII_DEV("SiI680", &sil_pata_port_ops),
782 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA", &sil_sata_port_ops),
783 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA", &sil_sata_port_ops)
787 * siimage_init_one - pci layer discovery entry
789 * @id: ident table entry
791 * Called by the PCI code when it finds an SI680 or SI3112 controller.
792 * We then use the IDE PCI generic helper to do most of the work.
795 static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
797 struct ide_port_info d;
798 u8 idx = id->driver_data;
800 d = siimage_chipsets[idx];
803 static int first = 1;
806 printk(KERN_INFO "siimage: For full SATA support you "
807 "should use the libata sata_sil module.\n");
811 d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
814 return ide_setup_pci_device(dev, &d);
817 static const struct pci_device_id siimage_pci_tbl[] = {
818 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 },
819 #ifdef CONFIG_BLK_DEV_IDE_SATA
820 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 },
821 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 2 },
825 MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
827 static struct pci_driver driver = {
829 .id_table = siimage_pci_tbl,
830 .probe = siimage_init_one,
833 static int __init siimage_ide_init(void)
835 return ide_pci_register_driver(&driver);
838 module_init(siimage_ide_init);
840 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
841 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
842 MODULE_LICENSE("GPL");