2 * Copyright (c) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
8 * This program is distributed in the hope that it would be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12 * You should have received a copy of the GNU General Public
13 * License along with this program; if not, write the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 * For further information regarding this notice, see:
18 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
21 #include <linux/module.h>
22 #include <linux/types.h>
23 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <linux/hdreg.h>
26 #include <linux/init.h>
27 #include <linux/kernel.h>
28 #include <linux/timer.h>
30 #include <linux/ioport.h>
31 #include <linux/blkdev.h>
32 #include <linux/scatterlist.h>
33 #include <linux/ioc4.h>
36 #include <linux/ide.h>
38 #define DRV_NAME "SGIIOC4"
40 /* IOC4 Specific Definitions */
41 #define IOC4_CMD_OFFSET 0x100
42 #define IOC4_CTRL_OFFSET 0x120
43 #define IOC4_DMA_OFFSET 0x140
44 #define IOC4_INTR_OFFSET 0x0
46 #define IOC4_TIMING 0x00
47 #define IOC4_DMA_PTR_L 0x01
48 #define IOC4_DMA_PTR_H 0x02
49 #define IOC4_DMA_ADDR_L 0x03
50 #define IOC4_DMA_ADDR_H 0x04
51 #define IOC4_BC_DEV 0x05
52 #define IOC4_BC_MEM 0x06
53 #define IOC4_DMA_CTRL 0x07
54 #define IOC4_DMA_END_ADDR 0x08
56 /* Bits in the IOC4 Control/Status Register */
57 #define IOC4_S_DMA_START 0x01
58 #define IOC4_S_DMA_STOP 0x02
59 #define IOC4_S_DMA_DIR 0x04
60 #define IOC4_S_DMA_ACTIVE 0x08
61 #define IOC4_S_DMA_ERROR 0x10
62 #define IOC4_ATA_MEMERR 0x02
64 /* Read/Write Directions */
65 #define IOC4_DMA_WRITE 0x04
66 #define IOC4_DMA_READ 0x00
68 /* Interrupt Register Offsets */
69 #define IOC4_INTR_REG 0x03
70 #define IOC4_INTR_SET 0x05
71 #define IOC4_INTR_CLEAR 0x07
73 #define IOC4_IDE_CACHELINE_SIZE 128
74 #define IOC4_CMD_CTL_BLK_SIZE 0x20
75 #define IOC4_SUPPORTED_FIRMWARE_REV 46
89 /* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
90 /* IOC4 has only 1 IDE channel */
91 #define IOC4_PRD_BYTES 16
92 #define IOC4_PRD_ENTRIES (PAGE_SIZE /(4*IOC4_PRD_BYTES))
96 sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
97 unsigned long ctrl_port, unsigned long irq_port)
99 unsigned long reg = data_port;
102 /* Registers are word (32 bit) aligned */
103 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
104 hw->io_ports[i] = reg + i * 4;
107 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
110 hw->io_ports[IDE_IRQ_OFFSET] = irq_port;
114 sgiioc4_maskproc(ide_drive_t * drive, int mask)
116 writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
117 (void __iomem *)IDE_CONTROL_REG);
122 sgiioc4_checkirq(ide_hwif_t * hwif)
124 unsigned long intr_addr =
125 hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4;
127 if ((u8)readl((void __iomem *)intr_addr) & 0x03)
133 static u8 sgiioc4_INB(unsigned long);
136 sgiioc4_clearirq(ide_drive_t * drive)
139 ide_hwif_t *hwif = HWIF(drive);
140 unsigned long other_ir =
141 hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2);
143 /* Code to check for PCI error conditions */
144 intr_reg = readl((void __iomem *)other_ir);
145 if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
147 * Using sgiioc4_INB to read the IDE_STATUS_REG has a side effect
148 * of clearing the interrupt. The first read should clear it
149 * if it is set. The second read should return a "clear" status
150 * if it got cleared. If not, then spin for a bit trying to
153 u8 stat = sgiioc4_INB(IDE_STATUS_REG);
155 stat = sgiioc4_INB(IDE_STATUS_REG);
156 while ((stat & 0x80) && (count++ < 100)) {
158 stat = sgiioc4_INB(IDE_STATUS_REG);
161 if (intr_reg & 0x02) {
162 /* Error when transferring DMA data on PCI bus */
163 u32 pci_err_addr_low, pci_err_addr_high,
167 readl((void __iomem *)hwif->io_ports[IDE_IRQ_OFFSET]);
169 readl((void __iomem *)(hwif->io_ports[IDE_IRQ_OFFSET] + 4));
170 pci_read_config_dword(hwif->pci_dev, PCI_COMMAND,
173 "%s(%s) : PCI Bus Error when doing DMA:"
174 " status-cmd reg is 0x%x\n",
175 __FUNCTION__, drive->name, pci_stat_cmd_reg);
177 "%s(%s) : PCI Error Address is 0x%x%x\n",
178 __FUNCTION__, drive->name,
179 pci_err_addr_high, pci_err_addr_low);
180 /* Clear the PCI Error indicator */
181 pci_write_config_dword(hwif->pci_dev, PCI_COMMAND,
185 /* Clear the Interrupt, Error bits on the IOC4 */
186 writel(0x03, (void __iomem *)other_ir);
188 intr_reg = readl((void __iomem *)other_ir);
194 static void sgiioc4_ide_dma_start(ide_drive_t * drive)
196 ide_hwif_t *hwif = HWIF(drive);
197 unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4;
198 unsigned int reg = readl((void __iomem *)ioc4_dma_addr);
199 unsigned int temp_reg = reg | IOC4_S_DMA_START;
201 writel(temp_reg, (void __iomem *)ioc4_dma_addr);
205 sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
207 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
212 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
213 while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
215 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
220 /* Stops the IOC4 DMA Engine */
222 sgiioc4_ide_dma_end(ide_drive_t * drive)
224 u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
225 ide_hwif_t *hwif = HWIF(drive);
226 unsigned long dma_base = hwif->dma_base;
228 unsigned long *ending_dma = ide_get_hwifdata(hwif);
230 writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4));
232 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
234 if (ioc4_dma & IOC4_S_DMA_STOP) {
236 "%s(%s): IOC4 DMA STOP bit is still 1 :"
237 "ioc4_dma_reg 0x%x\n",
238 __FUNCTION__, drive->name, ioc4_dma);
243 * The IOC4 will DMA 1's to the ending dma area to indicate that
244 * previous data DMA is complete. This is necessary because of relaxed
245 * ordering between register reads and DMA writes on the Altix.
247 while ((cnt++ < 200) && (!valid)) {
248 for (num = 0; num < 16; num++) {
249 if (ending_dma[num]) {
257 printk(KERN_ERR "%s(%s) : DMA incomplete\n", __FUNCTION__,
262 bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4));
263 bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4));
265 if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
266 if (bc_dev > bc_mem + 8) {
268 "%s(%s): WARNING!! byte_count_dev %d "
269 "!= byte_count_mem %d\n",
270 __FUNCTION__, drive->name, bc_dev, bc_mem);
274 drive->waiting_for_dma = 0;
275 ide_destroy_dmatable(drive);
280 static void sgiioc4_set_dma_mode(ide_drive_t *drive, const u8 speed)
284 /* returns 1 if dma irq issued, 0 otherwise */
286 sgiioc4_ide_dma_test_irq(ide_drive_t * drive)
288 return sgiioc4_checkirq(HWIF(drive));
291 static void sgiioc4_dma_host_on(ide_drive_t * drive)
295 static void sgiioc4_dma_host_off(ide_drive_t * drive)
297 sgiioc4_clearirq(drive);
301 sgiioc4_resetproc(ide_drive_t * drive)
303 sgiioc4_ide_dma_end(drive);
304 sgiioc4_clearirq(drive);
308 sgiioc4_dma_lost_irq(ide_drive_t * drive)
310 sgiioc4_resetproc(drive);
312 ide_dma_lost_irq(drive);
316 sgiioc4_INB(unsigned long port)
318 u8 reg = (u8) readb((void __iomem *) port);
320 if ((port & 0xFFF) == 0x11C) { /* Status register of IOC4 */
321 if (reg & 0x51) { /* Not busy...check for interrupt */
322 unsigned long other_ir = port - 0x110;
323 unsigned int intr_reg = (u32) readl((void __iomem *) other_ir);
325 /* Clear the Interrupt, Error bits on the IOC4 */
326 if (intr_reg & 0x03) {
327 writel(0x03, (void __iomem *) other_ir);
328 intr_reg = (u32) readl((void __iomem *) other_ir);
336 /* Creates a dma map for the scatter-gather list entries */
338 ide_dma_sgiioc4(ide_hwif_t * hwif, unsigned long dma_base)
340 void __iomem *virt_dma_base;
341 int num_ports = sizeof (ioc4_dma_regs_t);
344 printk(KERN_INFO "%s: BM-DMA at 0x%04lx-0x%04lx\n", hwif->name,
345 dma_base, dma_base + num_ports - 1);
347 if (!request_mem_region(dma_base, num_ports, hwif->name)) {
349 "%s(%s) -- ERROR, Addresses 0x%p to 0x%p "
351 __FUNCTION__, hwif->name, (void *) dma_base,
352 (void *) dma_base + num_ports - 1);
356 virt_dma_base = ioremap(dma_base, num_ports);
357 if (virt_dma_base == NULL) {
359 "%s(%s) -- ERROR, Unable to map addresses 0x%lx to 0x%lx\n",
360 __FUNCTION__, hwif->name, dma_base, dma_base + num_ports - 1);
361 goto dma_remap_failure;
363 hwif->dma_base = (unsigned long) virt_dma_base;
365 hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev,
366 IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
367 &hwif->dmatable_dma);
369 if (!hwif->dmatable_cpu)
370 goto dma_pci_alloc_failure;
372 hwif->sg_max_nents = IOC4_PRD_ENTRIES;
374 pad = pci_alloc_consistent(hwif->pci_dev, IOC4_IDE_CACHELINE_SIZE,
375 (dma_addr_t *) &(hwif->dma_status));
378 ide_set_hwifdata(hwif, pad);
382 pci_free_consistent(hwif->pci_dev,
383 IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
384 hwif->dmatable_cpu, hwif->dmatable_dma);
386 "%s() -- Error! Unable to allocate DMA Maps for drive %s\n",
387 __FUNCTION__, hwif->name);
389 "Changing from DMA to PIO mode for Drive %s\n", hwif->name);
391 dma_pci_alloc_failure:
392 iounmap(virt_dma_base);
395 release_mem_region(dma_base, num_ports);
400 /* Initializes the IOC4 DMA Engine */
402 sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
405 ide_hwif_t *hwif = HWIF(drive);
406 unsigned long dma_base = hwif->dma_base;
407 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
408 u32 dma_addr, ending_dma_addr;
410 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
412 if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
414 "%s(%s):Warning!! DMA from previous transfer was still active\n",
415 __FUNCTION__, drive->name);
416 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
417 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
419 if (ioc4_dma & IOC4_S_DMA_STOP)
421 "%s(%s) : IOC4 Dma STOP bit is still 1\n",
422 __FUNCTION__, drive->name);
425 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
426 if (ioc4_dma & IOC4_S_DMA_ERROR) {
428 "%s(%s) : Warning!! - DMA Error during Previous"
429 " transfer | status 0x%x\n",
430 __FUNCTION__, drive->name, ioc4_dma);
431 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
432 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
434 if (ioc4_dma & IOC4_S_DMA_STOP)
436 "%s(%s) : IOC4 DMA STOP bit is still 1\n",
437 __FUNCTION__, drive->name);
440 /* Address of the Scatter Gather List */
441 dma_addr = cpu_to_le32(hwif->dmatable_dma);
442 writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4));
444 /* Address of the Ending DMA */
445 memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE);
446 ending_dma_addr = cpu_to_le32(hwif->dma_status);
447 writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4));
449 writel(dma_direction, (void __iomem *)ioc4_dma_addr);
450 drive->waiting_for_dma = 1;
453 /* IOC4 Scatter Gather list Format */
454 /* 128 Bit entries to support 64 bit addresses in the future */
455 /* The Scatter Gather list Entry should be in the BIG-ENDIAN Format */
456 /* --------------------------------------------------------------------- */
457 /* | Upper 32 bits - Zero | Lower 32 bits- address | */
458 /* --------------------------------------------------------------------- */
459 /* | Upper 32 bits - Zero |EOL| 15 unused | 16 Bit Length| */
460 /* --------------------------------------------------------------------- */
461 /* Creates the scatter gather list, DMA Table */
463 sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir)
465 ide_hwif_t *hwif = HWIF(drive);
466 unsigned int *table = hwif->dmatable_cpu;
467 unsigned int count = 0, i = 1;
468 struct scatterlist *sg;
470 hwif->sg_nents = i = ide_build_sglist(drive, rq);
473 return 0; /* sglist of length Zero */
476 while (i && sg_dma_len(sg)) {
479 cur_addr = sg_dma_address(sg);
480 cur_len = sg_dma_len(sg);
483 if (count++ >= IOC4_PRD_ENTRIES) {
485 "%s: DMA table too small\n",
487 goto use_pio_instead;
490 0x10000 - (cur_addr & 0xffff);
492 if (bcount > cur_len)
495 /* put the addr, length in
496 * the IOC4 dma-table format */
499 *table = cpu_to_be32(cur_addr);
504 *table = cpu_to_be32(bcount);
518 *table |= cpu_to_be32(0x80000000);
523 pci_unmap_sg(hwif->pci_dev, hwif->sg_table, hwif->sg_nents,
524 hwif->sg_dma_direction);
526 return 0; /* revert to PIO for this request */
529 static int sgiioc4_ide_dma_setup(ide_drive_t *drive)
531 struct request *rq = HWGROUP(drive)->rq;
532 unsigned int count = 0;
536 ddir = PCI_DMA_TODEVICE;
538 ddir = PCI_DMA_FROMDEVICE;
540 if (!(count = sgiioc4_build_dma_table(drive, rq, ddir))) {
541 /* try PIO instead of DMA */
542 ide_map_sg(drive, rq);
547 /* Writes TO the IOC4 FROM Main Memory */
548 ddir = IOC4_DMA_READ;
550 /* Writes FROM the IOC4 TO Main Memory */
551 ddir = IOC4_DMA_WRITE;
553 sgiioc4_configure_for_dma(ddir, drive);
558 static void __devinit
559 ide_init_sgiioc4(ide_hwif_t * hwif)
562 hwif->pio_mask = 0x00;
563 hwif->set_pio_mode = NULL; /* Sets timing for PIO mode */
564 hwif->set_dma_mode = &sgiioc4_set_dma_mode;
565 hwif->selectproc = NULL;/* Use the default routine to select drive */
566 hwif->reset_poll = NULL;/* No HBA specific reset_poll needed */
567 hwif->pre_reset = NULL; /* No HBA specific pre_set needed */
568 hwif->resetproc = &sgiioc4_resetproc;/* Reset DMA engine,
570 hwif->maskproc = &sgiioc4_maskproc; /* Mask on/off NIEN register */
571 hwif->quirkproc = NULL;
572 hwif->busproc = NULL;
574 hwif->INB = &sgiioc4_INB;
576 if (hwif->dma_base == 0)
579 hwif->mwdma_mask = ATA_MWDMA2_ONLY;
581 hwif->dma_setup = &sgiioc4_ide_dma_setup;
582 hwif->dma_start = &sgiioc4_ide_dma_start;
583 hwif->ide_dma_end = &sgiioc4_ide_dma_end;
584 hwif->ide_dma_test_irq = &sgiioc4_ide_dma_test_irq;
585 hwif->dma_host_on = &sgiioc4_dma_host_on;
586 hwif->dma_host_off = &sgiioc4_dma_host_off;
587 hwif->dma_lost_irq = &sgiioc4_dma_lost_irq;
588 hwif->dma_timeout = &ide_dma_timeout;
592 sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
594 unsigned long cmd_base, dma_base, irqport;
595 unsigned long bar0, cmd_phys_base, ctl;
596 void __iomem *virt_base;
599 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
602 * Find an empty HWIF; if none available, return -ENOMEM.
604 for (h = 0; h < MAX_HWIFS; ++h) {
605 hwif = &ide_hwifs[h];
606 if (hwif->chipset == ide_unknown)
609 if (h == MAX_HWIFS) {
610 printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n",
615 /* Get the CmdBlk and CtrlBlk Base Registers */
616 bar0 = pci_resource_start(dev, 0);
617 virt_base = ioremap(bar0, pci_resource_len(dev, 0));
618 if (virt_base == NULL) {
619 printk(KERN_ERR "%s: Unable to remap BAR 0 address: 0x%lx\n",
623 cmd_base = (unsigned long) virt_base + IOC4_CMD_OFFSET;
624 ctl = (unsigned long) virt_base + IOC4_CTRL_OFFSET;
625 irqport = (unsigned long) virt_base + IOC4_INTR_OFFSET;
626 dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
628 cmd_phys_base = bar0 + IOC4_CMD_OFFSET;
629 if (!request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE,
632 "%s : %s -- ERROR, Addresses "
633 "0x%p to 0x%p ALREADY in use\n",
634 __FUNCTION__, hwif->name, (void *) cmd_phys_base,
635 (void *) cmd_phys_base + IOC4_CMD_CTL_BLK_SIZE);
639 if (hwif->io_ports[IDE_DATA_OFFSET] != cmd_base) {
642 /* Initialize the IO registers */
643 memset(&hw, 0, sizeof(hw));
644 sgiioc4_init_hwif_ports(&hw, cmd_base, ctl, irqport);
645 memcpy(hwif->io_ports, hw.io_ports, sizeof(hwif->io_ports));
646 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
649 hwif->irq = dev->irq;
650 hwif->chipset = ide_pci;
652 hwif->channel = 0; /* Single Channel chip */
653 hwif->gendev.parent = &dev->dev;/* setup proper ancestral information */
655 /* The IOC4 uses MMIO rather than Port IO. */
656 default_hwif_mmiops(hwif);
658 /* Initializing chipset IRQ Registers */
659 writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
661 if (dma_base == 0 || ide_dma_sgiioc4(hwif, dma_base))
662 printk(KERN_INFO "%s: %s Bus-Master DMA disabled\n",
663 hwif->name, DRV_NAME);
665 ide_init_sgiioc4(hwif);
667 idx[0] = hwif->index;
669 if (ide_device_add(idx))
675 static unsigned int __devinit
676 pci_init_sgiioc4(struct pci_dev *dev)
680 printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
681 DRV_NAME, pci_name(dev), dev->revision);
683 if (dev->revision < IOC4_SUPPORTED_FIRMWARE_REV) {
684 printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
685 "firmware is obsolete - please upgrade to "
686 "revision46 or higher\n",
687 DRV_NAME, pci_name(dev));
691 ret = sgiioc4_ide_setup_pci_device(dev);
697 ioc4_ide_attach_one(struct ioc4_driver_data *idd)
699 /* PCI-RT does not bring out IDE connection.
700 * Do not attach to this particular IOC4.
702 if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
705 return pci_init_sgiioc4(idd->idd_pdev);
708 static struct ioc4_submodule ioc4_ide_submodule = {
709 .is_name = "IOC4_ide",
710 .is_owner = THIS_MODULE,
711 .is_probe = ioc4_ide_attach_one,
712 /* .is_remove = ioc4_ide_remove_one, */
715 static int __init ioc4_ide_init(void)
717 return ioc4_register_submodule(&ioc4_ide_submodule);
720 late_initcall(ioc4_ide_init); /* Call only after IDE init is done */
722 MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon");
723 MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card");
724 MODULE_LICENSE("GPL");