drivers/ide/pci/pdc202xx_old.c

   1 /*
   2  *  linux/drivers/ide/pci/pdc202xx_old.c        Version 0.36    Sept 11, 2002
   3  *
   4  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   5  *
   6  *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
   7  *  compiled into the kernel if you have more than one card installed.
   8  *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
   9  *  safe chipset tuning, including this support is harmless
  10  *
  11  *  Promise Ultra66 cards with BIOS v1.11 this
  12  *  compiled into the kernel if you have more than one card installed.
  13  *
  14  *  Promise Ultra100 cards.
  15  *
  16  *  The latest chipset code will support the following ::
  17  *  Three Ultra33 controllers and 12 drives.
  18  *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
  19  *  The 8/4 ratio is a BIOS code limit by promise.
  20  *
  21  *  UNLESS you enable "CONFIG_PDC202XX_BURST"
  22  *
  23  */
  24
  25 /*
  26  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  27  *  Author: Frank Tiernan (frankt@promise.com)
  28  *  Released under terms of General Public License
  29  */
  30
  31 #include <linux/config.h>
  32 #include <linux/types.h>
  33 #include <linux/module.h>
  34 #include <linux/kernel.h>
  35 #include <linux/delay.h>
  36 #include <linux/timer.h>
  37 #include <linux/mm.h>
  38 #include <linux/ioport.h>
  39 #include <linux/blkdev.h>
  40 #include <linux/hdreg.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/pci.h>
  43 #include <linux/init.h>
  44 #include <linux/ide.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/irq.h>
  48
  49 #define PDC202_DEBUG_CABLE              0
  50 #define PDC202XX_DEBUG_DRIVE_INFO       0
  51
  52 static const char *pdc_quirk_drives[] = {
  53         "QUANTUM FIREBALLlct08 08",
  54         "QUANTUM FIREBALLP KA6.4",
  55         "QUANTUM FIREBALLP KA9.1",
  56         "QUANTUM FIREBALLP LM20.4",
  57         "QUANTUM FIREBALLP KX13.6",
  58         "QUANTUM FIREBALLP KX20.5",
  59         "QUANTUM FIREBALLP KX27.3",
  60         "QUANTUM FIREBALLP LM20.5",
  61         NULL
  62 };
  63
  64 /* A Register */
  65 #define SYNC_ERRDY_EN   0xC0
  66
  67 #define SYNC_IN         0x80    /* control bit, different for master vs. slave drives */
  68 #define ERRDY_EN        0x40    /* control bit, different for master vs. slave drives */
  69 #define IORDY_EN        0x20    /* PIO: IOREADY */
  70 #define PREFETCH_EN     0x10    /* PIO: PREFETCH */
  71
  72 #define PA3             0x08    /* PIO"A" timing */
  73 #define PA2             0x04    /* PIO"A" timing */
  74 #define PA1             0x02    /* PIO"A" timing */
  75 #define PA0             0x01    /* PIO"A" timing */
  76
  77 /* B Register */
  78
  79 #define MB2             0x80    /* DMA"B" timing */
  80 #define MB1             0x40    /* DMA"B" timing */
  81 #define MB0             0x20    /* DMA"B" timing */
  82
  83 #define PB4             0x10    /* PIO_FORCE 1:0 */
  84
  85 #define PB3             0x08    /* PIO"B" timing */     /* PIO flow Control mode */
  86 #define PB2             0x04    /* PIO"B" timing */     /* PIO 4 */
  87 #define PB1             0x02    /* PIO"B" timing */     /* PIO 3 half */
  88 #define PB0             0x01    /* PIO"B" timing */     /* PIO 3 other half */
  89
  90 /* C Register */
  91 #define IORDYp_NO_SPEED 0x4F
  92 #define SPEED_DIS       0x0F
  93
  94 #define DMARQp          0x80
  95 #define IORDYp          0x40
  96 #define DMAR_EN         0x20
  97 #define DMAW_EN         0x10
  98
  99 #define MC3             0x08    /* DMA"C" timing */
 100 #define MC2             0x04    /* DMA"C" timing */
 101 #define MC1             0x02    /* DMA"C" timing */
 102 #define MC0             0x01    /* DMA"C" timing */
 103
 104 static u8 pdc202xx_ratemask (ide_drive_t *drive)
 105 {
 106         u8 mode;
 107
 108         switch(HWIF(drive)->pci_dev->device) {
 109                 case PCI_DEVICE_ID_PROMISE_20267:
 110                 case PCI_DEVICE_ID_PROMISE_20265:
 111                         mode = 3;
 112                         break;
 113                 case PCI_DEVICE_ID_PROMISE_20263:
 114                 case PCI_DEVICE_ID_PROMISE_20262:
 115                         mode = 2;
 116                         break;
 117                 case PCI_DEVICE_ID_PROMISE_20246:
 118                         return 1;
 119                 default:
 120                         return 0;
 121         }
 122         if (!eighty_ninty_three(drive))
 123                 mode = min(mode, (u8)1);
 124         return mode;
 125 }
 126
 127 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
 128 {
 129         struct hd_driveid *id = drive->id;
 130
 131         if (pdc_quirk_drives == list) {
 132                 while (*list) {
 133                         if (strstr(id->model, *list++)) {
 134                                 return 2;
 135                         }
 136                 }
 137         } else {
 138                 while (*list) {
 139                         if (!strcmp(*list++,id->model)) {
 140                                 return 1;
 141                         }
 142                 }
 143         }
 144         return 0;
 145 }
 146
 147 static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 148 {
 149         ide_hwif_t *hwif        = HWIF(drive);
 150         struct pci_dev *dev     = hwif->pci_dev;
 151         u8 drive_pci            = 0x60 + (drive->dn << 2);
 152         u8 speed        = ide_rate_filter(pdc202xx_ratemask(drive), xferspeed);
 153
 154         u32                     drive_conf;
 155         u8                      AP, BP, CP, DP;
 156         u8                      TA = 0, TB = 0, TC = 0;
 157
 158         if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0))
 159                 return -1;
 160
 161         pci_read_config_dword(dev, drive_pci, &drive_conf);
 162         pci_read_config_byte(dev, (drive_pci), &AP);
 163         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 164         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 165         pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
 166
 167         if (speed < XFER_SW_DMA_0) {
 168                 if ((AP & 0x0F) || (BP & 0x07)) {
 169                         /* clear PIO modes of lower 8421 bits of A Register */
 170                         pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
 171                         pci_read_config_byte(dev, (drive_pci), &AP);
 172
 173                         /* clear PIO modes of lower 421 bits of B Register */
 174                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
 175                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 176
 177                         pci_read_config_byte(dev, (drive_pci), &AP);
 178                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 179                 }
 180         } else {
 181                 if ((BP & 0xF0) && (CP & 0x0F)) {
 182                         /* clear DMA modes of upper 842 bits of B Register */
 183                         /* clear PIO forced mode upper 1 bit of B Register */
 184                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
 185                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 186
 187                         /* clear DMA modes of lower 8421 bits of C Register */
 188                         pci_write_config_byte(dev, (drive_pci)|0x02, CP &~0x0F);
 189                         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 190                 }
 191         }
 192
 193         pci_read_config_byte(dev, (drive_pci), &AP);
 194         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 195         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 196
 197         switch(speed) {
 198                 case XFER_UDMA_6:       speed = XFER_UDMA_5;
 199                 case XFER_UDMA_5:
 200                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
 201                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
 202                 case XFER_UDMA_3:
 203                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
 204                 case XFER_UDMA_0:
 205                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
 206                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
 207                 case XFER_MW_DMA_0:
 208                 case XFER_SW_DMA_2:     TB = 0x60; TC = 0x05; break;
 209                 case XFER_SW_DMA_1:     TB = 0x80; TC = 0x06; break;
 210                 case XFER_SW_DMA_0:     TB = 0xC0; TC = 0x0B; break;
 211                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
 212                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
 213                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
 214                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
 215                 case XFER_PIO_0:
 216                 default:                TA = 0x09; TB = 0x13; break;
 217         }
 218
 219         if (speed < XFER_SW_DMA_0) {
 220                 pci_write_config_byte(dev, (drive_pci), AP|TA);
 221                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 222         } else {
 223                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 224                 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
 225         }
 226
 227 #if PDC202XX_DEBUG_DRIVE_INFO
 228         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 229                 drive->name, ide_xfer_verbose(speed),
 230                 drive->dn, drive_conf);
 231                 pci_read_config_dword(dev, drive_pci, &drive_conf);
 232         printk("0x%08x\n", drive_conf);
 233 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
 234
 235         return (ide_config_drive_speed(drive, speed));
 236 }
 237
 238
 239 /*   0    1    2    3    4    5    6   7   8
 240  * 960, 480, 390, 300, 240, 180, 120, 90, 60
 241  *           180, 150, 120,  90,  60
 242  * DMA_Speed
 243  * 180, 120,  90,  90,  90,  60,  30
 244  *  11,   5,   4,   3,   2,   1,   0
 245  */
 246 static void config_chipset_for_pio (ide_drive_t *drive, u8 pio)
 247 {
 248         u8 speed = 0;
 249
 250         if (pio == 5) pio = 4;
 251         speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, pio, NULL);
 252
 253         pdc202xx_tune_chipset(drive, speed);
 254 }
 255
 256 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
 257 {
 258         u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
 259         pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
 260         return (CIS & mask) ? 1 : 0;
 261 }
 262
 263 /*
 264  * Set the control register to use the 66MHz system
 265  * clock for UDMA 3/4/5 mode operation when necessary.
 266  *
 267  * It may also be possible to leave the 66MHz clock on
 268  * and readjust the timing parameters.
 269  */
 270 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
 271 {
 272         unsigned long clock_reg = hwif->dma_master + 0x11;
 273         u8 clock = hwif->INB(clock_reg);
 274
 275         hwif->OUTB(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
 276 }
 277
 278 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
 279 {
 280         unsigned long clock_reg = hwif->dma_master + 0x11;
 281         u8 clock = hwif->INB(clock_reg);
 282
 283         hwif->OUTB(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
 284 }
 285
 286 static int config_chipset_for_dma (ide_drive_t *drive)
 287 {
 288         struct hd_driveid *id   = drive->id;
 289         ide_hwif_t *hwif        = HWIF(drive);
 290         struct pci_dev *dev     = hwif->pci_dev;
 291         u32 drive_conf          = 0;
 292         u8 drive_pci            = 0x60 + (drive->dn << 2);
 293         u8 test1 = 0, test2 = 0, speed = -1;
 294         u8 AP = 0, cable = 0;
 295
 296         u8 ultra_66             = ((id->dma_ultra & 0x0010) ||
 297                                    (id->dma_ultra & 0x0008)) ? 1 : 0;
 298
 299         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
 300                 cable = pdc202xx_old_cable_detect(hwif);
 301         else
 302                 ultra_66 = 0;
 303
 304         if (ultra_66 && cable) {
 305                 printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
 306                 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
 307         }
 308
 309         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
 310                 pdc_old_disable_66MHz_clock(drive->hwif);
 311
 312         drive_pci = 0x60 + (drive->dn << 2);
 313         pci_read_config_dword(dev, drive_pci, &drive_conf);
 314         if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
 315                 goto chipset_is_set;
 316
 317         pci_read_config_byte(dev, drive_pci, &test1);
 318         if (!(test1 & SYNC_ERRDY_EN)) {
 319                 if (drive->select.b.unit & 0x01) {
 320                         pci_read_config_byte(dev, drive_pci - 4, &test2);
 321                         if ((test2 & SYNC_ERRDY_EN) &&
 322                             !(test1 & SYNC_ERRDY_EN)) {
 323                                 pci_write_config_byte(dev, drive_pci,
 324                                         test1|SYNC_ERRDY_EN);
 325                         }
 326                 } else {
 327                         pci_write_config_byte(dev, drive_pci,
 328                                 test1|SYNC_ERRDY_EN);
 329                 }
 330         }
 331
 332 chipset_is_set:
 333
 334         if (drive->media == ide_disk) {
 335                 pci_read_config_byte(dev, (drive_pci), &AP);
 336                 if (id->capability & 4) /* IORDY_EN */
 337                         pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
 338                 pci_read_config_byte(dev, (drive_pci), &AP);
 339                 if (drive->media == ide_disk)   /* PREFETCH_EN */
 340                         pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
 341         }
 342
 343         speed = ide_dma_speed(drive, pdc202xx_ratemask(drive));
 344
 345         if (!(speed)) {
 346                 /* restore original pci-config space */
 347                 pci_write_config_dword(dev, drive_pci, drive_conf);
 348                 return 0;
 349         }
 350
 351         (void) hwif->speedproc(drive, speed);
 352         return ide_dma_enable(drive);
 353 }
 354
 355 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
 356 {
 357         ide_hwif_t *hwif        = HWIF(drive);
 358         struct hd_driveid *id   = drive->id;
 359
 360         drive->init_speed = 0;
 361
 362         if (id && (id->capability & 1) && drive->autodma) {
 363
 364                 if (ide_use_dma(drive)) {
 365                         if (config_chipset_for_dma(drive))
 366                                 return hwif->ide_dma_on(drive);
 367                 }
 368
 369                 goto fast_ata_pio;
 370
 371         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 372 fast_ata_pio:
 373                 hwif->tuneproc(drive, 5);
 374                 return hwif->ide_dma_off_quietly(drive);
 375         }
 376         /* IORDY not supported */
 377         return 0;
 378 }
 379
 380 static int pdc202xx_quirkproc (ide_drive_t *drive)
 381 {
 382         return ((int) check_in_drive_lists(drive, pdc_quirk_drives));
 383 }
 384
 385 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
 386 {
 387         if (drive->current_speed > XFER_UDMA_2)
 388                 pdc_old_enable_66MHz_clock(drive->hwif);
 389         if (drive->addressing == 1) {
 390                 struct request *rq      = HWGROUP(drive)->rq;
 391                 ide_hwif_t *hwif        = HWIF(drive);
 392                 unsigned long high_16   = hwif->dma_master;
 393                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 394                 u32 word_count  = 0;
 395                 u8 clock = hwif->INB(high_16 + 0x11);
 396
 397                 hwif->OUTB(clock|(hwif->channel ? 0x08 : 0x02), high_16+0x11);
 398                 word_count = (rq->nr_sectors << 8);
 399                 word_count = (rq_data_dir(rq) == READ) ?
 400                                         word_count | 0x05000000 :
 401                                         word_count | 0x06000000;
 402                 hwif->OUTL(word_count, atapi_reg);
 403         }
 404         ide_dma_start(drive);
 405 }
 406
 407 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
 408 {
 409         if (drive->addressing == 1) {
 410                 ide_hwif_t *hwif        = HWIF(drive);
 411                 unsigned long high_16   = hwif->dma_master;
 412                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 413                 u8 clock                = 0;
 414
 415                 hwif->OUTL(0, atapi_reg); /* zero out extra */
 416                 clock = hwif->INB(high_16 + 0x11);
 417                 hwif->OUTB(clock & ~(hwif->channel ? 0x08:0x02), high_16+0x11);
 418         }
 419         if (drive->current_speed > XFER_UDMA_2)
 420                 pdc_old_disable_66MHz_clock(drive->hwif);
 421         return __ide_dma_end(drive);
 422 }
 423
 424 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
 425 {
 426         ide_hwif_t *hwif        = HWIF(drive);
 427         unsigned long high_16   = hwif->dma_master;
 428         u8 dma_stat             = hwif->INB(hwif->dma_status);
 429         u8 sc1d                 = hwif->INB((high_16 + 0x001d));
 430
 431         if (hwif->channel) {
 432                 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
 433                 if ((sc1d & 0x50) == 0x50)
 434                         goto somebody_else;
 435                 else if ((sc1d & 0x40) == 0x40)
 436                         return (dma_stat & 4) == 4;
 437         } else {
 438                 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
 439                 if ((sc1d & 0x05) == 0x05)
 440                         goto somebody_else;
 441                 else if ((sc1d & 0x04) == 0x04)
 442                         return (dma_stat & 4) == 4;
 443         }
 444 somebody_else:
 445         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
 446 }
 447
 448 static int pdc202xx_ide_dma_lostirq(ide_drive_t *drive)
 449 {
 450         if (HWIF(drive)->resetproc != NULL)
 451                 HWIF(drive)->resetproc(drive);
 452         return __ide_dma_lostirq(drive);
 453 }
 454
 455 static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
 456 {
 457         if (HWIF(drive)->resetproc != NULL)
 458                 HWIF(drive)->resetproc(drive);
 459         return __ide_dma_timeout(drive);
 460 }
 461
 462 static void pdc202xx_reset_host (ide_hwif_t *hwif)
 463 {
 464         unsigned long high_16   = hwif->dma_master;
 465         u8 udma_speed_flag      = hwif->INB(high_16|0x001f);
 466
 467         hwif->OUTB((udma_speed_flag | 0x10), (high_16|0x001f));
 468         mdelay(100);
 469         hwif->OUTB((udma_speed_flag & ~0x10), (high_16|0x001f));
 470         mdelay(2000);   /* 2 seconds ?! */
 471
 472         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 473                 hwif->channel ? "Secondary" : "Primary");
 474 }
 475
 476 static void pdc202xx_reset (ide_drive_t *drive)
 477 {
 478         ide_hwif_t *hwif        = HWIF(drive);
 479         ide_hwif_t *mate        = hwif->mate;
 480
 481         pdc202xx_reset_host(hwif);
 482         pdc202xx_reset_host(mate);
 483         hwif->tuneproc(drive, 5);
 484 }
 485
 486 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
 487                                                         const char *name)
 488 {
 489         /* This doesn't appear needed */
 490         if (dev->resource[PCI_ROM_RESOURCE].start) {
 491                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
 492                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 493                 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
 494                         (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
 495         }
 496
 497         return dev->irq;
 498 }
 499
 500 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
 501 {
 502         struct pci_dev *dev = hwif->pci_dev;
 503
 504         /* PDC20265 has problems with large LBA48 requests */
 505         if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
 506             (dev->device == PCI_DEVICE_ID_PROMISE_20265))
 507                 hwif->rqsize = 256;
 508
 509         hwif->autodma = 0;
 510         hwif->tuneproc  = &config_chipset_for_pio;
 511         hwif->quirkproc = &pdc202xx_quirkproc;
 512
 513         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
 514                 hwif->resetproc = &pdc202xx_reset;
 515
 516         hwif->speedproc = &pdc202xx_tune_chipset;
 517
 518         hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
 519
 520         hwif->ultra_mask = 0x3f;
 521         hwif->mwdma_mask = 0x07;
 522         hwif->swdma_mask = 0x07;
 523
 524         hwif->err_stops_fifo = 1;
 525
 526         hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
 527         hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
 528         hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
 529
 530         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 531                 if (!(hwif->udma_four))
 532                         hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
 533                 hwif->dma_start = &pdc202xx_old_ide_dma_start;
 534                 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
 535         }
 536         hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
 537
 538         if (!noautodma)
 539                 hwif->autodma = 1;
 540         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
 541 #if PDC202_DEBUG_CABLE
 542         printk(KERN_DEBUG "%s: %s-pin cable\n",
 543                 hwif->name, hwif->udma_four ? "80" : "40");
 544 #endif /* PDC202_DEBUG_CABLE */
 545 }
 546
 547 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
 548 {
 549         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 550
 551         if (hwif->channel) {
 552                 ide_setup_dma(hwif, dmabase, 8);
 553                 return;
 554         }
 555
 556         udma_speed_flag = hwif->INB((dmabase|0x1f));
 557         primary_mode    = hwif->INB((dmabase|0x1a));
 558         secondary_mode  = hwif->INB((dmabase|0x1b));
 559         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 560                 "Primary %s Mode " \
 561                 "Secondary %s Mode.\n", hwif->cds->name,
 562                 (udma_speed_flag & 1) ? "EN" : "DIS",
 563                 (primary_mode & 1) ? "MASTER" : "PCI",
 564                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 565
 566 #ifdef CONFIG_PDC202XX_BURST
 567         if (!(udma_speed_flag & 1)) {
 568                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 569                         hwif->cds->name, udma_speed_flag,
 570                         (udma_speed_flag|1));
 571                 hwif->OUTB(udma_speed_flag|1,(dmabase|0x1f));
 572                 printk("%sACTIVE\n",
 573                         (hwif->INB(dmabase|0x1f)&1) ? "":"IN");
 574         }
 575 #endif /* CONFIG_PDC202XX_BURST */
 576 #ifdef CONFIG_PDC202XX_MASTER
 577         if (!(primary_mode & 1)) {
 578                 printk(KERN_INFO "%s: FORCING PRIMARY MODE BIT "
 579                         "0x%02x -> 0x%02x ", hwif->cds->name,
 580                         primary_mode, (primary_mode|1));
 581                 hwif->OUTB(primary_mode|1, (dmabase|0x1a));
 582                 printk("%s\n",
 583                         (hwif->INB((dmabase|0x1a)) & 1) ? "MASTER" : "PCI");
 584         }
 585
 586         if (!(secondary_mode & 1)) {
 587                 printk(KERN_INFO "%s: FORCING SECONDARY MODE BIT "
 588                         "0x%02x -> 0x%02x ", hwif->cds->name,
 589                         secondary_mode, (secondary_mode|1));
 590                 hwif->OUTB(secondary_mode|1, (dmabase|0x1b));
 591                 printk("%s\n",
 592                         (hwif->INB((dmabase|0x1b)) & 1) ? "MASTER" : "PCI");
 593         }
 594 #endif /* CONFIG_PDC202XX_MASTER */
 595
 596         ide_setup_dma(hwif, dmabase, 8);
 597 }
 598
 599 static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
 600                                            ide_pci_device_t *d)
 601 {
 602         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 603                 u8 irq = 0, irq2 = 0;
 604                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 605                 /* 0xbc */
 606                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 607                 if (irq != irq2) {
 608                         pci_write_config_byte(dev,
 609                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 610                         printk(KERN_INFO "%s: pci-config space interrupt "
 611                                 "mirror fixed.\n", d->name);
 612                 }
 613         }
 614         return ide_setup_pci_device(dev, d);
 615 }
 616
 617 static int __devinit init_setup_pdc20265(struct pci_dev *dev,
 618                                          ide_pci_device_t *d)
 619 {
 620         if ((dev->bus->self) &&
 621             (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
 622             ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
 623              (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
 624                 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
 625                         "attached to I2O RAID controller.\n");
 626                 return -ENODEV;
 627         }
 628         return ide_setup_pci_device(dev, d);
 629 }
 630
 631 static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
 632                                          ide_pci_device_t *d)
 633 {
 634         return ide_setup_pci_device(dev, d);
 635 }
 636
 637 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
 638         {       /* 0 */
 639                 .name           = "PDC20246",
 640                 .init_setup     = init_setup_pdc202ata4,
 641                 .init_chipset   = init_chipset_pdc202xx,
 642                 .init_hwif      = init_hwif_pdc202xx,
 643                 .init_dma       = init_dma_pdc202xx,
 644                 .channels       = 2,
 645                 .autodma        = AUTODMA,
 646                 .bootable       = OFF_BOARD,
 647                 .extra          = 16,
 648         },{     /* 1 */
 649                 .name           = "PDC20262",
 650                 .init_setup     = init_setup_pdc202ata4,
 651                 .init_chipset   = init_chipset_pdc202xx,
 652                 .init_hwif      = init_hwif_pdc202xx,
 653                 .init_dma       = init_dma_pdc202xx,
 654                 .channels       = 2,
 655                 .autodma        = AUTODMA,
 656                 .bootable       = OFF_BOARD,
 657                 .extra          = 48,
 658         },{     /* 2 */
 659                 .name           = "PDC20263",
 660                 .init_setup     = init_setup_pdc202ata4,
 661                 .init_chipset   = init_chipset_pdc202xx,
 662                 .init_hwif      = init_hwif_pdc202xx,
 663                 .init_dma       = init_dma_pdc202xx,
 664                 .channels       = 2,
 665                 .autodma        = AUTODMA,
 666                 .bootable       = OFF_BOARD,
 667                 .extra          = 48,
 668         },{     /* 3 */
 669                 .name           = "PDC20265",
 670                 .init_setup     = init_setup_pdc20265,
 671                 .init_chipset   = init_chipset_pdc202xx,
 672                 .init_hwif      = init_hwif_pdc202xx,
 673                 .init_dma       = init_dma_pdc202xx,
 674                 .channels       = 2,
 675                 .autodma        = AUTODMA,
 676                 .bootable       = OFF_BOARD,
 677                 .extra          = 48,
 678         },{     /* 4 */
 679                 .name           = "PDC20267",
 680                 .init_setup     = init_setup_pdc202xx,
 681                 .init_chipset   = init_chipset_pdc202xx,
 682                 .init_hwif      = init_hwif_pdc202xx,
 683                 .init_dma       = init_dma_pdc202xx,
 684                 .channels       = 2,
 685                 .autodma        = AUTODMA,
 686                 .bootable       = OFF_BOARD,
 687                 .extra          = 48,
 688         }
 689 };
 690
 691 /**
 692  *      pdc202xx_init_one       -       called when a PDC202xx is found
 693  *      @dev: the pdc202xx device
 694  *      @id: the matching pci id
 695  *
 696  *      Called when the PCI registration layer (or the IDE initialization)
 697  *      finds a device matching our IDE device tables.
 698  */
 699
 700 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 701 {
 702         ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
 703
 704         return d->init_setup(dev, d);
 705 }
 706
 707 static struct pci_device_id pdc202xx_pci_tbl[] = {
 708         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 709         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 710         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 711         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 712         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 713         { 0, },
 714 };
 715 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
 716
 717 static struct pci_driver driver = {
 718         .name           = "Promise_Old_IDE",
 719         .id_table       = pdc202xx_pci_tbl,
 720         .probe          = pdc202xx_init_one,
 721 };
 722
 723 static int pdc202xx_ide_init(void)
 724 {
 725         return ide_pci_register_driver(&driver);
 726 }
 727
 728 module_init(pdc202xx_ide_init);
 729
 730 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 731 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 732 MODULE_LICENSE("GPL");