drivers/ide/pci/pdc202xx_old.c

   1 /*
   2  *  linux/drivers/ide/pci/pdc202xx_old.c        Version 0.36    Sept 11, 2002
   3  *
   4  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   5  *  Copyright (C) 2006-2007             MontaVista Software, Inc.
   6  *
   7  *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
   8  *  compiled into the kernel if you have more than one card installed.
   9  *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
  10  *  safe chipset tuning, including this support is harmless
  11  *
  12  *  Promise Ultra66 cards with BIOS v1.11 this
  13  *  compiled into the kernel if you have more than one card installed.
  14  *
  15  *  Promise Ultra100 cards.
  16  *
  17  *  The latest chipset code will support the following ::
  18  *  Three Ultra33 controllers and 12 drives.
  19  *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
  20  *  The 8/4 ratio is a BIOS code limit by promise.
  21  *
  22  *  UNLESS you enable "CONFIG_PDC202XX_BURST"
  23  *
  24  */
  25
  26 /*
  27  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  28  *  Author: Frank Tiernan (frankt@promise.com)
  29  *  Released under terms of General Public License
  30  */
  31
  32 #include <linux/types.h>
  33 #include <linux/module.h>
  34 #include <linux/kernel.h>
  35 #include <linux/delay.h>
  36 #include <linux/timer.h>
  37 #include <linux/mm.h>
  38 #include <linux/ioport.h>
  39 #include <linux/blkdev.h>
  40 #include <linux/hdreg.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/pci.h>
  43 #include <linux/init.h>
  44 #include <linux/ide.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/irq.h>
  48
  49 #define PDC202_DEBUG_CABLE              0
  50 #define PDC202XX_DEBUG_DRIVE_INFO       0
  51
  52 static const char *pdc_quirk_drives[] = {
  53         "QUANTUM FIREBALLlct08 08",
  54         "QUANTUM FIREBALLP KA6.4",
  55         "QUANTUM FIREBALLP KA9.1",
  56         "QUANTUM FIREBALLP LM20.4",
  57         "QUANTUM FIREBALLP KX13.6",
  58         "QUANTUM FIREBALLP KX20.5",
  59         "QUANTUM FIREBALLP KX27.3",
  60         "QUANTUM FIREBALLP LM20.5",
  61         NULL
  62 };
  63
  64 /* A Register */
  65 #define SYNC_ERRDY_EN   0xC0
  66
  67 #define SYNC_IN         0x80    /* control bit, different for master vs. slave drives */
  68 #define ERRDY_EN        0x40    /* control bit, different for master vs. slave drives */
  69 #define IORDY_EN        0x20    /* PIO: IOREADY */
  70 #define PREFETCH_EN     0x10    /* PIO: PREFETCH */
  71
  72 #define PA3             0x08    /* PIO"A" timing */
  73 #define PA2             0x04    /* PIO"A" timing */
  74 #define PA1             0x02    /* PIO"A" timing */
  75 #define PA0             0x01    /* PIO"A" timing */
  76
  77 /* B Register */
  78
  79 #define MB2             0x80    /* DMA"B" timing */
  80 #define MB1             0x40    /* DMA"B" timing */
  81 #define MB0             0x20    /* DMA"B" timing */
  82
  83 #define PB4             0x10    /* PIO_FORCE 1:0 */
  84
  85 #define PB3             0x08    /* PIO"B" timing */     /* PIO flow Control mode */
  86 #define PB2             0x04    /* PIO"B" timing */     /* PIO 4 */
  87 #define PB1             0x02    /* PIO"B" timing */     /* PIO 3 half */
  88 #define PB0             0x01    /* PIO"B" timing */     /* PIO 3 other half */
  89
  90 /* C Register */
  91 #define IORDYp_NO_SPEED 0x4F
  92 #define SPEED_DIS       0x0F
  93
  94 #define DMARQp          0x80
  95 #define IORDYp          0x40
  96 #define DMAR_EN         0x20
  97 #define DMAW_EN         0x10
  98
  99 #define MC3             0x08    /* DMA"C" timing */
 100 #define MC2             0x04    /* DMA"C" timing */
 101 #define MC1             0x02    /* DMA"C" timing */
 102 #define MC0             0x01    /* DMA"C" timing */
 103
 104 static u8 pdc202xx_ratemask (ide_drive_t *drive)
 105 {
 106         u8 mode;
 107
 108         switch(HWIF(drive)->pci_dev->device) {
 109                 case PCI_DEVICE_ID_PROMISE_20267:
 110                 case PCI_DEVICE_ID_PROMISE_20265:
 111                         mode = 3;
 112                         break;
 113                 case PCI_DEVICE_ID_PROMISE_20263:
 114                 case PCI_DEVICE_ID_PROMISE_20262:
 115                         mode = 2;
 116                         break;
 117                 case PCI_DEVICE_ID_PROMISE_20246:
 118                         return 1;
 119                 default:
 120                         return 0;
 121         }
 122         if (!eighty_ninty_three(drive))
 123                 mode = min(mode, (u8)1);
 124         return mode;
 125 }
 126
 127 static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 128 {
 129         ide_hwif_t *hwif        = HWIF(drive);
 130         struct pci_dev *dev     = hwif->pci_dev;
 131         u8 drive_pci            = 0x60 + (drive->dn << 2);
 132         u8 speed        = ide_rate_filter(pdc202xx_ratemask(drive), xferspeed);
 133
 134         u32                     drive_conf;
 135         u8                      AP, BP, CP, DP;
 136         u8                      TA = 0, TB = 0, TC = 0;
 137
 138         if (drive->media != ide_disk &&
 139                 drive->media != ide_cdrom && speed < XFER_SW_DMA_0)
 140                 return -1;
 141
 142         pci_read_config_dword(dev, drive_pci, &drive_conf);
 143         pci_read_config_byte(dev, (drive_pci), &AP);
 144         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 145         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 146         pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
 147
 148         if (speed < XFER_SW_DMA_0) {
 149                 if ((AP & 0x0F) || (BP & 0x07)) {
 150                         /* clear PIO modes of lower 8421 bits of A Register */
 151                         pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
 152                         pci_read_config_byte(dev, (drive_pci), &AP);
 153
 154                         /* clear PIO modes of lower 421 bits of B Register */
 155                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
 156                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 157
 158                         pci_read_config_byte(dev, (drive_pci), &AP);
 159                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 160                 }
 161         } else {
 162                 if ((BP & 0xF0) && (CP & 0x0F)) {
 163                         /* clear DMA modes of upper 842 bits of B Register */
 164                         /* clear PIO forced mode upper 1 bit of B Register */
 165                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
 166                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 167
 168                         /* clear DMA modes of lower 8421 bits of C Register */
 169                         pci_write_config_byte(dev, (drive_pci)|0x02, CP &~0x0F);
 170                         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 171                 }
 172         }
 173
 174         pci_read_config_byte(dev, (drive_pci), &AP);
 175         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 176         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 177
 178         switch(speed) {
 179                 case XFER_UDMA_6:       speed = XFER_UDMA_5;
 180                 case XFER_UDMA_5:
 181                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
 182                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
 183                 case XFER_UDMA_3:
 184                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
 185                 case XFER_UDMA_0:
 186                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
 187                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
 188                 case XFER_MW_DMA_0:
 189                 case XFER_SW_DMA_2:     TB = 0x60; TC = 0x05; break;
 190                 case XFER_SW_DMA_1:     TB = 0x80; TC = 0x06; break;
 191                 case XFER_SW_DMA_0:     TB = 0xC0; TC = 0x0B; break;
 192                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
 193                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
 194                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
 195                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
 196                 case XFER_PIO_0:
 197                 default:                TA = 0x09; TB = 0x13; break;
 198         }
 199
 200         if (speed < XFER_SW_DMA_0) {
 201                 pci_write_config_byte(dev, (drive_pci), AP|TA);
 202                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 203         } else {
 204                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 205                 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
 206         }
 207
 208 #if PDC202XX_DEBUG_DRIVE_INFO
 209         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 210                 drive->name, ide_xfer_verbose(speed),
 211                 drive->dn, drive_conf);
 212                 pci_read_config_dword(dev, drive_pci, &drive_conf);
 213         printk("0x%08x\n", drive_conf);
 214 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
 215
 216         return (ide_config_drive_speed(drive, speed));
 217 }
 218
 219
 220 static void pdc202xx_tune_drive(ide_drive_t *drive, u8 pio)
 221 {
 222         pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
 223         pdc202xx_tune_chipset(drive, XFER_PIO_0 + pio);
 224 }
 225
 226 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
 227 {
 228         u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
 229         pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
 230         return (CIS & mask) ? 1 : 0;
 231 }
 232
 233 /*
 234  * Set the control register to use the 66MHz system
 235  * clock for UDMA 3/4/5 mode operation when necessary.
 236  *
 237  * It may also be possible to leave the 66MHz clock on
 238  * and readjust the timing parameters.
 239  */
 240 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
 241 {
 242         unsigned long clock_reg = hwif->dma_master + 0x11;
 243         u8 clock = hwif->INB(clock_reg);
 244
 245         hwif->OUTB(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
 246 }
 247
 248 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
 249 {
 250         unsigned long clock_reg = hwif->dma_master + 0x11;
 251         u8 clock = hwif->INB(clock_reg);
 252
 253         hwif->OUTB(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
 254 }
 255
 256 static int config_chipset_for_dma (ide_drive_t *drive)
 257 {
 258         struct hd_driveid *id   = drive->id;
 259         ide_hwif_t *hwif        = HWIF(drive);
 260         struct pci_dev *dev     = hwif->pci_dev;
 261         u32 drive_conf          = 0;
 262         u8 drive_pci            = 0x60 + (drive->dn << 2);
 263         u8 test1 = 0, test2 = 0, speed = -1;
 264         u8 AP = 0, cable = 0;
 265
 266         u8 ultra_66             = ((id->dma_ultra & 0x0010) ||
 267                                    (id->dma_ultra & 0x0008)) ? 1 : 0;
 268
 269         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
 270                 cable = pdc202xx_old_cable_detect(hwif);
 271         else
 272                 ultra_66 = 0;
 273
 274         if (ultra_66 && cable) {
 275                 printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
 276                 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
 277         }
 278
 279         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
 280                 pdc_old_disable_66MHz_clock(drive->hwif);
 281
 282         drive_pci = 0x60 + (drive->dn << 2);
 283         pci_read_config_dword(dev, drive_pci, &drive_conf);
 284         if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
 285                 goto chipset_is_set;
 286
 287         pci_read_config_byte(dev, drive_pci, &test1);
 288         if (!(test1 & SYNC_ERRDY_EN)) {
 289                 if (drive->select.b.unit & 0x01) {
 290                         pci_read_config_byte(dev, drive_pci - 4, &test2);
 291                         if ((test2 & SYNC_ERRDY_EN) &&
 292                             !(test1 & SYNC_ERRDY_EN)) {
 293                                 pci_write_config_byte(dev, drive_pci,
 294                                         test1|SYNC_ERRDY_EN);
 295                         }
 296                 } else {
 297                         pci_write_config_byte(dev, drive_pci,
 298                                 test1|SYNC_ERRDY_EN);
 299                 }
 300         }
 301
 302 chipset_is_set:
 303
 304         pci_read_config_byte(dev, (drive_pci), &AP);
 305         if (id->capability & 4) /* IORDY_EN */
 306                 pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
 307         pci_read_config_byte(dev, (drive_pci), &AP);
 308         if (drive->media == ide_disk)   /* PREFETCH_EN */
 309                 pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
 310
 311         speed = ide_dma_speed(drive, pdc202xx_ratemask(drive));
 312
 313         if (!(speed)) {
 314                 /* restore original pci-config space */
 315                 pci_write_config_dword(dev, drive_pci, drive_conf);
 316                 return 0;
 317         }
 318
 319         (void) hwif->speedproc(drive, speed);
 320         return ide_dma_enable(drive);
 321 }
 322
 323 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
 324 {
 325         ide_hwif_t *hwif        = HWIF(drive);
 326         struct hd_driveid *id   = drive->id;
 327
 328         drive->init_speed = 0;
 329
 330         if (id && (id->capability & 1) && drive->autodma) {
 331
 332                 if (ide_use_dma(drive)) {
 333                         if (config_chipset_for_dma(drive))
 334                                 return hwif->ide_dma_on(drive);
 335                 }
 336
 337                 goto fast_ata_pio;
 338
 339         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 340 fast_ata_pio:
 341                 pdc202xx_tune_drive(drive, 255);
 342                 return hwif->ide_dma_off_quietly(drive);
 343         }
 344         /* IORDY not supported */
 345         return 0;
 346 }
 347
 348 static int pdc202xx_quirkproc (ide_drive_t *drive)
 349 {
 350         const char **list, *model = drive->id->model;
 351
 352         for (list = pdc_quirk_drives; *list != NULL; list++)
 353                 if (strstr(model, *list) != NULL)
 354                         return 2;
 355         return 0;
 356 }
 357
 358 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
 359 {
 360         if (drive->current_speed > XFER_UDMA_2)
 361                 pdc_old_enable_66MHz_clock(drive->hwif);
 362         if (drive->media != ide_disk || drive->addressing == 1) {
 363                 struct request *rq      = HWGROUP(drive)->rq;
 364                 ide_hwif_t *hwif        = HWIF(drive);
 365                 unsigned long high_16   = hwif->dma_master;
 366                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 367                 u32 word_count  = 0;
 368                 u8 clock = hwif->INB(high_16 + 0x11);
 369
 370                 hwif->OUTB(clock|(hwif->channel ? 0x08 : 0x02), high_16+0x11);
 371                 word_count = (rq->nr_sectors << 8);
 372                 word_count = (rq_data_dir(rq) == READ) ?
 373                                         word_count | 0x05000000 :
 374                                         word_count | 0x06000000;
 375                 hwif->OUTL(word_count, atapi_reg);
 376         }
 377         ide_dma_start(drive);
 378 }
 379
 380 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
 381 {
 382         if (drive->media != ide_disk || drive->addressing == 1) {
 383                 ide_hwif_t *hwif        = HWIF(drive);
 384                 unsigned long high_16   = hwif->dma_master;
 385                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 386                 u8 clock                = 0;
 387
 388                 hwif->OUTL(0, atapi_reg); /* zero out extra */
 389                 clock = hwif->INB(high_16 + 0x11);
 390                 hwif->OUTB(clock & ~(hwif->channel ? 0x08:0x02), high_16+0x11);
 391         }
 392         if (drive->current_speed > XFER_UDMA_2)
 393                 pdc_old_disable_66MHz_clock(drive->hwif);
 394         return __ide_dma_end(drive);
 395 }
 396
 397 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
 398 {
 399         ide_hwif_t *hwif        = HWIF(drive);
 400         unsigned long high_16   = hwif->dma_master;
 401         u8 dma_stat             = hwif->INB(hwif->dma_status);
 402         u8 sc1d                 = hwif->INB((high_16 + 0x001d));
 403
 404         if (hwif->channel) {
 405                 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
 406                 if ((sc1d & 0x50) == 0x50)
 407                         goto somebody_else;
 408                 else if ((sc1d & 0x40) == 0x40)
 409                         return (dma_stat & 4) == 4;
 410         } else {
 411                 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
 412                 if ((sc1d & 0x05) == 0x05)
 413                         goto somebody_else;
 414                 else if ((sc1d & 0x04) == 0x04)
 415                         return (dma_stat & 4) == 4;
 416         }
 417 somebody_else:
 418         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
 419 }
 420
 421 static int pdc202xx_ide_dma_lostirq(ide_drive_t *drive)
 422 {
 423         if (HWIF(drive)->resetproc != NULL)
 424                 HWIF(drive)->resetproc(drive);
 425         return __ide_dma_lostirq(drive);
 426 }
 427
 428 static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
 429 {
 430         if (HWIF(drive)->resetproc != NULL)
 431                 HWIF(drive)->resetproc(drive);
 432         return __ide_dma_timeout(drive);
 433 }
 434
 435 static void pdc202xx_reset_host (ide_hwif_t *hwif)
 436 {
 437         unsigned long high_16   = hwif->dma_master;
 438         u8 udma_speed_flag      = hwif->INB(high_16|0x001f);
 439
 440         hwif->OUTB((udma_speed_flag | 0x10), (high_16|0x001f));
 441         mdelay(100);
 442         hwif->OUTB((udma_speed_flag & ~0x10), (high_16|0x001f));
 443         mdelay(2000);   /* 2 seconds ?! */
 444
 445         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 446                 hwif->channel ? "Secondary" : "Primary");
 447 }
 448
 449 static void pdc202xx_reset (ide_drive_t *drive)
 450 {
 451         ide_hwif_t *hwif        = HWIF(drive);
 452         ide_hwif_t *mate        = hwif->mate;
 453
 454         pdc202xx_reset_host(hwif);
 455         pdc202xx_reset_host(mate);
 456         pdc202xx_tune_drive(drive, 255);
 457 }
 458
 459 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
 460                                                         const char *name)
 461 {
 462         /* This doesn't appear needed */
 463         if (dev->resource[PCI_ROM_RESOURCE].start) {
 464                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
 465                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 466                 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
 467                         (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
 468         }
 469
 470         return dev->irq;
 471 }
 472
 473 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
 474 {
 475         struct pci_dev *dev = hwif->pci_dev;
 476
 477         /* PDC20265 has problems with large LBA48 requests */
 478         if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
 479             (dev->device == PCI_DEVICE_ID_PROMISE_20265))
 480                 hwif->rqsize = 256;
 481
 482         hwif->autodma = 0;
 483         hwif->tuneproc  = &pdc202xx_tune_drive;
 484         hwif->quirkproc = &pdc202xx_quirkproc;
 485
 486         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
 487                 hwif->resetproc = &pdc202xx_reset;
 488
 489         hwif->speedproc = &pdc202xx_tune_chipset;
 490
 491         hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
 492
 493         hwif->ultra_mask = 0x3f;
 494         hwif->mwdma_mask = 0x07;
 495         hwif->swdma_mask = 0x07;
 496         hwif->atapi_dma = 1;
 497
 498         hwif->err_stops_fifo = 1;
 499
 500         hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
 501         hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
 502         hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
 503
 504         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 505                 if (!(hwif->udma_four))
 506                         hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
 507                 hwif->dma_start = &pdc202xx_old_ide_dma_start;
 508                 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
 509         }
 510         hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
 511
 512         if (!noautodma)
 513                 hwif->autodma = 1;
 514         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
 515 #if PDC202_DEBUG_CABLE
 516         printk(KERN_DEBUG "%s: %s-pin cable\n",
 517                 hwif->name, hwif->udma_four ? "80" : "40");
 518 #endif /* PDC202_DEBUG_CABLE */
 519 }
 520
 521 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
 522 {
 523         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 524
 525         if (hwif->channel) {
 526                 ide_setup_dma(hwif, dmabase, 8);
 527                 return;
 528         }
 529
 530         udma_speed_flag = hwif->INB((dmabase|0x1f));
 531         primary_mode    = hwif->INB((dmabase|0x1a));
 532         secondary_mode  = hwif->INB((dmabase|0x1b));
 533         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 534                 "Primary %s Mode " \
 535                 "Secondary %s Mode.\n", hwif->cds->name,
 536                 (udma_speed_flag & 1) ? "EN" : "DIS",
 537                 (primary_mode & 1) ? "MASTER" : "PCI",
 538                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 539
 540 #ifdef CONFIG_PDC202XX_BURST
 541         if (!(udma_speed_flag & 1)) {
 542                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 543                         hwif->cds->name, udma_speed_flag,
 544                         (udma_speed_flag|1));
 545                 hwif->OUTB(udma_speed_flag|1,(dmabase|0x1f));
 546                 printk("%sACTIVE\n",
 547                         (hwif->INB(dmabase|0x1f)&1) ? "":"IN");
 548         }
 549 #endif /* CONFIG_PDC202XX_BURST */
 550
 551         ide_setup_dma(hwif, dmabase, 8);
 552 }
 553
 554 static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
 555                                            ide_pci_device_t *d)
 556 {
 557         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 558                 u8 irq = 0, irq2 = 0;
 559                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 560                 /* 0xbc */
 561                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 562                 if (irq != irq2) {
 563                         pci_write_config_byte(dev,
 564                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 565                         printk(KERN_INFO "%s: pci-config space interrupt "
 566                                 "mirror fixed.\n", d->name);
 567                 }
 568         }
 569         return ide_setup_pci_device(dev, d);
 570 }
 571
 572 static int __devinit init_setup_pdc20265(struct pci_dev *dev,
 573                                          ide_pci_device_t *d)
 574 {
 575         if ((dev->bus->self) &&
 576             (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
 577             ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
 578              (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
 579                 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
 580                         "attached to I2O RAID controller.\n");
 581                 return -ENODEV;
 582         }
 583         return ide_setup_pci_device(dev, d);
 584 }
 585
 586 static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
 587                                          ide_pci_device_t *d)
 588 {
 589         return ide_setup_pci_device(dev, d);
 590 }
 591
 592 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
 593         {       /* 0 */
 594                 .name           = "PDC20246",
 595                 .init_setup     = init_setup_pdc202ata4,
 596                 .init_chipset   = init_chipset_pdc202xx,
 597                 .init_hwif      = init_hwif_pdc202xx,
 598                 .init_dma       = init_dma_pdc202xx,
 599                 .channels       = 2,
 600                 .autodma        = AUTODMA,
 601                 .bootable       = OFF_BOARD,
 602                 .extra          = 16,
 603         },{     /* 1 */
 604                 .name           = "PDC20262",
 605                 .init_setup     = init_setup_pdc202ata4,
 606                 .init_chipset   = init_chipset_pdc202xx,
 607                 .init_hwif      = init_hwif_pdc202xx,
 608                 .init_dma       = init_dma_pdc202xx,
 609                 .channels       = 2,
 610                 .autodma        = AUTODMA,
 611                 .bootable       = OFF_BOARD,
 612                 .extra          = 48,
 613         },{     /* 2 */
 614                 .name           = "PDC20263",
 615                 .init_setup     = init_setup_pdc202ata4,
 616                 .init_chipset   = init_chipset_pdc202xx,
 617                 .init_hwif      = init_hwif_pdc202xx,
 618                 .init_dma       = init_dma_pdc202xx,
 619                 .channels       = 2,
 620                 .autodma        = AUTODMA,
 621                 .bootable       = OFF_BOARD,
 622                 .extra          = 48,
 623         },{     /* 3 */
 624                 .name           = "PDC20265",
 625                 .init_setup     = init_setup_pdc20265,
 626                 .init_chipset   = init_chipset_pdc202xx,
 627                 .init_hwif      = init_hwif_pdc202xx,
 628                 .init_dma       = init_dma_pdc202xx,
 629                 .channels       = 2,
 630                 .autodma        = AUTODMA,
 631                 .bootable       = OFF_BOARD,
 632                 .extra          = 48,
 633         },{     /* 4 */
 634                 .name           = "PDC20267",
 635                 .init_setup     = init_setup_pdc202xx,
 636                 .init_chipset   = init_chipset_pdc202xx,
 637                 .init_hwif      = init_hwif_pdc202xx,
 638                 .init_dma       = init_dma_pdc202xx,
 639                 .channels       = 2,
 640                 .autodma        = AUTODMA,
 641                 .bootable       = OFF_BOARD,
 642                 .extra          = 48,
 643         }
 644 };
 645
 646 /**
 647  *      pdc202xx_init_one       -       called when a PDC202xx is found
 648  *      @dev: the pdc202xx device
 649  *      @id: the matching pci id
 650  *
 651  *      Called when the PCI registration layer (or the IDE initialization)
 652  *      finds a device matching our IDE device tables.
 653  */
 654
 655 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 656 {
 657         ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
 658
 659         return d->init_setup(dev, d);
 660 }
 661
 662 static struct pci_device_id pdc202xx_pci_tbl[] = {
 663         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 664         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 665         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 666         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 667         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 668         { 0, },
 669 };
 670 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
 671
 672 static struct pci_driver driver = {
 673         .name           = "Promise_Old_IDE",
 674         .id_table       = pdc202xx_pci_tbl,
 675         .probe          = pdc202xx_init_one,
 676 };
 677
 678 static int __init pdc202xx_ide_init(void)
 679 {
 680         return ide_pci_register_driver(&driver);
 681 }
 682
 683 module_init(pdc202xx_ide_init);
 684
 685 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 686 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 687 MODULE_LICENSE("GPL");