drivers/i2c/busses/i2c-tegra.c

   1 /*
   2  * drivers/i2c/busses/i2c-tegra.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Colin Cross <ccross@android.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/err.h>
  23 #include <linux/i2c.h>
  24 #include <linux/io.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/i2c-tegra.h>
  29 #include <linux/of_i2c.h>
  30
  31 #include <asm/unaligned.h>
  32
  33 #include <mach/clk.h>
  34
  35 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
  36 #define BYTES_PER_FIFO_WORD 4
  37
  38 #define I2C_CNFG                                0x000
  39 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
  40 #define I2C_CNFG_PACKET_MODE_EN                 (1<<10)
  41 #define I2C_CNFG_NEW_MASTER_FSM                 (1<<11)
  42 #define I2C_STATUS                              0x01C
  43 #define I2C_SL_CNFG                             0x020
  44 #define I2C_SL_CNFG_NACK                        (1<<1)
  45 #define I2C_SL_CNFG_NEWSL                       (1<<2)
  46 #define I2C_SL_ADDR1                            0x02c
  47 #define I2C_SL_ADDR2                            0x030
  48 #define I2C_TX_FIFO                             0x050
  49 #define I2C_RX_FIFO                             0x054
  50 #define I2C_PACKET_TRANSFER_STATUS              0x058
  51 #define I2C_FIFO_CONTROL                        0x05c
  52 #define I2C_FIFO_CONTROL_TX_FLUSH               (1<<1)
  53 #define I2C_FIFO_CONTROL_RX_FLUSH               (1<<0)
  54 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
  55 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
  56 #define I2C_FIFO_STATUS                         0x060
  57 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
  58 #define I2C_FIFO_STATUS_TX_SHIFT                4
  59 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
  60 #define I2C_FIFO_STATUS_RX_SHIFT                0
  61 #define I2C_INT_MASK                            0x064
  62 #define I2C_INT_STATUS                          0x068
  63 #define I2C_INT_PACKET_XFER_COMPLETE            (1<<7)
  64 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       (1<<6)
  65 #define I2C_INT_TX_FIFO_OVERFLOW                (1<<5)
  66 #define I2C_INT_RX_FIFO_UNDERFLOW               (1<<4)
  67 #define I2C_INT_NO_ACK                          (1<<3)
  68 #define I2C_INT_ARBITRATION_LOST                (1<<2)
  69 #define I2C_INT_TX_FIFO_DATA_REQ                (1<<1)
  70 #define I2C_INT_RX_FIFO_DATA_REQ                (1<<0)
  71 #define I2C_CLK_DIVISOR                         0x06c
  72
  73 #define DVC_CTRL_REG1                           0x000
  74 #define DVC_CTRL_REG1_INTR_EN                   (1<<10)
  75 #define DVC_CTRL_REG2                           0x004
  76 #define DVC_CTRL_REG3                           0x008
  77 #define DVC_CTRL_REG3_SW_PROG                   (1<<26)
  78 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          (1<<30)
  79 #define DVC_STATUS                              0x00c
  80 #define DVC_STATUS_I2C_DONE_INTR                (1<<30)
  81
  82 #define I2C_ERR_NONE                            0x00
  83 #define I2C_ERR_NO_ACK                          0x01
  84 #define I2C_ERR_ARBITRATION_LOST                0x02
  85 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
  86
  87 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
  88 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
  89 #define PACKET_HEADER0_CONT_ID_SHIFT            12
  90 #define PACKET_HEADER0_PROTOCOL_I2C             (1<<4)
  91
  92 #define I2C_HEADER_HIGHSPEED_MODE               (1<<22)
  93 #define I2C_HEADER_CONT_ON_NAK                  (1<<21)
  94 #define I2C_HEADER_SEND_START_BYTE              (1<<20)
  95 #define I2C_HEADER_READ                         (1<<19)
  96 #define I2C_HEADER_10BIT_ADDR                   (1<<18)
  97 #define I2C_HEADER_IE_ENABLE                    (1<<17)
  98 #define I2C_HEADER_REPEAT_START                 (1<<16)
  99 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
 100 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
 101
 102 /**
 103  * struct tegra_i2c_dev - per device i2c context
 104  * @dev: device reference for power management
 105  * @adapter: core i2c layer adapter information
 106  * @clk: clock reference for i2c controller
 107  * @i2c_clk: clock reference for i2c bus
 108  * @iomem: memory resource for registers
 109  * @base: ioremapped registers cookie
 110  * @cont_id: i2c controller id, used for for packet header
 111  * @irq: irq number of transfer complete interrupt
 112  * @is_dvc: identifies the DVC i2c controller, has a different register layout
 113  * @msg_complete: transfer completion notifier
 114  * @msg_err: error code for completed message
 115  * @msg_buf: pointer to current message data
 116  * @msg_buf_remaining: size of unsent data in the message buffer
 117  * @msg_read: identifies read transfers
 118  * @bus_clk_rate: current i2c bus clock rate
 119  * @is_suspended: prevents i2c controller accesses after suspend is called
 120  */
 121 struct tegra_i2c_dev {
 122         struct device *dev;
 123         struct i2c_adapter adapter;
 124         struct clk *clk;
 125         struct clk *i2c_clk;
 126         struct resource *iomem;
 127         void __iomem *base;
 128         int cont_id;
 129         int irq;
 130         bool irq_disabled;
 131         int is_dvc;
 132         struct completion msg_complete;
 133         int msg_err;
 134         u8 *msg_buf;
 135         size_t msg_buf_remaining;
 136         int msg_read;
 137         unsigned long bus_clk_rate;
 138         bool is_suspended;
 139 };
 140
 141 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
 142 {
 143         writel(val, i2c_dev->base + reg);
 144 }
 145
 146 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 147 {
 148         return readl(i2c_dev->base + reg);
 149 }
 150
 151 /*
 152  * i2c_writel and i2c_readl will offset the register if necessary to talk
 153  * to the I2C block inside the DVC block
 154  */
 155 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
 156         unsigned long reg)
 157 {
 158         if (i2c_dev->is_dvc)
 159                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 160         return reg;
 161 }
 162
 163 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 164         unsigned long reg)
 165 {
 166         writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 167 }
 168
 169 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 170 {
 171         return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 172 }
 173
 174 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 175         unsigned long reg, int len)
 176 {
 177         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 178 }
 179
 180 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 181         unsigned long reg, int len)
 182 {
 183         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 184 }
 185
 186 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 187 {
 188         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 189         int_mask &= ~mask;
 190         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 191 }
 192
 193 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 194 {
 195         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 196         int_mask |= mask;
 197         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 198 }
 199
 200 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 201 {
 202         unsigned long timeout = jiffies + HZ;
 203         u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
 204         val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
 205         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 206
 207         while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
 208                 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
 209                 if (time_after(jiffies, timeout)) {
 210                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 211                         return -ETIMEDOUT;
 212                 }
 213                 msleep(1);
 214         }
 215         return 0;
 216 }
 217
 218 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 219 {
 220         u32 val;
 221         int rx_fifo_avail;
 222         u8 *buf = i2c_dev->msg_buf;
 223         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 224         int words_to_transfer;
 225
 226         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 227         rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
 228                 I2C_FIFO_STATUS_RX_SHIFT;
 229
 230         /* Rounds down to not include partial word at the end of buf */
 231         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 232         if (words_to_transfer > rx_fifo_avail)
 233                 words_to_transfer = rx_fifo_avail;
 234
 235         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 236
 237         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 238         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 239         rx_fifo_avail -= words_to_transfer;
 240
 241         /*
 242          * If there is a partial word at the end of buf, handle it manually to
 243          * prevent overwriting past the end of buf
 244          */
 245         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 246                 BUG_ON(buf_remaining > 3);
 247                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 248                 memcpy(buf, &val, buf_remaining);
 249                 buf_remaining = 0;
 250                 rx_fifo_avail--;
 251         }
 252
 253         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
 254         i2c_dev->msg_buf_remaining = buf_remaining;
 255         i2c_dev->msg_buf = buf;
 256         return 0;
 257 }
 258
 259 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 260 {
 261         u32 val;
 262         int tx_fifo_avail;
 263         u8 *buf = i2c_dev->msg_buf;
 264         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 265         int words_to_transfer;
 266
 267         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 268         tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
 269                 I2C_FIFO_STATUS_TX_SHIFT;
 270
 271         /* Rounds down to not include partial word at the end of buf */
 272         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 273
 274         /* It's very common to have < 4 bytes, so optimize that case. */
 275         if (words_to_transfer) {
 276                 if (words_to_transfer > tx_fifo_avail)
 277                         words_to_transfer = tx_fifo_avail;
 278
 279                 /*
 280                  * Update state before writing to FIFO.  If this casues us
 281                  * to finish writing all bytes (AKA buf_remaining goes to 0) we
 282                  * have a potential for an interrupt (PACKET_XFER_COMPLETE is
 283                  * not maskable).  We need to make sure that the isr sees
 284                  * buf_remaining as 0 and doesn't call us back re-entrantly.
 285                  */
 286                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 287                 tx_fifo_avail -= words_to_transfer;
 288                 i2c_dev->msg_buf_remaining = buf_remaining;
 289                 i2c_dev->msg_buf = buf +
 290                         words_to_transfer * BYTES_PER_FIFO_WORD;
 291                 barrier();
 292
 293                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 294
 295                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 296         }
 297
 298         /*
 299          * If there is a partial word at the end of buf, handle it manually to
 300          * prevent reading past the end of buf, which could cross a page
 301          * boundary and fault.
 302          */
 303         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 304                 BUG_ON(buf_remaining > 3);
 305                 memcpy(&val, buf, buf_remaining);
 306
 307                 /* Again update before writing to FIFO to make sure isr sees. */
 308                 i2c_dev->msg_buf_remaining = 0;
 309                 i2c_dev->msg_buf = NULL;
 310                 barrier();
 311
 312                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 313         }
 314
 315         return 0;
 316 }
 317
 318 /*
 319  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 320  * block.  This block is identical to the rest of the I2C blocks, except that
 321  * it only supports master mode, it has registers moved around, and it needs
 322  * some extra init to get it into I2C mode.  The register moves are handled
 323  * by i2c_readl and i2c_writel
 324  */
 325 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 326 {
 327         u32 val = 0;
 328         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 329         val |= DVC_CTRL_REG3_SW_PROG;
 330         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 331         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 332
 333         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 334         val |= DVC_CTRL_REG1_INTR_EN;
 335         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 336 }
 337
 338 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 339 {
 340         u32 val;
 341         int err = 0;
 342
 343         clk_enable(i2c_dev->clk);
 344
 345         tegra_periph_reset_assert(i2c_dev->clk);
 346         udelay(2);
 347         tegra_periph_reset_deassert(i2c_dev->clk);
 348
 349         if (i2c_dev->is_dvc)
 350                 tegra_dvc_init(i2c_dev);
 351
 352         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 353                 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
 354         i2c_writel(i2c_dev, val, I2C_CNFG);
 355         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 356         clk_set_rate(i2c_dev->clk, i2c_dev->bus_clk_rate * 8);
 357
 358         if (!i2c_dev->is_dvc) {
 359                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 360                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 361                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 362                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 363                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 364
 365         }
 366
 367         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
 368                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
 369         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 370
 371         if (tegra_i2c_flush_fifos(i2c_dev))
 372                 err = -ETIMEDOUT;
 373
 374         clk_disable(i2c_dev->clk);
 375
 376         if (i2c_dev->irq_disabled) {
 377                 i2c_dev->irq_disabled = 0;
 378                 enable_irq(i2c_dev->irq);
 379         }
 380
 381         return err;
 382 }
 383
 384 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 385 {
 386         u32 status;
 387         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 388         struct tegra_i2c_dev *i2c_dev = dev_id;
 389
 390         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 391
 392         if (status == 0) {
 393                 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
 394                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 395                          i2c_readl(i2c_dev, I2C_STATUS),
 396                          i2c_readl(i2c_dev, I2C_CNFG));
 397                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 398
 399                 if (!i2c_dev->irq_disabled) {
 400                         disable_irq_nosync(i2c_dev->irq);
 401                         i2c_dev->irq_disabled = 1;
 402                 }
 403
 404                 complete(&i2c_dev->msg_complete);
 405                 goto err;
 406         }
 407
 408         if (unlikely(status & status_err)) {
 409                 if (status & I2C_INT_NO_ACK)
 410                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 411                 if (status & I2C_INT_ARBITRATION_LOST)
 412                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 413                 complete(&i2c_dev->msg_complete);
 414                 goto err;
 415         }
 416
 417         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 418                 if (i2c_dev->msg_buf_remaining)
 419                         tegra_i2c_empty_rx_fifo(i2c_dev);
 420                 else
 421                         BUG();
 422         }
 423
 424         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 425                 if (i2c_dev->msg_buf_remaining)
 426                         tegra_i2c_fill_tx_fifo(i2c_dev);
 427                 else
 428                         tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
 429         }
 430
 431         if (status & I2C_INT_PACKET_XFER_COMPLETE) {
 432                 BUG_ON(i2c_dev->msg_buf_remaining);
 433                 complete(&i2c_dev->msg_complete);
 434         }
 435
 436         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 437         if (i2c_dev->is_dvc)
 438                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 439         return IRQ_HANDLED;
 440 err:
 441         /* An error occurred, mask all interrupts */
 442         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 443                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 444                 I2C_INT_RX_FIFO_DATA_REQ);
 445         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 446         if (i2c_dev->is_dvc)
 447                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 448         return IRQ_HANDLED;
 449 }
 450
 451 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
 452         struct i2c_msg *msg, int stop)
 453 {
 454         u32 packet_header;
 455         u32 int_mask;
 456         int ret;
 457
 458         tegra_i2c_flush_fifos(i2c_dev);
 459         i2c_writel(i2c_dev, 0xFF, I2C_INT_STATUS);
 460
 461         if (msg->len == 0)
 462                 return -EINVAL;
 463
 464         i2c_dev->msg_buf = msg->buf;
 465         i2c_dev->msg_buf_remaining = msg->len;
 466         i2c_dev->msg_err = I2C_ERR_NONE;
 467         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
 468         INIT_COMPLETION(i2c_dev->msg_complete);
 469
 470         packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 471                         PACKET_HEADER0_PROTOCOL_I2C |
 472                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
 473                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
 474         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 475
 476         packet_header = msg->len - 1;
 477         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 478
 479         packet_header = msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
 480         packet_header |= I2C_HEADER_IE_ENABLE;
 481         if (!stop)
 482                 packet_header |= I2C_HEADER_REPEAT_START;
 483         if (msg->flags & I2C_M_TEN)
 484                 packet_header |= I2C_HEADER_10BIT_ADDR;
 485         if (msg->flags & I2C_M_IGNORE_NAK)
 486                 packet_header |= I2C_HEADER_CONT_ON_NAK;
 487         if (msg->flags & I2C_M_RD)
 488                 packet_header |= I2C_HEADER_READ;
 489         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 490
 491         if (!(msg->flags & I2C_M_RD))
 492                 tegra_i2c_fill_tx_fifo(i2c_dev);
 493
 494         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 495         if (msg->flags & I2C_M_RD)
 496                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
 497         else if (i2c_dev->msg_buf_remaining)
 498                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
 499         tegra_i2c_unmask_irq(i2c_dev, int_mask);
 500         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
 501                 i2c_readl(i2c_dev, I2C_INT_MASK));
 502
 503         ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
 504         tegra_i2c_mask_irq(i2c_dev, int_mask);
 505
 506         if (WARN_ON(ret == 0)) {
 507                 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
 508
 509                 tegra_i2c_init(i2c_dev);
 510                 return -ETIMEDOUT;
 511         }
 512
 513         dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
 514                 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
 515
 516         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
 517                 return 0;
 518
 519         tegra_i2c_init(i2c_dev);
 520         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
 521                 if (msg->flags & I2C_M_IGNORE_NAK)
 522                         return 0;
 523                 return -EREMOTEIO;
 524         }
 525
 526         return -EIO;
 527 }
 528
 529 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 530         int num)
 531 {
 532         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 533         int i;
 534         int ret = 0;
 535
 536         if (i2c_dev->is_suspended)
 537                 return -EBUSY;
 538
 539         clk_enable(i2c_dev->clk);
 540         for (i = 0; i < num; i++) {
 541                 int stop = (i == (num - 1)) ? 1  : 0;
 542                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], stop);
 543                 if (ret)
 544                         break;
 545         }
 546         clk_disable(i2c_dev->clk);
 547         return ret ?: i;
 548 }
 549
 550 static u32 tegra_i2c_func(struct i2c_adapter *adap)
 551 {
 552         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 553 }
 554
 555 static const struct i2c_algorithm tegra_i2c_algo = {
 556         .master_xfer    = tegra_i2c_xfer,
 557         .functionality  = tegra_i2c_func,
 558 };
 559
 560 static int tegra_i2c_probe(struct platform_device *pdev)
 561 {
 562         struct tegra_i2c_dev *i2c_dev;
 563         struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
 564         struct resource *res;
 565         struct resource *iomem;
 566         struct clk *clk;
 567         struct clk *i2c_clk;
 568         const unsigned int *prop;
 569         void *base;
 570         int irq;
 571         int ret = 0;
 572
 573         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 574         if (!res) {
 575                 dev_err(&pdev->dev, "no mem resource\n");
 576                 return -EINVAL;
 577         }
 578         iomem = request_mem_region(res->start, resource_size(res), pdev->name);
 579         if (!iomem) {
 580                 dev_err(&pdev->dev, "I2C region already claimed\n");
 581                 return -EBUSY;
 582         }
 583
 584         base = ioremap(iomem->start, resource_size(iomem));
 585         if (!base) {
 586                 dev_err(&pdev->dev, "Cannot ioremap I2C region\n");
 587                 return -ENOMEM;
 588         }
 589
 590         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 591         if (!res) {
 592                 dev_err(&pdev->dev, "no irq resource\n");
 593                 ret = -EINVAL;
 594                 goto err_iounmap;
 595         }
 596         irq = res->start;
 597
 598         clk = clk_get(&pdev->dev, NULL);
 599         if (IS_ERR(clk)) {
 600                 dev_err(&pdev->dev, "missing controller clock");
 601                 ret = PTR_ERR(clk);
 602                 goto err_release_region;
 603         }
 604
 605         i2c_clk = clk_get(&pdev->dev, "i2c");
 606         if (IS_ERR(i2c_clk)) {
 607                 dev_err(&pdev->dev, "missing bus clock");
 608                 ret = PTR_ERR(i2c_clk);
 609                 goto err_clk_put;
 610         }
 611
 612         i2c_dev = kzalloc(sizeof(struct tegra_i2c_dev), GFP_KERNEL);
 613         if (!i2c_dev) {
 614                 ret = -ENOMEM;
 615                 goto err_i2c_clk_put;
 616         }
 617
 618         i2c_dev->base = base;
 619         i2c_dev->clk = clk;
 620         i2c_dev->i2c_clk = i2c_clk;
 621         i2c_dev->iomem = iomem;
 622         i2c_dev->adapter.algo = &tegra_i2c_algo;
 623         i2c_dev->irq = irq;
 624         i2c_dev->cont_id = pdev->id;
 625         i2c_dev->dev = &pdev->dev;
 626
 627         i2c_dev->bus_clk_rate = 100000; /* default clock rate */
 628         if (pdata) {
 629                 i2c_dev->bus_clk_rate = pdata->bus_clk_rate;
 630
 631         } else if (i2c_dev->dev->of_node) {    /* if there is a device tree node ... */
 632                 prop = of_get_property(i2c_dev->dev->of_node,
 633                                 "clock-frequency", NULL);
 634                 if (prop)
 635                         i2c_dev->bus_clk_rate = be32_to_cpup(prop);
 636         }
 637
 638         if (pdev->id == 3)
 639                 i2c_dev->is_dvc = 1;
 640         init_completion(&i2c_dev->msg_complete);
 641
 642         platform_set_drvdata(pdev, i2c_dev);
 643
 644         ret = tegra_i2c_init(i2c_dev);
 645         if (ret) {
 646                 dev_err(&pdev->dev, "Failed to initialize i2c controller");
 647                 goto err_free;
 648         }
 649
 650         ret = request_irq(i2c_dev->irq, tegra_i2c_isr, 0, pdev->name, i2c_dev);
 651         if (ret) {
 652                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
 653                 goto err_free;
 654         }
 655
 656         clk_enable(i2c_dev->i2c_clk);
 657
 658         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
 659         i2c_dev->adapter.owner = THIS_MODULE;
 660         i2c_dev->adapter.class = I2C_CLASS_HWMON;
 661         strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
 662                 sizeof(i2c_dev->adapter.name));
 663         i2c_dev->adapter.algo = &tegra_i2c_algo;
 664         i2c_dev->adapter.dev.parent = &pdev->dev;
 665         i2c_dev->adapter.nr = pdev->id;
 666         i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
 667
 668         ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
 669         if (ret) {
 670                 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
 671                 goto err_free_irq;
 672         }
 673
 674         of_i2c_register_devices(&i2c_dev->adapter);
 675
 676         return 0;
 677 err_free_irq:
 678         free_irq(i2c_dev->irq, i2c_dev);
 679 err_free:
 680         kfree(i2c_dev);
 681 err_i2c_clk_put:
 682         clk_put(i2c_clk);
 683 err_clk_put:
 684         clk_put(clk);
 685 err_release_region:
 686         release_mem_region(iomem->start, resource_size(iomem));
 687 err_iounmap:
 688         iounmap(base);
 689         return ret;
 690 }
 691
 692 static int tegra_i2c_remove(struct platform_device *pdev)
 693 {
 694         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 695         i2c_del_adapter(&i2c_dev->adapter);
 696         free_irq(i2c_dev->irq, i2c_dev);
 697         clk_put(i2c_dev->i2c_clk);
 698         clk_put(i2c_dev->clk);
 699         release_mem_region(i2c_dev->iomem->start,
 700                 resource_size(i2c_dev->iomem));
 701         iounmap(i2c_dev->base);
 702         kfree(i2c_dev);
 703         return 0;
 704 }
 705
 706 #ifdef CONFIG_PM
 707 static int tegra_i2c_suspend(struct platform_device *pdev, pm_message_t state)
 708 {
 709         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 710
 711         i2c_lock_adapter(&i2c_dev->adapter);
 712         i2c_dev->is_suspended = true;
 713         i2c_unlock_adapter(&i2c_dev->adapter);
 714
 715         return 0;
 716 }
 717
 718 static int tegra_i2c_resume(struct platform_device *pdev)
 719 {
 720         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 721         int ret;
 722
 723         i2c_lock_adapter(&i2c_dev->adapter);
 724
 725         ret = tegra_i2c_init(i2c_dev);
 726
 727         if (ret) {
 728                 i2c_unlock_adapter(&i2c_dev->adapter);
 729                 return ret;
 730         }
 731
 732         i2c_dev->is_suspended = false;
 733
 734         i2c_unlock_adapter(&i2c_dev->adapter);
 735
 736         return 0;
 737 }
 738 #endif
 739
 740 #if defined(CONFIG_OF)
 741 /* Match table for of_platform binding */
 742 static const struct of_device_id tegra_i2c_of_match[] __devinitconst = {
 743         { .compatible = "nvidia,tegra20-i2c", },
 744         {},
 745 };
 746 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
 747 #else
 748 #define tegra_i2c_of_match NULL
 749 #endif
 750
 751 static struct platform_driver tegra_i2c_driver = {
 752         .probe   = tegra_i2c_probe,
 753         .remove  = tegra_i2c_remove,
 754 #ifdef CONFIG_PM
 755         .suspend = tegra_i2c_suspend,
 756         .resume  = tegra_i2c_resume,
 757 #endif
 758         .driver  = {
 759                 .name  = "tegra-i2c",
 760                 .owner = THIS_MODULE,
 761                 .of_match_table = tegra_i2c_of_match,
 762         },
 763 };
 764
 765 static int __init tegra_i2c_init_driver(void)
 766 {
 767         return platform_driver_register(&tegra_i2c_driver);
 768 }
 769
 770 static void __exit tegra_i2c_exit_driver(void)
 771 {
 772         platform_driver_unregister(&tegra_i2c_driver);
 773 }
 774
 775 subsys_initcall(tegra_i2c_init_driver);
 776 module_exit(tegra_i2c_exit_driver);
 777
 778 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
 779 MODULE_AUTHOR("Colin Cross");
 780 MODULE_LICENSE("GPL v2");