drivers/i2c/busses/i2c-omap.c

   1 /*
   2  * TI OMAP I2C master mode driver
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Copyright (C) 2004 Texas Instruments.
   6  *
   7  * Updated to work with multiple I2C interfaces on 24xx by
   8  * Tony Lindgren <tony@atomide.com> and Imre Deak <imre.deak@nokia.com>
   9  * Copyright (C) 2005 Nokia Corporation
  10  *
  11  * Cleaned up by Juha Yrjölä <juha.yrjola@nokia.com>
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26  */
  27
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/i2c.h>
  31 #include <linux/err.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/completion.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/clk.h>
  36
  37 #include <asm/io.h>
  38
  39 /* timeout waiting for the controller to respond */
  40 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
  41
  42 #define OMAP_I2C_REV_REG                0x00
  43 #define OMAP_I2C_IE_REG                 0x04
  44 #define OMAP_I2C_STAT_REG               0x08
  45 #define OMAP_I2C_IV_REG                 0x0c
  46 #define OMAP_I2C_SYSS_REG               0x10
  47 #define OMAP_I2C_BUF_REG                0x14
  48 #define OMAP_I2C_CNT_REG                0x18
  49 #define OMAP_I2C_DATA_REG               0x1c
  50 #define OMAP_I2C_SYSC_REG               0x20
  51 #define OMAP_I2C_CON_REG                0x24
  52 #define OMAP_I2C_OA_REG                 0x28
  53 #define OMAP_I2C_SA_REG                 0x2c
  54 #define OMAP_I2C_PSC_REG                0x30
  55 #define OMAP_I2C_SCLL_REG               0x34
  56 #define OMAP_I2C_SCLH_REG               0x38
  57 #define OMAP_I2C_SYSTEST_REG            0x3c
  58
  59 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  60 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
  61 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
  62 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
  63 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
  64 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
  65
  66 /* I2C Status Register (OMAP_I2C_STAT): */
  67 #define OMAP_I2C_STAT_SBD       (1 << 15)       /* Single byte data */
  68 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
  69 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
  70 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
  71 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
  72 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
  73 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
  74 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
  75 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
  76 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
  77 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
  78
  79 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
  80 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
  81 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
  82
  83 /* I2C Configuration Register (OMAP_I2C_CON): */
  84 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
  85 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
  86 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
  87 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
  88 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
  89 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
  90 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
  91 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
  92 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
  93
  94 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
  95 #ifdef DEBUG
  96 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
  97 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
  98 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
  99 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 100 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 101 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 102 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 103 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 104 #endif
 105
 106 /* I2C System Status register (OMAP_I2C_SYSS): */
 107 #define OMAP_I2C_SYSS_RDONE             (1 << 0)        /* Reset Done */
 108
 109 /* I2C System Configuration Register (OMAP_I2C_SYSC): */
 110 #define OMAP_I2C_SYSC_SRST              (1 << 1)        /* Soft Reset */
 111
 112 /* REVISIT: Use platform_data instead of module parameters */
 113 /* Fast Mode = 400 kHz, Standard = 100 kHz */
 114 static int clock = 100; /* Default: 100 kHz */
 115 module_param(clock, int, 0);
 116 MODULE_PARM_DESC(clock, "Set I2C clock in kHz: 400=fast mode (default == 100)");
 117
 118 struct omap_i2c_dev {
 119         struct device           *dev;
 120         void __iomem            *base;          /* virtual */
 121         int                     irq;
 122         struct clk              *iclk;          /* Interface clock */
 123         struct clk              *fclk;          /* Functional clock */
 124         struct completion       cmd_complete;
 125         struct resource         *ioarea;
 126         u16                     cmd_err;
 127         u8                      *buf;
 128         size_t                  buf_len;
 129         struct i2c_adapter      adapter;
 130         unsigned                rev1:1;
 131         unsigned                idle:1;
 132         u16                     iestate;        /* Saved interrupt register */
 133 };
 134
 135 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
 136                                       int reg, u16 val)
 137 {
 138         __raw_writew(val, i2c_dev->base + reg);
 139 }
 140
 141 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 142 {
 143         return __raw_readw(i2c_dev->base + reg);
 144 }
 145
 146 static int omap_i2c_get_clocks(struct omap_i2c_dev *dev)
 147 {
 148         if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
 149                 dev->iclk = clk_get(dev->dev, "i2c_ick");
 150                 if (IS_ERR(dev->iclk)) {
 151                         dev->iclk = NULL;
 152                         return -ENODEV;
 153                 }
 154         }
 155
 156         dev->fclk = clk_get(dev->dev, "i2c_fck");
 157         if (IS_ERR(dev->fclk)) {
 158                 if (dev->iclk != NULL) {
 159                         clk_put(dev->iclk);
 160                         dev->iclk = NULL;
 161                 }
 162                 dev->fclk = NULL;
 163                 return -ENODEV;
 164         }
 165
 166         return 0;
 167 }
 168
 169 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
 170 {
 171         clk_put(dev->fclk);
 172         dev->fclk = NULL;
 173         if (dev->iclk != NULL) {
 174                 clk_put(dev->iclk);
 175                 dev->iclk = NULL;
 176         }
 177 }
 178
 179 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
 180 {
 181         if (dev->iclk != NULL)
 182                 clk_enable(dev->iclk);
 183         clk_enable(dev->fclk);
 184         if (dev->iestate)
 185                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
 186         dev->idle = 0;
 187 }
 188
 189 static void omap_i2c_idle(struct omap_i2c_dev *dev)
 190 {
 191         u16 iv;
 192
 193         dev->idle = 1;
 194         dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 195         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
 196         if (dev->rev1)
 197                 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);   /* Read clears */
 198         else
 199                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
 200         clk_disable(dev->fclk);
 201         if (dev->iclk != NULL)
 202                 clk_disable(dev->iclk);
 203 }
 204
 205 static int omap_i2c_init(struct omap_i2c_dev *dev)
 206 {
 207         u16 psc = 0;
 208         unsigned long fclk_rate = 12000000;
 209         unsigned long timeout;
 210
 211         if (!dev->rev1) {
 212                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
 213                 /* For some reason we need to set the EN bit before the
 214                  * reset done bit gets set. */
 215                 timeout = jiffies + OMAP_I2C_TIMEOUT;
 216                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 217                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
 218                          OMAP_I2C_SYSS_RDONE)) {
 219                         if (time_after(jiffies, timeout)) {
 220                                 dev_warn(dev->dev, "timeout waiting "
 221                                                 "for controller reset\n");
 222                                 return -ETIMEDOUT;
 223                         }
 224                         msleep(1);
 225                 }
 226         }
 227         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 228
 229         if (cpu_class_is_omap1()) {
 230                 struct clk *armxor_ck;
 231
 232                 armxor_ck = clk_get(NULL, "armxor_ck");
 233                 if (IS_ERR(armxor_ck))
 234                         dev_warn(dev->dev, "Could not get armxor_ck\n");
 235                 else {
 236                         fclk_rate = clk_get_rate(armxor_ck);
 237                         clk_put(armxor_ck);
 238                 }
 239                 /* TRM for 5912 says the I2C clock must be prescaled to be
 240                  * between 7 - 12 MHz. The XOR input clock is typically
 241                  * 12, 13 or 19.2 MHz. So we should have code that produces:
 242                  *
 243                  * XOR MHz      Divider         Prescaler
 244                  * 12           1               0
 245                  * 13           2               1
 246                  * 19.2         2               1
 247                  */
 248                 if (fclk_rate > 12000000)
 249                         psc = fclk_rate / 12000000;
 250         }
 251
 252         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 253         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
 254
 255         /* Program desired operating rate */
 256         fclk_rate /= (psc + 1) * 1000;
 257         if (psc > 2)
 258                 psc = 2;
 259
 260         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG,
 261                            fclk_rate / (clock * 2) - 7 + psc);
 262         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG,
 263                            fclk_rate / (clock * 2) - 7 + psc);
 264
 265         /* Take the I2C module out of reset: */
 266         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 267
 268         /* Enable interrupts */
 269         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
 270                            (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 271                             OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
 272                             OMAP_I2C_IE_AL));
 273         return 0;
 274 }
 275
 276 /*
 277  * Waiting on Bus Busy
 278  */
 279 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 280 {
 281         unsigned long timeout;
 282
 283         timeout = jiffies + OMAP_I2C_TIMEOUT;
 284         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 285                 if (time_after(jiffies, timeout)) {
 286                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 287                         return -ETIMEDOUT;
 288                 }
 289                 msleep(1);
 290         }
 291
 292         return 0;
 293 }
 294
 295 /*
 296  * Low level master read/write transaction.
 297  */
 298 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 299                              struct i2c_msg *msg, int stop)
 300 {
 301         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 302         int r;
 303         u16 w;
 304
 305         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 306                 msg->addr, msg->len, msg->flags, stop);
 307
 308         if (msg->len == 0)
 309                 return -EINVAL;
 310
 311         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 312
 313         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
 314         dev->buf = msg->buf;
 315         dev->buf_len = msg->len;
 316
 317         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
 318
 319         init_completion(&dev->cmd_complete);
 320         dev->cmd_err = 0;
 321
 322         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 323         if (msg->flags & I2C_M_TEN)
 324                 w |= OMAP_I2C_CON_XA;
 325         if (!(msg->flags & I2C_M_RD))
 326                 w |= OMAP_I2C_CON_TRX;
 327         if (stop)
 328                 w |= OMAP_I2C_CON_STP;
 329         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 330
 331         r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
 332                                                       OMAP_I2C_TIMEOUT);
 333         dev->buf_len = 0;
 334         if (r < 0)
 335                 return r;
 336         if (r == 0) {
 337                 dev_err(dev->dev, "controller timed out\n");
 338                 omap_i2c_init(dev);
 339                 return -ETIMEDOUT;
 340         }
 341
 342         if (likely(!dev->cmd_err))
 343                 return 0;
 344
 345         /* We have an error */
 346         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
 347                             OMAP_I2C_STAT_XUDF)) {
 348                 omap_i2c_init(dev);
 349                 return -EIO;
 350         }
 351
 352         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
 353                 if (msg->flags & I2C_M_IGNORE_NAK)
 354                         return 0;
 355                 if (stop) {
 356                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 357                         w |= OMAP_I2C_CON_STP;
 358                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 359                 }
 360                 return -EREMOTEIO;
 361         }
 362         return -EIO;
 363 }
 364
 365
 366 /*
 367  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 368  * to do the work during IRQ processing.
 369  */
 370 static int
 371 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 372 {
 373         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 374         int i;
 375         int r;
 376
 377         omap_i2c_unidle(dev);
 378
 379         if ((r = omap_i2c_wait_for_bb(dev)) < 0)
 380                 goto out;
 381
 382         for (i = 0; i < num; i++) {
 383                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 384                 if (r != 0)
 385                         break;
 386         }
 387
 388         if (r == 0)
 389                 r = num;
 390 out:
 391         omap_i2c_idle(dev);
 392         return r;
 393 }
 394
 395 static u32
 396 omap_i2c_func(struct i2c_adapter *adap)
 397 {
 398         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 399 }
 400
 401 static inline void
 402 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
 403 {
 404         dev->cmd_err |= err;
 405         complete(&dev->cmd_complete);
 406 }
 407
 408 static inline void
 409 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
 410 {
 411         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 412 }
 413
 414 static irqreturn_t
 415 omap_i2c_rev1_isr(int this_irq, void *dev_id)
 416 {
 417         struct omap_i2c_dev *dev = dev_id;
 418         u16 iv, w;
 419
 420         if (dev->idle)
 421                 return IRQ_NONE;
 422
 423         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 424         switch (iv) {
 425         case 0x00:      /* None */
 426                 break;
 427         case 0x01:      /* Arbitration lost */
 428                 dev_err(dev->dev, "Arbitration lost\n");
 429                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 430                 break;
 431         case 0x02:      /* No acknowledgement */
 432                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 433                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 434                 break;
 435         case 0x03:      /* Register access ready */
 436                 omap_i2c_complete_cmd(dev, 0);
 437                 break;
 438         case 0x04:      /* Receive data ready */
 439                 if (dev->buf_len) {
 440                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 441                         *dev->buf++ = w;
 442                         dev->buf_len--;
 443                         if (dev->buf_len) {
 444                                 *dev->buf++ = w >> 8;
 445                                 dev->buf_len--;
 446                         }
 447                 } else
 448                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
 449                 break;
 450         case 0x05:      /* Transmit data ready */
 451                 if (dev->buf_len) {
 452                         w = *dev->buf++;
 453                         dev->buf_len--;
 454                         if (dev->buf_len) {
 455                                 w |= *dev->buf++ << 8;
 456                                 dev->buf_len--;
 457                         }
 458                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 459                 } else
 460                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
 461                 break;
 462         default:
 463                 return IRQ_NONE;
 464         }
 465
 466         return IRQ_HANDLED;
 467 }
 468
 469 static irqreturn_t
 470 omap_i2c_isr(int this_irq, void *dev_id)
 471 {
 472         struct omap_i2c_dev *dev = dev_id;
 473         u16 bits;
 474         u16 stat, w;
 475         int count = 0;
 476
 477         if (dev->idle)
 478                 return IRQ_NONE;
 479
 480         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 481         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
 482                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 483                 if (count++ == 100) {
 484                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 485                         break;
 486                 }
 487
 488                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 489
 490                 if (stat & OMAP_I2C_STAT_ARDY) {
 491                         omap_i2c_complete_cmd(dev, 0);
 492                         continue;
 493                 }
 494                 if (stat & OMAP_I2C_STAT_RRDY) {
 495                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 496                         if (dev->buf_len) {
 497                                 *dev->buf++ = w;
 498                                 dev->buf_len--;
 499                                 if (dev->buf_len) {
 500                                         *dev->buf++ = w >> 8;
 501                                         dev->buf_len--;
 502                                 }
 503                         } else
 504                                 dev_err(dev->dev, "RRDY IRQ while no data "
 505                                                 "requested\n");
 506                         omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
 507                         continue;
 508                 }
 509                 if (stat & OMAP_I2C_STAT_XRDY) {
 510                         w = 0;
 511                         if (dev->buf_len) {
 512                                 w = *dev->buf++;
 513                                 dev->buf_len--;
 514                                 if (dev->buf_len) {
 515                                         w |= *dev->buf++ << 8;
 516                                         dev->buf_len--;
 517                                 }
 518                         } else
 519                                 dev_err(dev->dev, "XRDY IRQ while no "
 520                                         "data to send\n");
 521                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 522                         omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
 523                         continue;
 524                 }
 525                 if (stat & OMAP_I2C_STAT_ROVR) {
 526                         dev_err(dev->dev, "Receive overrun\n");
 527                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 528                 }
 529                 if (stat & OMAP_I2C_STAT_XUDF) {
 530                         dev_err(dev->dev, "Transmit overflow\n");
 531                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 532                 }
 533                 if (stat & OMAP_I2C_STAT_NACK) {
 534                         omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 535                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 536                                            OMAP_I2C_CON_STP);
 537                 }
 538                 if (stat & OMAP_I2C_STAT_AL) {
 539                         dev_err(dev->dev, "Arbitration lost\n");
 540                         omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 541                 }
 542         }
 543
 544         return count ? IRQ_HANDLED : IRQ_NONE;
 545 }
 546
 547 static const struct i2c_algorithm omap_i2c_algo = {
 548         .master_xfer    = omap_i2c_xfer,
 549         .functionality  = omap_i2c_func,
 550 };
 551
 552 static int
 553 omap_i2c_probe(struct platform_device *pdev)
 554 {
 555         struct omap_i2c_dev     *dev;
 556         struct i2c_adapter      *adap;
 557         struct resource         *mem, *irq, *ioarea;
 558         int r;
 559
 560         /* NOTE: driver uses the static register mapping */
 561         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 562         if (!mem) {
 563                 dev_err(&pdev->dev, "no mem resource?\n");
 564                 return -ENODEV;
 565         }
 566         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 567         if (!irq) {
 568                 dev_err(&pdev->dev, "no irq resource?\n");
 569                 return -ENODEV;
 570         }
 571
 572         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
 573                         pdev->name);
 574         if (!ioarea) {
 575                 dev_err(&pdev->dev, "I2C region already claimed\n");
 576                 return -EBUSY;
 577         }
 578
 579         if (clock > 200)
 580                 clock = 400;    /* Fast mode */
 581         else
 582                 clock = 100;    /* Standard mode */
 583
 584         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
 585         if (!dev) {
 586                 r = -ENOMEM;
 587                 goto err_release_region;
 588         }
 589
 590         dev->dev = &pdev->dev;
 591         dev->irq = irq->start;
 592         dev->base = ioremap(mem->start, mem->end - mem->start + 1);
 593         if (!dev->base) {
 594                 r = -ENOMEM;
 595                 goto err_free_mem;
 596         }
 597
 598         platform_set_drvdata(pdev, dev);
 599
 600         if ((r = omap_i2c_get_clocks(dev)) != 0)
 601                 goto err_iounmap;
 602
 603         omap_i2c_unidle(dev);
 604
 605         if (cpu_is_omap15xx())
 606                 dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
 607
 608         /* reset ASAP, clearing any IRQs */
 609         omap_i2c_init(dev);
 610
 611         r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
 612                         0, pdev->name, dev);
 613
 614         if (r) {
 615                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
 616                 goto err_unuse_clocks;
 617         }
 618         r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
 619         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
 620                  pdev->id, r >> 4, r & 0xf, clock);
 621
 622         adap = &dev->adapter;
 623         i2c_set_adapdata(adap, dev);
 624         adap->owner = THIS_MODULE;
 625         adap->class = I2C_CLASS_HWMON;
 626         strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
 627         adap->algo = &omap_i2c_algo;
 628         adap->dev.parent = &pdev->dev;
 629
 630         /* i2c device drivers may be active on return from add_adapter() */
 631         adap->nr = pdev->id;
 632         r = i2c_add_numbered_adapter(adap);
 633         if (r) {
 634                 dev_err(dev->dev, "failure adding adapter\n");
 635                 goto err_free_irq;
 636         }
 637
 638         omap_i2c_idle(dev);
 639
 640         return 0;
 641
 642 err_free_irq:
 643         free_irq(dev->irq, dev);
 644 err_unuse_clocks:
 645         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 646         omap_i2c_idle(dev);
 647         omap_i2c_put_clocks(dev);
 648 err_iounmap:
 649         iounmap(dev->base);
 650 err_free_mem:
 651         platform_set_drvdata(pdev, NULL);
 652         kfree(dev);
 653 err_release_region:
 654         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 655
 656         return r;
 657 }
 658
 659 static int
 660 omap_i2c_remove(struct platform_device *pdev)
 661 {
 662         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
 663         struct resource         *mem;
 664
 665         platform_set_drvdata(pdev, NULL);
 666
 667         free_irq(dev->irq, dev);
 668         i2c_del_adapter(&dev->adapter);
 669         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 670         omap_i2c_put_clocks(dev);
 671         iounmap(dev->base);
 672         kfree(dev);
 673         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 674         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 675         return 0;
 676 }
 677
 678 static struct platform_driver omap_i2c_driver = {
 679         .probe          = omap_i2c_probe,
 680         .remove         = omap_i2c_remove,
 681         .driver         = {
 682                 .name   = "i2c_omap",
 683                 .owner  = THIS_MODULE,
 684         },
 685 };
 686
 687 /* I2C may be needed to bring up other drivers */
 688 static int __init
 689 omap_i2c_init_driver(void)
 690 {
 691         return platform_driver_register(&omap_i2c_driver);
 692 }
 693 subsys_initcall(omap_i2c_init_driver);
 694
 695 static void __exit omap_i2c_exit_driver(void)
 696 {
 697         platform_driver_unregister(&omap_i2c_driver);
 698 }
 699 module_exit(omap_i2c_exit_driver);
 700
 701 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
 702 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
 703 MODULE_LICENSE("GPL");
 704 MODULE_ALIAS("platform:i2c_omap");