2 * Copyright (C) 2009 ST-Ericsson SA
3 * Copyright (C) 2009 STMicroelectronics
5 * I2C master mode controller driver, used in Nomadik 8815
8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
9 * Author: Sachin Verma <sachin.verma@st.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2, as
13 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/delay.h>
19 #include <linux/slab.h>
20 #include <linux/interrupt.h>
21 #include <linux/i2c.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
25 #include <linux/regulator/consumer.h>
29 #define DRIVER_NAME "nmk-i2c"
31 /* I2C Controller register offsets */
32 #define I2C_CR (0x000)
33 #define I2C_SCR (0x004)
34 #define I2C_HSMCR (0x008)
35 #define I2C_MCR (0x00C)
36 #define I2C_TFR (0x010)
37 #define I2C_SR (0x014)
38 #define I2C_RFR (0x018)
39 #define I2C_TFTR (0x01C)
40 #define I2C_RFTR (0x020)
41 #define I2C_DMAR (0x024)
42 #define I2C_BRCR (0x028)
43 #define I2C_IMSCR (0x02C)
44 #define I2C_RISR (0x030)
45 #define I2C_MISR (0x034)
46 #define I2C_ICR (0x038)
48 /* Control registers */
49 #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */
50 #define I2C_CR_OM (0x3 << 1) /* Operating mode */
51 #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */
52 #define I2C_CR_SM (0x3 << 4) /* Speed mode */
53 #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */
54 #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */
55 #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */
56 #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */
57 #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */
58 #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */
59 #define I2C_CR_LM (0x1 << 12) /* Loopback mode */
60 #define I2C_CR_FON (0x3 << 13) /* Filtering on */
61 #define I2C_CR_FS (0x3 << 15) /* Force stop enable */
63 /* Master controller (MCR) register */
64 #define I2C_MCR_OP (0x1 << 0) /* Operation */
65 #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */
66 #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */
67 #define I2C_MCR_SB (0x1 << 11) /* Extended address */
68 #define I2C_MCR_AM (0x3 << 12) /* Address type */
69 #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */
70 #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */
72 /* Status register (SR) */
73 #define I2C_SR_OP (0x3 << 0) /* Operation */
74 #define I2C_SR_STATUS (0x3 << 2) /* controller status */
75 #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */
76 #define I2C_SR_TYPE (0x3 << 7) /* Receive type */
77 #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */
79 /* Interrupt mask set/clear (IMSCR) bits */
80 #define I2C_IT_TXFE (0x1 << 0)
81 #define I2C_IT_TXFNE (0x1 << 1)
82 #define I2C_IT_TXFF (0x1 << 2)
83 #define I2C_IT_TXFOVR (0x1 << 3)
84 #define I2C_IT_RXFE (0x1 << 4)
85 #define I2C_IT_RXFNF (0x1 << 5)
86 #define I2C_IT_RXFF (0x1 << 6)
87 #define I2C_IT_RFSR (0x1 << 16)
88 #define I2C_IT_RFSE (0x1 << 17)
89 #define I2C_IT_WTSR (0x1 << 18)
90 #define I2C_IT_MTD (0x1 << 19)
91 #define I2C_IT_STD (0x1 << 20)
92 #define I2C_IT_MAL (0x1 << 24)
93 #define I2C_IT_BERR (0x1 << 25)
94 #define I2C_IT_MTDWS (0x1 << 28)
96 #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask))
98 /* some bits in ICR are reserved */
99 #define I2C_CLEAR_ALL_INTS 0x131f007f
101 /* first three msb bits are reserved */
102 #define IRQ_MASK(mask) (mask & 0x1fffffff)
104 /* maximum threshold value */
105 #define MAX_I2C_FIFO_THRESHOLD 15
107 /* per-transfer delay, required for the hardware to stabilize */
108 #define I2C_DELAY 150
119 I2C_NO_OPERATION = 0xff,
125 * struct i2c_nmk_client - client specific data
126 * @slave_adr: 7-bit slave address
127 * @count: no. bytes to be transferred
128 * @buffer: client data buffer
129 * @xfer_bytes: bytes transferred till now
130 * @operation: current I2C operation
132 struct i2c_nmk_client {
133 unsigned short slave_adr;
135 unsigned char *buffer;
136 unsigned long xfer_bytes;
137 enum i2c_operation operation;
141 * struct nmk_i2c_dev - private data structure of the controller
142 * @pdev: parent platform device
143 * @adap: corresponding I2C adapter
144 * @irq: interrupt line for the controller
145 * @virtbase: virtual io memory area
146 * @clk: hardware i2c block clock
147 * @cfg: machine provided controller configuration
148 * @cli: holder of client specific data
149 * @stop: stop condition
150 * @xfer_complete: acknowledge completion for a I2C message
151 * @result: controller propogated result
152 * @busy: Busy doing transfer
155 struct platform_device *pdev;
156 struct i2c_adapter adap;
158 void __iomem *virtbase;
160 struct nmk_i2c_controller cfg;
161 struct i2c_nmk_client cli;
163 struct completion xfer_complete;
165 struct regulator *regulator;
169 /* controller's abort causes */
170 static const char *abort_causes[] = {
171 "no ack received after address transmission",
172 "no ack received during data phase",
173 "ack received after xmission of master code",
174 "master lost arbitration",
177 "overflow, maxsize is 2047 bytes",
180 static inline void i2c_set_bit(void __iomem *reg, u32 mask)
182 writel(readl(reg) | mask, reg);
185 static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
187 writel(readl(reg) & ~mask, reg);
191 * flush_i2c_fifo() - This function flushes the I2C FIFO
192 * @dev: private data of I2C Driver
194 * This function flushes the I2C Tx and Rx FIFOs. It returns
195 * 0 on successful flushing of FIFO
197 static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
199 #define LOOP_ATTEMPTS 10
201 unsigned long timeout;
204 * flush the transmit and receive FIFO. The flushing
205 * operation takes several cycles before to be completed.
206 * On the completion, the I2C internal logic clears these
207 * bits, until then no one must access Tx, Rx FIFO and
208 * should poll on these bits waiting for the completion.
210 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
212 for (i = 0; i < LOOP_ATTEMPTS; i++) {
213 timeout = jiffies + msecs_to_jiffies(dev->adap.timeout);
215 while (!time_after(jiffies, timeout)) {
216 if ((readl(dev->virtbase + I2C_CR) &
217 (I2C_CR_FTX | I2C_CR_FRX)) == 0)
222 dev_err(&dev->pdev->dev, "flushing operation timed out "
223 "giving up after %d attempts", LOOP_ATTEMPTS);
229 * disable_all_interrupts() - Disable all interrupts of this I2c Bus
230 * @dev: private data of I2C Driver
232 static void disable_all_interrupts(struct nmk_i2c_dev *dev)
234 u32 mask = IRQ_MASK(0);
235 writel(mask, dev->virtbase + I2C_IMSCR);
239 * clear_all_interrupts() - Clear all interrupts of I2C Controller
240 * @dev: private data of I2C Driver
242 static void clear_all_interrupts(struct nmk_i2c_dev *dev)
245 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
246 writel(mask, dev->virtbase + I2C_ICR);
250 * init_hw() - initialize the I2C hardware
251 * @dev: private data of I2C Driver
253 static int init_hw(struct nmk_i2c_dev *dev)
257 clk_enable(dev->clk);
259 stat = flush_i2c_fifo(dev);
263 /* disable the controller */
264 i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
266 disable_all_interrupts(dev);
268 clear_all_interrupts(dev);
270 dev->cli.operation = I2C_NO_OPERATION;
273 /* TODO: Why disable clocks after init hw? */
274 clk_disable(dev->clk);
276 * TODO: What is this delay for?
277 * Must be pretty pointless since the hw block
284 /* enable peripheral, master mode operation */
285 #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE)
288 * load_i2c_mcr_reg() - load the MCR register
289 * @dev: private data of controller
291 static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev)
295 /* 7-bit address transaction */
296 mcr |= GEN_MASK(1, I2C_MCR_AM, 12);
297 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);
299 /* start byte procedure not applied */
300 mcr |= GEN_MASK(0, I2C_MCR_SB, 11);
302 /* check the operation, master read/write? */
303 if (dev->cli.operation == I2C_WRITE)
304 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0);
306 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0);
308 /* stop or repeated start? */
310 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14);
312 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14));
314 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);
320 * setup_i2c_controller() - setup the controller
321 * @dev: private data of controller
323 static void setup_i2c_controller(struct nmk_i2c_dev *dev)
328 writel(0x0, dev->virtbase + I2C_CR);
329 writel(0x0, dev->virtbase + I2C_HSMCR);
330 writel(0x0, dev->virtbase + I2C_TFTR);
331 writel(0x0, dev->virtbase + I2C_RFTR);
332 writel(0x0, dev->virtbase + I2C_DMAR);
337 * slsu defines the data setup time after SCL clock
338 * stretching in terms of i2c clk cycles. The
339 * needed setup time for the three modes are 250ns,
340 * 100ns, 10ns respectively thus leading to the values
341 * of 14, 6, 2 for a 48 MHz i2c clk.
343 writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR);
345 i2c_clk = clk_get_rate(dev->clk);
347 /* fallback to std. mode if machine has not provided it */
348 if (dev->cfg.clk_freq == 0)
349 dev->cfg.clk_freq = 100000;
352 * The spec says, in case of std. mode the divider is
353 * 2 whereas it is 3 for fast and fastplus mode of
354 * operation. TODO - high speed support.
356 div = (dev->cfg.clk_freq > 100000) ? 3 : 2;
359 * generate the mask for baud rate counters. The controller
360 * has two baud rate counters. One is used for High speed
361 * operation, and the other is for std, fast mode, fast mode
362 * plus operation. Currently we do not supprt high speed mode
366 brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff;
368 /* set the baud rate counter register */
369 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
372 * set the speed mode. Currently we support
373 * only standard and fast mode of operation
374 * TODO - support for fast mode plus (up to 1Mb/s)
375 * and high speed (up to 3.4 Mb/s)
377 if (dev->cfg.sm > I2C_FREQ_MODE_FAST) {
378 dev_err(&dev->pdev->dev, "do not support this mode "
379 "defaulting to std. mode\n");
380 brcr2 = i2c_clk/(100000 * 2) & 0xffff;
381 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
382 writel(I2C_FREQ_MODE_STANDARD << 4,
383 dev->virtbase + I2C_CR);
385 writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR);
387 /* set the Tx and Rx FIFO threshold */
388 writel(dev->cfg.tft, dev->virtbase + I2C_TFTR);
389 writel(dev->cfg.rft, dev->virtbase + I2C_RFTR);
393 * read_i2c() - Read from I2C client device
394 * @dev: private data of I2C Driver
396 * This function reads from i2c client device when controller is in
397 * master mode. There is a completion timeout. If there is no transfer
398 * before timeout error is returned.
400 static int read_i2c(struct nmk_i2c_dev *dev)
407 mcr = load_i2c_mcr_reg(dev);
408 writel(mcr, dev->virtbase + I2C_MCR);
410 /* load the current CR value */
411 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
412 dev->virtbase + I2C_CR);
414 /* enable the controller */
415 i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
417 init_completion(&dev->xfer_complete);
419 /* enable interrupts by setting the mask */
420 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
421 I2C_IT_MAL | I2C_IT_BERR);
424 irq_mask |= I2C_IT_MTD;
426 irq_mask |= I2C_IT_MTDWS;
428 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
430 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
431 dev->virtbase + I2C_IMSCR);
433 timeout = wait_for_completion_interruptible_timeout(
434 &dev->xfer_complete, msecs_to_jiffies(dev->adap.timeout));
437 dev_err(&dev->pdev->dev,
438 "wait_for_completion_interruptible_timeout"
439 "returned %d waiting for event\n", timeout);
444 /* controller has timedout, re-init the h/w */
445 dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
453 * write_i2c() - Write data to I2C client.
454 * @dev: private data of I2C Driver
456 * This function writes data to I2C client
458 static int write_i2c(struct nmk_i2c_dev *dev)
465 mcr = load_i2c_mcr_reg(dev);
467 writel(mcr, dev->virtbase + I2C_MCR);
469 /* load the current CR value */
470 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
471 dev->virtbase + I2C_CR);
473 /* enable the controller */
474 i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
476 init_completion(&dev->xfer_complete);
478 /* enable interrupts by settings the masks */
479 irq_mask = (I2C_IT_TXFNE | I2C_IT_TXFOVR |
480 I2C_IT_MAL | I2C_IT_BERR);
483 * check if we want to transfer a single or multiple bytes, if so
484 * set the MTDWS bit (Master Transaction Done Without Stop)
485 * to start repeated start operation
488 irq_mask |= I2C_IT_MTD;
490 irq_mask |= I2C_IT_MTDWS;
492 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
494 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
495 dev->virtbase + I2C_IMSCR);
497 timeout = wait_for_completion_interruptible_timeout(
498 &dev->xfer_complete, msecs_to_jiffies(dev->adap.timeout));
501 dev_err(&dev->pdev->dev,
502 "wait_for_completion_interruptible_timeout"
503 "returned %d waiting for event\n", timeout);
508 /* controller has timedout, re-init the h/w */
509 dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
518 * nmk_i2c_xfer() - I2C transfer function used by kernel framework
519 * @i2c_adap: Adapter pointer to the controller
520 * @msgs: Pointer to data to be written.
521 * @num_msgs: Number of messages to be executed
523 * This is the function called by the generic kernel i2c_transfer()
524 * or i2c_smbus...() API calls. Note that this code is protected by the
525 * semaphore set in the kernel i2c_transfer() function.
528 * READ TRANSFER : We impose a restriction of the first message to be the
529 * index message for any read transaction.
530 * - a no index is coded as '0',
531 * - 2byte big endian index is coded as '3'
532 * !!! msg[0].buf holds the actual index.
533 * This is compatible with generic messages of smbus emulator
534 * that send a one byte index.
535 * eg. a I2C transation to read 2 bytes from index 0
537 * msg[0].addr = client->addr;
538 * msg[0].flags = 0x0;
542 * msg[1].addr = client->addr;
543 * msg[1].flags = I2C_M_RD;
545 * msg[1].buf = rd_buff
546 * i2c_transfer(adap, msg, 2);
548 * WRITE TRANSFER : The I2C standard interface interprets all data as payload.
549 * If you want to emulate an SMBUS write transaction put the
550 * index as first byte(or first and second) in the payload.
551 * eg. a I2C transation to write 2 bytes from index 1
555 * msg[0].flags = 0x0;
557 * msg[0].buf = wr_buff;
558 * i2c_transfer(adap, msg, 1);
560 * To read or write a block of data (multiple bytes) using SMBUS emulation
561 * please use the i2c_smbus_read_i2c_block_data()
562 * or i2c_smbus_write_i2c_block_data() API
564 static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
565 struct i2c_msg msgs[], int num_msgs)
570 struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
575 regulator_enable(dev->regulator);
577 status = init_hw(dev);
581 clk_enable(dev->clk);
583 /* setup the i2c controller */
584 setup_i2c_controller(dev);
586 for (i = 0; i < num_msgs; i++) {
587 if (unlikely(msgs[i].flags & I2C_M_TEN)) {
588 dev_err(&dev->pdev->dev, "10 bit addressing"
594 dev->cli.slave_adr = msgs[i].addr;
595 dev->cli.buffer = msgs[i].buf;
596 dev->cli.count = msgs[i].len;
597 dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
600 if (msgs[i].flags & I2C_M_RD) {
601 /* it is a read operation */
602 dev->cli.operation = I2C_READ;
603 status = read_i2c(dev);
605 /* write operation */
606 dev->cli.operation = I2C_WRITE;
607 status = write_i2c(dev);
609 if (status || (dev->result)) {
610 /* get the abort cause */
611 cause = (readl(dev->virtbase + I2C_SR) >> 4) & 0x7;
612 dev_err(&dev->pdev->dev, "error during I2C"
613 "message xfer: %d\n", cause);
614 dev_err(&dev->pdev->dev, "%s\n",
615 cause >= ARRAY_SIZE(abort_causes)
616 ? "unknown reason" : abort_causes[cause]);
618 status = status ? status : dev->result;
626 clk_disable(dev->clk);
629 regulator_disable(dev->regulator);
633 /* return the no. messages processed */
641 * disable_interrupts() - disable the interrupts
642 * @dev: private data of controller
643 * @irq: interrupt number
645 static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
648 writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
649 dev->virtbase + I2C_IMSCR);
654 * i2c_irq_handler() - interrupt routine
655 * @irq: interrupt number
656 * @arg: data passed to the handler
658 * This is the interrupt handler for the i2c driver. Currently
659 * it handles the major interrupts like Rx & Tx FIFO management
660 * interrupts, master transaction interrupts, arbitration and
661 * bus error interrupts. The rest of the interrupts are treated as
664 static irqreturn_t i2c_irq_handler(int irq, void *arg)
666 struct nmk_i2c_dev *dev = arg;
672 /* load Tx FIFO and Rx FIFO threshold values */
673 tft = readl(dev->virtbase + I2C_TFTR);
674 rft = readl(dev->virtbase + I2C_RFTR);
676 /* read interrupt status register */
677 misr = readl(dev->virtbase + I2C_MISR);
680 switch ((1 << src)) {
682 /* Transmit FIFO nearly empty interrupt */
685 if (dev->cli.operation == I2C_READ) {
687 * in read operation why do we care for writing?
688 * so disable the Transmit FIFO interrupt
690 disable_interrupts(dev, I2C_IT_TXFNE);
692 for (count = (MAX_I2C_FIFO_THRESHOLD - tft - 2);
694 (dev->cli.count != 0);
696 /* write to the Tx FIFO */
697 writeb(*dev->cli.buffer,
698 dev->virtbase + I2C_TFR);
701 dev->cli.xfer_bytes++;
704 * if done, close the transfer by disabling the
705 * corresponding TXFNE interrupt
707 if (dev->cli.count == 0)
708 disable_interrupts(dev, I2C_IT_TXFNE);
714 * Rx FIFO nearly full interrupt.
715 * This is set when the numer of entries in Rx FIFO is
716 * greater or equal than the threshold value programmed
720 for (count = rft; count > 0; count--) {
721 /* Read the Rx FIFO */
722 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
725 dev->cli.count -= rft;
726 dev->cli.xfer_bytes += rft;
731 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
732 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
735 dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;
736 dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
739 /* Master Transaction Done with/without stop */
742 if (dev->cli.operation == I2C_READ) {
743 while (!(readl(dev->virtbase + I2C_RISR)
745 if (dev->cli.count == 0)
748 readb(dev->virtbase + I2C_RFR);
751 dev->cli.xfer_bytes++;
755 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTD);
756 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTDWS);
758 disable_interrupts(dev,
759 (I2C_IT_TXFNE | I2C_IT_TXFE | I2C_IT_TXFF
760 | I2C_IT_TXFOVR | I2C_IT_RXFNF
761 | I2C_IT_RXFF | I2C_IT_RXFE));
763 if (dev->cli.count) {
765 dev_err(&dev->pdev->dev, "%lu bytes still remain to be"
766 "xfered\n", dev->cli.count);
769 complete(&dev->xfer_complete);
773 /* Master Arbitration lost interrupt */
778 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
779 complete(&dev->xfer_complete);
784 * Bus Error interrupt.
785 * This happens when an unexpected start/stop condition occurs
786 * during the transaction.
791 if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
794 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);
795 complete(&dev->xfer_complete);
800 * Tx FIFO overrun interrupt.
801 * This is set when a write operation in Tx FIFO is performed and
802 * the Tx FIFO is full.
808 dev_err(&dev->pdev->dev, "Tx Fifo Over run\n");
809 complete(&dev->xfer_complete);
813 /* unhandled interrupts by this driver - TODO*/
821 dev_err(&dev->pdev->dev, "unhandled Interrupt\n");
824 dev_err(&dev->pdev->dev, "spurious Interrupt..\n");
833 static int nmk_i2c_suspend(struct platform_device *pdev, pm_message_t mesg)
835 struct nmk_i2c_dev *dev = platform_get_drvdata(pdev);
843 #define nmk_i2c_suspend NULL
846 static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
848 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
851 static const struct i2c_algorithm nmk_i2c_algo = {
852 .master_xfer = nmk_i2c_xfer,
853 .functionality = nmk_i2c_functionality
856 static int __devinit nmk_i2c_probe(struct platform_device *pdev)
859 struct resource *res;
860 struct nmk_i2c_controller *pdata =
861 pdev->dev.platform_data;
862 struct nmk_i2c_dev *dev;
863 struct i2c_adapter *adap;
865 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
867 dev_err(&pdev->dev, "cannot allocate memory\n");
873 platform_set_drvdata(pdev, dev);
875 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
878 goto err_no_resource;
881 if (request_mem_region(res->start, resource_size(res),
882 DRIVER_NAME "I/O region") == NULL) {
887 dev->virtbase = ioremap(res->start, resource_size(res));
888 if (!dev->virtbase) {
893 dev->irq = platform_get_irq(pdev, 0);
894 ret = request_irq(dev->irq, i2c_irq_handler, IRQF_DISABLED,
897 dev_err(&pdev->dev, "cannot claim the irq %d\n", dev->irq);
901 dev->regulator = regulator_get(&pdev->dev, "v-i2c");
902 if (IS_ERR(dev->regulator)) {
903 dev_warn(&pdev->dev, "could not get i2c regulator\n");
904 dev->regulator = NULL;
907 dev->clk = clk_get(&pdev->dev, NULL);
908 if (IS_ERR(dev->clk)) {
909 dev_err(&pdev->dev, "could not get i2c clock\n");
910 ret = PTR_ERR(dev->clk);
915 adap->dev.parent = &pdev->dev;
916 adap->owner = THIS_MODULE;
917 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
918 adap->algo = &nmk_i2c_algo;
919 adap->timeout = pdata->timeout ? pdata->timeout : 20000;
920 snprintf(adap->name, sizeof(adap->name),
921 "Nomadik I2C%d at %lx", pdev->id, (unsigned long)res->start);
923 /* fetch the controller id */
926 /* fetch the controller configuration from machine */
927 dev->cfg.clk_freq = pdata->clk_freq;
928 dev->cfg.slsu = pdata->slsu;
929 dev->cfg.tft = pdata->tft;
930 dev->cfg.rft = pdata->rft;
931 dev->cfg.sm = pdata->sm;
933 i2c_set_adapdata(adap, dev);
935 dev_info(&pdev->dev, "initialize %s on virtual "
936 "base %p\n", adap->name, dev->virtbase);
938 ret = i2c_add_numbered_adapter(adap);
940 dev_err(&pdev->dev, "failed to add adapter\n");
950 regulator_put(dev->regulator);
951 free_irq(dev->irq, dev);
953 iounmap(dev->virtbase);
955 release_mem_region(res->start, resource_size(res));
957 platform_set_drvdata(pdev, NULL);
965 static int __devexit nmk_i2c_remove(struct platform_device *pdev)
967 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
968 struct nmk_i2c_dev *dev = platform_get_drvdata(pdev);
970 i2c_del_adapter(&dev->adap);
972 disable_all_interrupts(dev);
973 clear_all_interrupts(dev);
974 /* disable the controller */
975 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
976 free_irq(dev->irq, dev);
977 iounmap(dev->virtbase);
979 release_mem_region(res->start, resource_size(res));
982 regulator_put(dev->regulator);
983 platform_set_drvdata(pdev, NULL);
989 static struct platform_driver nmk_i2c_driver = {
991 .owner = THIS_MODULE,
994 .probe = nmk_i2c_probe,
995 .remove = __devexit_p(nmk_i2c_remove),
996 .suspend = nmk_i2c_suspend,
999 static int __init nmk_i2c_init(void)
1001 return platform_driver_register(&nmk_i2c_driver);
1004 static void __exit nmk_i2c_exit(void)
1006 platform_driver_unregister(&nmk_i2c_driver);
1009 subsys_initcall(nmk_i2c_init);
1010 module_exit(nmk_i2c_exit);
1012 MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR");
1013 MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
1014 MODULE_LICENSE("GPL");
1015 MODULE_ALIAS("platform:" DRIVER_NAME);