2 * Copyright (C) 2009 ST-Ericsson SA
3 * Copyright (C) 2009 STMicroelectronics
5 * I2C master mode controller driver, used in Nomadik 8815
8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
9 * Author: Sachin Verma <sachin.verma@st.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2, as
13 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/interrupt.h>
20 #include <linux/i2c.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/pm_runtime.h>
29 #define DRIVER_NAME "nmk-i2c"
31 /* I2C Controller register offsets */
32 #define I2C_CR (0x000)
33 #define I2C_SCR (0x004)
34 #define I2C_HSMCR (0x008)
35 #define I2C_MCR (0x00C)
36 #define I2C_TFR (0x010)
37 #define I2C_SR (0x014)
38 #define I2C_RFR (0x018)
39 #define I2C_TFTR (0x01C)
40 #define I2C_RFTR (0x020)
41 #define I2C_DMAR (0x024)
42 #define I2C_BRCR (0x028)
43 #define I2C_IMSCR (0x02C)
44 #define I2C_RISR (0x030)
45 #define I2C_MISR (0x034)
46 #define I2C_ICR (0x038)
48 /* Control registers */
49 #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */
50 #define I2C_CR_OM (0x3 << 1) /* Operating mode */
51 #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */
52 #define I2C_CR_SM (0x3 << 4) /* Speed mode */
53 #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */
54 #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */
55 #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */
56 #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */
57 #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */
58 #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */
59 #define I2C_CR_LM (0x1 << 12) /* Loopback mode */
60 #define I2C_CR_FON (0x3 << 13) /* Filtering on */
61 #define I2C_CR_FS (0x3 << 15) /* Force stop enable */
63 /* Master controller (MCR) register */
64 #define I2C_MCR_OP (0x1 << 0) /* Operation */
65 #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */
66 #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */
67 #define I2C_MCR_SB (0x1 << 11) /* Extended address */
68 #define I2C_MCR_AM (0x3 << 12) /* Address type */
69 #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */
70 #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */
72 /* Status register (SR) */
73 #define I2C_SR_OP (0x3 << 0) /* Operation */
74 #define I2C_SR_STATUS (0x3 << 2) /* controller status */
75 #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */
76 #define I2C_SR_TYPE (0x3 << 7) /* Receive type */
77 #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */
79 /* Interrupt mask set/clear (IMSCR) bits */
80 #define I2C_IT_TXFE (0x1 << 0)
81 #define I2C_IT_TXFNE (0x1 << 1)
82 #define I2C_IT_TXFF (0x1 << 2)
83 #define I2C_IT_TXFOVR (0x1 << 3)
84 #define I2C_IT_RXFE (0x1 << 4)
85 #define I2C_IT_RXFNF (0x1 << 5)
86 #define I2C_IT_RXFF (0x1 << 6)
87 #define I2C_IT_RFSR (0x1 << 16)
88 #define I2C_IT_RFSE (0x1 << 17)
89 #define I2C_IT_WTSR (0x1 << 18)
90 #define I2C_IT_MTD (0x1 << 19)
91 #define I2C_IT_STD (0x1 << 20)
92 #define I2C_IT_MAL (0x1 << 24)
93 #define I2C_IT_BERR (0x1 << 25)
94 #define I2C_IT_MTDWS (0x1 << 28)
96 #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask))
98 /* some bits in ICR are reserved */
99 #define I2C_CLEAR_ALL_INTS 0x131f007f
101 /* first three msb bits are reserved */
102 #define IRQ_MASK(mask) (mask & 0x1fffffff)
104 /* maximum threshold value */
105 #define MAX_I2C_FIFO_THRESHOLD 15
116 I2C_NO_OPERATION = 0xff,
122 * struct i2c_nmk_client - client specific data
123 * @slave_adr: 7-bit slave address
124 * @count: no. bytes to be transferred
125 * @buffer: client data buffer
126 * @xfer_bytes: bytes transferred till now
127 * @operation: current I2C operation
129 struct i2c_nmk_client {
130 unsigned short slave_adr;
132 unsigned char *buffer;
133 unsigned long xfer_bytes;
134 enum i2c_operation operation;
138 * struct nmk_i2c_dev - private data structure of the controller
139 * @pdev: parent platform device
140 * @adap: corresponding I2C adapter
141 * @irq: interrupt line for the controller
142 * @virtbase: virtual io memory area
143 * @clk: hardware i2c block clock
144 * @cfg: machine provided controller configuration
145 * @cli: holder of client specific data
146 * @stop: stop condition
147 * @xfer_complete: acknowledge completion for a I2C message
148 * @result: controller propogated result
149 * @busy: Busy doing transfer
152 struct platform_device *pdev;
153 struct i2c_adapter adap;
155 void __iomem *virtbase;
157 struct nmk_i2c_controller cfg;
158 struct i2c_nmk_client cli;
160 struct completion xfer_complete;
162 struct regulator *regulator;
166 /* controller's abort causes */
167 static const char *abort_causes[] = {
168 "no ack received after address transmission",
169 "no ack received during data phase",
170 "ack received after xmission of master code",
171 "master lost arbitration",
174 "overflow, maxsize is 2047 bytes",
177 static inline void i2c_set_bit(void __iomem *reg, u32 mask)
179 writel(readl(reg) | mask, reg);
182 static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
184 writel(readl(reg) & ~mask, reg);
188 * flush_i2c_fifo() - This function flushes the I2C FIFO
189 * @dev: private data of I2C Driver
191 * This function flushes the I2C Tx and Rx FIFOs. It returns
192 * 0 on successful flushing of FIFO
194 static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
196 #define LOOP_ATTEMPTS 10
198 unsigned long timeout;
201 * flush the transmit and receive FIFO. The flushing
202 * operation takes several cycles before to be completed.
203 * On the completion, the I2C internal logic clears these
204 * bits, until then no one must access Tx, Rx FIFO and
205 * should poll on these bits waiting for the completion.
207 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
209 for (i = 0; i < LOOP_ATTEMPTS; i++) {
210 timeout = jiffies + dev->adap.timeout;
212 while (!time_after(jiffies, timeout)) {
213 if ((readl(dev->virtbase + I2C_CR) &
214 (I2C_CR_FTX | I2C_CR_FRX)) == 0)
219 dev_err(&dev->pdev->dev, "flushing operation timed out "
220 "giving up after %d attempts", LOOP_ATTEMPTS);
226 * disable_all_interrupts() - Disable all interrupts of this I2c Bus
227 * @dev: private data of I2C Driver
229 static void disable_all_interrupts(struct nmk_i2c_dev *dev)
231 u32 mask = IRQ_MASK(0);
232 writel(mask, dev->virtbase + I2C_IMSCR);
236 * clear_all_interrupts() - Clear all interrupts of I2C Controller
237 * @dev: private data of I2C Driver
239 static void clear_all_interrupts(struct nmk_i2c_dev *dev)
242 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
243 writel(mask, dev->virtbase + I2C_ICR);
247 * init_hw() - initialize the I2C hardware
248 * @dev: private data of I2C Driver
250 static int init_hw(struct nmk_i2c_dev *dev)
254 stat = flush_i2c_fifo(dev);
258 /* disable the controller */
259 i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
261 disable_all_interrupts(dev);
263 clear_all_interrupts(dev);
265 dev->cli.operation = I2C_NO_OPERATION;
271 /* enable peripheral, master mode operation */
272 #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE)
275 * load_i2c_mcr_reg() - load the MCR register
276 * @dev: private data of controller
278 static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev)
282 /* 7-bit address transaction */
283 mcr |= GEN_MASK(1, I2C_MCR_AM, 12);
284 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);
286 /* start byte procedure not applied */
287 mcr |= GEN_MASK(0, I2C_MCR_SB, 11);
289 /* check the operation, master read/write? */
290 if (dev->cli.operation == I2C_WRITE)
291 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0);
293 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0);
295 /* stop or repeated start? */
297 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14);
299 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14));
301 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);
307 * setup_i2c_controller() - setup the controller
308 * @dev: private data of controller
310 static void setup_i2c_controller(struct nmk_i2c_dev *dev)
315 writel(0x0, dev->virtbase + I2C_CR);
316 writel(0x0, dev->virtbase + I2C_HSMCR);
317 writel(0x0, dev->virtbase + I2C_TFTR);
318 writel(0x0, dev->virtbase + I2C_RFTR);
319 writel(0x0, dev->virtbase + I2C_DMAR);
324 * slsu defines the data setup time after SCL clock
325 * stretching in terms of i2c clk cycles. The
326 * needed setup time for the three modes are 250ns,
327 * 100ns, 10ns respectively thus leading to the values
328 * of 14, 6, 2 for a 48 MHz i2c clk.
330 writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR);
332 i2c_clk = clk_get_rate(dev->clk);
334 /* fallback to std. mode if machine has not provided it */
335 if (dev->cfg.clk_freq == 0)
336 dev->cfg.clk_freq = 100000;
339 * The spec says, in case of std. mode the divider is
340 * 2 whereas it is 3 for fast and fastplus mode of
341 * operation. TODO - high speed support.
343 div = (dev->cfg.clk_freq > 100000) ? 3 : 2;
346 * generate the mask for baud rate counters. The controller
347 * has two baud rate counters. One is used for High speed
348 * operation, and the other is for std, fast mode, fast mode
349 * plus operation. Currently we do not supprt high speed mode
353 brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff;
355 /* set the baud rate counter register */
356 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
359 * set the speed mode. Currently we support
360 * only standard and fast mode of operation
361 * TODO - support for fast mode plus (up to 1Mb/s)
362 * and high speed (up to 3.4 Mb/s)
364 if (dev->cfg.sm > I2C_FREQ_MODE_FAST) {
365 dev_err(&dev->pdev->dev, "do not support this mode "
366 "defaulting to std. mode\n");
367 brcr2 = i2c_clk/(100000 * 2) & 0xffff;
368 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
369 writel(I2C_FREQ_MODE_STANDARD << 4,
370 dev->virtbase + I2C_CR);
372 writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR);
374 /* set the Tx and Rx FIFO threshold */
375 writel(dev->cfg.tft, dev->virtbase + I2C_TFTR);
376 writel(dev->cfg.rft, dev->virtbase + I2C_RFTR);
380 * read_i2c() - Read from I2C client device
381 * @dev: private data of I2C Driver
383 * This function reads from i2c client device when controller is in
384 * master mode. There is a completion timeout. If there is no transfer
385 * before timeout error is returned.
387 static int read_i2c(struct nmk_i2c_dev *dev)
394 mcr = load_i2c_mcr_reg(dev);
395 writel(mcr, dev->virtbase + I2C_MCR);
397 /* load the current CR value */
398 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
399 dev->virtbase + I2C_CR);
401 /* enable the controller */
402 i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
404 init_completion(&dev->xfer_complete);
406 /* enable interrupts by setting the mask */
407 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
408 I2C_IT_MAL | I2C_IT_BERR);
411 irq_mask |= I2C_IT_MTD;
413 irq_mask |= I2C_IT_MTDWS;
415 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
417 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
418 dev->virtbase + I2C_IMSCR);
420 timeout = wait_for_completion_interruptible_timeout(
421 &dev->xfer_complete, dev->adap.timeout);
424 dev_err(&dev->pdev->dev,
425 "wait_for_completion_interruptible_timeout"
426 "returned %d waiting for event\n", timeout);
431 /* Controller timed out */
432 dev_err(&dev->pdev->dev, "read from slave 0x%x timed out\n",
439 static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes)
443 for (count = (no_bytes - 2);
445 (dev->cli.count != 0);
447 /* write to the Tx FIFO */
448 writeb(*dev->cli.buffer,
449 dev->virtbase + I2C_TFR);
452 dev->cli.xfer_bytes++;
458 * write_i2c() - Write data to I2C client.
459 * @dev: private data of I2C Driver
461 * This function writes data to I2C client
463 static int write_i2c(struct nmk_i2c_dev *dev)
470 mcr = load_i2c_mcr_reg(dev);
472 writel(mcr, dev->virtbase + I2C_MCR);
474 /* load the current CR value */
475 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
476 dev->virtbase + I2C_CR);
478 /* enable the controller */
479 i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
481 init_completion(&dev->xfer_complete);
483 /* enable interrupts by settings the masks */
484 irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR);
486 /* Fill the TX FIFO with transmit data */
487 fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD);
489 if (dev->cli.count != 0)
490 irq_mask |= I2C_IT_TXFNE;
493 * check if we want to transfer a single or multiple bytes, if so
494 * set the MTDWS bit (Master Transaction Done Without Stop)
495 * to start repeated start operation
498 irq_mask |= I2C_IT_MTD;
500 irq_mask |= I2C_IT_MTDWS;
502 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
504 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
505 dev->virtbase + I2C_IMSCR);
507 timeout = wait_for_completion_interruptible_timeout(
508 &dev->xfer_complete, dev->adap.timeout);
511 dev_err(&dev->pdev->dev,
512 "wait_for_completion_interruptible_timeout"
513 "returned %d waiting for event\n", timeout);
518 /* Controller timed out */
519 dev_err(&dev->pdev->dev, "write to slave 0x%x timed out\n",
528 * nmk_i2c_xfer() - I2C transfer function used by kernel framework
529 * @i2c_adap: Adapter pointer to the controller
530 * @msgs: Pointer to data to be written.
531 * @num_msgs: Number of messages to be executed
533 * This is the function called by the generic kernel i2c_transfer()
534 * or i2c_smbus...() API calls. Note that this code is protected by the
535 * semaphore set in the kernel i2c_transfer() function.
538 * READ TRANSFER : We impose a restriction of the first message to be the
539 * index message for any read transaction.
540 * - a no index is coded as '0',
541 * - 2byte big endian index is coded as '3'
542 * !!! msg[0].buf holds the actual index.
543 * This is compatible with generic messages of smbus emulator
544 * that send a one byte index.
545 * eg. a I2C transation to read 2 bytes from index 0
547 * msg[0].addr = client->addr;
548 * msg[0].flags = 0x0;
552 * msg[1].addr = client->addr;
553 * msg[1].flags = I2C_M_RD;
555 * msg[1].buf = rd_buff
556 * i2c_transfer(adap, msg, 2);
558 * WRITE TRANSFER : The I2C standard interface interprets all data as payload.
559 * If you want to emulate an SMBUS write transaction put the
560 * index as first byte(or first and second) in the payload.
561 * eg. a I2C transation to write 2 bytes from index 1
565 * msg[0].flags = 0x0;
567 * msg[0].buf = wr_buff;
568 * i2c_transfer(adap, msg, 1);
570 * To read or write a block of data (multiple bytes) using SMBUS emulation
571 * please use the i2c_smbus_read_i2c_block_data()
572 * or i2c_smbus_write_i2c_block_data() API
574 static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
575 struct i2c_msg msgs[], int num_msgs)
580 struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
587 regulator_enable(dev->regulator);
588 pm_runtime_get_sync(&dev->pdev->dev);
590 clk_enable(dev->clk);
592 status = init_hw(dev);
596 for (j = 0; j < 3; j++) {
597 /* setup the i2c controller */
598 setup_i2c_controller(dev);
600 for (i = 0; i < num_msgs; i++) {
601 if (unlikely(msgs[i].flags & I2C_M_TEN)) {
602 dev_err(&dev->pdev->dev, "10 bit addressing"
608 dev->cli.slave_adr = msgs[i].addr;
609 dev->cli.buffer = msgs[i].buf;
610 dev->cli.count = msgs[i].len;
611 dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
614 if (msgs[i].flags & I2C_M_RD) {
615 /* it is a read operation */
616 dev->cli.operation = I2C_READ;
617 status = read_i2c(dev);
619 /* write operation */
620 dev->cli.operation = I2C_WRITE;
621 status = write_i2c(dev);
623 if (status || (dev->result)) {
624 i2c_sr = readl(dev->virtbase + I2C_SR);
626 * Check if the controller I2C operation status
627 * is set to ABORT(11b).
629 if (((i2c_sr >> 2) & 0x3) == 0x3) {
630 /* get the abort cause */
631 cause = (i2c_sr >> 4)
633 dev_err(&dev->pdev->dev, "%s\n", cause
634 >= ARRAY_SIZE(abort_causes) ?
636 abort_causes[cause]);
641 status = status ? status : dev->result;
651 clk_disable(dev->clk);
652 pm_runtime_put_sync(&dev->pdev->dev);
654 regulator_disable(dev->regulator);
658 /* return the no. messages processed */
666 * disable_interrupts() - disable the interrupts
667 * @dev: private data of controller
668 * @irq: interrupt number
670 static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
673 writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
674 dev->virtbase + I2C_IMSCR);
679 * i2c_irq_handler() - interrupt routine
680 * @irq: interrupt number
681 * @arg: data passed to the handler
683 * This is the interrupt handler for the i2c driver. Currently
684 * it handles the major interrupts like Rx & Tx FIFO management
685 * interrupts, master transaction interrupts, arbitration and
686 * bus error interrupts. The rest of the interrupts are treated as
689 static irqreturn_t i2c_irq_handler(int irq, void *arg)
691 struct nmk_i2c_dev *dev = arg;
697 /* load Tx FIFO and Rx FIFO threshold values */
698 tft = readl(dev->virtbase + I2C_TFTR);
699 rft = readl(dev->virtbase + I2C_RFTR);
701 /* read interrupt status register */
702 misr = readl(dev->virtbase + I2C_MISR);
705 switch ((1 << src)) {
707 /* Transmit FIFO nearly empty interrupt */
710 if (dev->cli.operation == I2C_READ) {
712 * in read operation why do we care for writing?
713 * so disable the Transmit FIFO interrupt
715 disable_interrupts(dev, I2C_IT_TXFNE);
717 fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft));
719 * if done, close the transfer by disabling the
720 * corresponding TXFNE interrupt
722 if (dev->cli.count == 0)
723 disable_interrupts(dev, I2C_IT_TXFNE);
729 * Rx FIFO nearly full interrupt.
730 * This is set when the numer of entries in Rx FIFO is
731 * greater or equal than the threshold value programmed
735 for (count = rft; count > 0; count--) {
736 /* Read the Rx FIFO */
737 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
740 dev->cli.count -= rft;
741 dev->cli.xfer_bytes += rft;
746 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
747 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
750 dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;
751 dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
754 /* Master Transaction Done with/without stop */
757 if (dev->cli.operation == I2C_READ) {
758 while (!(readl(dev->virtbase + I2C_RISR)
760 if (dev->cli.count == 0)
763 readb(dev->virtbase + I2C_RFR);
766 dev->cli.xfer_bytes++;
770 disable_all_interrupts(dev);
771 clear_all_interrupts(dev);
773 if (dev->cli.count) {
775 dev_err(&dev->pdev->dev, "%lu bytes still remain to be"
776 "xfered\n", dev->cli.count);
779 complete(&dev->xfer_complete);
783 /* Master Arbitration lost interrupt */
788 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
789 complete(&dev->xfer_complete);
794 * Bus Error interrupt.
795 * This happens when an unexpected start/stop condition occurs
796 * during the transaction.
801 if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
804 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);
805 complete(&dev->xfer_complete);
810 * Tx FIFO overrun interrupt.
811 * This is set when a write operation in Tx FIFO is performed and
812 * the Tx FIFO is full.
818 dev_err(&dev->pdev->dev, "Tx Fifo Over run\n");
819 complete(&dev->xfer_complete);
823 /* unhandled interrupts by this driver - TODO*/
831 dev_err(&dev->pdev->dev, "unhandled Interrupt\n");
834 dev_err(&dev->pdev->dev, "spurious Interrupt..\n");
843 static int nmk_i2c_suspend(struct device *dev)
845 struct platform_device *pdev = to_platform_device(dev);
846 struct nmk_i2c_dev *nmk_i2c = platform_get_drvdata(pdev);
854 static int nmk_i2c_resume(struct device *dev)
859 #define nmk_i2c_suspend NULL
860 #define nmk_i2c_resume NULL
864 * We use noirq so that we suspend late and resume before the wakeup interrupt
865 * to ensure that we do the !pm_runtime_suspended() check in resume before
866 * there has been a regular pm runtime resume (via pm_runtime_get_sync()).
868 static const struct dev_pm_ops nmk_i2c_pm = {
869 .suspend_noirq = nmk_i2c_suspend,
870 .resume_noirq = nmk_i2c_resume,
873 static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
875 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
878 static const struct i2c_algorithm nmk_i2c_algo = {
879 .master_xfer = nmk_i2c_xfer,
880 .functionality = nmk_i2c_functionality
883 static int __devinit nmk_i2c_probe(struct platform_device *pdev)
886 struct resource *res;
887 struct nmk_i2c_controller *pdata =
888 pdev->dev.platform_data;
889 struct nmk_i2c_dev *dev;
890 struct i2c_adapter *adap;
892 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
894 dev_err(&pdev->dev, "cannot allocate memory\n");
900 platform_set_drvdata(pdev, dev);
902 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
905 goto err_no_resource;
908 if (request_mem_region(res->start, resource_size(res),
909 DRIVER_NAME "I/O region") == NULL) {
914 dev->virtbase = ioremap(res->start, resource_size(res));
915 if (!dev->virtbase) {
920 dev->irq = platform_get_irq(pdev, 0);
921 ret = request_irq(dev->irq, i2c_irq_handler, IRQF_DISABLED,
924 dev_err(&pdev->dev, "cannot claim the irq %d\n", dev->irq);
928 dev->regulator = regulator_get(&pdev->dev, "v-i2c");
929 if (IS_ERR(dev->regulator)) {
930 dev_warn(&pdev->dev, "could not get i2c regulator\n");
931 dev->regulator = NULL;
934 pm_suspend_ignore_children(&pdev->dev, true);
935 pm_runtime_enable(&pdev->dev);
937 dev->clk = clk_get(&pdev->dev, NULL);
938 if (IS_ERR(dev->clk)) {
939 dev_err(&pdev->dev, "could not get i2c clock\n");
940 ret = PTR_ERR(dev->clk);
945 adap->dev.parent = &pdev->dev;
946 adap->owner = THIS_MODULE;
947 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
948 adap->algo = &nmk_i2c_algo;
949 adap->timeout = pdata->timeout ? msecs_to_jiffies(pdata->timeout) :
950 msecs_to_jiffies(20000);
951 snprintf(adap->name, sizeof(adap->name),
952 "Nomadik I2C%d at %lx", pdev->id, (unsigned long)res->start);
954 /* fetch the controller id */
957 /* fetch the controller configuration from machine */
958 dev->cfg.clk_freq = pdata->clk_freq;
959 dev->cfg.slsu = pdata->slsu;
960 dev->cfg.tft = pdata->tft;
961 dev->cfg.rft = pdata->rft;
962 dev->cfg.sm = pdata->sm;
964 i2c_set_adapdata(adap, dev);
966 dev_info(&pdev->dev, "initialize %s on virtual "
967 "base %p\n", adap->name, dev->virtbase);
969 ret = i2c_add_numbered_adapter(adap);
971 dev_err(&pdev->dev, "failed to add adapter\n");
981 regulator_put(dev->regulator);
982 pm_runtime_disable(&pdev->dev);
983 free_irq(dev->irq, dev);
985 iounmap(dev->virtbase);
987 release_mem_region(res->start, resource_size(res));
989 platform_set_drvdata(pdev, NULL);
997 static int __devexit nmk_i2c_remove(struct platform_device *pdev)
999 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1000 struct nmk_i2c_dev *dev = platform_get_drvdata(pdev);
1002 i2c_del_adapter(&dev->adap);
1003 flush_i2c_fifo(dev);
1004 disable_all_interrupts(dev);
1005 clear_all_interrupts(dev);
1006 /* disable the controller */
1007 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
1008 free_irq(dev->irq, dev);
1009 iounmap(dev->virtbase);
1011 release_mem_region(res->start, resource_size(res));
1014 regulator_put(dev->regulator);
1015 pm_runtime_disable(&pdev->dev);
1016 platform_set_drvdata(pdev, NULL);
1022 static struct platform_driver nmk_i2c_driver = {
1024 .owner = THIS_MODULE,
1025 .name = DRIVER_NAME,
1028 .probe = nmk_i2c_probe,
1029 .remove = __devexit_p(nmk_i2c_remove),
1032 static int __init nmk_i2c_init(void)
1034 return platform_driver_register(&nmk_i2c_driver);
1037 static void __exit nmk_i2c_exit(void)
1039 platform_driver_unregister(&nmk_i2c_driver);
1042 subsys_initcall(nmk_i2c_init);
1043 module_exit(nmk_i2c_exit);
1045 MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR");
1046 MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
1047 MODULE_LICENSE("GPL");
1048 MODULE_ALIAS("platform:" DRIVER_NAME);