drivers/i2c/busses/i2c-davinci.c

   1 /*
   2  * TI DAVINCI I2C adapter driver.
   3  *
   4  * Copyright (C) 2006 Texas Instruments.
   5  * Copyright (C) 2007 MontaVista Software Inc.
   6  *
   7  * Updated by Vinod & Sudhakar Feb 2005
   8  *
   9  * ----------------------------------------------------------------------------
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  * ----------------------------------------------------------------------------
  25  *
  26  */
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/i2c.h>
  31 #include <linux/clk.h>
  32 #include <linux/errno.h>
  33 #include <linux/sched.h>
  34 #include <linux/err.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/io.h>
  38
  39 #include <mach/hardware.h>
  40
  41 #include <mach/i2c.h>
  42
  43 /* ----- global defines ----------------------------------------------- */
  44
  45 #define DAVINCI_I2C_TIMEOUT     (1*HZ)
  46 #define I2C_DAVINCI_INTR_ALL    (DAVINCI_I2C_IMR_AAS | \
  47                                  DAVINCI_I2C_IMR_SCD | \
  48                                  DAVINCI_I2C_IMR_ARDY | \
  49                                  DAVINCI_I2C_IMR_NACK | \
  50                                  DAVINCI_I2C_IMR_AL)
  51
  52 #define DAVINCI_I2C_OAR_REG     0x00
  53 #define DAVINCI_I2C_IMR_REG     0x04
  54 #define DAVINCI_I2C_STR_REG     0x08
  55 #define DAVINCI_I2C_CLKL_REG    0x0c
  56 #define DAVINCI_I2C_CLKH_REG    0x10
  57 #define DAVINCI_I2C_CNT_REG     0x14
  58 #define DAVINCI_I2C_DRR_REG     0x18
  59 #define DAVINCI_I2C_SAR_REG     0x1c
  60 #define DAVINCI_I2C_DXR_REG     0x20
  61 #define DAVINCI_I2C_MDR_REG     0x24
  62 #define DAVINCI_I2C_IVR_REG     0x28
  63 #define DAVINCI_I2C_EMDR_REG    0x2c
  64 #define DAVINCI_I2C_PSC_REG     0x30
  65
  66 #define DAVINCI_I2C_IVR_AAS     0x07
  67 #define DAVINCI_I2C_IVR_SCD     0x06
  68 #define DAVINCI_I2C_IVR_XRDY    0x05
  69 #define DAVINCI_I2C_IVR_RDR     0x04
  70 #define DAVINCI_I2C_IVR_ARDY    0x03
  71 #define DAVINCI_I2C_IVR_NACK    0x02
  72 #define DAVINCI_I2C_IVR_AL      0x01
  73
  74 #define DAVINCI_I2C_STR_BB      (1 << 12)
  75 #define DAVINCI_I2C_STR_RSFULL  (1 << 11)
  76 #define DAVINCI_I2C_STR_SCD     (1 << 5)
  77 #define DAVINCI_I2C_STR_ARDY    (1 << 2)
  78 #define DAVINCI_I2C_STR_NACK    (1 << 1)
  79 #define DAVINCI_I2C_STR_AL      (1 << 0)
  80
  81 #define DAVINCI_I2C_MDR_NACK    (1 << 15)
  82 #define DAVINCI_I2C_MDR_STT     (1 << 13)
  83 #define DAVINCI_I2C_MDR_STP     (1 << 11)
  84 #define DAVINCI_I2C_MDR_MST     (1 << 10)
  85 #define DAVINCI_I2C_MDR_TRX     (1 << 9)
  86 #define DAVINCI_I2C_MDR_XA      (1 << 8)
  87 #define DAVINCI_I2C_MDR_RM      (1 << 7)
  88 #define DAVINCI_I2C_MDR_IRS     (1 << 5)
  89
  90 #define DAVINCI_I2C_IMR_AAS     (1 << 6)
  91 #define DAVINCI_I2C_IMR_SCD     (1 << 5)
  92 #define DAVINCI_I2C_IMR_XRDY    (1 << 4)
  93 #define DAVINCI_I2C_IMR_RRDY    (1 << 3)
  94 #define DAVINCI_I2C_IMR_ARDY    (1 << 2)
  95 #define DAVINCI_I2C_IMR_NACK    (1 << 1)
  96 #define DAVINCI_I2C_IMR_AL      (1 << 0)
  97
  98 #define MOD_REG_BIT(val, mask, set) do { \
  99         if (set) { \
 100                 val |= mask; \
 101         } else { \
 102                 val &= ~mask; \
 103         } \
 104 } while (0)
 105
 106 struct davinci_i2c_dev {
 107         struct device           *dev;
 108         void __iomem            *base;
 109         struct completion       cmd_complete;
 110         struct clk              *clk;
 111         int                     cmd_err;
 112         u8                      *buf;
 113         size_t                  buf_len;
 114         int                     irq;
 115         u8                      terminate;
 116         struct i2c_adapter      adapter;
 117 };
 118
 119 /* default platform data to use if not supplied in the platform_device */
 120 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
 121         .bus_freq       = 100,
 122         .bus_delay      = 0,
 123 };
 124
 125 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
 126                                          int reg, u16 val)
 127 {
 128         __raw_writew(val, i2c_dev->base + reg);
 129 }
 130
 131 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
 132 {
 133         return __raw_readw(i2c_dev->base + reg);
 134 }
 135
 136 /*
 137  * This functions configures I2C and brings I2C out of reset.
 138  * This function is called during I2C init function. This function
 139  * also gets called if I2C encounters any errors.
 140  */
 141 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
 142 {
 143         struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
 144         u16 psc;
 145         u32 clk;
 146         u32 d;
 147         u32 clkh;
 148         u32 clkl;
 149         u32 input_clock = clk_get_rate(dev->clk);
 150         u16 w;
 151
 152         if (!pdata)
 153                 pdata = &davinci_i2c_platform_data_default;
 154
 155         /* put I2C into reset */
 156         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 157         MOD_REG_BIT(w, DAVINCI_I2C_MDR_IRS, 0);
 158         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 159
 160         /* NOTE: I2C Clock divider programming info
 161          * As per I2C specs the following formulas provide prescaler
 162          * and low/high divider values
 163          * input clk --> PSC Div -----------> ICCL/H Div --> output clock
 164          *                       module clk
 165          *
 166          * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
 167          *
 168          * Thus,
 169          * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
 170          *
 171          * where if PSC == 0, d = 7,
 172          *       if PSC == 1, d = 6
 173          *       if PSC > 1 , d = 5
 174          */
 175
 176         /* get minimum of 7 MHz clock, but max of 12 MHz */
 177         psc = (input_clock / 7000000) - 1;
 178         if ((input_clock / (psc + 1)) > 12000000)
 179                 psc++;  /* better to run under spec than over */
 180         d = (psc >= 2) ? 5 : 7 - psc;
 181
 182         clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1);
 183         clkh = clk >> 1;
 184         clkl = clk - clkh;
 185
 186         davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
 187         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
 188         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
 189
 190         /* Respond at reserved "SMBus Host" slave address" (and zero);
 191          * we seem to have no option to not respond...
 192          */
 193         davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08);
 194
 195         dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
 196         dev_dbg(dev->dev, "PSC  = %d\n",
 197                 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
 198         dev_dbg(dev->dev, "CLKL = %d\n",
 199                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
 200         dev_dbg(dev->dev, "CLKH = %d\n",
 201                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
 202         dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
 203                 pdata->bus_freq, pdata->bus_delay);
 204
 205         /* Take the I2C module out of reset: */
 206         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 207         MOD_REG_BIT(w, DAVINCI_I2C_MDR_IRS, 1);
 208         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 209
 210         /* Enable interrupts */
 211         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
 212
 213         return 0;
 214 }
 215
 216 /*
 217  * Waiting for bus not busy
 218  */
 219 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
 220                                          char allow_sleep)
 221 {
 222         unsigned long timeout;
 223
 224         timeout = jiffies + dev->adapter.timeout;
 225         while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
 226                & DAVINCI_I2C_STR_BB) {
 227                 if (time_after(jiffies, timeout)) {
 228                         dev_warn(dev->dev,
 229                                  "timeout waiting for bus ready\n");
 230                         return -ETIMEDOUT;
 231                 }
 232                 if (allow_sleep)
 233                         schedule_timeout(1);
 234         }
 235
 236         return 0;
 237 }
 238
 239 /*
 240  * Low level master read/write transaction. This function is called
 241  * from i2c_davinci_xfer.
 242  */
 243 static int
 244 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
 245 {
 246         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 247         struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
 248         u32 flag;
 249         u16 w;
 250         int r;
 251
 252         if (msg->len == 0)
 253                 return -EINVAL;
 254
 255         if (!pdata)
 256                 pdata = &davinci_i2c_platform_data_default;
 257         /* Introduce a delay, required for some boards (e.g Davinci EVM) */
 258         if (pdata->bus_delay)
 259                 udelay(pdata->bus_delay);
 260
 261         /* set the slave address */
 262         davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
 263
 264         dev->buf = msg->buf;
 265         dev->buf_len = msg->len;
 266
 267         davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
 268
 269         INIT_COMPLETION(dev->cmd_complete);
 270         dev->cmd_err = 0;
 271
 272         /* Take I2C out of reset, configure it as master and set the
 273          * start bit */
 274         flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST | DAVINCI_I2C_MDR_STT;
 275
 276         /* if the slave address is ten bit address, enable XA bit */
 277         if (msg->flags & I2C_M_TEN)
 278                 flag |= DAVINCI_I2C_MDR_XA;
 279         if (!(msg->flags & I2C_M_RD))
 280                 flag |= DAVINCI_I2C_MDR_TRX;
 281         if (stop)
 282                 flag |= DAVINCI_I2C_MDR_STP;
 283
 284         /* Enable receive or transmit interrupts */
 285         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
 286         if (msg->flags & I2C_M_RD)
 287                 MOD_REG_BIT(w, DAVINCI_I2C_IMR_RRDY, 1);
 288         else
 289                 MOD_REG_BIT(w, DAVINCI_I2C_IMR_XRDY, 1);
 290         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
 291
 292         dev->terminate = 0;
 293         /* write the data into mode register */
 294         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 295
 296         r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
 297                                                       dev->adapter.timeout);
 298         if (r == 0) {
 299                 dev_err(dev->dev, "controller timed out\n");
 300                 i2c_davinci_init(dev);
 301                 dev->buf_len = 0;
 302                 return -ETIMEDOUT;
 303         }
 304         if (dev->buf_len) {
 305                 /* This should be 0 if all bytes were transferred
 306                  * or dev->cmd_err denotes an error.
 307                  * A signal may have aborted the transfer.
 308                  */
 309                 if (r >= 0) {
 310                         dev_err(dev->dev, "abnormal termination buf_len=%i\n",
 311                                 dev->buf_len);
 312                         r = -EREMOTEIO;
 313                 }
 314                 dev->terminate = 1;
 315                 wmb();
 316                 dev->buf_len = 0;
 317         }
 318         if (r < 0)
 319                 return r;
 320
 321         /* no error */
 322         if (likely(!dev->cmd_err))
 323                 return msg->len;
 324
 325         /* We have an error */
 326         if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
 327                 i2c_davinci_init(dev);
 328                 return -EIO;
 329         }
 330
 331         if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
 332                 if (msg->flags & I2C_M_IGNORE_NAK)
 333                         return msg->len;
 334                 if (stop) {
 335                         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 336                         MOD_REG_BIT(w, DAVINCI_I2C_MDR_STP, 1);
 337                         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 338                 }
 339                 return -EREMOTEIO;
 340         }
 341         return -EIO;
 342 }
 343
 344 /*
 345  * Prepare controller for a transaction and call i2c_davinci_xfer_msg
 346  */
 347 static int
 348 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 349 {
 350         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 351         int i;
 352         int ret;
 353
 354         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 355
 356         ret = i2c_davinci_wait_bus_not_busy(dev, 1);
 357         if (ret < 0) {
 358                 dev_warn(dev->dev, "timeout waiting for bus ready\n");
 359                 return ret;
 360         }
 361
 362         for (i = 0; i < num; i++) {
 363                 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 364                 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
 365                         ret);
 366                 if (ret < 0)
 367                         return ret;
 368         }
 369         return num;
 370 }
 371
 372 static u32 i2c_davinci_func(struct i2c_adapter *adap)
 373 {
 374         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 375 }
 376
 377 static void terminate_read(struct davinci_i2c_dev *dev)
 378 {
 379         u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 380         w |= DAVINCI_I2C_MDR_NACK;
 381         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 382
 383         /* Throw away data */
 384         davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
 385         if (!dev->terminate)
 386                 dev_err(dev->dev, "RDR IRQ while no data requested\n");
 387 }
 388 static void terminate_write(struct davinci_i2c_dev *dev)
 389 {
 390         u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 391         w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
 392         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 393
 394         if (!dev->terminate)
 395                 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
 396 }
 397
 398 /*
 399  * Interrupt service routine. This gets called whenever an I2C interrupt
 400  * occurs.
 401  */
 402 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
 403 {
 404         struct davinci_i2c_dev *dev = dev_id;
 405         u32 stat;
 406         int count = 0;
 407         u16 w;
 408
 409         while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
 410                 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
 411                 if (count++ == 100) {
 412                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 413                         break;
 414                 }
 415
 416                 switch (stat) {
 417                 case DAVINCI_I2C_IVR_AL:
 418                         /* Arbitration lost, must retry */
 419                         dev->cmd_err |= DAVINCI_I2C_STR_AL;
 420                         dev->buf_len = 0;
 421                         complete(&dev->cmd_complete);
 422                         break;
 423
 424                 case DAVINCI_I2C_IVR_NACK:
 425                         dev->cmd_err |= DAVINCI_I2C_STR_NACK;
 426                         dev->buf_len = 0;
 427                         complete(&dev->cmd_complete);
 428                         break;
 429
 430                 case DAVINCI_I2C_IVR_ARDY:
 431                         davinci_i2c_write_reg(dev,
 432                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
 433                         complete(&dev->cmd_complete);
 434                         break;
 435
 436                 case DAVINCI_I2C_IVR_RDR:
 437                         if (dev->buf_len) {
 438                                 *dev->buf++ =
 439                                     davinci_i2c_read_reg(dev,
 440                                                          DAVINCI_I2C_DRR_REG);
 441                                 dev->buf_len--;
 442                                 if (dev->buf_len)
 443                                         continue;
 444
 445                                 davinci_i2c_write_reg(dev,
 446                                         DAVINCI_I2C_STR_REG,
 447                                         DAVINCI_I2C_IMR_RRDY);
 448                         } else {
 449                                 /* signal can terminate transfer */
 450                                 terminate_read(dev);
 451                         }
 452                         break;
 453
 454                 case DAVINCI_I2C_IVR_XRDY:
 455                         if (dev->buf_len) {
 456                                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
 457                                                       *dev->buf++);
 458                                 dev->buf_len--;
 459                                 if (dev->buf_len)
 460                                         continue;
 461
 462                                 w = davinci_i2c_read_reg(dev,
 463                                                          DAVINCI_I2C_IMR_REG);
 464                                 MOD_REG_BIT(w, DAVINCI_I2C_IMR_XRDY, 0);
 465                                 davinci_i2c_write_reg(dev,
 466                                                       DAVINCI_I2C_IMR_REG,
 467                                                       w);
 468                         } else {
 469                                 /* signal can terminate transfer */
 470                                 terminate_write(dev);
 471                         }
 472                         break;
 473
 474                 case DAVINCI_I2C_IVR_SCD:
 475                         davinci_i2c_write_reg(dev,
 476                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
 477                         complete(&dev->cmd_complete);
 478                         break;
 479
 480                 case DAVINCI_I2C_IVR_AAS:
 481                         dev_dbg(dev->dev, "Address as slave interrupt\n");
 482                         break;
 483
 484                 default:
 485                         dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
 486                         break;
 487                 }
 488         }
 489
 490         return count ? IRQ_HANDLED : IRQ_NONE;
 491 }
 492
 493 static struct i2c_algorithm i2c_davinci_algo = {
 494         .master_xfer    = i2c_davinci_xfer,
 495         .functionality  = i2c_davinci_func,
 496 };
 497
 498 static int davinci_i2c_probe(struct platform_device *pdev)
 499 {
 500         struct davinci_i2c_dev *dev;
 501         struct i2c_adapter *adap;
 502         struct resource *mem, *irq, *ioarea;
 503         int r;
 504
 505         /* NOTE: driver uses the static register mapping */
 506         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 507         if (!mem) {
 508                 dev_err(&pdev->dev, "no mem resource?\n");
 509                 return -ENODEV;
 510         }
 511
 512         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 513         if (!irq) {
 514                 dev_err(&pdev->dev, "no irq resource?\n");
 515                 return -ENODEV;
 516         }
 517
 518         ioarea = request_mem_region(mem->start, resource_size(mem),
 519                                     pdev->name);
 520         if (!ioarea) {
 521                 dev_err(&pdev->dev, "I2C region already claimed\n");
 522                 return -EBUSY;
 523         }
 524
 525         dev = kzalloc(sizeof(struct davinci_i2c_dev), GFP_KERNEL);
 526         if (!dev) {
 527                 r = -ENOMEM;
 528                 goto err_release_region;
 529         }
 530
 531         init_completion(&dev->cmd_complete);
 532         dev->dev = get_device(&pdev->dev);
 533         dev->irq = irq->start;
 534         platform_set_drvdata(pdev, dev);
 535
 536         dev->clk = clk_get(&pdev->dev, NULL);
 537         if (IS_ERR(dev->clk)) {
 538                 r = -ENODEV;
 539                 goto err_free_mem;
 540         }
 541         clk_enable(dev->clk);
 542
 543         dev->base = (void __iomem *)IO_ADDRESS(mem->start);
 544         i2c_davinci_init(dev);
 545
 546         r = request_irq(dev->irq, i2c_davinci_isr, 0, pdev->name, dev);
 547         if (r) {
 548                 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
 549                 goto err_unuse_clocks;
 550         }
 551
 552         adap = &dev->adapter;
 553         i2c_set_adapdata(adap, dev);
 554         adap->owner = THIS_MODULE;
 555         adap->class = I2C_CLASS_HWMON;
 556         strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
 557         adap->algo = &i2c_davinci_algo;
 558         adap->dev.parent = &pdev->dev;
 559         adap->timeout = DAVINCI_I2C_TIMEOUT;
 560
 561         adap->nr = pdev->id;
 562         r = i2c_add_numbered_adapter(adap);
 563         if (r) {
 564                 dev_err(&pdev->dev, "failure adding adapter\n");
 565                 goto err_free_irq;
 566         }
 567
 568         return 0;
 569
 570 err_free_irq:
 571         free_irq(dev->irq, dev);
 572 err_unuse_clocks:
 573         clk_disable(dev->clk);
 574         clk_put(dev->clk);
 575         dev->clk = NULL;
 576 err_free_mem:
 577         platform_set_drvdata(pdev, NULL);
 578         put_device(&pdev->dev);
 579         kfree(dev);
 580 err_release_region:
 581         release_mem_region(mem->start, resource_size(mem));
 582
 583         return r;
 584 }
 585
 586 static int davinci_i2c_remove(struct platform_device *pdev)
 587 {
 588         struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
 589         struct resource *mem;
 590
 591         platform_set_drvdata(pdev, NULL);
 592         i2c_del_adapter(&dev->adapter);
 593         put_device(&pdev->dev);
 594
 595         clk_disable(dev->clk);
 596         clk_put(dev->clk);
 597         dev->clk = NULL;
 598
 599         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
 600         free_irq(IRQ_I2C, dev);
 601         kfree(dev);
 602
 603         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 604         release_mem_region(mem->start, resource_size(mem));
 605         return 0;
 606 }
 607
 608 /* work with hotplug and coldplug */
 609 MODULE_ALIAS("platform:i2c_davinci");
 610
 611 static struct platform_driver davinci_i2c_driver = {
 612         .probe          = davinci_i2c_probe,
 613         .remove         = davinci_i2c_remove,
 614         .driver         = {
 615                 .name   = "i2c_davinci",
 616                 .owner  = THIS_MODULE,
 617         },
 618 };
 619
 620 /* I2C may be needed to bring up other drivers */
 621 static int __init davinci_i2c_init_driver(void)
 622 {
 623         return platform_driver_register(&davinci_i2c_driver);
 624 }
 625 subsys_initcall(davinci_i2c_init_driver);
 626
 627 static void __exit davinci_i2c_exit_driver(void)
 628 {
 629         platform_driver_unregister(&davinci_i2c_driver);
 630 }
 631 module_exit(davinci_i2c_exit_driver);
 632
 633 MODULE_AUTHOR("Texas Instruments India");
 634 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
 635 MODULE_LICENSE("GPL");