drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

   1 /**************************************************************************
   2  *
   3  * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "drmP.h"
  29 #include "vmwgfx_drv.h"
  30 #include "ttm/ttm_placement.h"
  31 #include "ttm/ttm_bo_driver.h"
  32 #include "ttm/ttm_object.h"
  33 #include "ttm/ttm_module.h"
  34
  35 #define VMWGFX_DRIVER_NAME "vmwgfx"
  36 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
  37 #define VMWGFX_CHIP_SVGAII 0
  38 #define VMW_FB_RESERVATION 0
  39
  40 /**
  41  * Fully encoded drm commands. Might move to vmw_drm.h
  42  */
  43
  44 #define DRM_IOCTL_VMW_GET_PARAM                                 \
  45         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM,          \
  46                  struct drm_vmw_getparam_arg)
  47 #define DRM_IOCTL_VMW_ALLOC_DMABUF                              \
  48         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF,       \
  49                 union drm_vmw_alloc_dmabuf_arg)
  50 #define DRM_IOCTL_VMW_UNREF_DMABUF                              \
  51         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF,        \
  52                 struct drm_vmw_unref_dmabuf_arg)
  53 #define DRM_IOCTL_VMW_CURSOR_BYPASS                             \
  54         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS,       \
  55                  struct drm_vmw_cursor_bypass_arg)
  56
  57 #define DRM_IOCTL_VMW_CONTROL_STREAM                            \
  58         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM,      \
  59                  struct drm_vmw_control_stream_arg)
  60 #define DRM_IOCTL_VMW_CLAIM_STREAM                              \
  61         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM,        \
  62                  struct drm_vmw_stream_arg)
  63 #define DRM_IOCTL_VMW_UNREF_STREAM                              \
  64         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM,        \
  65                  struct drm_vmw_stream_arg)
  66
  67 #define DRM_IOCTL_VMW_CREATE_CONTEXT                            \
  68         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT,      \
  69                 struct drm_vmw_context_arg)
  70 #define DRM_IOCTL_VMW_UNREF_CONTEXT                             \
  71         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT,       \
  72                 struct drm_vmw_context_arg)
  73 #define DRM_IOCTL_VMW_CREATE_SURFACE                            \
  74         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE,     \
  75                  union drm_vmw_surface_create_arg)
  76 #define DRM_IOCTL_VMW_UNREF_SURFACE                             \
  77         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE,       \
  78                  struct drm_vmw_surface_arg)
  79 #define DRM_IOCTL_VMW_REF_SURFACE                               \
  80         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE,        \
  81                  union drm_vmw_surface_reference_arg)
  82 #define DRM_IOCTL_VMW_EXECBUF                                   \
  83         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,             \
  84                 struct drm_vmw_execbuf_arg)
  85 #define DRM_IOCTL_VMW_GET_3D_CAP                                \
  86         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP,          \
  87                  struct drm_vmw_get_3d_cap_arg)
  88 #define DRM_IOCTL_VMW_FENCE_WAIT                                \
  89         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,         \
  90                  struct drm_vmw_fence_wait_arg)
  91 #define DRM_IOCTL_VMW_FENCE_SIGNALED                            \
  92         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED,     \
  93                  struct drm_vmw_fence_signaled_arg)
  94 #define DRM_IOCTL_VMW_FENCE_UNREF                               \
  95         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF,         \
  96                  struct drm_vmw_fence_arg)
  97
  98 /**
  99  * The core DRM version of this macro doesn't account for
 100  * DRM_COMMAND_BASE.
 101  */
 102
 103 #define VMW_IOCTL_DEF(ioctl, func, flags) \
 104   [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
 105
 106 /**
 107  * Ioctl definitions.
 108  */
 109
 110 static struct drm_ioctl_desc vmw_ioctls[] = {
 111         VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
 112                       DRM_AUTH | DRM_UNLOCKED),
 113         VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
 114                       DRM_AUTH | DRM_UNLOCKED),
 115         VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
 116                       DRM_AUTH | DRM_UNLOCKED),
 117         VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
 118                       vmw_kms_cursor_bypass_ioctl,
 119                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 120
 121         VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
 122                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 123         VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
 124                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 125         VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
 126                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 127
 128         VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
 129                       DRM_AUTH | DRM_UNLOCKED),
 130         VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
 131                       DRM_AUTH | DRM_UNLOCKED),
 132         VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
 133                       DRM_AUTH | DRM_UNLOCKED),
 134         VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
 135                       DRM_AUTH | DRM_UNLOCKED),
 136         VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
 137                       DRM_AUTH | DRM_UNLOCKED),
 138         VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
 139                       DRM_AUTH | DRM_UNLOCKED),
 140         VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
 141                       DRM_AUTH | DRM_UNLOCKED),
 142         VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
 143                       vmw_fence_obj_signaled_ioctl,
 144                       DRM_AUTH | DRM_UNLOCKED),
 145         VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
 146                       DRM_AUTH | DRM_UNLOCKED),
 147         VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
 148                       DRM_AUTH | DRM_UNLOCKED),
 149 };
 150
 151 static struct pci_device_id vmw_pci_id_list[] = {
 152         {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
 153         {0, 0, 0}
 154 };
 155
 156 static int enable_fbdev;
 157
 158 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
 159 static void vmw_master_init(struct vmw_master *);
 160 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
 161                               void *ptr);
 162
 163 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
 164 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
 165
 166 static void vmw_print_capabilities(uint32_t capabilities)
 167 {
 168         DRM_INFO("Capabilities:\n");
 169         if (capabilities & SVGA_CAP_RECT_COPY)
 170                 DRM_INFO("  Rect copy.\n");
 171         if (capabilities & SVGA_CAP_CURSOR)
 172                 DRM_INFO("  Cursor.\n");
 173         if (capabilities & SVGA_CAP_CURSOR_BYPASS)
 174                 DRM_INFO("  Cursor bypass.\n");
 175         if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
 176                 DRM_INFO("  Cursor bypass 2.\n");
 177         if (capabilities & SVGA_CAP_8BIT_EMULATION)
 178                 DRM_INFO("  8bit emulation.\n");
 179         if (capabilities & SVGA_CAP_ALPHA_CURSOR)
 180                 DRM_INFO("  Alpha cursor.\n");
 181         if (capabilities & SVGA_CAP_3D)
 182                 DRM_INFO("  3D.\n");
 183         if (capabilities & SVGA_CAP_EXTENDED_FIFO)
 184                 DRM_INFO("  Extended Fifo.\n");
 185         if (capabilities & SVGA_CAP_MULTIMON)
 186                 DRM_INFO("  Multimon.\n");
 187         if (capabilities & SVGA_CAP_PITCHLOCK)
 188                 DRM_INFO("  Pitchlock.\n");
 189         if (capabilities & SVGA_CAP_IRQMASK)
 190                 DRM_INFO("  Irq mask.\n");
 191         if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
 192                 DRM_INFO("  Display Topology.\n");
 193         if (capabilities & SVGA_CAP_GMR)
 194                 DRM_INFO("  GMR.\n");
 195         if (capabilities & SVGA_CAP_TRACES)
 196                 DRM_INFO("  Traces.\n");
 197         if (capabilities & SVGA_CAP_GMR2)
 198                 DRM_INFO("  GMR2.\n");
 199         if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
 200                 DRM_INFO("  Screen Object 2.\n");
 201 }
 202
 203 static int vmw_request_device(struct vmw_private *dev_priv)
 204 {
 205         int ret;
 206
 207         ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
 208         if (unlikely(ret != 0)) {
 209                 DRM_ERROR("Unable to initialize FIFO.\n");
 210                 return ret;
 211         }
 212         vmw_fence_fifo_up(dev_priv->fman);
 213
 214         return 0;
 215 }
 216
 217 static void vmw_release_device(struct vmw_private *dev_priv)
 218 {
 219         vmw_fence_fifo_down(dev_priv->fman);
 220         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 221 }
 222
 223 /**
 224  * Increase the 3d resource refcount.
 225  * If the count was prevously zero, initialize the fifo, switching to svga
 226  * mode. Note that the master holds a ref as well, and may request an
 227  * explicit switch to svga mode if fb is not running, using @unhide_svga.
 228  */
 229 int vmw_3d_resource_inc(struct vmw_private *dev_priv,
 230                         bool unhide_svga)
 231 {
 232         int ret = 0;
 233
 234         mutex_lock(&dev_priv->release_mutex);
 235         if (unlikely(dev_priv->num_3d_resources++ == 0)) {
 236                 ret = vmw_request_device(dev_priv);
 237                 if (unlikely(ret != 0))
 238                         --dev_priv->num_3d_resources;
 239         } else if (unhide_svga) {
 240                 mutex_lock(&dev_priv->hw_mutex);
 241                 vmw_write(dev_priv, SVGA_REG_ENABLE,
 242                           vmw_read(dev_priv, SVGA_REG_ENABLE) &
 243                           ~SVGA_REG_ENABLE_HIDE);
 244                 mutex_unlock(&dev_priv->hw_mutex);
 245         }
 246
 247         mutex_unlock(&dev_priv->release_mutex);
 248         return ret;
 249 }
 250
 251 /**
 252  * Decrease the 3d resource refcount.
 253  * If the count reaches zero, disable the fifo, switching to vga mode.
 254  * Note that the master holds a refcount as well, and may request an
 255  * explicit switch to vga mode when it releases its refcount to account
 256  * for the situation of an X server vt switch to VGA with 3d resources
 257  * active.
 258  */
 259 void vmw_3d_resource_dec(struct vmw_private *dev_priv,
 260                          bool hide_svga)
 261 {
 262         int32_t n3d;
 263
 264         mutex_lock(&dev_priv->release_mutex);
 265         if (unlikely(--dev_priv->num_3d_resources == 0))
 266                 vmw_release_device(dev_priv);
 267         else if (hide_svga) {
 268                 mutex_lock(&dev_priv->hw_mutex);
 269                 vmw_write(dev_priv, SVGA_REG_ENABLE,
 270                           vmw_read(dev_priv, SVGA_REG_ENABLE) |
 271                           SVGA_REG_ENABLE_HIDE);
 272                 mutex_unlock(&dev_priv->hw_mutex);
 273         }
 274
 275         n3d = (int32_t) dev_priv->num_3d_resources;
 276         mutex_unlock(&dev_priv->release_mutex);
 277
 278         BUG_ON(n3d < 0);
 279 }
 280
 281 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
 282 {
 283         struct vmw_private *dev_priv;
 284         int ret;
 285         uint32_t svga_id;
 286
 287         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 288         if (unlikely(dev_priv == NULL)) {
 289                 DRM_ERROR("Failed allocating a device private struct.\n");
 290                 return -ENOMEM;
 291         }
 292         memset(dev_priv, 0, sizeof(*dev_priv));
 293
 294         dev_priv->dev = dev;
 295         dev_priv->vmw_chipset = chipset;
 296         dev_priv->last_read_seqno = (uint32_t) -100;
 297         mutex_init(&dev_priv->hw_mutex);
 298         mutex_init(&dev_priv->cmdbuf_mutex);
 299         mutex_init(&dev_priv->release_mutex);
 300         rwlock_init(&dev_priv->resource_lock);
 301         idr_init(&dev_priv->context_idr);
 302         idr_init(&dev_priv->surface_idr);
 303         idr_init(&dev_priv->stream_idr);
 304         mutex_init(&dev_priv->init_mutex);
 305         init_waitqueue_head(&dev_priv->fence_queue);
 306         init_waitqueue_head(&dev_priv->fifo_queue);
 307         dev_priv->fence_queue_waiters = 0;
 308         atomic_set(&dev_priv->fifo_queue_waiters, 0);
 309
 310         dev_priv->io_start = pci_resource_start(dev->pdev, 0);
 311         dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
 312         dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
 313
 314         dev_priv->enable_fb = enable_fbdev;
 315
 316         mutex_lock(&dev_priv->hw_mutex);
 317
 318         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
 319         svga_id = vmw_read(dev_priv, SVGA_REG_ID);
 320         if (svga_id != SVGA_ID_2) {
 321                 ret = -ENOSYS;
 322                 DRM_ERROR("Unsuported SVGA ID 0x%x\n", svga_id);
 323                 mutex_unlock(&dev_priv->hw_mutex);
 324                 goto out_err0;
 325         }
 326
 327         dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
 328
 329         if (dev_priv->capabilities & SVGA_CAP_GMR) {
 330                 dev_priv->max_gmr_descriptors =
 331                         vmw_read(dev_priv,
 332                                  SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
 333                 dev_priv->max_gmr_ids =
 334                         vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
 335         }
 336         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 337                 dev_priv->max_gmr_pages =
 338                         vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
 339                 dev_priv->memory_size =
 340                         vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
 341         }
 342
 343         dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
 344         dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
 345         dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
 346         dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
 347
 348         mutex_unlock(&dev_priv->hw_mutex);
 349
 350         vmw_print_capabilities(dev_priv->capabilities);
 351
 352         if (dev_priv->capabilities & SVGA_CAP_GMR) {
 353                 DRM_INFO("Max GMR ids is %u\n",
 354                          (unsigned)dev_priv->max_gmr_ids);
 355                 DRM_INFO("Max GMR descriptors is %u\n",
 356                          (unsigned)dev_priv->max_gmr_descriptors);
 357         }
 358         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 359                 DRM_INFO("Max number of GMR pages is %u\n",
 360                          (unsigned)dev_priv->max_gmr_pages);
 361                 DRM_INFO("Max dedicated hypervisor graphics memory is %u\n",
 362                          (unsigned)dev_priv->memory_size);
 363         }
 364         DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
 365                  dev_priv->vram_start, dev_priv->vram_size / 1024);
 366         DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
 367                  dev_priv->mmio_start, dev_priv->mmio_size / 1024);
 368
 369         ret = vmw_ttm_global_init(dev_priv);
 370         if (unlikely(ret != 0))
 371                 goto out_err0;
 372
 373
 374         vmw_master_init(&dev_priv->fbdev_master);
 375         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
 376         dev_priv->active_master = &dev_priv->fbdev_master;
 377
 378
 379         ret = ttm_bo_device_init(&dev_priv->bdev,
 380                                  dev_priv->bo_global_ref.ref.object,
 381                                  &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
 382                                  false);
 383         if (unlikely(ret != 0)) {
 384                 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
 385                 goto out_err1;
 386         }
 387
 388         ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
 389                              (dev_priv->vram_size >> PAGE_SHIFT));
 390         if (unlikely(ret != 0)) {
 391                 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
 392                 goto out_err2;
 393         }
 394
 395         dev_priv->has_gmr = true;
 396         if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
 397                            dev_priv->max_gmr_ids) != 0) {
 398                 DRM_INFO("No GMR memory available. "
 399                          "Graphics memory resources are very limited.\n");
 400                 dev_priv->has_gmr = false;
 401         }
 402
 403         dev_priv->mmio_mtrr = drm_mtrr_add(dev_priv->mmio_start,
 404                                            dev_priv->mmio_size, DRM_MTRR_WC);
 405
 406         dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
 407                                          dev_priv->mmio_size);
 408
 409         if (unlikely(dev_priv->mmio_virt == NULL)) {
 410                 ret = -ENOMEM;
 411                 DRM_ERROR("Failed mapping MMIO.\n");
 412                 goto out_err3;
 413         }
 414
 415         /* Need mmio memory to check for fifo pitchlock cap. */
 416         if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
 417             !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
 418             !vmw_fifo_have_pitchlock(dev_priv)) {
 419                 ret = -ENOSYS;
 420                 DRM_ERROR("Hardware has no pitchlock\n");
 421                 goto out_err4;
 422         }
 423
 424         dev_priv->tdev = ttm_object_device_init
 425             (dev_priv->mem_global_ref.object, 12);
 426
 427         if (unlikely(dev_priv->tdev == NULL)) {
 428                 DRM_ERROR("Unable to initialize TTM object management.\n");
 429                 ret = -ENOMEM;
 430                 goto out_err4;
 431         }
 432
 433         dev->dev_private = dev_priv;
 434
 435         ret = pci_request_regions(dev->pdev, "vmwgfx probe");
 436         dev_priv->stealth = (ret != 0);
 437         if (dev_priv->stealth) {
 438                 /**
 439                  * Request at least the mmio PCI resource.
 440                  */
 441
 442                 DRM_INFO("It appears like vesafb is loaded. "
 443                          "Ignore above error if any.\n");
 444                 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
 445                 if (unlikely(ret != 0)) {
 446                         DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
 447                         goto out_no_device;
 448                 }
 449         }
 450
 451         dev_priv->fman = vmw_fence_manager_init(dev_priv);
 452         if (unlikely(dev_priv->fman == NULL))
 453                 goto out_no_fman;
 454         ret = vmw_kms_init(dev_priv);
 455         if (unlikely(ret != 0))
 456                 goto out_no_kms;
 457         vmw_overlay_init(dev_priv);
 458         if (dev_priv->enable_fb) {
 459                 ret = vmw_3d_resource_inc(dev_priv, false);
 460                 if (unlikely(ret != 0))
 461                         goto out_no_fifo;
 462                 vmw_kms_save_vga(dev_priv);
 463                 vmw_fb_init(dev_priv);
 464                 DRM_INFO("%s", vmw_fifo_have_3d(dev_priv) ?
 465                          "Detected device 3D availability.\n" :
 466                          "Detected no device 3D availability.\n");
 467         } else {
 468                 DRM_INFO("Delayed 3D detection since we're not "
 469                          "running the device in SVGA mode yet.\n");
 470         }
 471
 472         if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
 473                 ret = drm_irq_install(dev);
 474                 if (unlikely(ret != 0)) {
 475                         DRM_ERROR("Failed installing irq: %d\n", ret);
 476                         goto out_no_irq;
 477                 }
 478         }
 479
 480         dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
 481         register_pm_notifier(&dev_priv->pm_nb);
 482
 483         return 0;
 484
 485 out_no_irq:
 486         if (dev_priv->enable_fb) {
 487                 vmw_fb_close(dev_priv);
 488                 vmw_kms_restore_vga(dev_priv);
 489                 vmw_3d_resource_dec(dev_priv, false);
 490         }
 491 out_no_fifo:
 492         vmw_overlay_close(dev_priv);
 493         vmw_kms_close(dev_priv);
 494 out_no_kms:
 495         vmw_fence_manager_takedown(dev_priv->fman);
 496 out_no_fman:
 497         if (dev_priv->stealth)
 498                 pci_release_region(dev->pdev, 2);
 499         else
 500                 pci_release_regions(dev->pdev);
 501 out_no_device:
 502         ttm_object_device_release(&dev_priv->tdev);
 503 out_err4:
 504         iounmap(dev_priv->mmio_virt);
 505 out_err3:
 506         drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
 507                      dev_priv->mmio_size, DRM_MTRR_WC);
 508         if (dev_priv->has_gmr)
 509                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 510         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 511 out_err2:
 512         (void)ttm_bo_device_release(&dev_priv->bdev);
 513 out_err1:
 514         vmw_ttm_global_release(dev_priv);
 515 out_err0:
 516         idr_destroy(&dev_priv->surface_idr);
 517         idr_destroy(&dev_priv->context_idr);
 518         idr_destroy(&dev_priv->stream_idr);
 519         kfree(dev_priv);
 520         return ret;
 521 }
 522
 523 static int vmw_driver_unload(struct drm_device *dev)
 524 {
 525         struct vmw_private *dev_priv = vmw_priv(dev);
 526
 527         unregister_pm_notifier(&dev_priv->pm_nb);
 528
 529         if (dev_priv->ctx.cmd_bounce)
 530                 vfree(dev_priv->ctx.cmd_bounce);
 531         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
 532                 drm_irq_uninstall(dev_priv->dev);
 533         if (dev_priv->enable_fb) {
 534                 vmw_fb_close(dev_priv);
 535                 vmw_kms_restore_vga(dev_priv);
 536                 vmw_3d_resource_dec(dev_priv, false);
 537         }
 538         vmw_kms_close(dev_priv);
 539         vmw_overlay_close(dev_priv);
 540         vmw_fence_manager_takedown(dev_priv->fman);
 541         if (dev_priv->stealth)
 542                 pci_release_region(dev->pdev, 2);
 543         else
 544                 pci_release_regions(dev->pdev);
 545
 546         ttm_object_device_release(&dev_priv->tdev);
 547         iounmap(dev_priv->mmio_virt);
 548         drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
 549                      dev_priv->mmio_size, DRM_MTRR_WC);
 550         if (dev_priv->has_gmr)
 551                 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 552         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 553         (void)ttm_bo_device_release(&dev_priv->bdev);
 554         vmw_ttm_global_release(dev_priv);
 555         idr_destroy(&dev_priv->surface_idr);
 556         idr_destroy(&dev_priv->context_idr);
 557         idr_destroy(&dev_priv->stream_idr);
 558
 559         kfree(dev_priv);
 560
 561         return 0;
 562 }
 563
 564 static void vmw_postclose(struct drm_device *dev,
 565                          struct drm_file *file_priv)
 566 {
 567         struct vmw_fpriv *vmw_fp;
 568
 569         vmw_fp = vmw_fpriv(file_priv);
 570         ttm_object_file_release(&vmw_fp->tfile);
 571         if (vmw_fp->locked_master)
 572                 drm_master_put(&vmw_fp->locked_master);
 573         kfree(vmw_fp);
 574 }
 575
 576 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
 577 {
 578         struct vmw_private *dev_priv = vmw_priv(dev);
 579         struct vmw_fpriv *vmw_fp;
 580         int ret = -ENOMEM;
 581
 582         vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
 583         if (unlikely(vmw_fp == NULL))
 584                 return ret;
 585
 586         vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
 587         if (unlikely(vmw_fp->tfile == NULL))
 588                 goto out_no_tfile;
 589
 590         file_priv->driver_priv = vmw_fp;
 591
 592         if (unlikely(dev_priv->bdev.dev_mapping == NULL))
 593                 dev_priv->bdev.dev_mapping =
 594                         file_priv->filp->f_path.dentry->d_inode->i_mapping;
 595
 596         return 0;
 597
 598 out_no_tfile:
 599         kfree(vmw_fp);
 600         return ret;
 601 }
 602
 603 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
 604                                unsigned long arg)
 605 {
 606         struct drm_file *file_priv = filp->private_data;
 607         struct drm_device *dev = file_priv->minor->dev;
 608         unsigned int nr = DRM_IOCTL_NR(cmd);
 609
 610         /*
 611          * Do extra checking on driver private ioctls.
 612          */
 613
 614         if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
 615             && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
 616                 struct drm_ioctl_desc *ioctl =
 617                     &vmw_ioctls[nr - DRM_COMMAND_BASE];
 618
 619                 if (unlikely(ioctl->cmd_drv != cmd)) {
 620                         DRM_ERROR("Invalid command format, ioctl %d\n",
 621                                   nr - DRM_COMMAND_BASE);
 622                         return -EINVAL;
 623                 }
 624         }
 625
 626         return drm_ioctl(filp, cmd, arg);
 627 }
 628
 629 static int vmw_firstopen(struct drm_device *dev)
 630 {
 631         struct vmw_private *dev_priv = vmw_priv(dev);
 632         dev_priv->is_opened = true;
 633
 634         return 0;
 635 }
 636
 637 static void vmw_lastclose(struct drm_device *dev)
 638 {
 639         struct vmw_private *dev_priv = vmw_priv(dev);
 640         struct drm_crtc *crtc;
 641         struct drm_mode_set set;
 642         int ret;
 643
 644         /**
 645          * Do nothing on the lastclose call from drm_unload.
 646          */
 647
 648         if (!dev_priv->is_opened)
 649                 return;
 650
 651         dev_priv->is_opened = false;
 652         set.x = 0;
 653         set.y = 0;
 654         set.fb = NULL;
 655         set.mode = NULL;
 656         set.connectors = NULL;
 657         set.num_connectors = 0;
 658
 659         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 660                 set.crtc = crtc;
 661                 ret = crtc->funcs->set_config(&set);
 662                 WARN_ON(ret != 0);
 663         }
 664
 665 }
 666
 667 static void vmw_master_init(struct vmw_master *vmaster)
 668 {
 669         ttm_lock_init(&vmaster->lock);
 670         INIT_LIST_HEAD(&vmaster->fb_surf);
 671         mutex_init(&vmaster->fb_surf_mutex);
 672 }
 673
 674 static int vmw_master_create(struct drm_device *dev,
 675                              struct drm_master *master)
 676 {
 677         struct vmw_master *vmaster;
 678
 679         vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
 680         if (unlikely(vmaster == NULL))
 681                 return -ENOMEM;
 682
 683         vmw_master_init(vmaster);
 684         ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
 685         master->driver_priv = vmaster;
 686
 687         return 0;
 688 }
 689
 690 static void vmw_master_destroy(struct drm_device *dev,
 691                                struct drm_master *master)
 692 {
 693         struct vmw_master *vmaster = vmw_master(master);
 694
 695         master->driver_priv = NULL;
 696         kfree(vmaster);
 697 }
 698
 699
 700 static int vmw_master_set(struct drm_device *dev,
 701                           struct drm_file *file_priv,
 702                           bool from_open)
 703 {
 704         struct vmw_private *dev_priv = vmw_priv(dev);
 705         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
 706         struct vmw_master *active = dev_priv->active_master;
 707         struct vmw_master *vmaster = vmw_master(file_priv->master);
 708         int ret = 0;
 709
 710         if (!dev_priv->enable_fb) {
 711                 ret = vmw_3d_resource_inc(dev_priv, true);
 712                 if (unlikely(ret != 0))
 713                         return ret;
 714                 vmw_kms_save_vga(dev_priv);
 715                 mutex_lock(&dev_priv->hw_mutex);
 716                 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
 717                 mutex_unlock(&dev_priv->hw_mutex);
 718         }
 719
 720         if (active) {
 721                 BUG_ON(active != &dev_priv->fbdev_master);
 722                 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
 723                 if (unlikely(ret != 0))
 724                         goto out_no_active_lock;
 725
 726                 ttm_lock_set_kill(&active->lock, true, SIGTERM);
 727                 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
 728                 if (unlikely(ret != 0)) {
 729                         DRM_ERROR("Unable to clean VRAM on "
 730                                   "master drop.\n");
 731                 }
 732
 733                 dev_priv->active_master = NULL;
 734         }
 735
 736         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
 737         if (!from_open) {
 738                 ttm_vt_unlock(&vmaster->lock);
 739                 BUG_ON(vmw_fp->locked_master != file_priv->master);
 740                 drm_master_put(&vmw_fp->locked_master);
 741         }
 742
 743         dev_priv->active_master = vmaster;
 744
 745         return 0;
 746
 747 out_no_active_lock:
 748         if (!dev_priv->enable_fb) {
 749                 mutex_lock(&dev_priv->hw_mutex);
 750                 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
 751                 mutex_unlock(&dev_priv->hw_mutex);
 752                 vmw_kms_restore_vga(dev_priv);
 753                 vmw_3d_resource_dec(dev_priv, true);
 754         }
 755         return ret;
 756 }
 757
 758 static void vmw_master_drop(struct drm_device *dev,
 759                             struct drm_file *file_priv,
 760                             bool from_release)
 761 {
 762         struct vmw_private *dev_priv = vmw_priv(dev);
 763         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
 764         struct vmw_master *vmaster = vmw_master(file_priv->master);
 765         int ret;
 766
 767         /**
 768          * Make sure the master doesn't disappear while we have
 769          * it locked.
 770          */
 771
 772         vmw_fp->locked_master = drm_master_get(file_priv->master);
 773         ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
 774         vmw_kms_idle_workqueues(vmaster);
 775
 776         if (unlikely((ret != 0))) {
 777                 DRM_ERROR("Unable to lock TTM at VT switch.\n");
 778                 drm_master_put(&vmw_fp->locked_master);
 779         }
 780
 781         ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
 782
 783         if (!dev_priv->enable_fb) {
 784                 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
 785                 if (unlikely(ret != 0))
 786                         DRM_ERROR("Unable to clean VRAM on master drop.\n");
 787                 mutex_lock(&dev_priv->hw_mutex);
 788                 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
 789                 mutex_unlock(&dev_priv->hw_mutex);
 790                 vmw_kms_restore_vga(dev_priv);
 791                 vmw_3d_resource_dec(dev_priv, true);
 792         }
 793
 794         dev_priv->active_master = &dev_priv->fbdev_master;
 795         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
 796         ttm_vt_unlock(&dev_priv->fbdev_master.lock);
 797
 798         if (dev_priv->enable_fb)
 799                 vmw_fb_on(dev_priv);
 800 }
 801
 802
 803 static void vmw_remove(struct pci_dev *pdev)
 804 {
 805         struct drm_device *dev = pci_get_drvdata(pdev);
 806
 807         drm_put_dev(dev);
 808 }
 809
 810 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
 811                               void *ptr)
 812 {
 813         struct vmw_private *dev_priv =
 814                 container_of(nb, struct vmw_private, pm_nb);
 815         struct vmw_master *vmaster = dev_priv->active_master;
 816
 817         switch (val) {
 818         case PM_HIBERNATION_PREPARE:
 819         case PM_SUSPEND_PREPARE:
 820                 ttm_suspend_lock(&vmaster->lock);
 821
 822                 /**
 823                  * This empties VRAM and unbinds all GMR bindings.
 824                  * Buffer contents is moved to swappable memory.
 825                  */
 826                 ttm_bo_swapout_all(&dev_priv->bdev);
 827
 828                 break;
 829         case PM_POST_HIBERNATION:
 830         case PM_POST_SUSPEND:
 831         case PM_POST_RESTORE:
 832                 ttm_suspend_unlock(&vmaster->lock);
 833
 834                 break;
 835         case PM_RESTORE_PREPARE:
 836                 break;
 837         default:
 838                 break;
 839         }
 840         return 0;
 841 }
 842
 843 /**
 844  * These might not be needed with the virtual SVGA device.
 845  */
 846
 847 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 848 {
 849         struct drm_device *dev = pci_get_drvdata(pdev);
 850         struct vmw_private *dev_priv = vmw_priv(dev);
 851
 852         if (dev_priv->num_3d_resources != 0) {
 853                 DRM_INFO("Can't suspend or hibernate "
 854                          "while 3D resources are active.\n");
 855                 return -EBUSY;
 856         }
 857
 858         pci_save_state(pdev);
 859         pci_disable_device(pdev);
 860         pci_set_power_state(pdev, PCI_D3hot);
 861         return 0;
 862 }
 863
 864 static int vmw_pci_resume(struct pci_dev *pdev)
 865 {
 866         pci_set_power_state(pdev, PCI_D0);
 867         pci_restore_state(pdev);
 868         return pci_enable_device(pdev);
 869 }
 870
 871 static int vmw_pm_suspend(struct device *kdev)
 872 {
 873         struct pci_dev *pdev = to_pci_dev(kdev);
 874         struct pm_message dummy;
 875
 876         dummy.event = 0;
 877
 878         return vmw_pci_suspend(pdev, dummy);
 879 }
 880
 881 static int vmw_pm_resume(struct device *kdev)
 882 {
 883         struct pci_dev *pdev = to_pci_dev(kdev);
 884
 885         return vmw_pci_resume(pdev);
 886 }
 887
 888 static int vmw_pm_prepare(struct device *kdev)
 889 {
 890         struct pci_dev *pdev = to_pci_dev(kdev);
 891         struct drm_device *dev = pci_get_drvdata(pdev);
 892         struct vmw_private *dev_priv = vmw_priv(dev);
 893
 894         /**
 895          * Release 3d reference held by fbdev and potentially
 896          * stop fifo.
 897          */
 898         dev_priv->suspended = true;
 899         if (dev_priv->enable_fb)
 900                         vmw_3d_resource_dec(dev_priv, true);
 901
 902         if (dev_priv->num_3d_resources != 0) {
 903
 904                 DRM_INFO("Can't suspend or hibernate "
 905                          "while 3D resources are active.\n");
 906
 907                 if (dev_priv->enable_fb)
 908                         vmw_3d_resource_inc(dev_priv, true);
 909                 dev_priv->suspended = false;
 910                 return -EBUSY;
 911         }
 912
 913         return 0;
 914 }
 915
 916 static void vmw_pm_complete(struct device *kdev)
 917 {
 918         struct pci_dev *pdev = to_pci_dev(kdev);
 919         struct drm_device *dev = pci_get_drvdata(pdev);
 920         struct vmw_private *dev_priv = vmw_priv(dev);
 921
 922         /**
 923          * Reclaim 3d reference held by fbdev and potentially
 924          * start fifo.
 925          */
 926         if (dev_priv->enable_fb)
 927                         vmw_3d_resource_inc(dev_priv, false);
 928
 929         dev_priv->suspended = false;
 930 }
 931
 932 static const struct dev_pm_ops vmw_pm_ops = {
 933         .prepare = vmw_pm_prepare,
 934         .complete = vmw_pm_complete,
 935         .suspend = vmw_pm_suspend,
 936         .resume = vmw_pm_resume,
 937 };
 938
 939 static struct drm_driver driver = {
 940         .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
 941         DRIVER_MODESET,
 942         .load = vmw_driver_load,
 943         .unload = vmw_driver_unload,
 944         .firstopen = vmw_firstopen,
 945         .lastclose = vmw_lastclose,
 946         .irq_preinstall = vmw_irq_preinstall,
 947         .irq_postinstall = vmw_irq_postinstall,
 948         .irq_uninstall = vmw_irq_uninstall,
 949         .irq_handler = vmw_irq_handler,
 950         .get_vblank_counter = vmw_get_vblank_counter,
 951         .reclaim_buffers_locked = NULL,
 952         .ioctls = vmw_ioctls,
 953         .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
 954         .dma_quiescent = NULL,  /*vmw_dma_quiescent, */
 955         .master_create = vmw_master_create,
 956         .master_destroy = vmw_master_destroy,
 957         .master_set = vmw_master_set,
 958         .master_drop = vmw_master_drop,
 959         .open = vmw_driver_open,
 960         .postclose = vmw_postclose,
 961         .fops = {
 962                  .owner = THIS_MODULE,
 963                  .open = drm_open,
 964                  .release = drm_release,
 965                  .unlocked_ioctl = vmw_unlocked_ioctl,
 966                  .mmap = vmw_mmap,
 967                  .poll = drm_poll,
 968                  .fasync = drm_fasync,
 969 #if defined(CONFIG_COMPAT)
 970                  .compat_ioctl = drm_compat_ioctl,
 971 #endif
 972                  .llseek = noop_llseek,
 973         },
 974         .name = VMWGFX_DRIVER_NAME,
 975         .desc = VMWGFX_DRIVER_DESC,
 976         .date = VMWGFX_DRIVER_DATE,
 977         .major = VMWGFX_DRIVER_MAJOR,
 978         .minor = VMWGFX_DRIVER_MINOR,
 979         .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
 980 };
 981
 982 static struct pci_driver vmw_pci_driver = {
 983         .name = VMWGFX_DRIVER_NAME,
 984         .id_table = vmw_pci_id_list,
 985         .probe = vmw_probe,
 986         .remove = vmw_remove,
 987         .driver = {
 988                 .pm = &vmw_pm_ops
 989         }
 990 };
 991
 992 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 993 {
 994         return drm_get_pci_dev(pdev, ent, &driver);
 995 }
 996
 997 static int __init vmwgfx_init(void)
 998 {
 999         int ret;
1000         ret = drm_pci_init(&driver, &vmw_pci_driver);
1001         if (ret)
1002                 DRM_ERROR("Failed initializing DRM.\n");
1003         return ret;
1004 }
1005
1006 static void __exit vmwgfx_exit(void)
1007 {
1008         drm_pci_exit(&driver, &vmw_pci_driver);
1009 }
1010
1011 module_init(vmwgfx_init);
1012 module_exit(vmwgfx_exit);
1013
1014 MODULE_AUTHOR("VMware Inc. and others");
1015 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1016 MODULE_LICENSE("GPL and additional rights");
1017 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1018                __stringify(VMWGFX_DRIVER_MINOR) "."
1019                __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1020                "0");