drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

   1 /**************************************************************************
   2  *
   3  * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "drmP.h"
  29 #include "vmwgfx_drv.h"
  30 #include "ttm/ttm_placement.h"
  31 #include "ttm/ttm_bo_driver.h"
  32 #include "ttm/ttm_object.h"
  33 #include "ttm/ttm_module.h"
  34
  35 #define VMWGFX_DRIVER_NAME "vmwgfx"
  36 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
  37 #define VMWGFX_CHIP_SVGAII 0
  38 #define VMW_FB_RESERVATION 0
  39
  40 /**
  41  * Fully encoded drm commands. Might move to vmw_drm.h
  42  */
  43
  44 #define DRM_IOCTL_VMW_GET_PARAM                                 \
  45         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM,          \
  46                  struct drm_vmw_getparam_arg)
  47 #define DRM_IOCTL_VMW_ALLOC_DMABUF                              \
  48         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF,       \
  49                 union drm_vmw_alloc_dmabuf_arg)
  50 #define DRM_IOCTL_VMW_UNREF_DMABUF                              \
  51         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF,        \
  52                 struct drm_vmw_unref_dmabuf_arg)
  53 #define DRM_IOCTL_VMW_CURSOR_BYPASS                             \
  54         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS,       \
  55                  struct drm_vmw_cursor_bypass_arg)
  56
  57 #define DRM_IOCTL_VMW_CONTROL_STREAM                            \
  58         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM,      \
  59                  struct drm_vmw_control_stream_arg)
  60 #define DRM_IOCTL_VMW_CLAIM_STREAM                              \
  61         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM,        \
  62                  struct drm_vmw_stream_arg)
  63 #define DRM_IOCTL_VMW_UNREF_STREAM                              \
  64         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM,        \
  65                  struct drm_vmw_stream_arg)
  66
  67 #define DRM_IOCTL_VMW_CREATE_CONTEXT                            \
  68         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT,      \
  69                 struct drm_vmw_context_arg)
  70 #define DRM_IOCTL_VMW_UNREF_CONTEXT                             \
  71         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT,       \
  72                 struct drm_vmw_context_arg)
  73 #define DRM_IOCTL_VMW_CREATE_SURFACE                            \
  74         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE,     \
  75                  union drm_vmw_surface_create_arg)
  76 #define DRM_IOCTL_VMW_UNREF_SURFACE                             \
  77         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE,       \
  78                  struct drm_vmw_surface_arg)
  79 #define DRM_IOCTL_VMW_REF_SURFACE                               \
  80         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE,        \
  81                  union drm_vmw_surface_reference_arg)
  82 #define DRM_IOCTL_VMW_EXECBUF                                   \
  83         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,             \
  84                 struct drm_vmw_execbuf_arg)
  85 #define DRM_IOCTL_VMW_GET_3D_CAP                                \
  86         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP,          \
  87                  struct drm_vmw_get_3d_cap_arg)
  88 #define DRM_IOCTL_VMW_FENCE_WAIT                                \
  89         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,         \
  90                  struct drm_vmw_fence_wait_arg)
  91 #define DRM_IOCTL_VMW_FENCE_SIGNALED                            \
  92         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED,     \
  93                  struct drm_vmw_fence_signaled_arg)
  94 #define DRM_IOCTL_VMW_FENCE_UNREF                               \
  95         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF,         \
  96                  struct drm_vmw_fence_arg)
  97 #define DRM_IOCTL_VMW_PRESENT                                   \
  98         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT,             \
  99                  struct drm_vmw_present_arg)
 100 #define DRM_IOCTL_VMW_PRESENT_READBACK                          \
 101         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK,    \
 102                  struct drm_vmw_present_readback_arg)
 103
 104 /**
 105  * The core DRM version of this macro doesn't account for
 106  * DRM_COMMAND_BASE.
 107  */
 108
 109 #define VMW_IOCTL_DEF(ioctl, func, flags) \
 110   [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
 111
 112 /**
 113  * Ioctl definitions.
 114  */
 115
 116 static struct drm_ioctl_desc vmw_ioctls[] = {
 117         VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
 118                       DRM_AUTH | DRM_UNLOCKED),
 119         VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
 120                       DRM_AUTH | DRM_UNLOCKED),
 121         VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
 122                       DRM_AUTH | DRM_UNLOCKED),
 123         VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
 124                       vmw_kms_cursor_bypass_ioctl,
 125                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 126
 127         VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
 128                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 129         VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
 130                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 131         VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
 132                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 133
 134         VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
 135                       DRM_AUTH | DRM_UNLOCKED),
 136         VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
 137                       DRM_AUTH | DRM_UNLOCKED),
 138         VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
 139                       DRM_AUTH | DRM_UNLOCKED),
 140         VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
 141                       DRM_AUTH | DRM_UNLOCKED),
 142         VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
 143                       DRM_AUTH | DRM_UNLOCKED),
 144         VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
 145                       DRM_AUTH | DRM_UNLOCKED),
 146         VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
 147                       DRM_AUTH | DRM_UNLOCKED),
 148         VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
 149                       vmw_fence_obj_signaled_ioctl,
 150                       DRM_AUTH | DRM_UNLOCKED),
 151         VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
 152                       DRM_AUTH | DRM_UNLOCKED),
 153         VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
 154                       DRM_AUTH | DRM_UNLOCKED),
 155
 156         /* these allow direct access to the framebuffers mark as master only */
 157         VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
 158                       DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
 159         VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
 160                       vmw_present_readback_ioctl,
 161                       DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
 162 };
 163
 164 static struct pci_device_id vmw_pci_id_list[] = {
 165         {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
 166         {0, 0, 0}
 167 };
 168
 169 static int enable_fbdev;
 170
 171 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
 172 static void vmw_master_init(struct vmw_master *);
 173 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
 174                               void *ptr);
 175
 176 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
 177 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
 178
 179 static void vmw_print_capabilities(uint32_t capabilities)
 180 {
 181         DRM_INFO("Capabilities:\n");
 182         if (capabilities & SVGA_CAP_RECT_COPY)
 183                 DRM_INFO("  Rect copy.\n");
 184         if (capabilities & SVGA_CAP_CURSOR)
 185                 DRM_INFO("  Cursor.\n");
 186         if (capabilities & SVGA_CAP_CURSOR_BYPASS)
 187                 DRM_INFO("  Cursor bypass.\n");
 188         if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
 189                 DRM_INFO("  Cursor bypass 2.\n");
 190         if (capabilities & SVGA_CAP_8BIT_EMULATION)
 191                 DRM_INFO("  8bit emulation.\n");
 192         if (capabilities & SVGA_CAP_ALPHA_CURSOR)
 193                 DRM_INFO("  Alpha cursor.\n");
 194         if (capabilities & SVGA_CAP_3D)
 195                 DRM_INFO("  3D.\n");
 196         if (capabilities & SVGA_CAP_EXTENDED_FIFO)
 197                 DRM_INFO("  Extended Fifo.\n");
 198         if (capabilities & SVGA_CAP_MULTIMON)
 199                 DRM_INFO("  Multimon.\n");
 200         if (capabilities & SVGA_CAP_PITCHLOCK)
 201                 DRM_INFO("  Pitchlock.\n");
 202         if (capabilities & SVGA_CAP_IRQMASK)
 203                 DRM_INFO("  Irq mask.\n");
 204         if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
 205                 DRM_INFO("  Display Topology.\n");
 206         if (capabilities & SVGA_CAP_GMR)
 207                 DRM_INFO("  GMR.\n");
 208         if (capabilities & SVGA_CAP_TRACES)
 209                 DRM_INFO("  Traces.\n");
 210         if (capabilities & SVGA_CAP_GMR2)
 211                 DRM_INFO("  GMR2.\n");
 212         if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
 213                 DRM_INFO("  Screen Object 2.\n");
 214 }
 215
 216
 217 /**
 218  * vmw_execbuf_prepare_dummy_query - Initialize a query result structure at
 219  * the start of a buffer object.
 220  *
 221  * @dev_priv: The device private structure.
 222  *
 223  * This function will idle the buffer using an uninterruptible wait, then
 224  * map the first page and initialize a pending occlusion query result structure,
 225  * Finally it will unmap the buffer.
 226  *
 227  * TODO: Since we're only mapping a single page, we should optimize the map
 228  * to use kmap_atomic / iomap_atomic.
 229  */
 230 static void vmw_dummy_query_bo_prepare(struct vmw_private *dev_priv)
 231 {
 232         struct ttm_bo_kmap_obj map;
 233         volatile SVGA3dQueryResult *result;
 234         bool dummy;
 235         int ret;
 236         struct ttm_bo_device *bdev = &dev_priv->bdev;
 237         struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
 238
 239         ttm_bo_reserve(bo, false, false, false, 0);
 240         spin_lock(&bdev->fence_lock);
 241         ret = ttm_bo_wait(bo, false, false, false, TTM_USAGE_READWRITE);
 242         spin_unlock(&bdev->fence_lock);
 243         if (unlikely(ret != 0))
 244                 (void) vmw_fallback_wait(dev_priv, false, true, 0, false,
 245                                          10*HZ);
 246
 247         ret = ttm_bo_kmap(bo, 0, 1, &map);
 248         if (likely(ret == 0)) {
 249                 result = ttm_kmap_obj_virtual(&map, &dummy);
 250                 result->totalSize = sizeof(*result);
 251                 result->state = SVGA3D_QUERYSTATE_PENDING;
 252                 result->result32 = 0xff;
 253                 ttm_bo_kunmap(&map);
 254         } else
 255                 DRM_ERROR("Dummy query buffer map failed.\n");
 256         ttm_bo_unreserve(bo);
 257 }
 258
 259
 260 /**
 261  * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
 262  *
 263  * @dev_priv: A device private structure.
 264  *
 265  * This function creates a small buffer object that holds the query
 266  * result for dummy queries emitted as query barriers.
 267  * No interruptible waits are done within this function.
 268  *
 269  * Returns an error if bo creation fails.
 270  */
 271 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
 272 {
 273         return ttm_bo_create(&dev_priv->bdev,
 274                              PAGE_SIZE,
 275                              ttm_bo_type_device,
 276                              &vmw_vram_sys_placement,
 277                              0, 0, false, NULL,
 278                              &dev_priv->dummy_query_bo);
 279 }
 280
 281
 282 static int vmw_request_device(struct vmw_private *dev_priv)
 283 {
 284         int ret;
 285
 286         ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
 287         if (unlikely(ret != 0)) {
 288                 DRM_ERROR("Unable to initialize FIFO.\n");
 289                 return ret;
 290         }
 291         vmw_fence_fifo_up(dev_priv->fman);
 292         ret = vmw_dummy_query_bo_create(dev_priv);
 293         if (unlikely(ret != 0))
 294                 goto out_no_query_bo;
 295         vmw_dummy_query_bo_prepare(dev_priv);
 296
 297         return 0;
 298
 299 out_no_query_bo:
 300         vmw_fence_fifo_down(dev_priv->fman);
 301         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 302         return ret;
 303 }
 304
 305 static void vmw_release_device(struct vmw_private *dev_priv)
 306 {
 307         /*
 308          * Previous destructions should've released
 309          * the pinned bo.
 310          */
 311
 312         BUG_ON(dev_priv->pinned_bo != NULL);
 313
 314         ttm_bo_unref(&dev_priv->dummy_query_bo);
 315         vmw_fence_fifo_down(dev_priv->fman);
 316         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 317 }
 318
 319 /**
 320  * Increase the 3d resource refcount.
 321  * If the count was prevously zero, initialize the fifo, switching to svga
 322  * mode. Note that the master holds a ref as well, and may request an
 323  * explicit switch to svga mode if fb is not running, using @unhide_svga.
 324  */
 325 int vmw_3d_resource_inc(struct vmw_private *dev_priv,
 326                         bool unhide_svga)
 327 {
 328         int ret = 0;
 329
 330         mutex_lock(&dev_priv->release_mutex);
 331         if (unlikely(dev_priv->num_3d_resources++ == 0)) {
 332                 ret = vmw_request_device(dev_priv);
 333                 if (unlikely(ret != 0))
 334                         --dev_priv->num_3d_resources;
 335         } else if (unhide_svga) {
 336                 mutex_lock(&dev_priv->hw_mutex);
 337                 vmw_write(dev_priv, SVGA_REG_ENABLE,
 338                           vmw_read(dev_priv, SVGA_REG_ENABLE) &
 339                           ~SVGA_REG_ENABLE_HIDE);
 340                 mutex_unlock(&dev_priv->hw_mutex);
 341         }
 342
 343         mutex_unlock(&dev_priv->release_mutex);
 344         return ret;
 345 }
 346
 347 /**
 348  * Decrease the 3d resource refcount.
 349  * If the count reaches zero, disable the fifo, switching to vga mode.
 350  * Note that the master holds a refcount as well, and may request an
 351  * explicit switch to vga mode when it releases its refcount to account
 352  * for the situation of an X server vt switch to VGA with 3d resources
 353  * active.
 354  */
 355 void vmw_3d_resource_dec(struct vmw_private *dev_priv,
 356                          bool hide_svga)
 357 {
 358         int32_t n3d;
 359
 360         mutex_lock(&dev_priv->release_mutex);
 361         if (unlikely(--dev_priv->num_3d_resources == 0))
 362                 vmw_release_device(dev_priv);
 363         else if (hide_svga) {
 364                 mutex_lock(&dev_priv->hw_mutex);
 365                 vmw_write(dev_priv, SVGA_REG_ENABLE,
 366                           vmw_read(dev_priv, SVGA_REG_ENABLE) |
 367                           SVGA_REG_ENABLE_HIDE);
 368                 mutex_unlock(&dev_priv->hw_mutex);
 369         }
 370
 371         n3d = (int32_t) dev_priv->num_3d_resources;
 372         mutex_unlock(&dev_priv->release_mutex);
 373
 374         BUG_ON(n3d < 0);
 375 }
 376
 377 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
 378 {
 379         struct vmw_private *dev_priv;
 380         int ret;
 381         uint32_t svga_id;
 382
 383         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 384         if (unlikely(dev_priv == NULL)) {
 385                 DRM_ERROR("Failed allocating a device private struct.\n");
 386                 return -ENOMEM;
 387         }
 388         memset(dev_priv, 0, sizeof(*dev_priv));
 389
 390         dev_priv->dev = dev;
 391         dev_priv->vmw_chipset = chipset;
 392         dev_priv->last_read_seqno = (uint32_t) -100;
 393         mutex_init(&dev_priv->hw_mutex);
 394         mutex_init(&dev_priv->cmdbuf_mutex);
 395         mutex_init(&dev_priv->release_mutex);
 396         rwlock_init(&dev_priv->resource_lock);
 397         idr_init(&dev_priv->context_idr);
 398         idr_init(&dev_priv->surface_idr);
 399         idr_init(&dev_priv->stream_idr);
 400         mutex_init(&dev_priv->init_mutex);
 401         init_waitqueue_head(&dev_priv->fence_queue);
 402         init_waitqueue_head(&dev_priv->fifo_queue);
 403         dev_priv->fence_queue_waiters = 0;
 404         atomic_set(&dev_priv->fifo_queue_waiters, 0);
 405         INIT_LIST_HEAD(&dev_priv->surface_lru);
 406         dev_priv->used_memory_size = 0;
 407
 408         dev_priv->io_start = pci_resource_start(dev->pdev, 0);
 409         dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
 410         dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
 411
 412         dev_priv->enable_fb = enable_fbdev;
 413
 414         mutex_lock(&dev_priv->hw_mutex);
 415
 416         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
 417         svga_id = vmw_read(dev_priv, SVGA_REG_ID);
 418         if (svga_id != SVGA_ID_2) {
 419                 ret = -ENOSYS;
 420                 DRM_ERROR("Unsuported SVGA ID 0x%x\n", svga_id);
 421                 mutex_unlock(&dev_priv->hw_mutex);
 422                 goto out_err0;
 423         }
 424
 425         dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
 426
 427         dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
 428         dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
 429         dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
 430         dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
 431         if (dev_priv->capabilities & SVGA_CAP_GMR) {
 432                 dev_priv->max_gmr_descriptors =
 433                         vmw_read(dev_priv,
 434                                  SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
 435                 dev_priv->max_gmr_ids =
 436                         vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
 437         }
 438         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 439                 dev_priv->max_gmr_pages =
 440                         vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
 441                 dev_priv->memory_size =
 442                         vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
 443                 dev_priv->memory_size -= dev_priv->vram_size;
 444         } else {
 445                 /*
 446                  * An arbitrary limit of 512MiB on surface
 447                  * memory. But all HWV8 hardware supports GMR2.
 448                  */
 449                 dev_priv->memory_size = 512*1024*1024;
 450         }
 451
 452         mutex_unlock(&dev_priv->hw_mutex);
 453
 454         vmw_print_capabilities(dev_priv->capabilities);
 455
 456         if (dev_priv->capabilities & SVGA_CAP_GMR) {
 457                 DRM_INFO("Max GMR ids is %u\n",
 458                          (unsigned)dev_priv->max_gmr_ids);
 459                 DRM_INFO("Max GMR descriptors is %u\n",
 460                          (unsigned)dev_priv->max_gmr_descriptors);
 461         }
 462         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 463                 DRM_INFO("Max number of GMR pages is %u\n",
 464                          (unsigned)dev_priv->max_gmr_pages);
 465                 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
 466                          (unsigned)dev_priv->memory_size / 1024);
 467         }
 468         DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
 469                  dev_priv->vram_start, dev_priv->vram_size / 1024);
 470         DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
 471                  dev_priv->mmio_start, dev_priv->mmio_size / 1024);
 472
 473         ret = vmw_ttm_global_init(dev_priv);
 474         if (unlikely(ret != 0))
 475                 goto out_err0;
 476
 477
 478         vmw_master_init(&dev_priv->fbdev_master);
 479         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
 480         dev_priv->active_master = &dev_priv->fbdev_master;
 481
 482
 483         ret = ttm_bo_device_init(&dev_priv->bdev,
 484                                  dev_priv->bo_global_ref.ref.object,
 485                                  &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
 486                                  false);
 487         if (unlikely(ret != 0)) {
 488                 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
 489                 goto out_err1;
 490         }
 491
 492         ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
 493                              (dev_priv->vram_size >> PAGE_SHIFT));
 494         if (unlikely(ret != 0)) {
 495                 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
 496                 goto out_err2;
 497         }
 498
 499         dev_priv->has_gmr = true;
 500         if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
 501                            dev_priv->max_gmr_ids) != 0) {
 502                 DRM_INFO("No GMR memory available. "
 503                          "Graphics memory resources are very limited.\n");
 504                 dev_priv->has_gmr = false;
 505         }
 506
 507         dev_priv->mmio_mtrr = drm_mtrr_add(dev_priv->mmio_start,
 508                                            dev_priv->mmio_size, DRM_MTRR_WC);
 509
 510         dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
 511                                          dev_priv->mmio_size);
 512
 513         if (unlikely(dev_priv->mmio_virt == NULL)) {
 514                 ret = -ENOMEM;
 515                 DRM_ERROR("Failed mapping MMIO.\n");
 516                 goto out_err3;
 517         }
 518
 519         /* Need mmio memory to check for fifo pitchlock cap. */
 520         if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
 521             !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
 522             !vmw_fifo_have_pitchlock(dev_priv)) {
 523                 ret = -ENOSYS;
 524                 DRM_ERROR("Hardware has no pitchlock\n");
 525                 goto out_err4;
 526         }
 527
 528         dev_priv->tdev = ttm_object_device_init
 529             (dev_priv->mem_global_ref.object, 12);
 530
 531         if (unlikely(dev_priv->tdev == NULL)) {
 532                 DRM_ERROR("Unable to initialize TTM object management.\n");
 533                 ret = -ENOMEM;
 534                 goto out_err4;
 535         }
 536
 537         dev->dev_private = dev_priv;
 538
 539         ret = pci_request_regions(dev->pdev, "vmwgfx probe");
 540         dev_priv->stealth = (ret != 0);
 541         if (dev_priv->stealth) {
 542                 /**
 543                  * Request at least the mmio PCI resource.
 544                  */
 545
 546                 DRM_INFO("It appears like vesafb is loaded. "
 547                          "Ignore above error if any.\n");
 548                 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
 549                 if (unlikely(ret != 0)) {
 550                         DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
 551                         goto out_no_device;
 552                 }
 553         }
 554
 555         dev_priv->fman = vmw_fence_manager_init(dev_priv);
 556         if (unlikely(dev_priv->fman == NULL))
 557                 goto out_no_fman;
 558
 559         /* Need to start the fifo to check if we can do screen objects */
 560         ret = vmw_3d_resource_inc(dev_priv, true);
 561         if (unlikely(ret != 0))
 562                 goto out_no_fifo;
 563         vmw_kms_save_vga(dev_priv);
 564
 565         /* Start kms and overlay systems, needs fifo. */
 566         ret = vmw_kms_init(dev_priv);
 567         if (unlikely(ret != 0))
 568                 goto out_no_kms;
 569         vmw_overlay_init(dev_priv);
 570
 571         /* 3D Depends on Screen Objects being used. */
 572         DRM_INFO("Detected %sdevice 3D availability.\n",
 573                  vmw_fifo_have_3d(dev_priv) ?
 574                  "" : "no ");
 575
 576         /* We might be done with the fifo now */
 577         if (dev_priv->enable_fb) {
 578                 vmw_fb_init(dev_priv);
 579         } else {
 580                 vmw_kms_restore_vga(dev_priv);
 581                 vmw_3d_resource_dec(dev_priv, true);
 582         }
 583
 584         if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
 585                 ret = drm_irq_install(dev);
 586                 if (unlikely(ret != 0)) {
 587                         DRM_ERROR("Failed installing irq: %d\n", ret);
 588                         goto out_no_irq;
 589                 }
 590         }
 591
 592         dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
 593         register_pm_notifier(&dev_priv->pm_nb);
 594
 595         return 0;
 596
 597 out_no_irq:
 598         if (dev_priv->enable_fb)
 599                 vmw_fb_close(dev_priv);
 600         vmw_overlay_close(dev_priv);
 601         vmw_kms_close(dev_priv);
 602 out_no_kms:
 603         /* We still have a 3D resource reference held */
 604         if (dev_priv->enable_fb) {
 605                 vmw_kms_restore_vga(dev_priv);
 606                 vmw_3d_resource_dec(dev_priv, false);
 607         }
 608 out_no_fifo:
 609         vmw_fence_manager_takedown(dev_priv->fman);
 610 out_no_fman:
 611         if (dev_priv->stealth)
 612                 pci_release_region(dev->pdev, 2);
 613         else
 614                 pci_release_regions(dev->pdev);
 615 out_no_device:
 616         ttm_object_device_release(&dev_priv->tdev);
 617 out_err4:
 618         iounmap(dev_priv->mmio_virt);
 619 out_err3:
 620         drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
 621                      dev_priv->mmio_size, DRM_MTRR_WC);
 622         if (dev_priv->has_gmr)
 623                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 624         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 625 out_err2:
 626         (void)ttm_bo_device_release(&dev_priv->bdev);
 627 out_err1:
 628         vmw_ttm_global_release(dev_priv);
 629 out_err0:
 630         idr_destroy(&dev_priv->surface_idr);
 631         idr_destroy(&dev_priv->context_idr);
 632         idr_destroy(&dev_priv->stream_idr);
 633         kfree(dev_priv);
 634         return ret;
 635 }
 636
 637 static int vmw_driver_unload(struct drm_device *dev)
 638 {
 639         struct vmw_private *dev_priv = vmw_priv(dev);
 640
 641         unregister_pm_notifier(&dev_priv->pm_nb);
 642
 643         if (dev_priv->ctx.cmd_bounce)
 644                 vfree(dev_priv->ctx.cmd_bounce);
 645         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
 646                 drm_irq_uninstall(dev_priv->dev);
 647         if (dev_priv->enable_fb) {
 648                 vmw_fb_close(dev_priv);
 649                 vmw_kms_restore_vga(dev_priv);
 650                 vmw_3d_resource_dec(dev_priv, false);
 651         }
 652         vmw_kms_close(dev_priv);
 653         vmw_overlay_close(dev_priv);
 654         vmw_fence_manager_takedown(dev_priv->fman);
 655         if (dev_priv->stealth)
 656                 pci_release_region(dev->pdev, 2);
 657         else
 658                 pci_release_regions(dev->pdev);
 659
 660         ttm_object_device_release(&dev_priv->tdev);
 661         iounmap(dev_priv->mmio_virt);
 662         drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
 663                      dev_priv->mmio_size, DRM_MTRR_WC);
 664         if (dev_priv->has_gmr)
 665                 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 666         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 667         (void)ttm_bo_device_release(&dev_priv->bdev);
 668         vmw_ttm_global_release(dev_priv);
 669         idr_destroy(&dev_priv->surface_idr);
 670         idr_destroy(&dev_priv->context_idr);
 671         idr_destroy(&dev_priv->stream_idr);
 672
 673         kfree(dev_priv);
 674
 675         return 0;
 676 }
 677
 678 static void vmw_postclose(struct drm_device *dev,
 679                          struct drm_file *file_priv)
 680 {
 681         struct vmw_fpriv *vmw_fp;
 682
 683         vmw_fp = vmw_fpriv(file_priv);
 684         ttm_object_file_release(&vmw_fp->tfile);
 685         if (vmw_fp->locked_master)
 686                 drm_master_put(&vmw_fp->locked_master);
 687         kfree(vmw_fp);
 688 }
 689
 690 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
 691 {
 692         struct vmw_private *dev_priv = vmw_priv(dev);
 693         struct vmw_fpriv *vmw_fp;
 694         int ret = -ENOMEM;
 695
 696         vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
 697         if (unlikely(vmw_fp == NULL))
 698                 return ret;
 699
 700         vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
 701         if (unlikely(vmw_fp->tfile == NULL))
 702                 goto out_no_tfile;
 703
 704         file_priv->driver_priv = vmw_fp;
 705
 706         if (unlikely(dev_priv->bdev.dev_mapping == NULL))
 707                 dev_priv->bdev.dev_mapping =
 708                         file_priv->filp->f_path.dentry->d_inode->i_mapping;
 709
 710         return 0;
 711
 712 out_no_tfile:
 713         kfree(vmw_fp);
 714         return ret;
 715 }
 716
 717 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
 718                                unsigned long arg)
 719 {
 720         struct drm_file *file_priv = filp->private_data;
 721         struct drm_device *dev = file_priv->minor->dev;
 722         unsigned int nr = DRM_IOCTL_NR(cmd);
 723
 724         /*
 725          * Do extra checking on driver private ioctls.
 726          */
 727
 728         if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
 729             && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
 730                 struct drm_ioctl_desc *ioctl =
 731                     &vmw_ioctls[nr - DRM_COMMAND_BASE];
 732
 733                 if (unlikely(ioctl->cmd_drv != cmd)) {
 734                         DRM_ERROR("Invalid command format, ioctl %d\n",
 735                                   nr - DRM_COMMAND_BASE);
 736                         return -EINVAL;
 737                 }
 738         }
 739
 740         return drm_ioctl(filp, cmd, arg);
 741 }
 742
 743 static int vmw_firstopen(struct drm_device *dev)
 744 {
 745         struct vmw_private *dev_priv = vmw_priv(dev);
 746         dev_priv->is_opened = true;
 747
 748         return 0;
 749 }
 750
 751 static void vmw_lastclose(struct drm_device *dev)
 752 {
 753         struct vmw_private *dev_priv = vmw_priv(dev);
 754         struct drm_crtc *crtc;
 755         struct drm_mode_set set;
 756         int ret;
 757
 758         /**
 759          * Do nothing on the lastclose call from drm_unload.
 760          */
 761
 762         if (!dev_priv->is_opened)
 763                 return;
 764
 765         dev_priv->is_opened = false;
 766         set.x = 0;
 767         set.y = 0;
 768         set.fb = NULL;
 769         set.mode = NULL;
 770         set.connectors = NULL;
 771         set.num_connectors = 0;
 772
 773         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 774                 set.crtc = crtc;
 775                 ret = crtc->funcs->set_config(&set);
 776                 WARN_ON(ret != 0);
 777         }
 778
 779 }
 780
 781 static void vmw_master_init(struct vmw_master *vmaster)
 782 {
 783         ttm_lock_init(&vmaster->lock);
 784         INIT_LIST_HEAD(&vmaster->fb_surf);
 785         mutex_init(&vmaster->fb_surf_mutex);
 786 }
 787
 788 static int vmw_master_create(struct drm_device *dev,
 789                              struct drm_master *master)
 790 {
 791         struct vmw_master *vmaster;
 792
 793         vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
 794         if (unlikely(vmaster == NULL))
 795                 return -ENOMEM;
 796
 797         vmw_master_init(vmaster);
 798         ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
 799         master->driver_priv = vmaster;
 800
 801         return 0;
 802 }
 803
 804 static void vmw_master_destroy(struct drm_device *dev,
 805                                struct drm_master *master)
 806 {
 807         struct vmw_master *vmaster = vmw_master(master);
 808
 809         master->driver_priv = NULL;
 810         kfree(vmaster);
 811 }
 812
 813
 814 static int vmw_master_set(struct drm_device *dev,
 815                           struct drm_file *file_priv,
 816                           bool from_open)
 817 {
 818         struct vmw_private *dev_priv = vmw_priv(dev);
 819         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
 820         struct vmw_master *active = dev_priv->active_master;
 821         struct vmw_master *vmaster = vmw_master(file_priv->master);
 822         int ret = 0;
 823
 824         if (!dev_priv->enable_fb) {
 825                 ret = vmw_3d_resource_inc(dev_priv, true);
 826                 if (unlikely(ret != 0))
 827                         return ret;
 828                 vmw_kms_save_vga(dev_priv);
 829                 mutex_lock(&dev_priv->hw_mutex);
 830                 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
 831                 mutex_unlock(&dev_priv->hw_mutex);
 832         }
 833
 834         if (active) {
 835                 BUG_ON(active != &dev_priv->fbdev_master);
 836                 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
 837                 if (unlikely(ret != 0))
 838                         goto out_no_active_lock;
 839
 840                 ttm_lock_set_kill(&active->lock, true, SIGTERM);
 841                 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
 842                 if (unlikely(ret != 0)) {
 843                         DRM_ERROR("Unable to clean VRAM on "
 844                                   "master drop.\n");
 845                 }
 846
 847                 dev_priv->active_master = NULL;
 848         }
 849
 850         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
 851         if (!from_open) {
 852                 ttm_vt_unlock(&vmaster->lock);
 853                 BUG_ON(vmw_fp->locked_master != file_priv->master);
 854                 drm_master_put(&vmw_fp->locked_master);
 855         }
 856
 857         dev_priv->active_master = vmaster;
 858
 859         return 0;
 860
 861 out_no_active_lock:
 862         if (!dev_priv->enable_fb) {
 863                 mutex_lock(&dev_priv->hw_mutex);
 864                 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
 865                 mutex_unlock(&dev_priv->hw_mutex);
 866                 vmw_kms_restore_vga(dev_priv);
 867                 vmw_3d_resource_dec(dev_priv, true);
 868         }
 869         return ret;
 870 }
 871
 872 static void vmw_master_drop(struct drm_device *dev,
 873                             struct drm_file *file_priv,
 874                             bool from_release)
 875 {
 876         struct vmw_private *dev_priv = vmw_priv(dev);
 877         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
 878         struct vmw_master *vmaster = vmw_master(file_priv->master);
 879         int ret;
 880
 881         /**
 882          * Make sure the master doesn't disappear while we have
 883          * it locked.
 884          */
 885
 886         vmw_fp->locked_master = drm_master_get(file_priv->master);
 887         ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
 888         vmw_execbuf_release_pinned_bo(dev_priv, false, 0);
 889
 890         if (unlikely((ret != 0))) {
 891                 DRM_ERROR("Unable to lock TTM at VT switch.\n");
 892                 drm_master_put(&vmw_fp->locked_master);
 893         }
 894
 895         ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
 896
 897         if (!dev_priv->enable_fb) {
 898                 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
 899                 if (unlikely(ret != 0))
 900                         DRM_ERROR("Unable to clean VRAM on master drop.\n");
 901                 mutex_lock(&dev_priv->hw_mutex);
 902                 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
 903                 mutex_unlock(&dev_priv->hw_mutex);
 904                 vmw_kms_restore_vga(dev_priv);
 905                 vmw_3d_resource_dec(dev_priv, true);
 906         }
 907
 908         dev_priv->active_master = &dev_priv->fbdev_master;
 909         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
 910         ttm_vt_unlock(&dev_priv->fbdev_master.lock);
 911
 912         if (dev_priv->enable_fb)
 913                 vmw_fb_on(dev_priv);
 914 }
 915
 916
 917 static void vmw_remove(struct pci_dev *pdev)
 918 {
 919         struct drm_device *dev = pci_get_drvdata(pdev);
 920
 921         drm_put_dev(dev);
 922 }
 923
 924 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
 925                               void *ptr)
 926 {
 927         struct vmw_private *dev_priv =
 928                 container_of(nb, struct vmw_private, pm_nb);
 929         struct vmw_master *vmaster = dev_priv->active_master;
 930
 931         switch (val) {
 932         case PM_HIBERNATION_PREPARE:
 933         case PM_SUSPEND_PREPARE:
 934                 ttm_suspend_lock(&vmaster->lock);
 935
 936                 /**
 937                  * This empties VRAM and unbinds all GMR bindings.
 938                  * Buffer contents is moved to swappable memory.
 939                  */
 940                 vmw_execbuf_release_pinned_bo(dev_priv, false, 0);
 941                 ttm_bo_swapout_all(&dev_priv->bdev);
 942
 943                 break;
 944         case PM_POST_HIBERNATION:
 945         case PM_POST_SUSPEND:
 946         case PM_POST_RESTORE:
 947                 ttm_suspend_unlock(&vmaster->lock);
 948
 949                 break;
 950         case PM_RESTORE_PREPARE:
 951                 break;
 952         default:
 953                 break;
 954         }
 955         return 0;
 956 }
 957
 958 /**
 959  * These might not be needed with the virtual SVGA device.
 960  */
 961
 962 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 963 {
 964         struct drm_device *dev = pci_get_drvdata(pdev);
 965         struct vmw_private *dev_priv = vmw_priv(dev);
 966
 967         if (dev_priv->num_3d_resources != 0) {
 968                 DRM_INFO("Can't suspend or hibernate "
 969                          "while 3D resources are active.\n");
 970                 return -EBUSY;
 971         }
 972
 973         pci_save_state(pdev);
 974         pci_disable_device(pdev);
 975         pci_set_power_state(pdev, PCI_D3hot);
 976         return 0;
 977 }
 978
 979 static int vmw_pci_resume(struct pci_dev *pdev)
 980 {
 981         pci_set_power_state(pdev, PCI_D0);
 982         pci_restore_state(pdev);
 983         return pci_enable_device(pdev);
 984 }
 985
 986 static int vmw_pm_suspend(struct device *kdev)
 987 {
 988         struct pci_dev *pdev = to_pci_dev(kdev);
 989         struct pm_message dummy;
 990
 991         dummy.event = 0;
 992
 993         return vmw_pci_suspend(pdev, dummy);
 994 }
 995
 996 static int vmw_pm_resume(struct device *kdev)
 997 {
 998         struct pci_dev *pdev = to_pci_dev(kdev);
 999
1000         return vmw_pci_resume(pdev);
1001 }
1002
1003 static int vmw_pm_prepare(struct device *kdev)
1004 {
1005         struct pci_dev *pdev = to_pci_dev(kdev);
1006         struct drm_device *dev = pci_get_drvdata(pdev);
1007         struct vmw_private *dev_priv = vmw_priv(dev);
1008
1009         /**
1010          * Release 3d reference held by fbdev and potentially
1011          * stop fifo.
1012          */
1013         dev_priv->suspended = true;
1014         if (dev_priv->enable_fb)
1015                         vmw_3d_resource_dec(dev_priv, true);
1016
1017         if (dev_priv->num_3d_resources != 0) {
1018
1019                 DRM_INFO("Can't suspend or hibernate "
1020                          "while 3D resources are active.\n");
1021
1022                 if (dev_priv->enable_fb)
1023                         vmw_3d_resource_inc(dev_priv, true);
1024                 dev_priv->suspended = false;
1025                 return -EBUSY;
1026         }
1027
1028         return 0;
1029 }
1030
1031 static void vmw_pm_complete(struct device *kdev)
1032 {
1033         struct pci_dev *pdev = to_pci_dev(kdev);
1034         struct drm_device *dev = pci_get_drvdata(pdev);
1035         struct vmw_private *dev_priv = vmw_priv(dev);
1036
1037         /**
1038          * Reclaim 3d reference held by fbdev and potentially
1039          * start fifo.
1040          */
1041         if (dev_priv->enable_fb)
1042                         vmw_3d_resource_inc(dev_priv, false);
1043
1044         dev_priv->suspended = false;
1045 }
1046
1047 static const struct dev_pm_ops vmw_pm_ops = {
1048         .prepare = vmw_pm_prepare,
1049         .complete = vmw_pm_complete,
1050         .suspend = vmw_pm_suspend,
1051         .resume = vmw_pm_resume,
1052 };
1053
1054 static struct drm_driver driver = {
1055         .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1056         DRIVER_MODESET,
1057         .load = vmw_driver_load,
1058         .unload = vmw_driver_unload,
1059         .firstopen = vmw_firstopen,
1060         .lastclose = vmw_lastclose,
1061         .irq_preinstall = vmw_irq_preinstall,
1062         .irq_postinstall = vmw_irq_postinstall,
1063         .irq_uninstall = vmw_irq_uninstall,
1064         .irq_handler = vmw_irq_handler,
1065         .get_vblank_counter = vmw_get_vblank_counter,
1066         .reclaim_buffers_locked = NULL,
1067         .ioctls = vmw_ioctls,
1068         .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
1069         .dma_quiescent = NULL,  /*vmw_dma_quiescent, */
1070         .master_create = vmw_master_create,
1071         .master_destroy = vmw_master_destroy,
1072         .master_set = vmw_master_set,
1073         .master_drop = vmw_master_drop,
1074         .open = vmw_driver_open,
1075         .postclose = vmw_postclose,
1076         .fops = {
1077                  .owner = THIS_MODULE,
1078                  .open = drm_open,
1079                  .release = drm_release,
1080                  .unlocked_ioctl = vmw_unlocked_ioctl,
1081                  .mmap = vmw_mmap,
1082                  .poll = drm_poll,
1083                  .fasync = drm_fasync,
1084 #if defined(CONFIG_COMPAT)
1085                  .compat_ioctl = drm_compat_ioctl,
1086 #endif
1087                  .llseek = noop_llseek,
1088         },
1089         .name = VMWGFX_DRIVER_NAME,
1090         .desc = VMWGFX_DRIVER_DESC,
1091         .date = VMWGFX_DRIVER_DATE,
1092         .major = VMWGFX_DRIVER_MAJOR,
1093         .minor = VMWGFX_DRIVER_MINOR,
1094         .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1095 };
1096
1097 static struct pci_driver vmw_pci_driver = {
1098         .name = VMWGFX_DRIVER_NAME,
1099         .id_table = vmw_pci_id_list,
1100         .probe = vmw_probe,
1101         .remove = vmw_remove,
1102         .driver = {
1103                 .pm = &vmw_pm_ops
1104         }
1105 };
1106
1107 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1108 {
1109         return drm_get_pci_dev(pdev, ent, &driver);
1110 }
1111
1112 static int __init vmwgfx_init(void)
1113 {
1114         int ret;
1115         ret = drm_pci_init(&driver, &vmw_pci_driver);
1116         if (ret)
1117                 DRM_ERROR("Failed initializing DRM.\n");
1118         return ret;
1119 }
1120
1121 static void __exit vmwgfx_exit(void)
1122 {
1123         drm_pci_exit(&driver, &vmw_pci_driver);
1124 }
1125
1126 module_init(vmwgfx_init);
1127 module_exit(vmwgfx_exit);
1128
1129 MODULE_AUTHOR("VMware Inc. and others");
1130 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1131 MODULE_LICENSE("GPL and additional rights");
1132 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1133                __stringify(VMWGFX_DRIVER_MINOR) "."
1134                __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1135                "0");