drivers/gpu/drm/via/via_irq.c

   1 /* via_irq.c
   2  *
   3  * Copyright 2004 BEAM Ltd.
   4  * Copyright 2002 Tungsten Graphics, Inc.
   5  * Copyright 2005 Thomas Hellstrom.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * BEAM LTD, TUNGSTEN GRAPHICS  AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  23  * DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Terry Barnaby <terry1@beam.ltd.uk>
  30  *    Keith Whitwell <keith@tungstengraphics.com>
  31  *    Thomas Hellstrom <unichrome@shipmail.org>
  32  *
  33  * This code provides standard DRM access to the Via Unichrome / Pro Vertical blank
  34  * interrupt, as well as an infrastructure to handle other interrupts of the chip.
  35  * The refresh rate is also calculated for video playback sync purposes.
  36  */
  37
  38 #include "drmP.h"
  39 #include "drm.h"
  40 #include "via_drm.h"
  41 #include "via_drv.h"
  42
  43 #define VIA_REG_INTERRUPT       0x200
  44
  45 /* VIA_REG_INTERRUPT */
  46 #define VIA_IRQ_GLOBAL    (1 << 31)
  47 #define VIA_IRQ_VBLANK_ENABLE   (1 << 19)
  48 #define VIA_IRQ_VBLANK_PENDING  (1 << 3)
  49 #define VIA_IRQ_HQV0_ENABLE     (1 << 11)
  50 #define VIA_IRQ_HQV1_ENABLE     (1 << 25)
  51 #define VIA_IRQ_HQV0_PENDING    (1 << 9)
  52 #define VIA_IRQ_HQV1_PENDING    (1 << 10)
  53 #define VIA_IRQ_DMA0_DD_ENABLE  (1 << 20)
  54 #define VIA_IRQ_DMA0_TD_ENABLE  (1 << 21)
  55 #define VIA_IRQ_DMA1_DD_ENABLE  (1 << 22)
  56 #define VIA_IRQ_DMA1_TD_ENABLE  (1 << 23)
  57 #define VIA_IRQ_DMA0_DD_PENDING (1 << 4)
  58 #define VIA_IRQ_DMA0_TD_PENDING (1 << 5)
  59 #define VIA_IRQ_DMA1_DD_PENDING (1 << 6)
  60 #define VIA_IRQ_DMA1_TD_PENDING (1 << 7)
  61
  62
  63 /*
  64  * Device-specific IRQs go here. This type might need to be extended with
  65  * the register if there are multiple IRQ control registers.
  66  * Currently we activate the HQV interrupts of  Unichrome Pro group A.
  67  */
  68
  69 static maskarray_t via_pro_group_a_irqs[] = {
  70         {VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010,
  71          0x00000000 },
  72         {VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010,
  73          0x00000000 },
  74         {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
  75          VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
  76         {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
  77          VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
  78 };
  79 static int via_num_pro_group_a = ARRAY_SIZE(via_pro_group_a_irqs);
  80 static int via_irqmap_pro_group_a[] = {0, 1, -1, 2, -1, 3};
  81
  82 static maskarray_t via_unichrome_irqs[] = {
  83         {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
  84          VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
  85         {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
  86          VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}
  87 };
  88 static int via_num_unichrome = ARRAY_SIZE(via_unichrome_irqs);
  89 static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1};
  90
  91
  92 static unsigned time_diff(struct timeval *now, struct timeval *then)
  93 {
  94         return (now->tv_usec >= then->tv_usec) ?
  95                 now->tv_usec - then->tv_usec :
  96                 1000000 - (then->tv_usec - now->tv_usec);
  97 }
  98
  99 u32 via_get_vblank_counter(struct drm_device *dev, int crtc)
 100 {
 101         drm_via_private_t *dev_priv = dev->dev_private;
 102         if (crtc != 0)
 103                 return 0;
 104
 105         return atomic_read(&dev_priv->vbl_received);
 106 }
 107
 108 irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
 109 {
 110         struct drm_device *dev = (struct drm_device *) arg;
 111         drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
 112         u32 status;
 113         int handled = 0;
 114         struct timeval cur_vblank;
 115         drm_via_irq_t *cur_irq = dev_priv->via_irqs;
 116         int i;
 117
 118         status = VIA_READ(VIA_REG_INTERRUPT);
 119         if (status & VIA_IRQ_VBLANK_PENDING) {
 120                 atomic_inc(&dev_priv->vbl_received);
 121                 if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) {
 122                         do_gettimeofday(&cur_vblank);
 123                         if (dev_priv->last_vblank_valid) {
 124                                 dev_priv->usec_per_vblank =
 125                                         time_diff(&cur_vblank,
 126                                                   &dev_priv->last_vblank) >> 4;
 127                         }
 128                         dev_priv->last_vblank = cur_vblank;
 129                         dev_priv->last_vblank_valid = 1;
 130                 }
 131                 if (!(atomic_read(&dev_priv->vbl_received) & 0xFF)) {
 132                         DRM_DEBUG("US per vblank is: %u\n",
 133                                   dev_priv->usec_per_vblank);
 134                 }
 135                 drm_handle_vblank(dev, 0);
 136                 handled = 1;
 137         }
 138
 139         for (i = 0; i < dev_priv->num_irqs; ++i) {
 140                 if (status & cur_irq->pending_mask) {
 141                         atomic_inc(&cur_irq->irq_received);
 142                         DRM_WAKEUP(&cur_irq->irq_queue);
 143                         handled = 1;
 144                         if (dev_priv->irq_map[drm_via_irq_dma0_td] == i) {
 145                                 via_dmablit_handler(dev, 0, 1);
 146                         } else if (dev_priv->irq_map[drm_via_irq_dma1_td] == i) {
 147                                 via_dmablit_handler(dev, 1, 1);
 148                         }
 149                 }
 150                 cur_irq++;
 151         }
 152
 153         /* Acknowlege interrupts */
 154         VIA_WRITE(VIA_REG_INTERRUPT, status);
 155
 156
 157         if (handled)
 158                 return IRQ_HANDLED;
 159         else
 160                 return IRQ_NONE;
 161 }
 162
 163 static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t * dev_priv)
 164 {
 165         u32 status;
 166
 167         if (dev_priv) {
 168                 /* Acknowlege interrupts */
 169                 status = VIA_READ(VIA_REG_INTERRUPT);
 170                 VIA_WRITE(VIA_REG_INTERRUPT, status |
 171                           dev_priv->irq_pending_mask);
 172         }
 173 }
 174
 175 int via_enable_vblank(struct drm_device *dev, int crtc)
 176 {
 177         drm_via_private_t *dev_priv = dev->dev_private;
 178         u32 status;
 179
 180         if (crtc != 0) {
 181                 DRM_ERROR("%s:  bad crtc %d\n", __func__, crtc);
 182                 return -EINVAL;
 183         }
 184
 185         status = VIA_READ(VIA_REG_INTERRUPT);
 186         VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_VBLANK_ENABLE);
 187
 188         VIA_WRITE8(0x83d4, 0x11);
 189         VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
 190
 191         return 0;
 192 }
 193
 194 void via_disable_vblank(struct drm_device *dev, int crtc)
 195 {
 196         drm_via_private_t *dev_priv = dev->dev_private;
 197         u32 status;
 198
 199         status = VIA_READ(VIA_REG_INTERRUPT);
 200         VIA_WRITE(VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBLANK_ENABLE);
 201
 202         VIA_WRITE8(0x83d4, 0x11);
 203         VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
 204
 205         if (crtc != 0)
 206                 DRM_ERROR("%s:  bad crtc %d\n", __func__, crtc);
 207 }
 208
 209 static int
 210 via_driver_irq_wait(struct drm_device * dev, unsigned int irq, int force_sequence,
 211                     unsigned int *sequence)
 212 {
 213         drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
 214         unsigned int cur_irq_sequence;
 215         drm_via_irq_t *cur_irq;
 216         int ret = 0;
 217         maskarray_t *masks;
 218         int real_irq;
 219
 220         DRM_DEBUG("\n");
 221
 222         if (!dev_priv) {
 223                 DRM_ERROR("called with no initialization\n");
 224                 return -EINVAL;
 225         }
 226
 227         if (irq >= drm_via_irq_num) {
 228                 DRM_ERROR("Trying to wait on unknown irq %d\n", irq);
 229                 return -EINVAL;
 230         }
 231
 232         real_irq = dev_priv->irq_map[irq];
 233
 234         if (real_irq < 0) {
 235                 DRM_ERROR("Video IRQ %d not available on this hardware.\n",
 236                           irq);
 237                 return -EINVAL;
 238         }
 239
 240         masks = dev_priv->irq_masks;
 241         cur_irq = dev_priv->via_irqs + real_irq;
 242
 243         if (masks[real_irq][2] && !force_sequence) {
 244                 DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
 245                             ((VIA_READ(masks[irq][2]) & masks[irq][3]) ==
 246                              masks[irq][4]));
 247                 cur_irq_sequence = atomic_read(&cur_irq->irq_received);
 248         } else {
 249                 DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
 250                             (((cur_irq_sequence =
 251                                atomic_read(&cur_irq->irq_received)) -
 252                               *sequence) <= (1 << 23)));
 253         }
 254         *sequence = cur_irq_sequence;
 255         return ret;
 256 }
 257
 258
 259 /*
 260  * drm_dma.h hooks
 261  */
 262
 263 void via_driver_irq_preinstall(struct drm_device * dev)
 264 {
 265         drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
 266         u32 status;
 267         drm_via_irq_t *cur_irq;
 268         int i;
 269
 270         DRM_DEBUG("dev_priv: %p\n", dev_priv);
 271         if (dev_priv) {
 272                 cur_irq = dev_priv->via_irqs;
 273
 274                 dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE;
 275                 dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING;
 276
 277                 if (dev_priv->chipset == VIA_PRO_GROUP_A ||
 278                     dev_priv->chipset == VIA_DX9_0) {
 279                         dev_priv->irq_masks = via_pro_group_a_irqs;
 280                         dev_priv->num_irqs = via_num_pro_group_a;
 281                         dev_priv->irq_map = via_irqmap_pro_group_a;
 282                 } else {
 283                         dev_priv->irq_masks = via_unichrome_irqs;
 284                         dev_priv->num_irqs = via_num_unichrome;
 285                         dev_priv->irq_map = via_irqmap_unichrome;
 286                 }
 287
 288                 for (i = 0; i < dev_priv->num_irqs; ++i) {
 289                         atomic_set(&cur_irq->irq_received, 0);
 290                         cur_irq->enable_mask = dev_priv->irq_masks[i][0];
 291                         cur_irq->pending_mask = dev_priv->irq_masks[i][1];
 292                         DRM_INIT_WAITQUEUE(&cur_irq->irq_queue);
 293                         dev_priv->irq_enable_mask |= cur_irq->enable_mask;
 294                         dev_priv->irq_pending_mask |= cur_irq->pending_mask;
 295                         cur_irq++;
 296
 297                         DRM_DEBUG("Initializing IRQ %d\n", i);
 298                 }
 299
 300                 dev_priv->last_vblank_valid = 0;
 301
 302                 /* Clear VSync interrupt regs */
 303                 status = VIA_READ(VIA_REG_INTERRUPT);
 304                 VIA_WRITE(VIA_REG_INTERRUPT, status &
 305                           ~(dev_priv->irq_enable_mask));
 306
 307                 /* Clear bits if they're already high */
 308                 viadrv_acknowledge_irqs(dev_priv);
 309         }
 310 }
 311
 312 int via_driver_irq_postinstall(struct drm_device *dev)
 313 {
 314         drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
 315         u32 status;
 316
 317         DRM_DEBUG("via_driver_irq_postinstall\n");
 318         if (!dev_priv)
 319                 return -EINVAL;
 320
 321         status = VIA_READ(VIA_REG_INTERRUPT);
 322         VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
 323                   | dev_priv->irq_enable_mask);
 324
 325         /* Some magic, oh for some data sheets ! */
 326         VIA_WRITE8(0x83d4, 0x11);
 327         VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
 328
 329         return 0;
 330 }
 331
 332 void via_driver_irq_uninstall(struct drm_device * dev)
 333 {
 334         drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
 335         u32 status;
 336
 337         DRM_DEBUG("\n");
 338         if (dev_priv) {
 339
 340                 /* Some more magic, oh for some data sheets ! */
 341
 342                 VIA_WRITE8(0x83d4, 0x11);
 343                 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
 344
 345                 status = VIA_READ(VIA_REG_INTERRUPT);
 346                 VIA_WRITE(VIA_REG_INTERRUPT, status &
 347                           ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask));
 348         }
 349 }
 350
 351 int via_wait_irq(struct drm_device *dev, void *data, struct drm_file *file_priv)
 352 {
 353         drm_via_irqwait_t *irqwait = data;
 354         struct timeval now;
 355         int ret = 0;
 356         drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
 357         drm_via_irq_t *cur_irq = dev_priv->via_irqs;
 358         int force_sequence;
 359
 360         if (irqwait->request.irq >= dev_priv->num_irqs) {
 361                 DRM_ERROR("Trying to wait on unknown irq %d\n",
 362                           irqwait->request.irq);
 363                 return -EINVAL;
 364         }
 365
 366         cur_irq += irqwait->request.irq;
 367
 368         switch (irqwait->request.type & ~VIA_IRQ_FLAGS_MASK) {
 369         case VIA_IRQ_RELATIVE:
 370                 irqwait->request.sequence +=
 371                         atomic_read(&cur_irq->irq_received);
 372                 irqwait->request.type &= ~_DRM_VBLANK_RELATIVE;
 373         case VIA_IRQ_ABSOLUTE:
 374                 break;
 375         default:
 376                 return -EINVAL;
 377         }
 378
 379         if (irqwait->request.type & VIA_IRQ_SIGNAL) {
 380                 DRM_ERROR("Signals on Via IRQs not implemented yet.\n");
 381                 return -EINVAL;
 382         }
 383
 384         force_sequence = (irqwait->request.type & VIA_IRQ_FORCE_SEQUENCE);
 385
 386         ret = via_driver_irq_wait(dev, irqwait->request.irq, force_sequence,
 387                                   &irqwait->request.sequence);
 388         do_gettimeofday(&now);
 389         irqwait->reply.tval_sec = now.tv_sec;
 390         irqwait->reply.tval_usec = now.tv_usec;
 391
 392         return ret;
 393 }