drivers/gpu/drm/radeon/rs690.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31 #include "rs690d.h"
  32
  33 static int rs690_mc_wait_for_idle(struct radeon_device *rdev)
  34 {
  35         unsigned i;
  36         uint32_t tmp;
  37
  38         for (i = 0; i < rdev->usec_timeout; i++) {
  39                 /* read MC_STATUS */
  40                 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
  41                 if (G_000090_MC_SYSTEM_IDLE(tmp))
  42                         return 0;
  43                 udelay(1);
  44         }
  45         return -1;
  46 }
  47
  48 static void rs690_gpu_init(struct radeon_device *rdev)
  49 {
  50         /* FIXME: HDP same place on rs690 ? */
  51         r100_hdp_reset(rdev);
  52         /* FIXME: is this correct ? */
  53         r420_pipes_init(rdev);
  54         if (rs690_mc_wait_for_idle(rdev)) {
  55                 printk(KERN_WARNING "Failed to wait MC idle while "
  56                        "programming pipes. Bad things might happen.\n");
  57         }
  58 }
  59
  60 void rs690_pm_info(struct radeon_device *rdev)
  61 {
  62         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
  63         struct _ATOM_INTEGRATED_SYSTEM_INFO *info;
  64         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *info_v2;
  65         void *ptr;
  66         uint16_t data_offset;
  67         uint8_t frev, crev;
  68         fixed20_12 tmp;
  69
  70         atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
  71                                &frev, &crev, &data_offset);
  72         ptr = rdev->mode_info.atom_context->bios + data_offset;
  73         info = (struct _ATOM_INTEGRATED_SYSTEM_INFO *)ptr;
  74         info_v2 = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *)ptr;
  75         /* Get various system informations from bios */
  76         switch (crev) {
  77         case 1:
  78                 tmp.full = rfixed_const(100);
  79                 rdev->pm.igp_sideport_mclk.full = rfixed_const(info->ulBootUpMemoryClock);
  80                 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
  81                 rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->usK8MemoryClock));
  82                 rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->usFSBClock));
  83                 rdev->pm.igp_ht_link_width.full = rfixed_const(info->ucHTLinkWidth);
  84                 break;
  85         case 2:
  86                 tmp.full = rfixed_const(100);
  87                 rdev->pm.igp_sideport_mclk.full = rfixed_const(info_v2->ulBootUpSidePortClock);
  88                 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
  89                 rdev->pm.igp_system_mclk.full = rfixed_const(info_v2->ulBootUpUMAClock);
  90                 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
  91                 rdev->pm.igp_ht_link_clk.full = rfixed_const(info_v2->ulHTLinkFreq);
  92                 rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp);
  93                 rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info_v2->usMinHTLinkWidth));
  94                 break;
  95         default:
  96                 tmp.full = rfixed_const(100);
  97                 /* We assume the slower possible clock ie worst case */
  98                 /* DDR 333Mhz */
  99                 rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
 100                 /* FIXME: system clock ? */
 101                 rdev->pm.igp_system_mclk.full = rfixed_const(100);
 102                 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
 103                 rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
 104                 rdev->pm.igp_ht_link_width.full = rfixed_const(8);
 105                 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
 106                 break;
 107         }
 108         /* Compute various bandwidth */
 109         /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4  */
 110         tmp.full = rfixed_const(4);
 111         rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp);
 112         /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
 113          *              = ht_clk * ht_width / 5
 114          */
 115         tmp.full = rfixed_const(5);
 116         rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk,
 117                                                 rdev->pm.igp_ht_link_width);
 118         rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp);
 119         if (tmp.full < rdev->pm.max_bandwidth.full) {
 120                 /* HT link is a limiting factor */
 121                 rdev->pm.max_bandwidth.full = tmp.full;
 122         }
 123         /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
 124          *                    = (sideport_clk * 14) / 10
 125          */
 126         tmp.full = rfixed_const(14);
 127         rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
 128         tmp.full = rfixed_const(10);
 129         rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp);
 130 }
 131
 132 void rs690_mc_init(struct radeon_device *rdev)
 133 {
 134         fixed20_12 a;
 135         u64 base;
 136
 137         rs400_gart_adjust_size(rdev);
 138         rdev->mc.vram_is_ddr = true;
 139         rdev->mc.vram_width = 128;
 140         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
 141         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 142         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 143         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 144         rdev->mc.visible_vram_size = rdev->mc.aper_size;
 145         base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
 146         base = G_000100_MC_FB_START(base) << 16;
 147         rs690_pm_info(rdev);
 148         /* FIXME: we should enforce default clock in case GPU is not in
 149          * default setup
 150          */
 151         a.full = rfixed_const(100);
 152         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 153         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 154         a.full = rfixed_const(16);
 155         /* core_bandwidth = sclk(Mhz) * 16 */
 156         rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a);
 157         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 158         radeon_vram_location(rdev, &rdev->mc, base);
 159         radeon_gtt_location(rdev, &rdev->mc);
 160 }
 161
 162 void rs690_line_buffer_adjust(struct radeon_device *rdev,
 163                               struct drm_display_mode *mode1,
 164                               struct drm_display_mode *mode2)
 165 {
 166         u32 tmp;
 167
 168         /*
 169          * Line Buffer Setup
 170          * There is a single line buffer shared by both display controllers.
 171          * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 172          * the display controllers.  The paritioning can either be done
 173          * manually or via one of four preset allocations specified in bits 1:0:
 174          *  0 - line buffer is divided in half and shared between crtc
 175          *  1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
 176          *  2 - D1 gets the whole buffer
 177          *  3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
 178          * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
 179          * allocation mode. In manual allocation mode, D1 always starts at 0,
 180          * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
 181          */
 182         tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
 183         tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
 184         /* auto */
 185         if (mode1 && mode2) {
 186                 if (mode1->hdisplay > mode2->hdisplay) {
 187                         if (mode1->hdisplay > 2560)
 188                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
 189                         else
 190                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 191                 } else if (mode2->hdisplay > mode1->hdisplay) {
 192                         if (mode2->hdisplay > 2560)
 193                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
 194                         else
 195                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 196                 } else
 197                         tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 198         } else if (mode1) {
 199                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
 200         } else if (mode2) {
 201                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
 202         }
 203         WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
 204 }
 205
 206 struct rs690_watermark {
 207         u32        lb_request_fifo_depth;
 208         fixed20_12 num_line_pair;
 209         fixed20_12 estimated_width;
 210         fixed20_12 worst_case_latency;
 211         fixed20_12 consumption_rate;
 212         fixed20_12 active_time;
 213         fixed20_12 dbpp;
 214         fixed20_12 priority_mark_max;
 215         fixed20_12 priority_mark;
 216         fixed20_12 sclk;
 217 };
 218
 219 void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
 220                                   struct radeon_crtc *crtc,
 221                                   struct rs690_watermark *wm)
 222 {
 223         struct drm_display_mode *mode = &crtc->base.mode;
 224         fixed20_12 a, b, c;
 225         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
 226         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
 227         /* FIXME: detect IGP with sideport memory, i don't think there is any
 228          * such product available
 229          */
 230         bool sideport = false;
 231
 232         if (!crtc->base.enabled) {
 233                 /* FIXME: wouldn't it better to set priority mark to maximum */
 234                 wm->lb_request_fifo_depth = 4;
 235                 return;
 236         }
 237
 238         if (crtc->vsc.full > rfixed_const(2))
 239                 wm->num_line_pair.full = rfixed_const(2);
 240         else
 241                 wm->num_line_pair.full = rfixed_const(1);
 242
 243         b.full = rfixed_const(mode->crtc_hdisplay);
 244         c.full = rfixed_const(256);
 245         a.full = rfixed_div(b, c);
 246         request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
 247         request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
 248         if (a.full < rfixed_const(4)) {
 249                 wm->lb_request_fifo_depth = 4;
 250         } else {
 251                 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
 252         }
 253
 254         /* Determine consumption rate
 255          *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
 256          *  vtaps = number of vertical taps,
 257          *  vsc = vertical scaling ratio, defined as source/destination
 258          *  hsc = horizontal scaling ration, defined as source/destination
 259          */
 260         a.full = rfixed_const(mode->clock);
 261         b.full = rfixed_const(1000);
 262         a.full = rfixed_div(a, b);
 263         pclk.full = rfixed_div(b, a);
 264         if (crtc->rmx_type != RMX_OFF) {
 265                 b.full = rfixed_const(2);
 266                 if (crtc->vsc.full > b.full)
 267                         b.full = crtc->vsc.full;
 268                 b.full = rfixed_mul(b, crtc->hsc);
 269                 c.full = rfixed_const(2);
 270                 b.full = rfixed_div(b, c);
 271                 consumption_time.full = rfixed_div(pclk, b);
 272         } else {
 273                 consumption_time.full = pclk.full;
 274         }
 275         a.full = rfixed_const(1);
 276         wm->consumption_rate.full = rfixed_div(a, consumption_time);
 277
 278
 279         /* Determine line time
 280          *  LineTime = total time for one line of displayhtotal
 281          *  LineTime = total number of horizontal pixels
 282          *  pclk = pixel clock period(ns)
 283          */
 284         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
 285         line_time.full = rfixed_mul(a, pclk);
 286
 287         /* Determine active time
 288          *  ActiveTime = time of active region of display within one line,
 289          *  hactive = total number of horizontal active pixels
 290          *  htotal = total number of horizontal pixels
 291          */
 292         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
 293         b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
 294         wm->active_time.full = rfixed_mul(line_time, b);
 295         wm->active_time.full = rfixed_div(wm->active_time, a);
 296
 297         /* Maximun bandwidth is the minimun bandwidth of all component */
 298         rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
 299         if (sideport) {
 300                 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
 301                         rdev->pm.sideport_bandwidth.full)
 302                         rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
 303                 read_delay_latency.full = rfixed_const(370 * 800 * 1000);
 304                 read_delay_latency.full = rfixed_div(read_delay_latency,
 305                         rdev->pm.igp_sideport_mclk);
 306         } else {
 307                 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
 308                         rdev->pm.k8_bandwidth.full)
 309                         rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
 310                 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
 311                         rdev->pm.ht_bandwidth.full)
 312                         rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
 313                 read_delay_latency.full = rfixed_const(5000);
 314         }
 315
 316         /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
 317         a.full = rfixed_const(16);
 318         rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a);
 319         a.full = rfixed_const(1000);
 320         rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk);
 321         /* Determine chunk time
 322          * ChunkTime = the time it takes the DCP to send one chunk of data
 323          * to the LB which consists of pipeline delay and inter chunk gap
 324          * sclk = system clock(ns)
 325          */
 326         a.full = rfixed_const(256 * 13);
 327         chunk_time.full = rfixed_mul(rdev->pm.sclk, a);
 328         a.full = rfixed_const(10);
 329         chunk_time.full = rfixed_div(chunk_time, a);
 330
 331         /* Determine the worst case latency
 332          * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
 333          * WorstCaseLatency = worst case time from urgent to when the MC starts
 334          *                    to return data
 335          * READ_DELAY_IDLE_MAX = constant of 1us
 336          * ChunkTime = time it takes the DCP to send one chunk of data to the LB
 337          *             which consists of pipeline delay and inter chunk gap
 338          */
 339         if (rfixed_trunc(wm->num_line_pair) > 1) {
 340                 a.full = rfixed_const(3);
 341                 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
 342                 wm->worst_case_latency.full += read_delay_latency.full;
 343         } else {
 344                 a.full = rfixed_const(2);
 345                 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
 346                 wm->worst_case_latency.full += read_delay_latency.full;
 347         }
 348
 349         /* Determine the tolerable latency
 350          * TolerableLatency = Any given request has only 1 line time
 351          *                    for the data to be returned
 352          * LBRequestFifoDepth = Number of chunk requests the LB can
 353          *                      put into the request FIFO for a display
 354          *  LineTime = total time for one line of display
 355          *  ChunkTime = the time it takes the DCP to send one chunk
 356          *              of data to the LB which consists of
 357          *  pipeline delay and inter chunk gap
 358          */
 359         if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
 360                 tolerable_latency.full = line_time.full;
 361         } else {
 362                 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
 363                 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
 364                 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
 365                 tolerable_latency.full = line_time.full - tolerable_latency.full;
 366         }
 367         /* We assume worst case 32bits (4 bytes) */
 368         wm->dbpp.full = rfixed_const(4 * 8);
 369
 370         /* Determine the maximum priority mark
 371          *  width = viewport width in pixels
 372          */
 373         a.full = rfixed_const(16);
 374         wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
 375         wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
 376         wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
 377
 378         /* Determine estimated width */
 379         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
 380         estimated_width.full = rfixed_div(estimated_width, consumption_time);
 381         if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
 382                 wm->priority_mark.full = rfixed_const(10);
 383         } else {
 384                 a.full = rfixed_const(16);
 385                 wm->priority_mark.full = rfixed_div(estimated_width, a);
 386                 wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
 387                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
 388         }
 389 }
 390
 391 void rs690_bandwidth_update(struct radeon_device *rdev)
 392 {
 393         struct drm_display_mode *mode0 = NULL;
 394         struct drm_display_mode *mode1 = NULL;
 395         struct rs690_watermark wm0;
 396         struct rs690_watermark wm1;
 397         u32 tmp;
 398         fixed20_12 priority_mark02, priority_mark12, fill_rate;
 399         fixed20_12 a, b;
 400
 401         if (rdev->mode_info.crtcs[0]->base.enabled)
 402                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
 403         if (rdev->mode_info.crtcs[1]->base.enabled)
 404                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 405         /*
 406          * Set display0/1 priority up in the memory controller for
 407          * modes if the user specifies HIGH for displaypriority
 408          * option.
 409          */
 410         if (rdev->disp_priority == 2) {
 411                 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
 412                 tmp &= C_000104_MC_DISP0R_INIT_LAT;
 413                 tmp &= C_000104_MC_DISP1R_INIT_LAT;
 414                 if (mode0)
 415                         tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
 416                 if (mode1)
 417                         tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
 418                 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
 419         }
 420         rs690_line_buffer_adjust(rdev, mode0, mode1);
 421
 422         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
 423                 WREG32(R_006C9C_DCP_CONTROL, 0);
 424         if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
 425                 WREG32(R_006C9C_DCP_CONTROL, 2);
 426
 427         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
 428         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
 429
 430         tmp = (wm0.lb_request_fifo_depth - 1);
 431         tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
 432         WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
 433
 434         if (mode0 && mode1) {
 435                 if (rfixed_trunc(wm0.dbpp) > 64)
 436                         a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
 437                 else
 438                         a.full = wm0.num_line_pair.full;
 439                 if (rfixed_trunc(wm1.dbpp) > 64)
 440                         b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
 441                 else
 442                         b.full = wm1.num_line_pair.full;
 443                 a.full += b.full;
 444                 fill_rate.full = rfixed_div(wm0.sclk, a);
 445                 if (wm0.consumption_rate.full > fill_rate.full) {
 446                         b.full = wm0.consumption_rate.full - fill_rate.full;
 447                         b.full = rfixed_mul(b, wm0.active_time);
 448                         a.full = rfixed_mul(wm0.worst_case_latency,
 449                                                 wm0.consumption_rate);
 450                         a.full = a.full + b.full;
 451                         b.full = rfixed_const(16 * 1000);
 452                         priority_mark02.full = rfixed_div(a, b);
 453                 } else {
 454                         a.full = rfixed_mul(wm0.worst_case_latency,
 455                                                 wm0.consumption_rate);
 456                         b.full = rfixed_const(16 * 1000);
 457                         priority_mark02.full = rfixed_div(a, b);
 458                 }
 459                 if (wm1.consumption_rate.full > fill_rate.full) {
 460                         b.full = wm1.consumption_rate.full - fill_rate.full;
 461                         b.full = rfixed_mul(b, wm1.active_time);
 462                         a.full = rfixed_mul(wm1.worst_case_latency,
 463                                                 wm1.consumption_rate);
 464                         a.full = a.full + b.full;
 465                         b.full = rfixed_const(16 * 1000);
 466                         priority_mark12.full = rfixed_div(a, b);
 467                 } else {
 468                         a.full = rfixed_mul(wm1.worst_case_latency,
 469                                                 wm1.consumption_rate);
 470                         b.full = rfixed_const(16 * 1000);
 471                         priority_mark12.full = rfixed_div(a, b);
 472                 }
 473                 if (wm0.priority_mark.full > priority_mark02.full)
 474                         priority_mark02.full = wm0.priority_mark.full;
 475                 if (rfixed_trunc(priority_mark02) < 0)
 476                         priority_mark02.full = 0;
 477                 if (wm0.priority_mark_max.full > priority_mark02.full)
 478                         priority_mark02.full = wm0.priority_mark_max.full;
 479                 if (wm1.priority_mark.full > priority_mark12.full)
 480                         priority_mark12.full = wm1.priority_mark.full;
 481                 if (rfixed_trunc(priority_mark12) < 0)
 482                         priority_mark12.full = 0;
 483                 if (wm1.priority_mark_max.full > priority_mark12.full)
 484                         priority_mark12.full = wm1.priority_mark_max.full;
 485                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
 486                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
 487                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
 488                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
 489         } else if (mode0) {
 490                 if (rfixed_trunc(wm0.dbpp) > 64)
 491                         a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
 492                 else
 493                         a.full = wm0.num_line_pair.full;
 494                 fill_rate.full = rfixed_div(wm0.sclk, a);
 495                 if (wm0.consumption_rate.full > fill_rate.full) {
 496                         b.full = wm0.consumption_rate.full - fill_rate.full;
 497                         b.full = rfixed_mul(b, wm0.active_time);
 498                         a.full = rfixed_mul(wm0.worst_case_latency,
 499                                                 wm0.consumption_rate);
 500                         a.full = a.full + b.full;
 501                         b.full = rfixed_const(16 * 1000);
 502                         priority_mark02.full = rfixed_div(a, b);
 503                 } else {
 504                         a.full = rfixed_mul(wm0.worst_case_latency,
 505                                                 wm0.consumption_rate);
 506                         b.full = rfixed_const(16 * 1000);
 507                         priority_mark02.full = rfixed_div(a, b);
 508                 }
 509                 if (wm0.priority_mark.full > priority_mark02.full)
 510                         priority_mark02.full = wm0.priority_mark.full;
 511                 if (rfixed_trunc(priority_mark02) < 0)
 512                         priority_mark02.full = 0;
 513                 if (wm0.priority_mark_max.full > priority_mark02.full)
 514                         priority_mark02.full = wm0.priority_mark_max.full;
 515                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
 516                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
 517                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
 518                         S_006D48_D2MODE_PRIORITY_A_OFF(1));
 519                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
 520                         S_006D4C_D2MODE_PRIORITY_B_OFF(1));
 521         } else {
 522                 if (rfixed_trunc(wm1.dbpp) > 64)
 523                         a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
 524                 else
 525                         a.full = wm1.num_line_pair.full;
 526                 fill_rate.full = rfixed_div(wm1.sclk, a);
 527                 if (wm1.consumption_rate.full > fill_rate.full) {
 528                         b.full = wm1.consumption_rate.full - fill_rate.full;
 529                         b.full = rfixed_mul(b, wm1.active_time);
 530                         a.full = rfixed_mul(wm1.worst_case_latency,
 531                                                 wm1.consumption_rate);
 532                         a.full = a.full + b.full;
 533                         b.full = rfixed_const(16 * 1000);
 534                         priority_mark12.full = rfixed_div(a, b);
 535                 } else {
 536                         a.full = rfixed_mul(wm1.worst_case_latency,
 537                                                 wm1.consumption_rate);
 538                         b.full = rfixed_const(16 * 1000);
 539                         priority_mark12.full = rfixed_div(a, b);
 540                 }
 541                 if (wm1.priority_mark.full > priority_mark12.full)
 542                         priority_mark12.full = wm1.priority_mark.full;
 543                 if (rfixed_trunc(priority_mark12) < 0)
 544                         priority_mark12.full = 0;
 545                 if (wm1.priority_mark_max.full > priority_mark12.full)
 546                         priority_mark12.full = wm1.priority_mark_max.full;
 547                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
 548                         S_006548_D1MODE_PRIORITY_A_OFF(1));
 549                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
 550                         S_00654C_D1MODE_PRIORITY_B_OFF(1));
 551                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
 552                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
 553         }
 554 }
 555
 556 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 557 {
 558         uint32_t r;
 559
 560         WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
 561         r = RREG32(R_00007C_MC_DATA);
 562         WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
 563         return r;
 564 }
 565
 566 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 567 {
 568         WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
 569                 S_000078_MC_IND_WR_EN(1));
 570         WREG32(R_00007C_MC_DATA, v);
 571         WREG32(R_000078_MC_INDEX, 0x7F);
 572 }
 573
 574 void rs690_mc_program(struct radeon_device *rdev)
 575 {
 576         struct rv515_mc_save save;
 577
 578         /* Stops all mc clients */
 579         rv515_mc_stop(rdev, &save);
 580
 581         /* Wait for mc idle */
 582         if (rs690_mc_wait_for_idle(rdev))
 583                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 584         /* Program MC, should be a 32bits limited address space */
 585         WREG32_MC(R_000100_MCCFG_FB_LOCATION,
 586                         S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
 587                         S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
 588         WREG32(R_000134_HDP_FB_LOCATION,
 589                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 590
 591         rv515_mc_resume(rdev, &save);
 592 }
 593
 594 static int rs690_startup(struct radeon_device *rdev)
 595 {
 596         int r;
 597
 598         rs690_mc_program(rdev);
 599         /* Resume clock */
 600         rv515_clock_startup(rdev);
 601         /* Initialize GPU configuration (# pipes, ...) */
 602         rs690_gpu_init(rdev);
 603         /* Initialize GART (initialize after TTM so we can allocate
 604          * memory through TTM but finalize after TTM) */
 605         r = rs400_gart_enable(rdev);
 606         if (r)
 607                 return r;
 608         /* Enable IRQ */
 609         rs600_irq_set(rdev);
 610         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 611         /* 1M ring buffer */
 612         r = r100_cp_init(rdev, 1024 * 1024);
 613         if (r) {
 614                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 615                 return r;
 616         }
 617         r = r100_wb_init(rdev);
 618         if (r)
 619                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 620         r = r100_ib_init(rdev);
 621         if (r) {
 622                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 623                 return r;
 624         }
 625         return 0;
 626 }
 627
 628 int rs690_resume(struct radeon_device *rdev)
 629 {
 630         /* Make sur GART are not working */
 631         rs400_gart_disable(rdev);
 632         /* Resume clock before doing reset */
 633         rv515_clock_startup(rdev);
 634         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 635         if (radeon_gpu_reset(rdev)) {
 636                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 637                         RREG32(R_000E40_RBBM_STATUS),
 638                         RREG32(R_0007C0_CP_STAT));
 639         }
 640         /* post */
 641         atom_asic_init(rdev->mode_info.atom_context);
 642         /* Resume clock after posting */
 643         rv515_clock_startup(rdev);
 644         /* Initialize surface registers */
 645         radeon_surface_init(rdev);
 646         return rs690_startup(rdev);
 647 }
 648
 649 int rs690_suspend(struct radeon_device *rdev)
 650 {
 651         r100_cp_disable(rdev);
 652         r100_wb_disable(rdev);
 653         rs600_irq_disable(rdev);
 654         rs400_gart_disable(rdev);
 655         return 0;
 656 }
 657
 658 void rs690_fini(struct radeon_device *rdev)
 659 {
 660         r100_cp_fini(rdev);
 661         r100_wb_fini(rdev);
 662         r100_ib_fini(rdev);
 663         radeon_gem_fini(rdev);
 664         rs400_gart_fini(rdev);
 665         radeon_irq_kms_fini(rdev);
 666         radeon_fence_driver_fini(rdev);
 667         radeon_bo_fini(rdev);
 668         radeon_atombios_fini(rdev);
 669         kfree(rdev->bios);
 670         rdev->bios = NULL;
 671 }
 672
 673 int rs690_init(struct radeon_device *rdev)
 674 {
 675         int r;
 676
 677         /* Disable VGA */
 678         rv515_vga_render_disable(rdev);
 679         /* Initialize scratch registers */
 680         radeon_scratch_init(rdev);
 681         /* Initialize surface registers */
 682         radeon_surface_init(rdev);
 683         /* TODO: disable VGA need to use VGA request */
 684         /* BIOS*/
 685         if (!radeon_get_bios(rdev)) {
 686                 if (ASIC_IS_AVIVO(rdev))
 687                         return -EINVAL;
 688         }
 689         if (rdev->is_atom_bios) {
 690                 r = radeon_atombios_init(rdev);
 691                 if (r)
 692                         return r;
 693         } else {
 694                 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
 695                 return -EINVAL;
 696         }
 697         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 698         if (radeon_gpu_reset(rdev)) {
 699                 dev_warn(rdev->dev,
 700                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 701                         RREG32(R_000E40_RBBM_STATUS),
 702                         RREG32(R_0007C0_CP_STAT));
 703         }
 704         /* check if cards are posted or not */
 705         if (radeon_boot_test_post_card(rdev) == false)
 706                 return -EINVAL;
 707
 708         /* Initialize clocks */
 709         radeon_get_clock_info(rdev->ddev);
 710         /* Initialize power management */
 711         radeon_pm_init(rdev);
 712         /* initialize memory controller */
 713         rs690_mc_init(rdev);
 714         rv515_debugfs(rdev);
 715         /* Fence driver */
 716         r = radeon_fence_driver_init(rdev);
 717         if (r)
 718                 return r;
 719         r = radeon_irq_kms_init(rdev);
 720         if (r)
 721                 return r;
 722         /* Memory manager */
 723         r = radeon_bo_init(rdev);
 724         if (r)
 725                 return r;
 726         r = rs400_gart_init(rdev);
 727         if (r)
 728                 return r;
 729         rs600_set_safe_registers(rdev);
 730         rdev->accel_working = true;
 731         r = rs690_startup(rdev);
 732         if (r) {
 733                 /* Somethings want wront with the accel init stop accel */
 734                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 735                 r100_cp_fini(rdev);
 736                 r100_wb_fini(rdev);
 737                 r100_ib_fini(rdev);
 738                 rs400_gart_fini(rdev);
 739                 radeon_irq_kms_fini(rdev);
 740                 rdev->accel_working = false;
 741         }
 742         return 0;
 743 }