drivers/gpu/drm/radeon/rs690.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include "atom.h"
  32 #include "rs690d.h"
  33
  34 static int rs690_mc_wait_for_idle(struct radeon_device *rdev)
  35 {
  36         unsigned i;
  37         uint32_t tmp;
  38
  39         for (i = 0; i < rdev->usec_timeout; i++) {
  40                 /* read MC_STATUS */
  41                 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
  42                 if (G_000090_MC_SYSTEM_IDLE(tmp))
  43                         return 0;
  44                 udelay(1);
  45         }
  46         return -1;
  47 }
  48
  49 static void rs690_gpu_init(struct radeon_device *rdev)
  50 {
  51         /* FIXME: HDP same place on rs690 ? */
  52         r100_hdp_reset(rdev);
  53         /* FIXME: is this correct ? */
  54         r420_pipes_init(rdev);
  55         if (rs690_mc_wait_for_idle(rdev)) {
  56                 printk(KERN_WARNING "Failed to wait MC idle while "
  57                        "programming pipes. Bad things might happen.\n");
  58         }
  59 }
  60
  61 union igp_info {
  62         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
  63         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
  64 };
  65
  66 void rs690_pm_info(struct radeon_device *rdev)
  67 {
  68         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
  69         union igp_info *info;
  70         uint16_t data_offset;
  71         uint8_t frev, crev;
  72         fixed20_12 tmp;
  73
  74         if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
  75                                    &frev, &crev, &data_offset)) {
  76                 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
  77
  78                 /* Get various system informations from bios */
  79                 switch (crev) {
  80                 case 1:
  81                         tmp.full = rfixed_const(100);
  82                         rdev->pm.igp_sideport_mclk.full = rfixed_const(info->info.ulBootUpMemoryClock);
  83                         rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
  84                         rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
  85                         rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->info.usFSBClock));
  86                         rdev->pm.igp_ht_link_width.full = rfixed_const(info->info.ucHTLinkWidth);
  87                         break;
  88                 case 2:
  89                         tmp.full = rfixed_const(100);
  90                         rdev->pm.igp_sideport_mclk.full = rfixed_const(info->info_v2.ulBootUpSidePortClock);
  91                         rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
  92                         rdev->pm.igp_system_mclk.full = rfixed_const(info->info_v2.ulBootUpUMAClock);
  93                         rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
  94                         rdev->pm.igp_ht_link_clk.full = rfixed_const(info->info_v2.ulHTLinkFreq);
  95                         rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp);
  96                         rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
  97                         break;
  98                 default:
  99                         tmp.full = rfixed_const(100);
 100                         /* We assume the slower possible clock ie worst case */
 101                         /* DDR 333Mhz */
 102                         rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
 103                         /* FIXME: system clock ? */
 104                         rdev->pm.igp_system_mclk.full = rfixed_const(100);
 105                         rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
 106                         rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
 107                         rdev->pm.igp_ht_link_width.full = rfixed_const(8);
 108                         DRM_ERROR("No integrated system info for your GPU, using safe default\n");
 109                         break;
 110                 }
 111         } else {
 112                 tmp.full = rfixed_const(100);
 113                 /* We assume the slower possible clock ie worst case */
 114                 /* DDR 333Mhz */
 115                 rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
 116                 /* FIXME: system clock ? */
 117                 rdev->pm.igp_system_mclk.full = rfixed_const(100);
 118                 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
 119                 rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
 120                 rdev->pm.igp_ht_link_width.full = rfixed_const(8);
 121                 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
 122         }
 123         /* Compute various bandwidth */
 124         /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4  */
 125         tmp.full = rfixed_const(4);
 126         rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp);
 127         /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
 128          *              = ht_clk * ht_width / 5
 129          */
 130         tmp.full = rfixed_const(5);
 131         rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk,
 132                                                 rdev->pm.igp_ht_link_width);
 133         rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp);
 134         if (tmp.full < rdev->pm.max_bandwidth.full) {
 135                 /* HT link is a limiting factor */
 136                 rdev->pm.max_bandwidth.full = tmp.full;
 137         }
 138         /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
 139          *                    = (sideport_clk * 14) / 10
 140          */
 141         tmp.full = rfixed_const(14);
 142         rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
 143         tmp.full = rfixed_const(10);
 144         rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp);
 145 }
 146
 147 void rs690_mc_init(struct radeon_device *rdev)
 148 {
 149         u64 base;
 150
 151         rs400_gart_adjust_size(rdev);
 152         rdev->mc.vram_is_ddr = true;
 153         rdev->mc.vram_width = 128;
 154         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
 155         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 156         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 157         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 158         rdev->mc.visible_vram_size = rdev->mc.aper_size;
 159         base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
 160         base = G_000100_MC_FB_START(base) << 16;
 161         rs690_pm_info(rdev);
 162         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 163         radeon_vram_location(rdev, &rdev->mc, base);
 164         radeon_gtt_location(rdev, &rdev->mc);
 165         radeon_update_bandwidth_info(rdev);
 166 }
 167
 168 void rs690_line_buffer_adjust(struct radeon_device *rdev,
 169                               struct drm_display_mode *mode1,
 170                               struct drm_display_mode *mode2)
 171 {
 172         u32 tmp;
 173
 174         /*
 175          * Line Buffer Setup
 176          * There is a single line buffer shared by both display controllers.
 177          * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 178          * the display controllers.  The paritioning can either be done
 179          * manually or via one of four preset allocations specified in bits 1:0:
 180          *  0 - line buffer is divided in half and shared between crtc
 181          *  1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
 182          *  2 - D1 gets the whole buffer
 183          *  3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
 184          * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
 185          * allocation mode. In manual allocation mode, D1 always starts at 0,
 186          * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
 187          */
 188         tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
 189         tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
 190         /* auto */
 191         if (mode1 && mode2) {
 192                 if (mode1->hdisplay > mode2->hdisplay) {
 193                         if (mode1->hdisplay > 2560)
 194                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
 195                         else
 196                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 197                 } else if (mode2->hdisplay > mode1->hdisplay) {
 198                         if (mode2->hdisplay > 2560)
 199                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
 200                         else
 201                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 202                 } else
 203                         tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 204         } else if (mode1) {
 205                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
 206         } else if (mode2) {
 207                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
 208         }
 209         WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
 210 }
 211
 212 struct rs690_watermark {
 213         u32        lb_request_fifo_depth;
 214         fixed20_12 num_line_pair;
 215         fixed20_12 estimated_width;
 216         fixed20_12 worst_case_latency;
 217         fixed20_12 consumption_rate;
 218         fixed20_12 active_time;
 219         fixed20_12 dbpp;
 220         fixed20_12 priority_mark_max;
 221         fixed20_12 priority_mark;
 222         fixed20_12 sclk;
 223 };
 224
 225 void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
 226                                   struct radeon_crtc *crtc,
 227                                   struct rs690_watermark *wm)
 228 {
 229         struct drm_display_mode *mode = &crtc->base.mode;
 230         fixed20_12 a, b, c;
 231         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
 232         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
 233         /* FIXME: detect IGP with sideport memory, i don't think there is any
 234          * such product available
 235          */
 236         bool sideport = false;
 237
 238         if (!crtc->base.enabled) {
 239                 /* FIXME: wouldn't it better to set priority mark to maximum */
 240                 wm->lb_request_fifo_depth = 4;
 241                 return;
 242         }
 243
 244         if (crtc->vsc.full > rfixed_const(2))
 245                 wm->num_line_pair.full = rfixed_const(2);
 246         else
 247                 wm->num_line_pair.full = rfixed_const(1);
 248
 249         b.full = rfixed_const(mode->crtc_hdisplay);
 250         c.full = rfixed_const(256);
 251         a.full = rfixed_div(b, c);
 252         request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
 253         request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
 254         if (a.full < rfixed_const(4)) {
 255                 wm->lb_request_fifo_depth = 4;
 256         } else {
 257                 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
 258         }
 259
 260         /* Determine consumption rate
 261          *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
 262          *  vtaps = number of vertical taps,
 263          *  vsc = vertical scaling ratio, defined as source/destination
 264          *  hsc = horizontal scaling ration, defined as source/destination
 265          */
 266         a.full = rfixed_const(mode->clock);
 267         b.full = rfixed_const(1000);
 268         a.full = rfixed_div(a, b);
 269         pclk.full = rfixed_div(b, a);
 270         if (crtc->rmx_type != RMX_OFF) {
 271                 b.full = rfixed_const(2);
 272                 if (crtc->vsc.full > b.full)
 273                         b.full = crtc->vsc.full;
 274                 b.full = rfixed_mul(b, crtc->hsc);
 275                 c.full = rfixed_const(2);
 276                 b.full = rfixed_div(b, c);
 277                 consumption_time.full = rfixed_div(pclk, b);
 278         } else {
 279                 consumption_time.full = pclk.full;
 280         }
 281         a.full = rfixed_const(1);
 282         wm->consumption_rate.full = rfixed_div(a, consumption_time);
 283
 284
 285         /* Determine line time
 286          *  LineTime = total time for one line of displayhtotal
 287          *  LineTime = total number of horizontal pixels
 288          *  pclk = pixel clock period(ns)
 289          */
 290         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
 291         line_time.full = rfixed_mul(a, pclk);
 292
 293         /* Determine active time
 294          *  ActiveTime = time of active region of display within one line,
 295          *  hactive = total number of horizontal active pixels
 296          *  htotal = total number of horizontal pixels
 297          */
 298         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
 299         b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
 300         wm->active_time.full = rfixed_mul(line_time, b);
 301         wm->active_time.full = rfixed_div(wm->active_time, a);
 302
 303         /* Maximun bandwidth is the minimun bandwidth of all component */
 304         rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
 305         if (sideport) {
 306                 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
 307                         rdev->pm.sideport_bandwidth.full)
 308                         rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
 309                 read_delay_latency.full = rfixed_const(370 * 800 * 1000);
 310                 read_delay_latency.full = rfixed_div(read_delay_latency,
 311                         rdev->pm.igp_sideport_mclk);
 312         } else {
 313                 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
 314                         rdev->pm.k8_bandwidth.full)
 315                         rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
 316                 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
 317                         rdev->pm.ht_bandwidth.full)
 318                         rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
 319                 read_delay_latency.full = rfixed_const(5000);
 320         }
 321
 322         /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
 323         a.full = rfixed_const(16);
 324         rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a);
 325         a.full = rfixed_const(1000);
 326         rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk);
 327         /* Determine chunk time
 328          * ChunkTime = the time it takes the DCP to send one chunk of data
 329          * to the LB which consists of pipeline delay and inter chunk gap
 330          * sclk = system clock(ns)
 331          */
 332         a.full = rfixed_const(256 * 13);
 333         chunk_time.full = rfixed_mul(rdev->pm.sclk, a);
 334         a.full = rfixed_const(10);
 335         chunk_time.full = rfixed_div(chunk_time, a);
 336
 337         /* Determine the worst case latency
 338          * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
 339          * WorstCaseLatency = worst case time from urgent to when the MC starts
 340          *                    to return data
 341          * READ_DELAY_IDLE_MAX = constant of 1us
 342          * ChunkTime = time it takes the DCP to send one chunk of data to the LB
 343          *             which consists of pipeline delay and inter chunk gap
 344          */
 345         if (rfixed_trunc(wm->num_line_pair) > 1) {
 346                 a.full = rfixed_const(3);
 347                 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
 348                 wm->worst_case_latency.full += read_delay_latency.full;
 349         } else {
 350                 a.full = rfixed_const(2);
 351                 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
 352                 wm->worst_case_latency.full += read_delay_latency.full;
 353         }
 354
 355         /* Determine the tolerable latency
 356          * TolerableLatency = Any given request has only 1 line time
 357          *                    for the data to be returned
 358          * LBRequestFifoDepth = Number of chunk requests the LB can
 359          *                      put into the request FIFO for a display
 360          *  LineTime = total time for one line of display
 361          *  ChunkTime = the time it takes the DCP to send one chunk
 362          *              of data to the LB which consists of
 363          *  pipeline delay and inter chunk gap
 364          */
 365         if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
 366                 tolerable_latency.full = line_time.full;
 367         } else {
 368                 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
 369                 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
 370                 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
 371                 tolerable_latency.full = line_time.full - tolerable_latency.full;
 372         }
 373         /* We assume worst case 32bits (4 bytes) */
 374         wm->dbpp.full = rfixed_const(4 * 8);
 375
 376         /* Determine the maximum priority mark
 377          *  width = viewport width in pixels
 378          */
 379         a.full = rfixed_const(16);
 380         wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
 381         wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
 382         wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
 383
 384         /* Determine estimated width */
 385         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
 386         estimated_width.full = rfixed_div(estimated_width, consumption_time);
 387         if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
 388                 wm->priority_mark.full = rfixed_const(10);
 389         } else {
 390                 a.full = rfixed_const(16);
 391                 wm->priority_mark.full = rfixed_div(estimated_width, a);
 392                 wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
 393                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
 394         }
 395 }
 396
 397 void rs690_bandwidth_update(struct radeon_device *rdev)
 398 {
 399         struct drm_display_mode *mode0 = NULL;
 400         struct drm_display_mode *mode1 = NULL;
 401         struct rs690_watermark wm0;
 402         struct rs690_watermark wm1;
 403         u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt;
 404         fixed20_12 priority_mark02, priority_mark12, fill_rate;
 405         fixed20_12 a, b;
 406
 407         radeon_update_display_priority(rdev);
 408
 409         if (rdev->mode_info.crtcs[0]->base.enabled)
 410                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
 411         if (rdev->mode_info.crtcs[1]->base.enabled)
 412                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 413         /*
 414          * Set display0/1 priority up in the memory controller for
 415          * modes if the user specifies HIGH for displaypriority
 416          * option.
 417          */
 418         if ((rdev->disp_priority == 2) &&
 419             ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
 420                 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
 421                 tmp &= C_000104_MC_DISP0R_INIT_LAT;
 422                 tmp &= C_000104_MC_DISP1R_INIT_LAT;
 423                 if (mode0)
 424                         tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
 425                 if (mode1)
 426                         tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
 427                 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
 428         }
 429         rs690_line_buffer_adjust(rdev, mode0, mode1);
 430
 431         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
 432                 WREG32(R_006C9C_DCP_CONTROL, 0);
 433         if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
 434                 WREG32(R_006C9C_DCP_CONTROL, 2);
 435
 436         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
 437         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
 438
 439         tmp = (wm0.lb_request_fifo_depth - 1);
 440         tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
 441         WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
 442
 443         if (mode0 && mode1) {
 444                 if (rfixed_trunc(wm0.dbpp) > 64)
 445                         a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
 446                 else
 447                         a.full = wm0.num_line_pair.full;
 448                 if (rfixed_trunc(wm1.dbpp) > 64)
 449                         b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
 450                 else
 451                         b.full = wm1.num_line_pair.full;
 452                 a.full += b.full;
 453                 fill_rate.full = rfixed_div(wm0.sclk, a);
 454                 if (wm0.consumption_rate.full > fill_rate.full) {
 455                         b.full = wm0.consumption_rate.full - fill_rate.full;
 456                         b.full = rfixed_mul(b, wm0.active_time);
 457                         a.full = rfixed_mul(wm0.worst_case_latency,
 458                                                 wm0.consumption_rate);
 459                         a.full = a.full + b.full;
 460                         b.full = rfixed_const(16 * 1000);
 461                         priority_mark02.full = rfixed_div(a, b);
 462                 } else {
 463                         a.full = rfixed_mul(wm0.worst_case_latency,
 464                                                 wm0.consumption_rate);
 465                         b.full = rfixed_const(16 * 1000);
 466                         priority_mark02.full = rfixed_div(a, b);
 467                 }
 468                 if (wm1.consumption_rate.full > fill_rate.full) {
 469                         b.full = wm1.consumption_rate.full - fill_rate.full;
 470                         b.full = rfixed_mul(b, wm1.active_time);
 471                         a.full = rfixed_mul(wm1.worst_case_latency,
 472                                                 wm1.consumption_rate);
 473                         a.full = a.full + b.full;
 474                         b.full = rfixed_const(16 * 1000);
 475                         priority_mark12.full = rfixed_div(a, b);
 476                 } else {
 477                         a.full = rfixed_mul(wm1.worst_case_latency,
 478                                                 wm1.consumption_rate);
 479                         b.full = rfixed_const(16 * 1000);
 480                         priority_mark12.full = rfixed_div(a, b);
 481                 }
 482                 if (wm0.priority_mark.full > priority_mark02.full)
 483                         priority_mark02.full = wm0.priority_mark.full;
 484                 if (rfixed_trunc(priority_mark02) < 0)
 485                         priority_mark02.full = 0;
 486                 if (wm0.priority_mark_max.full > priority_mark02.full)
 487                         priority_mark02.full = wm0.priority_mark_max.full;
 488                 if (wm1.priority_mark.full > priority_mark12.full)
 489                         priority_mark12.full = wm1.priority_mark.full;
 490                 if (rfixed_trunc(priority_mark12) < 0)
 491                         priority_mark12.full = 0;
 492                 if (wm1.priority_mark_max.full > priority_mark12.full)
 493                         priority_mark12.full = wm1.priority_mark_max.full;
 494                 d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
 495                 d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
 496                 if (rdev->disp_priority == 2) {
 497                         d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
 498                         d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
 499                 }
 500                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
 501                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
 502                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
 503                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
 504         } else if (mode0) {
 505                 if (rfixed_trunc(wm0.dbpp) > 64)
 506                         a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
 507                 else
 508                         a.full = wm0.num_line_pair.full;
 509                 fill_rate.full = rfixed_div(wm0.sclk, a);
 510                 if (wm0.consumption_rate.full > fill_rate.full) {
 511                         b.full = wm0.consumption_rate.full - fill_rate.full;
 512                         b.full = rfixed_mul(b, wm0.active_time);
 513                         a.full = rfixed_mul(wm0.worst_case_latency,
 514                                                 wm0.consumption_rate);
 515                         a.full = a.full + b.full;
 516                         b.full = rfixed_const(16 * 1000);
 517                         priority_mark02.full = rfixed_div(a, b);
 518                 } else {
 519                         a.full = rfixed_mul(wm0.worst_case_latency,
 520                                                 wm0.consumption_rate);
 521                         b.full = rfixed_const(16 * 1000);
 522                         priority_mark02.full = rfixed_div(a, b);
 523                 }
 524                 if (wm0.priority_mark.full > priority_mark02.full)
 525                         priority_mark02.full = wm0.priority_mark.full;
 526                 if (rfixed_trunc(priority_mark02) < 0)
 527                         priority_mark02.full = 0;
 528                 if (wm0.priority_mark_max.full > priority_mark02.full)
 529                         priority_mark02.full = wm0.priority_mark_max.full;
 530                 d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
 531                 if (rdev->disp_priority == 2)
 532                         d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
 533                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
 534                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
 535                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
 536                         S_006D48_D2MODE_PRIORITY_A_OFF(1));
 537                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
 538                         S_006D4C_D2MODE_PRIORITY_B_OFF(1));
 539         } else {
 540                 if (rfixed_trunc(wm1.dbpp) > 64)
 541                         a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
 542                 else
 543                         a.full = wm1.num_line_pair.full;
 544                 fill_rate.full = rfixed_div(wm1.sclk, a);
 545                 if (wm1.consumption_rate.full > fill_rate.full) {
 546                         b.full = wm1.consumption_rate.full - fill_rate.full;
 547                         b.full = rfixed_mul(b, wm1.active_time);
 548                         a.full = rfixed_mul(wm1.worst_case_latency,
 549                                                 wm1.consumption_rate);
 550                         a.full = a.full + b.full;
 551                         b.full = rfixed_const(16 * 1000);
 552                         priority_mark12.full = rfixed_div(a, b);
 553                 } else {
 554                         a.full = rfixed_mul(wm1.worst_case_latency,
 555                                                 wm1.consumption_rate);
 556                         b.full = rfixed_const(16 * 1000);
 557                         priority_mark12.full = rfixed_div(a, b);
 558                 }
 559                 if (wm1.priority_mark.full > priority_mark12.full)
 560                         priority_mark12.full = wm1.priority_mark.full;
 561                 if (rfixed_trunc(priority_mark12) < 0)
 562                         priority_mark12.full = 0;
 563                 if (wm1.priority_mark_max.full > priority_mark12.full)
 564                         priority_mark12.full = wm1.priority_mark_max.full;
 565                 d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
 566                 if (rdev->disp_priority == 2)
 567                         d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
 568                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
 569                         S_006548_D1MODE_PRIORITY_A_OFF(1));
 570                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
 571                         S_00654C_D1MODE_PRIORITY_B_OFF(1));
 572                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
 573                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
 574         }
 575 }
 576
 577 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 578 {
 579         uint32_t r;
 580
 581         WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
 582         r = RREG32(R_00007C_MC_DATA);
 583         WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
 584         return r;
 585 }
 586
 587 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 588 {
 589         WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
 590                 S_000078_MC_IND_WR_EN(1));
 591         WREG32(R_00007C_MC_DATA, v);
 592         WREG32(R_000078_MC_INDEX, 0x7F);
 593 }
 594
 595 void rs690_mc_program(struct radeon_device *rdev)
 596 {
 597         struct rv515_mc_save save;
 598
 599         /* Stops all mc clients */
 600         rv515_mc_stop(rdev, &save);
 601
 602         /* Wait for mc idle */
 603         if (rs690_mc_wait_for_idle(rdev))
 604                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 605         /* Program MC, should be a 32bits limited address space */
 606         WREG32_MC(R_000100_MCCFG_FB_LOCATION,
 607                         S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
 608                         S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
 609         WREG32(R_000134_HDP_FB_LOCATION,
 610                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 611
 612         rv515_mc_resume(rdev, &save);
 613 }
 614
 615 static int rs690_startup(struct radeon_device *rdev)
 616 {
 617         int r;
 618
 619         rs690_mc_program(rdev);
 620         /* Resume clock */
 621         rv515_clock_startup(rdev);
 622         /* Initialize GPU configuration (# pipes, ...) */
 623         rs690_gpu_init(rdev);
 624         /* Initialize GART (initialize after TTM so we can allocate
 625          * memory through TTM but finalize after TTM) */
 626         r = rs400_gart_enable(rdev);
 627         if (r)
 628                 return r;
 629         /* Enable IRQ */
 630         rs600_irq_set(rdev);
 631         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 632         /* 1M ring buffer */
 633         r = r100_cp_init(rdev, 1024 * 1024);
 634         if (r) {
 635                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 636                 return r;
 637         }
 638         r = r100_wb_init(rdev);
 639         if (r)
 640                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 641         r = r100_ib_init(rdev);
 642         if (r) {
 643                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 644                 return r;
 645         }
 646         return 0;
 647 }
 648
 649 int rs690_resume(struct radeon_device *rdev)
 650 {
 651         /* Make sur GART are not working */
 652         rs400_gart_disable(rdev);
 653         /* Resume clock before doing reset */
 654         rv515_clock_startup(rdev);
 655         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 656         if (radeon_gpu_reset(rdev)) {
 657                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 658                         RREG32(R_000E40_RBBM_STATUS),
 659                         RREG32(R_0007C0_CP_STAT));
 660         }
 661         /* post */
 662         atom_asic_init(rdev->mode_info.atom_context);
 663         /* Resume clock after posting */
 664         rv515_clock_startup(rdev);
 665         /* Initialize surface registers */
 666         radeon_surface_init(rdev);
 667         return rs690_startup(rdev);
 668 }
 669
 670 int rs690_suspend(struct radeon_device *rdev)
 671 {
 672         r100_cp_disable(rdev);
 673         r100_wb_disable(rdev);
 674         rs600_irq_disable(rdev);
 675         rs400_gart_disable(rdev);
 676         return 0;
 677 }
 678
 679 void rs690_fini(struct radeon_device *rdev)
 680 {
 681         radeon_pm_fini(rdev);
 682         r100_cp_fini(rdev);
 683         r100_wb_fini(rdev);
 684         r100_ib_fini(rdev);
 685         radeon_gem_fini(rdev);
 686         rs400_gart_fini(rdev);
 687         radeon_irq_kms_fini(rdev);
 688         radeon_fence_driver_fini(rdev);
 689         radeon_bo_fini(rdev);
 690         radeon_atombios_fini(rdev);
 691         kfree(rdev->bios);
 692         rdev->bios = NULL;
 693 }
 694
 695 int rs690_init(struct radeon_device *rdev)
 696 {
 697         int r;
 698
 699         /* Disable VGA */
 700         rv515_vga_render_disable(rdev);
 701         /* Initialize scratch registers */
 702         radeon_scratch_init(rdev);
 703         /* Initialize surface registers */
 704         radeon_surface_init(rdev);
 705         /* TODO: disable VGA need to use VGA request */
 706         /* BIOS*/
 707         if (!radeon_get_bios(rdev)) {
 708                 if (ASIC_IS_AVIVO(rdev))
 709                         return -EINVAL;
 710         }
 711         if (rdev->is_atom_bios) {
 712                 r = radeon_atombios_init(rdev);
 713                 if (r)
 714                         return r;
 715         } else {
 716                 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
 717                 return -EINVAL;
 718         }
 719         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 720         if (radeon_gpu_reset(rdev)) {
 721                 dev_warn(rdev->dev,
 722                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 723                         RREG32(R_000E40_RBBM_STATUS),
 724                         RREG32(R_0007C0_CP_STAT));
 725         }
 726         /* check if cards are posted or not */
 727         if (radeon_boot_test_post_card(rdev) == false)
 728                 return -EINVAL;
 729
 730         /* Initialize clocks */
 731         radeon_get_clock_info(rdev->ddev);
 732         /* Initialize power management */
 733         radeon_pm_init(rdev);
 734         /* initialize memory controller */
 735         rs690_mc_init(rdev);
 736         rv515_debugfs(rdev);
 737         /* Fence driver */
 738         r = radeon_fence_driver_init(rdev);
 739         if (r)
 740                 return r;
 741         r = radeon_irq_kms_init(rdev);
 742         if (r)
 743                 return r;
 744         /* Memory manager */
 745         r = radeon_bo_init(rdev);
 746         if (r)
 747                 return r;
 748         r = rs400_gart_init(rdev);
 749         if (r)
 750                 return r;
 751         rs600_set_safe_registers(rdev);
 752         rdev->accel_working = true;
 753         r = rs690_startup(rdev);
 754         if (r) {
 755                 /* Somethings want wront with the accel init stop accel */
 756                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 757                 r100_cp_fini(rdev);
 758                 r100_wb_fini(rdev);
 759                 r100_ib_fini(rdev);
 760                 rs400_gart_fini(rdev);
 761                 radeon_irq_kms_fini(rdev);
 762                 rdev->accel_working = false;
 763         }
 764         return 0;
 765 }