drivers/gpu/drm/radeon/rs690.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include "atom.h"
  32 #include "rs690d.h"
  33
  34 static int rs690_mc_wait_for_idle(struct radeon_device *rdev)
  35 {
  36         unsigned i;
  37         uint32_t tmp;
  38
  39         for (i = 0; i < rdev->usec_timeout; i++) {
  40                 /* read MC_STATUS */
  41                 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
  42                 if (G_000090_MC_SYSTEM_IDLE(tmp))
  43                         return 0;
  44                 udelay(1);
  45         }
  46         return -1;
  47 }
  48
  49 static void rs690_gpu_init(struct radeon_device *rdev)
  50 {
  51         /* FIXME: is this correct ? */
  52         r420_pipes_init(rdev);
  53         if (rs690_mc_wait_for_idle(rdev)) {
  54                 printk(KERN_WARNING "Failed to wait MC idle while "
  55                        "programming pipes. Bad things might happen.\n");
  56         }
  57 }
  58
  59 union igp_info {
  60         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
  61         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
  62 };
  63
  64 void rs690_pm_info(struct radeon_device *rdev)
  65 {
  66         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
  67         union igp_info *info;
  68         uint16_t data_offset;
  69         uint8_t frev, crev;
  70         fixed20_12 tmp;
  71
  72         if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
  73                                    &frev, &crev, &data_offset)) {
  74                 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
  75
  76                 /* Get various system informations from bios */
  77                 switch (crev) {
  78                 case 1:
  79                         tmp.full = dfixed_const(100);
  80                         rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock));
  81                         rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
  82                         if (le16_to_cpu(info->info.usK8MemoryClock))
  83                                 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
  84                         else if (rdev->clock.default_mclk) {
  85                                 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
  86                                 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
  87                         } else
  88                                 rdev->pm.igp_system_mclk.full = dfixed_const(400);
  89                         rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
  90                         rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
  91                         break;
  92                 case 2:
  93                         tmp.full = dfixed_const(100);
  94                         rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock));
  95                         rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
  96                         if (le32_to_cpu(info->info_v2.ulBootUpUMAClock))
  97                                 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock));
  98                         else if (rdev->clock.default_mclk)
  99                                 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
 100                         else
 101                                 rdev->pm.igp_system_mclk.full = dfixed_const(66700);
 102                         rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
 103                         rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq));
 104                         rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
 105                         rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
 106                         break;
 107                 default:
 108                         /* We assume the slower possible clock ie worst case */
 109                         rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
 110                         rdev->pm.igp_system_mclk.full = dfixed_const(200);
 111                         rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
 112                         rdev->pm.igp_ht_link_width.full = dfixed_const(8);
 113                         DRM_ERROR("No integrated system info for your GPU, using safe default\n");
 114                         break;
 115                 }
 116         } else {
 117                 /* We assume the slower possible clock ie worst case */
 118                 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
 119                 rdev->pm.igp_system_mclk.full = dfixed_const(200);
 120                 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
 121                 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
 122                 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
 123         }
 124         /* Compute various bandwidth */
 125         /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4  */
 126         tmp.full = dfixed_const(4);
 127         rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
 128         /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
 129          *              = ht_clk * ht_width / 5
 130          */
 131         tmp.full = dfixed_const(5);
 132         rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
 133                                                 rdev->pm.igp_ht_link_width);
 134         rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
 135         if (tmp.full < rdev->pm.max_bandwidth.full) {
 136                 /* HT link is a limiting factor */
 137                 rdev->pm.max_bandwidth.full = tmp.full;
 138         }
 139         /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
 140          *                    = (sideport_clk * 14) / 10
 141          */
 142         tmp.full = dfixed_const(14);
 143         rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
 144         tmp.full = dfixed_const(10);
 145         rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
 146 }
 147
 148 void rs690_mc_init(struct radeon_device *rdev)
 149 {
 150         u64 base;
 151
 152         rs400_gart_adjust_size(rdev);
 153         rdev->mc.vram_is_ddr = true;
 154         rdev->mc.vram_width = 128;
 155         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
 156         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 157         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
 158         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
 159         rdev->mc.visible_vram_size = rdev->mc.aper_size;
 160         base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
 161         base = G_000100_MC_FB_START(base) << 16;
 162         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 163         /* Some boards seem to be configured for 128MB of sideport memory,
 164          * but really only have 64MB.  Just skip the sideport and use
 165          * UMA memory.
 166          */
 167         if (rdev->mc.igp_sideport_enabled &&
 168             (rdev->mc.real_vram_size == (384 * 1024 * 1024))) {
 169                 base += 128 * 1024 * 1024;
 170                 rdev->mc.real_vram_size -= 128 * 1024 * 1024;
 171                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 172         }
 173         rs690_pm_info(rdev);
 174         radeon_vram_location(rdev, &rdev->mc, base);
 175         rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
 176         radeon_gtt_location(rdev, &rdev->mc);
 177         radeon_update_bandwidth_info(rdev);
 178 }
 179
 180 void rs690_line_buffer_adjust(struct radeon_device *rdev,
 181                               struct drm_display_mode *mode1,
 182                               struct drm_display_mode *mode2)
 183 {
 184         u32 tmp;
 185
 186         /*
 187          * Line Buffer Setup
 188          * There is a single line buffer shared by both display controllers.
 189          * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 190          * the display controllers.  The paritioning can either be done
 191          * manually or via one of four preset allocations specified in bits 1:0:
 192          *  0 - line buffer is divided in half and shared between crtc
 193          *  1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
 194          *  2 - D1 gets the whole buffer
 195          *  3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
 196          * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
 197          * allocation mode. In manual allocation mode, D1 always starts at 0,
 198          * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
 199          */
 200         tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
 201         tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
 202         /* auto */
 203         if (mode1 && mode2) {
 204                 if (mode1->hdisplay > mode2->hdisplay) {
 205                         if (mode1->hdisplay > 2560)
 206                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
 207                         else
 208                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 209                 } else if (mode2->hdisplay > mode1->hdisplay) {
 210                         if (mode2->hdisplay > 2560)
 211                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
 212                         else
 213                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 214                 } else
 215                         tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
 216         } else if (mode1) {
 217                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
 218         } else if (mode2) {
 219                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
 220         }
 221         WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
 222 }
 223
 224 struct rs690_watermark {
 225         u32        lb_request_fifo_depth;
 226         fixed20_12 num_line_pair;
 227         fixed20_12 estimated_width;
 228         fixed20_12 worst_case_latency;
 229         fixed20_12 consumption_rate;
 230         fixed20_12 active_time;
 231         fixed20_12 dbpp;
 232         fixed20_12 priority_mark_max;
 233         fixed20_12 priority_mark;
 234         fixed20_12 sclk;
 235 };
 236
 237 void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
 238                                   struct radeon_crtc *crtc,
 239                                   struct rs690_watermark *wm)
 240 {
 241         struct drm_display_mode *mode = &crtc->base.mode;
 242         fixed20_12 a, b, c;
 243         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
 244         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
 245
 246         if (!crtc->base.enabled) {
 247                 /* FIXME: wouldn't it better to set priority mark to maximum */
 248                 wm->lb_request_fifo_depth = 4;
 249                 return;
 250         }
 251
 252         if (crtc->vsc.full > dfixed_const(2))
 253                 wm->num_line_pair.full = dfixed_const(2);
 254         else
 255                 wm->num_line_pair.full = dfixed_const(1);
 256
 257         b.full = dfixed_const(mode->crtc_hdisplay);
 258         c.full = dfixed_const(256);
 259         a.full = dfixed_div(b, c);
 260         request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
 261         request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
 262         if (a.full < dfixed_const(4)) {
 263                 wm->lb_request_fifo_depth = 4;
 264         } else {
 265                 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
 266         }
 267
 268         /* Determine consumption rate
 269          *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
 270          *  vtaps = number of vertical taps,
 271          *  vsc = vertical scaling ratio, defined as source/destination
 272          *  hsc = horizontal scaling ration, defined as source/destination
 273          */
 274         a.full = dfixed_const(mode->clock);
 275         b.full = dfixed_const(1000);
 276         a.full = dfixed_div(a, b);
 277         pclk.full = dfixed_div(b, a);
 278         if (crtc->rmx_type != RMX_OFF) {
 279                 b.full = dfixed_const(2);
 280                 if (crtc->vsc.full > b.full)
 281                         b.full = crtc->vsc.full;
 282                 b.full = dfixed_mul(b, crtc->hsc);
 283                 c.full = dfixed_const(2);
 284                 b.full = dfixed_div(b, c);
 285                 consumption_time.full = dfixed_div(pclk, b);
 286         } else {
 287                 consumption_time.full = pclk.full;
 288         }
 289         a.full = dfixed_const(1);
 290         wm->consumption_rate.full = dfixed_div(a, consumption_time);
 291
 292
 293         /* Determine line time
 294          *  LineTime = total time for one line of displayhtotal
 295          *  LineTime = total number of horizontal pixels
 296          *  pclk = pixel clock period(ns)
 297          */
 298         a.full = dfixed_const(crtc->base.mode.crtc_htotal);
 299         line_time.full = dfixed_mul(a, pclk);
 300
 301         /* Determine active time
 302          *  ActiveTime = time of active region of display within one line,
 303          *  hactive = total number of horizontal active pixels
 304          *  htotal = total number of horizontal pixels
 305          */
 306         a.full = dfixed_const(crtc->base.mode.crtc_htotal);
 307         b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
 308         wm->active_time.full = dfixed_mul(line_time, b);
 309         wm->active_time.full = dfixed_div(wm->active_time, a);
 310
 311         /* Maximun bandwidth is the minimun bandwidth of all component */
 312         rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
 313         if (rdev->mc.igp_sideport_enabled) {
 314                 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
 315                         rdev->pm.sideport_bandwidth.full)
 316                         rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
 317                 read_delay_latency.full = dfixed_const(370 * 800 * 1000);
 318                 read_delay_latency.full = dfixed_div(read_delay_latency,
 319                         rdev->pm.igp_sideport_mclk);
 320         } else {
 321                 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
 322                         rdev->pm.k8_bandwidth.full)
 323                         rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
 324                 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
 325                         rdev->pm.ht_bandwidth.full)
 326                         rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
 327                 read_delay_latency.full = dfixed_const(5000);
 328         }
 329
 330         /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
 331         a.full = dfixed_const(16);
 332         rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a);
 333         a.full = dfixed_const(1000);
 334         rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk);
 335         /* Determine chunk time
 336          * ChunkTime = the time it takes the DCP to send one chunk of data
 337          * to the LB which consists of pipeline delay and inter chunk gap
 338          * sclk = system clock(ns)
 339          */
 340         a.full = dfixed_const(256 * 13);
 341         chunk_time.full = dfixed_mul(rdev->pm.sclk, a);
 342         a.full = dfixed_const(10);
 343         chunk_time.full = dfixed_div(chunk_time, a);
 344
 345         /* Determine the worst case latency
 346          * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
 347          * WorstCaseLatency = worst case time from urgent to when the MC starts
 348          *                    to return data
 349          * READ_DELAY_IDLE_MAX = constant of 1us
 350          * ChunkTime = time it takes the DCP to send one chunk of data to the LB
 351          *             which consists of pipeline delay and inter chunk gap
 352          */
 353         if (dfixed_trunc(wm->num_line_pair) > 1) {
 354                 a.full = dfixed_const(3);
 355                 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
 356                 wm->worst_case_latency.full += read_delay_latency.full;
 357         } else {
 358                 a.full = dfixed_const(2);
 359                 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
 360                 wm->worst_case_latency.full += read_delay_latency.full;
 361         }
 362
 363         /* Determine the tolerable latency
 364          * TolerableLatency = Any given request has only 1 line time
 365          *                    for the data to be returned
 366          * LBRequestFifoDepth = Number of chunk requests the LB can
 367          *                      put into the request FIFO for a display
 368          *  LineTime = total time for one line of display
 369          *  ChunkTime = the time it takes the DCP to send one chunk
 370          *              of data to the LB which consists of
 371          *  pipeline delay and inter chunk gap
 372          */
 373         if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
 374                 tolerable_latency.full = line_time.full;
 375         } else {
 376                 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
 377                 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
 378                 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
 379                 tolerable_latency.full = line_time.full - tolerable_latency.full;
 380         }
 381         /* We assume worst case 32bits (4 bytes) */
 382         wm->dbpp.full = dfixed_const(4 * 8);
 383
 384         /* Determine the maximum priority mark
 385          *  width = viewport width in pixels
 386          */
 387         a.full = dfixed_const(16);
 388         wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
 389         wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
 390         wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
 391
 392         /* Determine estimated width */
 393         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
 394         estimated_width.full = dfixed_div(estimated_width, consumption_time);
 395         if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
 396                 wm->priority_mark.full = dfixed_const(10);
 397         } else {
 398                 a.full = dfixed_const(16);
 399                 wm->priority_mark.full = dfixed_div(estimated_width, a);
 400                 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
 401                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
 402         }
 403 }
 404
 405 void rs690_bandwidth_update(struct radeon_device *rdev)
 406 {
 407         struct drm_display_mode *mode0 = NULL;
 408         struct drm_display_mode *mode1 = NULL;
 409         struct rs690_watermark wm0;
 410         struct rs690_watermark wm1;
 411         u32 tmp;
 412         u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
 413         u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
 414         fixed20_12 priority_mark02, priority_mark12, fill_rate;
 415         fixed20_12 a, b;
 416
 417         radeon_update_display_priority(rdev);
 418
 419         if (rdev->mode_info.crtcs[0]->base.enabled)
 420                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
 421         if (rdev->mode_info.crtcs[1]->base.enabled)
 422                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 423         /*
 424          * Set display0/1 priority up in the memory controller for
 425          * modes if the user specifies HIGH for displaypriority
 426          * option.
 427          */
 428         if ((rdev->disp_priority == 2) &&
 429             ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
 430                 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
 431                 tmp &= C_000104_MC_DISP0R_INIT_LAT;
 432                 tmp &= C_000104_MC_DISP1R_INIT_LAT;
 433                 if (mode0)
 434                         tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
 435                 if (mode1)
 436                         tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
 437                 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
 438         }
 439         rs690_line_buffer_adjust(rdev, mode0, mode1);
 440
 441         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
 442                 WREG32(R_006C9C_DCP_CONTROL, 0);
 443         if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
 444                 WREG32(R_006C9C_DCP_CONTROL, 2);
 445
 446         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
 447         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
 448
 449         tmp = (wm0.lb_request_fifo_depth - 1);
 450         tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
 451         WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
 452
 453         if (mode0 && mode1) {
 454                 if (dfixed_trunc(wm0.dbpp) > 64)
 455                         a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
 456                 else
 457                         a.full = wm0.num_line_pair.full;
 458                 if (dfixed_trunc(wm1.dbpp) > 64)
 459                         b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
 460                 else
 461                         b.full = wm1.num_line_pair.full;
 462                 a.full += b.full;
 463                 fill_rate.full = dfixed_div(wm0.sclk, a);
 464                 if (wm0.consumption_rate.full > fill_rate.full) {
 465                         b.full = wm0.consumption_rate.full - fill_rate.full;
 466                         b.full = dfixed_mul(b, wm0.active_time);
 467                         a.full = dfixed_mul(wm0.worst_case_latency,
 468                                                 wm0.consumption_rate);
 469                         a.full = a.full + b.full;
 470                         b.full = dfixed_const(16 * 1000);
 471                         priority_mark02.full = dfixed_div(a, b);
 472                 } else {
 473                         a.full = dfixed_mul(wm0.worst_case_latency,
 474                                                 wm0.consumption_rate);
 475                         b.full = dfixed_const(16 * 1000);
 476                         priority_mark02.full = dfixed_div(a, b);
 477                 }
 478                 if (wm1.consumption_rate.full > fill_rate.full) {
 479                         b.full = wm1.consumption_rate.full - fill_rate.full;
 480                         b.full = dfixed_mul(b, wm1.active_time);
 481                         a.full = dfixed_mul(wm1.worst_case_latency,
 482                                                 wm1.consumption_rate);
 483                         a.full = a.full + b.full;
 484                         b.full = dfixed_const(16 * 1000);
 485                         priority_mark12.full = dfixed_div(a, b);
 486                 } else {
 487                         a.full = dfixed_mul(wm1.worst_case_latency,
 488                                                 wm1.consumption_rate);
 489                         b.full = dfixed_const(16 * 1000);
 490                         priority_mark12.full = dfixed_div(a, b);
 491                 }
 492                 if (wm0.priority_mark.full > priority_mark02.full)
 493                         priority_mark02.full = wm0.priority_mark.full;
 494                 if (dfixed_trunc(priority_mark02) < 0)
 495                         priority_mark02.full = 0;
 496                 if (wm0.priority_mark_max.full > priority_mark02.full)
 497                         priority_mark02.full = wm0.priority_mark_max.full;
 498                 if (wm1.priority_mark.full > priority_mark12.full)
 499                         priority_mark12.full = wm1.priority_mark.full;
 500                 if (dfixed_trunc(priority_mark12) < 0)
 501                         priority_mark12.full = 0;
 502                 if (wm1.priority_mark_max.full > priority_mark12.full)
 503                         priority_mark12.full = wm1.priority_mark_max.full;
 504                 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
 505                 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
 506                 if (rdev->disp_priority == 2) {
 507                         d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
 508                         d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
 509                 }
 510         } else if (mode0) {
 511                 if (dfixed_trunc(wm0.dbpp) > 64)
 512                         a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
 513                 else
 514                         a.full = wm0.num_line_pair.full;
 515                 fill_rate.full = dfixed_div(wm0.sclk, a);
 516                 if (wm0.consumption_rate.full > fill_rate.full) {
 517                         b.full = wm0.consumption_rate.full - fill_rate.full;
 518                         b.full = dfixed_mul(b, wm0.active_time);
 519                         a.full = dfixed_mul(wm0.worst_case_latency,
 520                                                 wm0.consumption_rate);
 521                         a.full = a.full + b.full;
 522                         b.full = dfixed_const(16 * 1000);
 523                         priority_mark02.full = dfixed_div(a, b);
 524                 } else {
 525                         a.full = dfixed_mul(wm0.worst_case_latency,
 526                                                 wm0.consumption_rate);
 527                         b.full = dfixed_const(16 * 1000);
 528                         priority_mark02.full = dfixed_div(a, b);
 529                 }
 530                 if (wm0.priority_mark.full > priority_mark02.full)
 531                         priority_mark02.full = wm0.priority_mark.full;
 532                 if (dfixed_trunc(priority_mark02) < 0)
 533                         priority_mark02.full = 0;
 534                 if (wm0.priority_mark_max.full > priority_mark02.full)
 535                         priority_mark02.full = wm0.priority_mark_max.full;
 536                 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
 537                 if (rdev->disp_priority == 2)
 538                         d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
 539         } else if (mode1) {
 540                 if (dfixed_trunc(wm1.dbpp) > 64)
 541                         a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
 542                 else
 543                         a.full = wm1.num_line_pair.full;
 544                 fill_rate.full = dfixed_div(wm1.sclk, a);
 545                 if (wm1.consumption_rate.full > fill_rate.full) {
 546                         b.full = wm1.consumption_rate.full - fill_rate.full;
 547                         b.full = dfixed_mul(b, wm1.active_time);
 548                         a.full = dfixed_mul(wm1.worst_case_latency,
 549                                                 wm1.consumption_rate);
 550                         a.full = a.full + b.full;
 551                         b.full = dfixed_const(16 * 1000);
 552                         priority_mark12.full = dfixed_div(a, b);
 553                 } else {
 554                         a.full = dfixed_mul(wm1.worst_case_latency,
 555                                                 wm1.consumption_rate);
 556                         b.full = dfixed_const(16 * 1000);
 557                         priority_mark12.full = dfixed_div(a, b);
 558                 }
 559                 if (wm1.priority_mark.full > priority_mark12.full)
 560                         priority_mark12.full = wm1.priority_mark.full;
 561                 if (dfixed_trunc(priority_mark12) < 0)
 562                         priority_mark12.full = 0;
 563                 if (wm1.priority_mark_max.full > priority_mark12.full)
 564                         priority_mark12.full = wm1.priority_mark_max.full;
 565                 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
 566                 if (rdev->disp_priority == 2)
 567                         d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
 568         }
 569
 570         WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
 571         WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
 572         WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
 573         WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
 574 }
 575
 576 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 577 {
 578         uint32_t r;
 579
 580         WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
 581         r = RREG32(R_00007C_MC_DATA);
 582         WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
 583         return r;
 584 }
 585
 586 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 587 {
 588         WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
 589                 S_000078_MC_IND_WR_EN(1));
 590         WREG32(R_00007C_MC_DATA, v);
 591         WREG32(R_000078_MC_INDEX, 0x7F);
 592 }
 593
 594 void rs690_mc_program(struct radeon_device *rdev)
 595 {
 596         struct rv515_mc_save save;
 597
 598         /* Stops all mc clients */
 599         rv515_mc_stop(rdev, &save);
 600
 601         /* Wait for mc idle */
 602         if (rs690_mc_wait_for_idle(rdev))
 603                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 604         /* Program MC, should be a 32bits limited address space */
 605         WREG32_MC(R_000100_MCCFG_FB_LOCATION,
 606                         S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
 607                         S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
 608         WREG32(R_000134_HDP_FB_LOCATION,
 609                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 610
 611         rv515_mc_resume(rdev, &save);
 612 }
 613
 614 static int rs690_startup(struct radeon_device *rdev)
 615 {
 616         int r;
 617
 618         rs690_mc_program(rdev);
 619         /* Resume clock */
 620         rv515_clock_startup(rdev);
 621         /* Initialize GPU configuration (# pipes, ...) */
 622         rs690_gpu_init(rdev);
 623         /* Initialize GART (initialize after TTM so we can allocate
 624          * memory through TTM but finalize after TTM) */
 625         r = rs400_gart_enable(rdev);
 626         if (r)
 627                 return r;
 628
 629         /* allocate wb buffer */
 630         r = radeon_wb_init(rdev);
 631         if (r)
 632                 return r;
 633
 634         /* Enable IRQ */
 635         if (!rdev->irq.installed) {
 636                 r = radeon_irq_kms_init(rdev);
 637                 if (r)
 638                         return r;
 639         }
 640
 641         rs600_irq_set(rdev);
 642         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 643         /* 1M ring buffer */
 644         r = r100_cp_init(rdev, 1024 * 1024);
 645         if (r) {
 646                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
 647                 return r;
 648         }
 649         r = r100_ib_init(rdev);
 650         if (r) {
 651                 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
 652                 return r;
 653         }
 654
 655         r = r600_audio_init(rdev);
 656         if (r) {
 657                 dev_err(rdev->dev, "failed initializing audio\n");
 658                 return r;
 659         }
 660
 661         return 0;
 662 }
 663
 664 int rs690_resume(struct radeon_device *rdev)
 665 {
 666         /* Make sur GART are not working */
 667         rs400_gart_disable(rdev);
 668         /* Resume clock before doing reset */
 669         rv515_clock_startup(rdev);
 670         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 671         if (radeon_asic_reset(rdev)) {
 672                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 673                         RREG32(R_000E40_RBBM_STATUS),
 674                         RREG32(R_0007C0_CP_STAT));
 675         }
 676         /* post */
 677         atom_asic_init(rdev->mode_info.atom_context);
 678         /* Resume clock after posting */
 679         rv515_clock_startup(rdev);
 680         /* Initialize surface registers */
 681         radeon_surface_init(rdev);
 682         return rs690_startup(rdev);
 683 }
 684
 685 int rs690_suspend(struct radeon_device *rdev)
 686 {
 687         r600_audio_fini(rdev);
 688         r100_cp_disable(rdev);
 689         radeon_wb_disable(rdev);
 690         rs600_irq_disable(rdev);
 691         rs400_gart_disable(rdev);
 692         return 0;
 693 }
 694
 695 void rs690_fini(struct radeon_device *rdev)
 696 {
 697         r600_audio_fini(rdev);
 698         r100_cp_fini(rdev);
 699         radeon_wb_fini(rdev);
 700         r100_ib_fini(rdev);
 701         radeon_gem_fini(rdev);
 702         rs400_gart_fini(rdev);
 703         radeon_irq_kms_fini(rdev);
 704         radeon_fence_driver_fini(rdev);
 705         radeon_bo_fini(rdev);
 706         radeon_atombios_fini(rdev);
 707         kfree(rdev->bios);
 708         rdev->bios = NULL;
 709 }
 710
 711 int rs690_init(struct radeon_device *rdev)
 712 {
 713         int r;
 714
 715         /* Disable VGA */
 716         rv515_vga_render_disable(rdev);
 717         /* Initialize scratch registers */
 718         radeon_scratch_init(rdev);
 719         /* Initialize surface registers */
 720         radeon_surface_init(rdev);
 721         /* restore some register to sane defaults */
 722         r100_restore_sanity(rdev);
 723         /* TODO: disable VGA need to use VGA request */
 724         /* BIOS*/
 725         if (!radeon_get_bios(rdev)) {
 726                 if (ASIC_IS_AVIVO(rdev))
 727                         return -EINVAL;
 728         }
 729         if (rdev->is_atom_bios) {
 730                 r = radeon_atombios_init(rdev);
 731                 if (r)
 732                         return r;
 733         } else {
 734                 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
 735                 return -EINVAL;
 736         }
 737         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 738         if (radeon_asic_reset(rdev)) {
 739                 dev_warn(rdev->dev,
 740                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 741                         RREG32(R_000E40_RBBM_STATUS),
 742                         RREG32(R_0007C0_CP_STAT));
 743         }
 744         /* check if cards are posted or not */
 745         if (radeon_boot_test_post_card(rdev) == false)
 746                 return -EINVAL;
 747
 748         /* Initialize clocks */
 749         radeon_get_clock_info(rdev->ddev);
 750         /* initialize memory controller */
 751         rs690_mc_init(rdev);
 752         rv515_debugfs(rdev);
 753         /* Fence driver */
 754         r = radeon_fence_driver_init(rdev);
 755         if (r)
 756                 return r;
 757         /* Memory manager */
 758         r = radeon_bo_init(rdev);
 759         if (r)
 760                 return r;
 761         r = rs400_gart_init(rdev);
 762         if (r)
 763                 return r;
 764         rs600_set_safe_registers(rdev);
 765         rdev->accel_working = true;
 766         r = rs690_startup(rdev);
 767         if (r) {
 768                 /* Somethings want wront with the accel init stop accel */
 769                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 770                 r100_cp_fini(rdev);
 771                 radeon_wb_fini(rdev);
 772                 r100_ib_fini(rdev);
 773                 rs400_gart_fini(rdev);
 774                 radeon_irq_kms_fini(rdev);
 775                 rdev->accel_working = false;
 776         }
 777         return 0;
 778 }