drivers/gpu/drm/radeon/radeon_legacy_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon_fixed.h"
  30 #include "radeon.h"
  31 #include "atom.h"
  32
  33 static void radeon_overscan_setup(struct drm_crtc *crtc,
  34                                   struct drm_display_mode *mode)
  35 {
  36         struct drm_device *dev = crtc->dev;
  37         struct radeon_device *rdev = dev->dev_private;
  38         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  39
  40         WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
  41         WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
  42         WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
  43 }
  44
  45 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
  46                                        struct drm_display_mode *mode,
  47                                        struct drm_display_mode *adjusted_mode)
  48 {
  49         struct drm_device *dev = crtc->dev;
  50         struct radeon_device *rdev = dev->dev_private;
  51         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  52         int xres = mode->hdisplay;
  53         int yres = mode->vdisplay;
  54         bool hscale = true, vscale = true;
  55         int hsync_wid;
  56         int vsync_wid;
  57         int hsync_start;
  58         int blank_width;
  59         u32 scale, inc, crtc_more_cntl;
  60         u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
  61         u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
  62         u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
  63         struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
  64
  65         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
  66                 (RADEON_VERT_STRETCH_RESERVED |
  67                  RADEON_VERT_AUTO_RATIO_INC);
  68         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
  69                 (RADEON_HORZ_FP_LOOP_STRETCH |
  70                  RADEON_HORZ_AUTO_RATIO_INC);
  71
  72         crtc_more_cntl = 0;
  73         if ((rdev->family == CHIP_RS100) ||
  74             (rdev->family == CHIP_RS200)) {
  75                 /* This is to workaround the asic bug for RMX, some versions
  76                    of BIOS dosen't have this register initialized correctly. */
  77                 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
  78         }
  79
  80
  81         fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
  82                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
  83
  84         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
  85         if (!hsync_wid)
  86                 hsync_wid = 1;
  87         hsync_start = mode->crtc_hsync_start - 8;
  88
  89         fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
  90                               | ((hsync_wid & 0x3f) << 16)
  91                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
  92                                  ? RADEON_CRTC_H_SYNC_POL
  93                                  : 0));
  94
  95         fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
  96                                 | ((mode->crtc_vdisplay - 1) << 16));
  97
  98         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
  99         if (!vsync_wid)
 100                 vsync_wid = 1;
 101
 102         fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 103                               | ((vsync_wid & 0x1f) << 16)
 104                               | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 105                                  ? RADEON_CRTC_V_SYNC_POL
 106                                  : 0));
 107
 108         fp_horz_vert_active = 0;
 109
 110         if (native_mode->hdisplay == 0 ||
 111             native_mode->vdisplay == 0) {
 112                 hscale = false;
 113                 vscale = false;
 114         } else {
 115                 if (xres > native_mode->hdisplay)
 116                         xres = native_mode->hdisplay;
 117                 if (yres > native_mode->vdisplay)
 118                         yres = native_mode->vdisplay;
 119
 120                 if (xres == native_mode->hdisplay)
 121                         hscale = false;
 122                 if (yres == native_mode->vdisplay)
 123                         vscale = false;
 124         }
 125
 126         switch (radeon_crtc->rmx_type) {
 127         case RMX_FULL:
 128         case RMX_ASPECT:
 129                 if (!hscale)
 130                         fp_horz_stretch |= ((xres/8-1) << 16);
 131                 else {
 132                         inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
 133                         scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
 134                                 / native_mode->hdisplay + 1;
 135                         fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
 136                                         RADEON_HORZ_STRETCH_BLEND |
 137                                         RADEON_HORZ_STRETCH_ENABLE |
 138                                         ((native_mode->hdisplay/8-1) << 16));
 139                 }
 140
 141                 if (!vscale)
 142                         fp_vert_stretch |= ((yres-1) << 12);
 143                 else {
 144                         inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
 145                         scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
 146                                 / native_mode->vdisplay + 1;
 147                         fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
 148                                         RADEON_VERT_STRETCH_ENABLE |
 149                                         RADEON_VERT_STRETCH_BLEND |
 150                                         ((native_mode->vdisplay-1) << 12));
 151                 }
 152                 break;
 153         case RMX_CENTER:
 154                 fp_horz_stretch |= ((xres/8-1) << 16);
 155                 fp_vert_stretch |= ((yres-1) << 12);
 156
 157                 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
 158                                 RADEON_CRTC_AUTO_VERT_CENTER_EN);
 159
 160                 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
 161                 if (blank_width > 110)
 162                         blank_width = 110;
 163
 164                 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
 165                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 166
 167                 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 168                 if (!hsync_wid)
 169                         hsync_wid = 1;
 170
 171                 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
 172                                 | ((hsync_wid & 0x3f) << 16)
 173                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 174                                         ? RADEON_CRTC_H_SYNC_POL
 175                                         : 0));
 176
 177                 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
 178                                 | ((mode->crtc_vdisplay - 1) << 16));
 179
 180                 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 181                 if (!vsync_wid)
 182                         vsync_wid = 1;
 183
 184                 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
 185                                         | ((vsync_wid & 0x1f) << 16)
 186                                         | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 187                                                 ? RADEON_CRTC_V_SYNC_POL
 188                                                 : 0)));
 189
 190                 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
 191                                 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
 192                 break;
 193         case RMX_OFF:
 194         default:
 195                 fp_horz_stretch |= ((xres/8-1) << 16);
 196                 fp_vert_stretch |= ((yres-1) << 12);
 197                 break;
 198         }
 199
 200         WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
 201         WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
 202         WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
 203         WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
 204         WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
 205         WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
 206         WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
 207         WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
 208 }
 209
 210 void radeon_restore_common_regs(struct drm_device *dev)
 211 {
 212         /* don't need this yet */
 213 }
 214
 215 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
 216 {
 217         struct radeon_device *rdev = dev->dev_private;
 218         int i = 0;
 219
 220         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 221            the cause yet, but this workaround will mask the problem for now.
 222            Other chips usually will pass at the very first test, so the
 223            workaround shouldn't have any effect on them. */
 224         for (i = 0;
 225              (i < 10000 &&
 226               RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 227              i++);
 228 }
 229
 230 static void radeon_pll_write_update(struct drm_device *dev)
 231 {
 232         struct radeon_device *rdev = dev->dev_private;
 233
 234         while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 235
 236         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 237                            RADEON_PPLL_ATOMIC_UPDATE_W,
 238                            ~(RADEON_PPLL_ATOMIC_UPDATE_W));
 239 }
 240
 241 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
 242 {
 243         struct radeon_device *rdev = dev->dev_private;
 244         int i = 0;
 245
 246
 247         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 248            the cause yet, but this workaround will mask the problem for now.
 249            Other chips usually will pass at the very first test, so the
 250            workaround shouldn't have any effect on them. */
 251         for (i = 0;
 252              (i < 10000 &&
 253               RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 254              i++);
 255 }
 256
 257 static void radeon_pll2_write_update(struct drm_device *dev)
 258 {
 259         struct radeon_device *rdev = dev->dev_private;
 260
 261         while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 262
 263         WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 264                            RADEON_P2PLL_ATOMIC_UPDATE_W,
 265                            ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
 266 }
 267
 268 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
 269                                        uint16_t fb_div)
 270 {
 271         unsigned int vcoFreq;
 272
 273         if (!ref_div)
 274                 return 1;
 275
 276         vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
 277
 278         /*
 279          * This is horribly crude: the VCO frequency range is divided into
 280          * 3 parts, each part having a fixed PLL gain value.
 281          */
 282         if (vcoFreq >= 30000)
 283                 /*
 284                  * [300..max] MHz : 7
 285                  */
 286                 return 7;
 287         else if (vcoFreq >= 18000)
 288                 /*
 289                  * [180..300) MHz : 4
 290                  */
 291                 return 4;
 292         else
 293                 /*
 294                  * [0..180) MHz : 1
 295                  */
 296                 return 1;
 297 }
 298
 299 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 300 {
 301         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 302         struct drm_device *dev = crtc->dev;
 303         struct radeon_device *rdev = dev->dev_private;
 304         uint32_t mask;
 305
 306         if (radeon_crtc->crtc_id)
 307                 mask = (RADEON_CRTC2_DISP_DIS |
 308                         RADEON_CRTC2_VSYNC_DIS |
 309                         RADEON_CRTC2_HSYNC_DIS |
 310                         RADEON_CRTC2_DISP_REQ_EN_B);
 311         else
 312                 mask = (RADEON_CRTC_DISPLAY_DIS |
 313                         RADEON_CRTC_VSYNC_DIS |
 314                         RADEON_CRTC_HSYNC_DIS);
 315
 316         switch (mode) {
 317         case DRM_MODE_DPMS_ON:
 318                 if (radeon_crtc->crtc_id)
 319                         WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
 320                 else {
 321                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
 322                                                                          RADEON_CRTC_DISP_REQ_EN_B));
 323                         WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
 324                 }
 325                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 326                 radeon_crtc_load_lut(crtc);
 327                 break;
 328         case DRM_MODE_DPMS_STANDBY:
 329         case DRM_MODE_DPMS_SUSPEND:
 330         case DRM_MODE_DPMS_OFF:
 331                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 332                 if (radeon_crtc->crtc_id)
 333                         WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
 334                 else {
 335                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
 336                                                                                     RADEON_CRTC_DISP_REQ_EN_B));
 337                         WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
 338                 }
 339                 break;
 340         }
 341 }
 342
 343 /* properly set crtc bpp when using atombios */
 344 void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
 345 {
 346         struct drm_device *dev = crtc->dev;
 347         struct radeon_device *rdev = dev->dev_private;
 348         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 349         int format;
 350         uint32_t crtc_gen_cntl;
 351         uint32_t disp_merge_cntl;
 352         uint32_t crtc_pitch;
 353
 354         switch (crtc->fb->bits_per_pixel) {
 355         case 8:
 356                 format = 2;
 357                 break;
 358         case 15:      /*  555 */
 359                 format = 3;
 360                 break;
 361         case 16:      /*  565 */
 362                 format = 4;
 363                 break;
 364         case 24:      /*  RGB */
 365                 format = 5;
 366                 break;
 367         case 32:      /* xRGB */
 368                 format = 6;
 369                 break;
 370         default:
 371                 return;
 372         }
 373
 374         crtc_pitch  = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
 375                         ((crtc->fb->bits_per_pixel * 8) - 1)) /
 376                        (crtc->fb->bits_per_pixel * 8));
 377         crtc_pitch |= crtc_pitch << 16;
 378
 379         WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 380
 381         switch (radeon_crtc->crtc_id) {
 382         case 0:
 383                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
 384                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 385                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 386
 387                 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
 388                 crtc_gen_cntl |= (format << 8);
 389                 crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
 390                 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 391                 break;
 392         case 1:
 393                 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
 394                 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 395                 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
 396
 397                 crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
 398                 crtc_gen_cntl |= (format << 8);
 399                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
 400                 WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
 401                 WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
 402                 break;
 403         }
 404 }
 405
 406 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 407                          struct drm_framebuffer *old_fb)
 408 {
 409         struct drm_device *dev = crtc->dev;
 410         struct radeon_device *rdev = dev->dev_private;
 411         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 412         struct radeon_framebuffer *radeon_fb;
 413         struct drm_gem_object *obj;
 414         struct radeon_bo *rbo;
 415         uint64_t base;
 416         uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
 417         uint32_t crtc_pitch, pitch_pixels;
 418         uint32_t tiling_flags;
 419         int format;
 420         uint32_t gen_cntl_reg, gen_cntl_val;
 421         int r;
 422
 423         DRM_DEBUG("\n");
 424         /* no fb bound */
 425         if (!crtc->fb) {
 426                 DRM_DEBUG("No FB bound\n");
 427                 return 0;
 428         }
 429
 430         radeon_fb = to_radeon_framebuffer(crtc->fb);
 431
 432         switch (crtc->fb->bits_per_pixel) {
 433         case 8:
 434                 format = 2;
 435                 break;
 436         case 15:      /*  555 */
 437                 format = 3;
 438                 break;
 439         case 16:      /*  565 */
 440                 format = 4;
 441                 break;
 442         case 24:      /*  RGB */
 443                 format = 5;
 444                 break;
 445         case 32:      /* xRGB */
 446                 format = 6;
 447                 break;
 448         default:
 449                 return false;
 450         }
 451
 452         /* Pin framebuffer & get tilling informations */
 453         obj = radeon_fb->obj;
 454         rbo = obj->driver_private;
 455         r = radeon_bo_reserve(rbo, false);
 456         if (unlikely(r != 0))
 457                 return r;
 458         r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
 459         if (unlikely(r != 0)) {
 460                 radeon_bo_unreserve(rbo);
 461                 return -EINVAL;
 462         }
 463         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 464         radeon_bo_unreserve(rbo);
 465         if (tiling_flags & RADEON_TILING_MICRO)
 466                 DRM_ERROR("trying to scanout microtiled buffer\n");
 467
 468         /* if scanout was in GTT this really wouldn't work */
 469         /* crtc offset is from display base addr not FB location */
 470         radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
 471
 472         base -= radeon_crtc->legacy_display_base_addr;
 473
 474         crtc_offset_cntl = 0;
 475
 476         pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
 477         crtc_pitch  = (((pitch_pixels * crtc->fb->bits_per_pixel) +
 478                         ((crtc->fb->bits_per_pixel * 8) - 1)) /
 479                        (crtc->fb->bits_per_pixel * 8));
 480         crtc_pitch |= crtc_pitch << 16;
 481
 482
 483         if (tiling_flags & RADEON_TILING_MACRO) {
 484                 if (ASIC_IS_R300(rdev))
 485                         crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 486                                              R300_CRTC_MICRO_TILE_BUFFER_DIS |
 487                                              R300_CRTC_MACRO_TILE_EN);
 488                 else
 489                         crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
 490         } else {
 491                 if (ASIC_IS_R300(rdev))
 492                         crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 493                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
 494                                               R300_CRTC_MACRO_TILE_EN);
 495                 else
 496                         crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 497         }
 498
 499         if (tiling_flags & RADEON_TILING_MACRO) {
 500                 if (ASIC_IS_R300(rdev)) {
 501                         crtc_tile_x0_y0 = x | (y << 16);
 502                         base &= ~0x7ff;
 503                 } else {
 504                         int byteshift = crtc->fb->bits_per_pixel >> 4;
 505                         int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
 506                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 507                         crtc_offset_cntl |= (y % 16);
 508                 }
 509         } else {
 510                 int offset = y * pitch_pixels + x;
 511                 switch (crtc->fb->bits_per_pixel) {
 512                 case 8:
 513                         offset *= 1;
 514                         break;
 515                 case 15:
 516                 case 16:
 517                         offset *= 2;
 518                         break;
 519                 case 24:
 520                         offset *= 3;
 521                         break;
 522                 case 32:
 523                         offset *= 4;
 524                         break;
 525                 default:
 526                         return false;
 527                 }
 528                 base += offset;
 529         }
 530
 531         base &= ~7;
 532
 533         if (radeon_crtc->crtc_id == 1)
 534                 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
 535         else
 536                 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
 537
 538         gen_cntl_val = RREG32(gen_cntl_reg);
 539         gen_cntl_val &= ~(0xf << 8);
 540         gen_cntl_val |= (format << 8);
 541         WREG32(gen_cntl_reg, gen_cntl_val);
 542
 543         crtc_offset = (u32)base;
 544
 545         WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
 546
 547         if (ASIC_IS_R300(rdev)) {
 548                 if (radeon_crtc->crtc_id)
 549                         WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
 550                 else
 551                         WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
 552         }
 553         WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
 554         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
 555         WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 556
 557         if (old_fb && old_fb != crtc->fb) {
 558                 radeon_fb = to_radeon_framebuffer(old_fb);
 559                 rbo = radeon_fb->obj->driver_private;
 560                 r = radeon_bo_reserve(rbo, false);
 561                 if (unlikely(r != 0))
 562                         return r;
 563                 radeon_bo_unpin(rbo);
 564                 radeon_bo_unreserve(rbo);
 565         }
 566
 567         /* Bytes per pixel may have changed */
 568         radeon_bandwidth_update(rdev);
 569
 570         return 0;
 571 }
 572
 573 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 574 {
 575         struct drm_device *dev = crtc->dev;
 576         struct radeon_device *rdev = dev->dev_private;
 577         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 578         struct drm_encoder *encoder;
 579         int format;
 580         int hsync_start;
 581         int hsync_wid;
 582         int vsync_wid;
 583         uint32_t crtc_h_total_disp;
 584         uint32_t crtc_h_sync_strt_wid;
 585         uint32_t crtc_v_total_disp;
 586         uint32_t crtc_v_sync_strt_wid;
 587         bool is_tv = false;
 588
 589         DRM_DEBUG("\n");
 590         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 591                 if (encoder->crtc == crtc) {
 592                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 593                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 594                                 is_tv = true;
 595                                 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
 596                                 break;
 597                         }
 598                 }
 599         }
 600
 601         switch (crtc->fb->bits_per_pixel) {
 602         case 8:
 603                 format = 2;
 604                 break;
 605         case 15:      /*  555 */
 606                 format = 3;
 607                 break;
 608         case 16:      /*  565 */
 609                 format = 4;
 610                 break;
 611         case 24:      /*  RGB */
 612                 format = 5;
 613                 break;
 614         case 32:      /* xRGB */
 615                 format = 6;
 616                 break;
 617         default:
 618                 return false;
 619         }
 620
 621         crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 622                              | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 623
 624         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 625         if (!hsync_wid)
 626                 hsync_wid = 1;
 627         hsync_start = mode->crtc_hsync_start - 8;
 628
 629         crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
 630                                 | ((hsync_wid & 0x3f) << 16)
 631                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 632                                    ? RADEON_CRTC_H_SYNC_POL
 633                                    : 0));
 634
 635         /* This works for double scan mode. */
 636         crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 637                              | ((mode->crtc_vdisplay - 1) << 16));
 638
 639         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 640         if (!vsync_wid)
 641                 vsync_wid = 1;
 642
 643         crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 644                                 | ((vsync_wid & 0x1f) << 16)
 645                                 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 646                                    ? RADEON_CRTC_V_SYNC_POL
 647                                    : 0));
 648
 649         /* TODO -> Dell Server */
 650         if (0) {
 651                 uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
 652                 uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
 653                 uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 654                 uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 655
 656                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
 657                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
 658
 659                 /* For CRT on DAC2, don't turn it on if BIOS didn't
 660                    enable it, even it's detected.
 661                 */
 662                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 663                 tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
 664                 tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
 665
 666                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 667                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
 668                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 669                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 670         }
 671
 672         if (radeon_crtc->crtc_id) {
 673                 uint32_t crtc2_gen_cntl;
 674                 uint32_t disp2_merge_cntl;
 675
 676                 /* if TV DAC is enabled for another crtc and keep it enabled */
 677                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
 678                 crtc2_gen_cntl |= ((format << 8)
 679                                    | RADEON_CRTC2_VSYNC_DIS
 680                                    | RADEON_CRTC2_HSYNC_DIS
 681                                    | RADEON_CRTC2_DISP_DIS
 682                                    | RADEON_CRTC2_DISP_REQ_EN_B
 683                                    | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 684                                       ? RADEON_CRTC2_DBL_SCAN_EN
 685                                       : 0)
 686                                    | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 687                                       ? RADEON_CRTC2_CSYNC_EN
 688                                       : 0)
 689                                    | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 690                                       ? RADEON_CRTC2_INTERLACE_EN
 691                                       : 0));
 692
 693                 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
 694                 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 695
 696                 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
 697                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 698
 699                 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
 700                 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
 701         } else {
 702                 uint32_t crtc_gen_cntl;
 703                 uint32_t crtc_ext_cntl;
 704                 uint32_t disp_merge_cntl;
 705
 706                 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
 707                 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
 708                                  | (format << 8)
 709                                  | RADEON_CRTC_DISP_REQ_EN_B
 710                                  | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 711                                     ? RADEON_CRTC_DBL_SCAN_EN
 712                                     : 0)
 713                                  | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 714                                     ? RADEON_CRTC_CSYNC_EN
 715                                     : 0)
 716                                  | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 717                                     ? RADEON_CRTC_INTERLACE_EN
 718                                     : 0));
 719
 720                 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 721                 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
 722                                   RADEON_CRTC_VSYNC_DIS |
 723                                   RADEON_CRTC_HSYNC_DIS |
 724                                   RADEON_CRTC_DISPLAY_DIS);
 725
 726                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
 727                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 728
 729                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 730                 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 731                 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 732         }
 733
 734         if (is_tv)
 735                 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
 736                                                  &crtc_h_sync_strt_wid, &crtc_v_total_disp,
 737                                                  &crtc_v_sync_strt_wid);
 738
 739         WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
 740         WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
 741         WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
 742         WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
 743
 744         return true;
 745 }
 746
 747 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 748 {
 749         struct drm_device *dev = crtc->dev;
 750         struct radeon_device *rdev = dev->dev_private;
 751         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 752         struct drm_encoder *encoder;
 753         uint32_t feedback_div = 0;
 754         uint32_t frac_fb_div = 0;
 755         uint32_t reference_div = 0;
 756         uint32_t post_divider = 0;
 757         uint32_t freq = 0;
 758         uint8_t pll_gain;
 759         int pll_flags = RADEON_PLL_LEGACY;
 760         bool use_bios_divs = false;
 761         /* PLL registers */
 762         uint32_t pll_ref_div = 0;
 763         uint32_t pll_fb_post_div = 0;
 764         uint32_t htotal_cntl = 0;
 765         bool is_tv = false;
 766         struct radeon_pll *pll;
 767
 768         struct {
 769                 int divider;
 770                 int bitvalue;
 771         } *post_div, post_divs[]   = {
 772                 /* From RAGE 128 VR/RAGE 128 GL Register
 773                  * Reference Manual (Technical Reference
 774                  * Manual P/N RRG-G04100-C Rev. 0.04), page
 775                  * 3-17 (PLL_DIV_[3:0]).
 776                  */
 777                 {  1, 0 },              /* VCLK_SRC                 */
 778                 {  2, 1 },              /* VCLK_SRC/2               */
 779                 {  4, 2 },              /* VCLK_SRC/4               */
 780                 {  8, 3 },              /* VCLK_SRC/8               */
 781                 {  3, 4 },              /* VCLK_SRC/3               */
 782                 { 16, 5 },              /* VCLK_SRC/16              */
 783                 {  6, 6 },              /* VCLK_SRC/6               */
 784                 { 12, 7 },              /* VCLK_SRC/12              */
 785                 {  0, 0 }
 786         };
 787
 788         if (radeon_crtc->crtc_id)
 789                 pll = &rdev->clock.p2pll;
 790         else
 791                 pll = &rdev->clock.p1pll;
 792
 793         if (mode->clock > 200000) /* range limits??? */
 794                 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 795         else
 796                 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 797
 798         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 799                 if (encoder->crtc == crtc) {
 800                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 801
 802                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 803                                 is_tv = true;
 804                                 break;
 805                         }
 806
 807                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 808                                 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 809                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
 810                                 if (!rdev->is_atom_bios) {
 811                                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 812                                         struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 813                                         if (lvds) {
 814                                                 if (lvds->use_bios_dividers) {
 815                                                         pll_ref_div = lvds->panel_ref_divider;
 816                                                         pll_fb_post_div   = (lvds->panel_fb_divider |
 817                                                                              (lvds->panel_post_divider << 16));
 818                                                         htotal_cntl  = 0;
 819                                                         use_bios_divs = true;
 820                                                 }
 821                                         }
 822                                 }
 823                                 pll_flags |= RADEON_PLL_USE_REF_DIV;
 824                         }
 825                 }
 826         }
 827
 828         DRM_DEBUG("\n");
 829
 830         if (!use_bios_divs) {
 831                 radeon_compute_pll(pll, mode->clock,
 832                                    &freq, &feedback_div, &frac_fb_div,
 833                                    &reference_div, &post_divider,
 834                                    pll_flags);
 835
 836                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 837                         if (post_div->divider == post_divider)
 838                                 break;
 839                 }
 840
 841                 if (!post_div->divider)
 842                         post_div = &post_divs[0];
 843
 844                 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
 845                           (unsigned)freq,
 846                           feedback_div,
 847                           reference_div,
 848                           post_divider);
 849
 850                 pll_ref_div   = reference_div;
 851 #if defined(__powerpc__) && (0) /* TODO */
 852                 /* apparently programming this otherwise causes a hang??? */
 853                 if (info->MacModel == RADEON_MAC_IBOOK)
 854                         pll_fb_post_div = 0x000600ad;
 855                 else
 856 #endif
 857                         pll_fb_post_div     = (feedback_div | (post_div->bitvalue << 16));
 858
 859                 htotal_cntl    = mode->htotal & 0x7;
 860
 861         }
 862
 863         pll_gain = radeon_compute_pll_gain(pll->reference_freq,
 864                                            pll_ref_div & 0x3ff,
 865                                            pll_fb_post_div & 0x7ff);
 866
 867         if (radeon_crtc->crtc_id) {
 868                 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
 869                                           ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
 870                                          RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 871
 872                 if (is_tv) {
 873                         radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
 874                                                      &pll_ref_div, &pll_fb_post_div,
 875                                                      &pixclks_cntl);
 876                 }
 877
 878                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 879                              RADEON_PIX2CLK_SRC_SEL_CPUCLK,
 880                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 881
 882                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 883                              RADEON_P2PLL_RESET
 884                              | RADEON_P2PLL_ATOMIC_UPDATE_EN
 885                              | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
 886                              ~(RADEON_P2PLL_RESET
 887                                | RADEON_P2PLL_ATOMIC_UPDATE_EN
 888                                | RADEON_P2PLL_PVG_MASK));
 889
 890                 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 891                              pll_ref_div,
 892                              ~RADEON_P2PLL_REF_DIV_MASK);
 893
 894                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 895                              pll_fb_post_div,
 896                              ~RADEON_P2PLL_FB0_DIV_MASK);
 897
 898                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 899                              pll_fb_post_div,
 900                              ~RADEON_P2PLL_POST0_DIV_MASK);
 901
 902                 radeon_pll2_write_update(dev);
 903                 radeon_pll2_wait_for_read_update_complete(dev);
 904
 905                 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
 906
 907                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 908                              0,
 909                              ~(RADEON_P2PLL_RESET
 910                                | RADEON_P2PLL_SLEEP
 911                                | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 912
 913                 DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 914                           (unsigned)pll_ref_div,
 915                           (unsigned)pll_fb_post_div,
 916                           (unsigned)htotal_cntl,
 917                           RREG32_PLL(RADEON_P2PLL_CNTL));
 918                 DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
 919                           (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 920                           (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
 921                           (unsigned)((pll_fb_post_div &
 922                                       RADEON_P2PLL_POST0_DIV_MASK) >> 16));
 923
 924                 mdelay(50); /* Let the clock to lock */
 925
 926                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 927                              RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
 928                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 929
 930                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 931         } else {
 932                 uint32_t pixclks_cntl;
 933
 934
 935                 if (is_tv) {
 936                         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
 937                         radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
 938                                                      &pll_fb_post_div, &pixclks_cntl);
 939                 }
 940
 941                 if (rdev->flags & RADEON_IS_MOBILITY) {
 942                         /* A temporal workaround for the occational blanking on certain laptop panels.
 943                            This appears to related to the PLL divider registers (fail to lock?).
 944                            It occurs even when all dividers are the same with their old settings.
 945                            In this case we really don't need to fiddle with PLL registers.
 946                            By doing this we can avoid the blanking problem with some panels.
 947                         */
 948                         if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
 949                             (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
 950                                                  (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
 951                                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 952                                          RADEON_PLL_DIV_SEL,
 953                                          ~(RADEON_PLL_DIV_SEL));
 954                                 r100_pll_errata_after_index(rdev);
 955                                 return;
 956                         }
 957                 }
 958
 959                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
 960                              RADEON_VCLK_SRC_SEL_CPUCLK,
 961                              ~(RADEON_VCLK_SRC_SEL_MASK));
 962                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 963                              RADEON_PPLL_RESET
 964                              | RADEON_PPLL_ATOMIC_UPDATE_EN
 965                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 966                              | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
 967                              ~(RADEON_PPLL_RESET
 968                                | RADEON_PPLL_ATOMIC_UPDATE_EN
 969                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 970                                | RADEON_PPLL_PVG_MASK));
 971
 972                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 973                          RADEON_PLL_DIV_SEL,
 974                          ~(RADEON_PLL_DIV_SEL));
 975                 r100_pll_errata_after_index(rdev);
 976
 977                 if (ASIC_IS_R300(rdev) ||
 978                     (rdev->family == CHIP_RS300) ||
 979                     (rdev->family == CHIP_RS400) ||
 980                     (rdev->family == CHIP_RS480)) {
 981                         if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
 982                                 /* When restoring console mode, use saved PPLL_REF_DIV
 983                                  * setting.
 984                                  */
 985                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 986                                              pll_ref_div,
 987                                              0);
 988                         } else {
 989                                 /* R300 uses ref_div_acc field as real ref divider */
 990                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 991                                              (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
 992                                              ~R300_PPLL_REF_DIV_ACC_MASK);
 993                         }
 994                 } else
 995                         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 996                                      pll_ref_div,
 997                                      ~RADEON_PPLL_REF_DIV_MASK);
 998
 999                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
1000                              pll_fb_post_div,
1001                              ~RADEON_PPLL_FB3_DIV_MASK);
1002
1003                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
1004                              pll_fb_post_div,
1005                              ~RADEON_PPLL_POST3_DIV_MASK);
1006
1007                 radeon_pll_write_update(dev);
1008                 radeon_pll_wait_for_read_update_complete(dev);
1009
1010                 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
1011
1012                 WREG32_PLL_P(RADEON_PPLL_CNTL,
1013                              0,
1014                              ~(RADEON_PPLL_RESET
1015                                | RADEON_PPLL_SLEEP
1016                                | RADEON_PPLL_ATOMIC_UPDATE_EN
1017                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
1018
1019                 DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
1020                           pll_ref_div,
1021                           pll_fb_post_div,
1022                           (unsigned)htotal_cntl,
1023                           RREG32_PLL(RADEON_PPLL_CNTL));
1024                 DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
1025                           pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
1026                           pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
1027                           (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
1028
1029                 mdelay(50); /* Let the clock to lock */
1030
1031                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
1032                              RADEON_VCLK_SRC_SEL_PPLLCLK,
1033                              ~(RADEON_VCLK_SRC_SEL_MASK));
1034
1035                 if (is_tv)
1036                         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1037         }
1038 }
1039
1040 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
1041                                    struct drm_display_mode *mode,
1042                                    struct drm_display_mode *adjusted_mode)
1043 {
1044         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1045                 return false;
1046         return true;
1047 }
1048
1049 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1050                                  struct drm_display_mode *mode,
1051                                  struct drm_display_mode *adjusted_mode,
1052                                  int x, int y, struct drm_framebuffer *old_fb)
1053 {
1054         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1055
1056         /* TODO TV */
1057         radeon_crtc_set_base(crtc, x, y, old_fb);
1058         radeon_set_crtc_timing(crtc, adjusted_mode);
1059         radeon_set_pll(crtc, adjusted_mode);
1060         radeon_overscan_setup(crtc, adjusted_mode);
1061         if (radeon_crtc->crtc_id == 0) {
1062                 radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode);
1063         } else {
1064                 if (radeon_crtc->rmx_type != RMX_OFF) {
1065                         /* FIXME: only first crtc has rmx what should we
1066                          * do ?
1067                          */
1068                         DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1069                 }
1070         }
1071         return 0;
1072 }
1073
1074 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1075 {
1076         struct drm_device *dev = crtc->dev;
1077         struct drm_crtc *crtci;
1078
1079         /*
1080         * The hardware wedges sometimes if you reconfigure one CRTC
1081         * whilst another is running (see fdo bug #24611).
1082         */
1083         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1084                 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1085 }
1086
1087 static void radeon_crtc_commit(struct drm_crtc *crtc)
1088 {
1089         struct drm_device *dev = crtc->dev;
1090         struct drm_crtc *crtci;
1091
1092         /*
1093         * Reenable the CRTCs that should be running.
1094         */
1095         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1096                 if (crtci->enabled)
1097                         radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1098         }
1099 }
1100
1101 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1102         .dpms = radeon_crtc_dpms,
1103         .mode_fixup = radeon_crtc_mode_fixup,
1104         .mode_set = radeon_crtc_mode_set,
1105         .mode_set_base = radeon_crtc_set_base,
1106         .prepare = radeon_crtc_prepare,
1107         .commit = radeon_crtc_commit,
1108         .load_lut = radeon_crtc_load_lut,
1109 };
1110
1111
1112 void radeon_legacy_init_crtc(struct drm_device *dev,
1113                                struct radeon_crtc *radeon_crtc)
1114 {
1115         if (radeon_crtc->crtc_id == 1)
1116                 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1117         drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1118 }