drivers/gpu/drm/radeon/radeon_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "drm_sarea.h"
  30 #include "radeon.h"
  31 #include "radeon_drm.h"
  32
  33 #include <linux/vga_switcheroo.h>
  34 #include <linux/slab.h>
  35
  36 int radeon_driver_unload_kms(struct drm_device *dev)
  37 {
  38         struct radeon_device *rdev = dev->dev_private;
  39
  40         if (rdev == NULL)
  41                 return 0;
  42         if (rdev->rmmio == NULL)
  43                 goto done_free;
  44         radeon_modeset_fini(rdev);
  45         radeon_device_fini(rdev);
  46
  47 done_free:
  48         kfree(rdev);
  49         dev->dev_private = NULL;
  50         return 0;
  51 }
  52
  53 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  54 {
  55         struct radeon_device *rdev;
  56         int r, acpi_status;
  57
  58         rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
  59         if (rdev == NULL) {
  60                 return -ENOMEM;
  61         }
  62         dev->dev_private = (void *)rdev;
  63
  64         /* update BUS flag */
  65         if (drm_pci_device_is_agp(dev)) {
  66                 flags |= RADEON_IS_AGP;
  67         } else if (pci_is_pcie(dev->pdev)) {
  68                 flags |= RADEON_IS_PCIE;
  69         } else {
  70                 flags |= RADEON_IS_PCI;
  71         }
  72
  73         /* radeon_device_init should report only fatal error
  74          * like memory allocation failure or iomapping failure,
  75          * or memory manager initialization failure, it must
  76          * properly initialize the GPU MC controller and permit
  77          * VRAM allocation
  78          */
  79         r = radeon_device_init(rdev, dev, dev->pdev, flags);
  80         if (r) {
  81                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
  82                 goto out;
  83         }
  84
  85         /* Call ACPI methods */
  86         acpi_status = radeon_acpi_init(rdev);
  87         if (acpi_status)
  88                 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
  89
  90         /* Again modeset_init should fail only on fatal error
  91          * otherwise it should provide enough functionalities
  92          * for shadowfb to run
  93          */
  94         r = radeon_modeset_init(rdev);
  95         if (r)
  96                 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
  97 out:
  98         if (r)
  99                 radeon_driver_unload_kms(dev);
 100         return r;
 101 }
 102
 103 static void radeon_set_filp_rights(struct drm_device *dev,
 104                                    struct drm_file **owner,
 105                                    struct drm_file *applier,
 106                                    uint32_t *value)
 107 {
 108         mutex_lock(&dev->struct_mutex);
 109         if (*value == 1) {
 110                 /* wants rights */
 111                 if (!*owner)
 112                         *owner = applier;
 113         } else if (*value == 0) {
 114                 /* revokes rights */
 115                 if (*owner == applier)
 116                         *owner = NULL;
 117         }
 118         *value = *owner == applier ? 1 : 0;
 119         mutex_unlock(&dev->struct_mutex);
 120 }
 121
 122 /*
 123  * Userspace get information ioctl
 124  */
 125 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 126 {
 127         struct radeon_device *rdev = dev->dev_private;
 128         struct drm_radeon_info *info;
 129         struct radeon_mode_info *minfo = &rdev->mode_info;
 130         uint32_t *value_ptr;
 131         uint32_t value;
 132         struct drm_crtc *crtc;
 133         int i, found;
 134
 135         info = data;
 136         value_ptr = (uint32_t *)((unsigned long)info->value);
 137         if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value)))
 138                 return -EFAULT;
 139
 140         switch (info->request) {
 141         case RADEON_INFO_DEVICE_ID:
 142                 value = dev->pci_device;
 143                 break;
 144         case RADEON_INFO_NUM_GB_PIPES:
 145                 value = rdev->num_gb_pipes;
 146                 break;
 147         case RADEON_INFO_NUM_Z_PIPES:
 148                 value = rdev->num_z_pipes;
 149                 break;
 150         case RADEON_INFO_ACCEL_WORKING:
 151                 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
 152                 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
 153                         value = false;
 154                 else
 155                         value = rdev->accel_working;
 156                 break;
 157         case RADEON_INFO_CRTC_FROM_ID:
 158                 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
 159                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 160                         if (crtc && crtc->base.id == value) {
 161                                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 162                                 value = radeon_crtc->crtc_id;
 163                                 found = 1;
 164                                 break;
 165                         }
 166                 }
 167                 if (!found) {
 168                         DRM_DEBUG_KMS("unknown crtc id %d\n", value);
 169                         return -EINVAL;
 170                 }
 171                 break;
 172         case RADEON_INFO_ACCEL_WORKING2:
 173                 value = rdev->accel_working;
 174                 break;
 175         case RADEON_INFO_TILING_CONFIG:
 176                 if (rdev->family >= CHIP_CAYMAN)
 177                         value = rdev->config.cayman.tile_config;
 178                 else if (rdev->family >= CHIP_CEDAR)
 179                         value = rdev->config.evergreen.tile_config;
 180                 else if (rdev->family >= CHIP_RV770)
 181                         value = rdev->config.rv770.tile_config;
 182                 else if (rdev->family >= CHIP_R600)
 183                         value = rdev->config.r600.tile_config;
 184                 else {
 185                         DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
 186                         return -EINVAL;
 187                 }
 188                 break;
 189         case RADEON_INFO_WANT_HYPERZ:
 190                 /* The "value" here is both an input and output parameter.
 191                  * If the input value is 1, filp requests hyper-z access.
 192                  * If the input value is 0, filp revokes its hyper-z access.
 193                  *
 194                  * When returning, the value is 1 if filp owns hyper-z access,
 195                  * 0 otherwise. */
 196                 if (value >= 2) {
 197                         DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
 198                         return -EINVAL;
 199                 }
 200                 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value);
 201                 break;
 202         case RADEON_INFO_WANT_CMASK:
 203                 /* The same logic as Hyper-Z. */
 204                 if (value >= 2) {
 205                         DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value);
 206                         return -EINVAL;
 207                 }
 208                 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value);
 209                 break;
 210         case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
 211                 /* return clock value in KHz */
 212                 value = rdev->clock.spll.reference_freq * 10;
 213                 break;
 214         case RADEON_INFO_NUM_BACKENDS:
 215                 if (rdev->family >= CHIP_CAYMAN)
 216                         value = rdev->config.cayman.max_backends_per_se *
 217                                 rdev->config.cayman.max_shader_engines;
 218                 else if (rdev->family >= CHIP_CEDAR)
 219                         value = rdev->config.evergreen.max_backends;
 220                 else if (rdev->family >= CHIP_RV770)
 221                         value = rdev->config.rv770.max_backends;
 222                 else if (rdev->family >= CHIP_R600)
 223                         value = rdev->config.r600.max_backends;
 224                 else {
 225                         return -EINVAL;
 226                 }
 227                 break;
 228         case RADEON_INFO_NUM_TILE_PIPES:
 229                 if (rdev->family >= CHIP_CAYMAN)
 230                         value = rdev->config.cayman.max_tile_pipes;
 231                 else if (rdev->family >= CHIP_CEDAR)
 232                         value = rdev->config.evergreen.max_tile_pipes;
 233                 else if (rdev->family >= CHIP_RV770)
 234                         value = rdev->config.rv770.max_tile_pipes;
 235                 else if (rdev->family >= CHIP_R600)
 236                         value = rdev->config.r600.max_tile_pipes;
 237                 else {
 238                         return -EINVAL;
 239                 }
 240                 break;
 241         case RADEON_INFO_FUSION_GART_WORKING:
 242                 value = 1;
 243                 break;
 244         case RADEON_INFO_BACKEND_MAP:
 245                 if (rdev->family >= CHIP_CAYMAN)
 246                         value = rdev->config.cayman.backend_map;
 247                 else if (rdev->family >= CHIP_CEDAR)
 248                         value = rdev->config.evergreen.backend_map;
 249                 else if (rdev->family >= CHIP_RV770)
 250                         value = rdev->config.rv770.backend_map;
 251                 else if (rdev->family >= CHIP_R600)
 252                         value = rdev->config.r600.backend_map;
 253                 else {
 254                         return -EINVAL;
 255                 }
 256                 break;
 257         default:
 258                 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
 259                 return -EINVAL;
 260         }
 261         if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
 262                 DRM_ERROR("copy_to_user\n");
 263                 return -EFAULT;
 264         }
 265         return 0;
 266 }
 267
 268
 269 /*
 270  * Outdated mess for old drm with Xorg being in charge (void function now).
 271  */
 272 int radeon_driver_firstopen_kms(struct drm_device *dev)
 273 {
 274         return 0;
 275 }
 276
 277
 278 void radeon_driver_lastclose_kms(struct drm_device *dev)
 279 {
 280         vga_switcheroo_process_delayed_switch();
 281 }
 282
 283 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 284 {
 285         return 0;
 286 }
 287
 288 void radeon_driver_postclose_kms(struct drm_device *dev,
 289                                  struct drm_file *file_priv)
 290 {
 291 }
 292
 293 void radeon_driver_preclose_kms(struct drm_device *dev,
 294                                 struct drm_file *file_priv)
 295 {
 296         struct radeon_device *rdev = dev->dev_private;
 297         if (rdev->hyperz_filp == file_priv)
 298                 rdev->hyperz_filp = NULL;
 299         if (rdev->cmask_filp == file_priv)
 300                 rdev->cmask_filp = NULL;
 301 }
 302
 303 /*
 304  * VBlank related functions.
 305  */
 306 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
 307 {
 308         struct radeon_device *rdev = dev->dev_private;
 309
 310         if (crtc < 0 || crtc >= rdev->num_crtc) {
 311                 DRM_ERROR("Invalid crtc %d\n", crtc);
 312                 return -EINVAL;
 313         }
 314
 315         return radeon_get_vblank_counter(rdev, crtc);
 316 }
 317
 318 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
 319 {
 320         struct radeon_device *rdev = dev->dev_private;
 321
 322         if (crtc < 0 || crtc >= rdev->num_crtc) {
 323                 DRM_ERROR("Invalid crtc %d\n", crtc);
 324                 return -EINVAL;
 325         }
 326
 327         rdev->irq.crtc_vblank_int[crtc] = true;
 328
 329         return radeon_irq_set(rdev);
 330 }
 331
 332 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
 333 {
 334         struct radeon_device *rdev = dev->dev_private;
 335
 336         if (crtc < 0 || crtc >= rdev->num_crtc) {
 337                 DRM_ERROR("Invalid crtc %d\n", crtc);
 338                 return;
 339         }
 340
 341         rdev->irq.crtc_vblank_int[crtc] = false;
 342
 343         radeon_irq_set(rdev);
 344 }
 345
 346 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
 347                                     int *max_error,
 348                                     struct timeval *vblank_time,
 349                                     unsigned flags)
 350 {
 351         struct drm_crtc *drmcrtc;
 352         struct radeon_device *rdev = dev->dev_private;
 353
 354         if (crtc < 0 || crtc >= dev->num_crtcs) {
 355                 DRM_ERROR("Invalid crtc %d\n", crtc);
 356                 return -EINVAL;
 357         }
 358
 359         /* Get associated drm_crtc: */
 360         drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
 361
 362         /* Helper routine in DRM core does all the work: */
 363         return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
 364                                                      vblank_time, flags,
 365                                                      drmcrtc);
 366 }
 367
 368 /*
 369  * IOCTL.
 370  */
 371 int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
 372                          struct drm_file *file_priv)
 373 {
 374         /* Not valid in KMS. */
 375         return -EINVAL;
 376 }
 377
 378 #define KMS_INVALID_IOCTL(name)                                         \
 379 int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
 380 {                                                                       \
 381         DRM_ERROR("invalid ioctl with kms %s\n", __func__);             \
 382         return -EINVAL;                                                 \
 383 }
 384
 385 /*
 386  * All these ioctls are invalid in kms world.
 387  */
 388 KMS_INVALID_IOCTL(radeon_cp_init_kms)
 389 KMS_INVALID_IOCTL(radeon_cp_start_kms)
 390 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
 391 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
 392 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
 393 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
 394 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
 395 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
 396 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
 397 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
 398 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
 399 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
 400 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
 401 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
 402 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
 403 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
 404 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
 405 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
 406 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
 407 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
 408 KMS_INVALID_IOCTL(radeon_mem_free_kms)
 409 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
 410 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
 411 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
 412 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
 413 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
 414 KMS_INVALID_IOCTL(radeon_surface_free_kms)
 415
 416
 417 struct drm_ioctl_desc radeon_ioctls_kms[] = {
 418         DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 419         DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 420         DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 421         DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 422         DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
 423         DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
 424         DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
 425         DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
 426         DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
 427         DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
 428         DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
 429         DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
 430         DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
 431         DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
 432         DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 433         DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
 434         DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
 435         DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
 436         DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
 437         DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
 438         DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
 439         DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 440         DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
 441         DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
 442         DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
 443         DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
 444         DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
 445         /* KMS */
 446         DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
 447         DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
 448         DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
 449         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
 450         DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
 451         DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
 452         DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
 453         DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
 454         DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
 455         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
 456         DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
 457         DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
 458 };
 459 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);