2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 extern int atom_debug;
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
62 if (clone_encoder == encoder)
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
69 index_mask |= (1 << count);
74 void radeon_setup_encoder_clones(struct drm_device *dev)
76 struct drm_encoder *encoder;
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
86 struct radeon_device *rdev = dev->dev_private;
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
104 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
113 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
120 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
128 ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
138 ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
149 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
180 radeon_link_encoder_connector(struct drm_device *dev)
182 struct drm_connector *connector;
183 struct radeon_connector *radeon_connector;
184 struct drm_encoder *encoder;
185 struct radeon_encoder *radeon_encoder;
187 /* walk the list and link encoders to connectors */
188 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
189 radeon_connector = to_radeon_connector(connector);
190 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
191 radeon_encoder = to_radeon_encoder(encoder);
192 if (radeon_encoder->devices & radeon_connector->devices)
193 drm_mode_connector_attach_encoder(connector, encoder);
198 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
200 struct drm_device *dev = encoder->dev;
201 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
202 struct drm_connector *connector;
204 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
205 if (connector->encoder == encoder) {
206 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
207 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
208 DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
209 radeon_encoder->active_device, radeon_encoder->devices,
210 radeon_connector->devices, encoder->encoder_type);
215 static struct drm_connector *
216 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
218 struct drm_device *dev = encoder->dev;
219 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
220 struct drm_connector *connector;
221 struct radeon_connector *radeon_connector;
223 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
224 radeon_connector = to_radeon_connector(connector);
225 if (radeon_encoder->active_device & radeon_connector->devices)
231 static struct radeon_connector_atom_dig *
232 radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder)
234 struct drm_device *dev = encoder->dev;
235 struct radeon_device *rdev = dev->dev_private;
236 struct drm_connector *connector;
237 struct radeon_connector *radeon_connector;
238 struct radeon_connector_atom_dig *dig_connector;
240 if (!rdev->is_atom_bios)
243 connector = radeon_get_connector_for_encoder(encoder);
247 radeon_connector = to_radeon_connector(connector);
249 if (!radeon_connector->con_priv)
252 dig_connector = radeon_connector->con_priv;
254 return dig_connector;
257 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
258 struct drm_display_mode *mode,
259 struct drm_display_mode *adjusted_mode)
261 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
262 struct drm_device *dev = encoder->dev;
263 struct radeon_device *rdev = dev->dev_private;
265 /* adjust pm to upcoming mode change */
266 radeon_pm_compute_clocks(rdev);
268 /* set the active encoder to connector routing */
269 radeon_encoder_set_active_device(encoder);
270 drm_mode_set_crtcinfo(adjusted_mode, 0);
273 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
274 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
275 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
277 /* get the native mode for LVDS */
278 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
279 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
280 int mode_id = adjusted_mode->base.id;
281 *adjusted_mode = *native_mode;
282 if (!ASIC_IS_AVIVO(rdev)) {
283 adjusted_mode->hdisplay = mode->hdisplay;
284 adjusted_mode->vdisplay = mode->vdisplay;
285 adjusted_mode->crtc_hdisplay = mode->hdisplay;
286 adjusted_mode->crtc_vdisplay = mode->vdisplay;
288 adjusted_mode->base.id = mode_id;
291 /* get the native mode for TV */
292 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
293 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
295 if (tv_dac->tv_std == TV_STD_NTSC ||
296 tv_dac->tv_std == TV_STD_NTSC_J ||
297 tv_dac->tv_std == TV_STD_PAL_M)
298 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
300 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
304 if (ASIC_IS_DCE3(rdev) &&
305 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT))) {
306 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
307 radeon_dp_set_link_config(connector, mode);
314 atombios_dac_setup(struct drm_encoder *encoder, int action)
316 struct drm_device *dev = encoder->dev;
317 struct radeon_device *rdev = dev->dev_private;
318 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
319 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
320 int index = 0, num = 0;
321 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
322 enum radeon_tv_std tv_std = TV_STD_NTSC;
324 if (dac_info->tv_std)
325 tv_std = dac_info->tv_std;
327 memset(&args, 0, sizeof(args));
329 switch (radeon_encoder->encoder_id) {
330 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
331 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
332 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
335 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
336 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
337 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
342 args.ucAction = action;
344 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
345 args.ucDacStandard = ATOM_DAC1_PS2;
346 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
347 args.ucDacStandard = ATOM_DAC1_CV;
352 case TV_STD_SCART_PAL:
355 args.ucDacStandard = ATOM_DAC1_PAL;
361 args.ucDacStandard = ATOM_DAC1_NTSC;
365 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
367 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
372 atombios_tv_setup(struct drm_encoder *encoder, int action)
374 struct drm_device *dev = encoder->dev;
375 struct radeon_device *rdev = dev->dev_private;
376 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
377 TV_ENCODER_CONTROL_PS_ALLOCATION args;
379 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
380 enum radeon_tv_std tv_std = TV_STD_NTSC;
382 if (dac_info->tv_std)
383 tv_std = dac_info->tv_std;
385 memset(&args, 0, sizeof(args));
387 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
389 args.sTVEncoder.ucAction = action;
391 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
392 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
396 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
399 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
402 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
405 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
408 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
410 case TV_STD_SCART_PAL:
411 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
414 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
417 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
420 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
425 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
427 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
432 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
434 struct drm_device *dev = encoder->dev;
435 struct radeon_device *rdev = dev->dev_private;
436 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
437 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
440 memset(&args, 0, sizeof(args));
442 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
444 args.sXTmdsEncoder.ucEnable = action;
446 if (radeon_encoder->pixel_clock > 165000)
447 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
449 /*if (pScrn->rgbBits == 8)*/
450 args.sXTmdsEncoder.ucMisc |= (1 << 1);
452 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
457 atombios_ddia_setup(struct drm_encoder *encoder, int action)
459 struct drm_device *dev = encoder->dev;
460 struct radeon_device *rdev = dev->dev_private;
461 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
462 DVO_ENCODER_CONTROL_PS_ALLOCATION args;
465 memset(&args, 0, sizeof(args));
467 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
469 args.sDVOEncoder.ucAction = action;
470 args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
472 if (radeon_encoder->pixel_clock > 165000)
473 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
475 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
479 union lvds_encoder_control {
480 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
481 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
485 atombios_digital_setup(struct drm_encoder *encoder, int action)
487 struct drm_device *dev = encoder->dev;
488 struct radeon_device *rdev = dev->dev_private;
489 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
490 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
491 struct radeon_connector_atom_dig *dig_connector =
492 radeon_get_atom_connector_priv_from_encoder(encoder);
493 union lvds_encoder_control args;
495 int hdmi_detected = 0;
498 if (!dig || !dig_connector)
501 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
504 memset(&args, 0, sizeof(args));
506 switch (radeon_encoder->encoder_id) {
507 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
508 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
510 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
511 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
512 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
514 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
515 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
516 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
518 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
522 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
531 args.v1.ucAction = action;
533 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
534 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
535 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
536 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
537 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
538 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
539 args.v1.ucMisc |= (1 << 1);
541 if (dig_connector->linkb)
542 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
543 if (radeon_encoder->pixel_clock > 165000)
544 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
545 /*if (pScrn->rgbBits == 8) */
546 args.v1.ucMisc |= (1 << 1);
552 args.v2.ucAction = action;
554 if (dig->coherent_mode)
555 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
558 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
559 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
560 args.v2.ucTruncate = 0;
561 args.v2.ucSpatial = 0;
562 args.v2.ucTemporal = 0;
564 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
565 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
566 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
567 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
568 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
569 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
570 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
572 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
573 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
574 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
575 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
576 if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
577 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
580 if (dig_connector->linkb)
581 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
582 if (radeon_encoder->pixel_clock > 165000)
583 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
587 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
592 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
596 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
600 atombios_get_encoder_mode(struct drm_encoder *encoder)
602 struct drm_connector *connector;
603 struct radeon_connector *radeon_connector;
604 struct radeon_connector_atom_dig *dig_connector;
606 connector = radeon_get_connector_for_encoder(encoder);
610 radeon_connector = to_radeon_connector(connector);
612 switch (connector->connector_type) {
613 case DRM_MODE_CONNECTOR_DVII:
614 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
615 if (drm_detect_hdmi_monitor(radeon_connector->edid))
616 return ATOM_ENCODER_MODE_HDMI;
617 else if (radeon_connector->use_digital)
618 return ATOM_ENCODER_MODE_DVI;
620 return ATOM_ENCODER_MODE_CRT;
622 case DRM_MODE_CONNECTOR_DVID:
623 case DRM_MODE_CONNECTOR_HDMIA:
625 if (drm_detect_hdmi_monitor(radeon_connector->edid))
626 return ATOM_ENCODER_MODE_HDMI;
628 return ATOM_ENCODER_MODE_DVI;
630 case DRM_MODE_CONNECTOR_LVDS:
631 return ATOM_ENCODER_MODE_LVDS;
633 case DRM_MODE_CONNECTOR_DisplayPort:
634 case DRM_MODE_CONNECTOR_eDP:
635 dig_connector = radeon_connector->con_priv;
636 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
637 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
638 return ATOM_ENCODER_MODE_DP;
639 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
640 return ATOM_ENCODER_MODE_HDMI;
642 return ATOM_ENCODER_MODE_DVI;
644 case DRM_MODE_CONNECTOR_DVIA:
645 case DRM_MODE_CONNECTOR_VGA:
646 return ATOM_ENCODER_MODE_CRT;
648 case DRM_MODE_CONNECTOR_Composite:
649 case DRM_MODE_CONNECTOR_SVIDEO:
650 case DRM_MODE_CONNECTOR_9PinDIN:
652 return ATOM_ENCODER_MODE_TV;
653 /*return ATOM_ENCODER_MODE_CV;*/
659 * DIG Encoder/Transmitter Setup
662 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
663 * Supports up to 3 digital outputs
664 * - 2 DIG encoder blocks.
665 * DIG1 can drive UNIPHY link A or link B
666 * DIG2 can drive UNIPHY link B or LVTMA
669 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
670 * Supports up to 5 digital outputs
671 * - 2 DIG encoder blocks.
672 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
675 * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
676 * Supports up to 6 digital outputs
677 * - 6 DIG encoder blocks.
678 * - DIG to PHY mapping is hardcoded
679 * DIG1 drives UNIPHY0 link A, A+B
680 * DIG2 drives UNIPHY0 link B
681 * DIG3 drives UNIPHY1 link A, A+B
682 * DIG4 drives UNIPHY1 link B
683 * DIG5 drives UNIPHY2 link A, A+B
684 * DIG6 drives UNIPHY2 link B
687 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
689 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
690 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
691 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
692 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
695 union dig_encoder_control {
696 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
697 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
698 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
702 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
704 struct drm_device *dev = encoder->dev;
705 struct radeon_device *rdev = dev->dev_private;
706 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
707 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
708 struct radeon_connector_atom_dig *dig_connector =
709 radeon_get_atom_connector_priv_from_encoder(encoder);
710 union dig_encoder_control args;
711 int index = 0, num = 0;
714 if (!dig || !dig_connector)
717 memset(&args, 0, sizeof(args));
719 if (ASIC_IS_DCE4(rdev))
720 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
722 if (dig->dig_encoder)
723 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
725 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
727 num = dig->dig_encoder + 1;
729 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
732 args.v1.ucAction = action;
733 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
734 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
736 if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
737 if (dig_connector->dp_clock == 270000)
738 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
739 args.v1.ucLaneNum = dig_connector->dp_lane_count;
740 } else if (radeon_encoder->pixel_clock > 165000)
741 args.v1.ucLaneNum = 8;
743 args.v1.ucLaneNum = 4;
745 if (ASIC_IS_DCE4(rdev)) {
746 args.v3.acConfig.ucDigSel = dig->dig_encoder;
747 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
749 switch (radeon_encoder->encoder_id) {
750 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
751 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
753 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
754 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
755 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
757 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
758 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
761 if (dig_connector->linkb)
762 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
764 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
767 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771 union dig_transmitter_control {
772 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
773 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
774 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
778 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
780 struct drm_device *dev = encoder->dev;
781 struct radeon_device *rdev = dev->dev_private;
782 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
783 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
784 struct radeon_connector_atom_dig *dig_connector =
785 radeon_get_atom_connector_priv_from_encoder(encoder);
786 struct drm_connector *connector;
787 struct radeon_connector *radeon_connector;
788 union dig_transmitter_control args;
789 int index = 0, num = 0;
794 if (!dig || !dig_connector)
797 connector = radeon_get_connector_for_encoder(encoder);
798 radeon_connector = to_radeon_connector(connector);
800 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
803 memset(&args, 0, sizeof(args));
805 if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev))
806 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
808 switch (radeon_encoder->encoder_id) {
809 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
810 index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
812 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
813 index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
818 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
821 args.v1.ucAction = action;
822 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
823 args.v1.usInitInfo = radeon_connector->connector_object_id;
824 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
825 args.v1.asMode.ucLaneSel = lane_num;
826 args.v1.asMode.ucLaneSet = lane_set;
829 args.v1.usPixelClock =
830 cpu_to_le16(dig_connector->dp_clock / 10);
831 else if (radeon_encoder->pixel_clock > 165000)
832 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
834 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
836 if (ASIC_IS_DCE4(rdev)) {
838 args.v3.ucLaneNum = dig_connector->dp_lane_count;
839 else if (radeon_encoder->pixel_clock > 165000)
840 args.v3.ucLaneNum = 8;
842 args.v3.ucLaneNum = 4;
844 if (dig_connector->linkb) {
845 args.v3.acConfig.ucLinkSel = 1;
846 args.v3.acConfig.ucEncoderSel = 1;
849 /* Select the PLL for the PHY
850 * DP PHY should be clocked from external src if there is
854 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
855 pll_id = radeon_crtc->pll_id;
857 if (is_dp && rdev->clock.dp_extclk)
858 args.v3.acConfig.ucRefClkSource = 2; /* external src */
860 args.v3.acConfig.ucRefClkSource = pll_id;
862 switch (radeon_encoder->encoder_id) {
863 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
864 args.v3.acConfig.ucTransmitterSel = 0;
867 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
868 args.v3.acConfig.ucTransmitterSel = 1;
871 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
872 args.v3.acConfig.ucTransmitterSel = 2;
878 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
879 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
880 if (dig->coherent_mode)
881 args.v3.acConfig.fCoherentMode = 1;
883 } else if (ASIC_IS_DCE32(rdev)) {
884 if (dig->dig_encoder == 1)
885 args.v2.acConfig.ucEncoderSel = 1;
886 if (dig_connector->linkb)
887 args.v2.acConfig.ucLinkSel = 1;
889 switch (radeon_encoder->encoder_id) {
890 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
891 args.v2.acConfig.ucTransmitterSel = 0;
894 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
895 args.v2.acConfig.ucTransmitterSel = 1;
898 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
899 args.v2.acConfig.ucTransmitterSel = 2;
905 args.v2.acConfig.fCoherentMode = 1;
906 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
907 if (dig->coherent_mode)
908 args.v2.acConfig.fCoherentMode = 1;
911 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
913 if (dig->dig_encoder)
914 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
916 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
918 switch (radeon_encoder->encoder_id) {
919 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
920 if (rdev->flags & RADEON_IS_IGP) {
921 if (radeon_encoder->pixel_clock > 165000) {
922 if (dig_connector->igp_lane_info & 0x3)
923 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
924 else if (dig_connector->igp_lane_info & 0xc)
925 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
927 if (dig_connector->igp_lane_info & 0x1)
928 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
929 else if (dig_connector->igp_lane_info & 0x2)
930 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
931 else if (dig_connector->igp_lane_info & 0x4)
932 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
933 else if (dig_connector->igp_lane_info & 0x8)
934 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
940 if (radeon_encoder->pixel_clock > 165000)
941 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
943 if (dig_connector->linkb)
944 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
946 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
949 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
950 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
951 if (dig->coherent_mode)
952 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
956 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
960 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
962 struct drm_device *dev = encoder->dev;
963 struct radeon_device *rdev = dev->dev_private;
964 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
965 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
966 ENABLE_YUV_PS_ALLOCATION args;
967 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
970 memset(&args, 0, sizeof(args));
972 if (rdev->family >= CHIP_R600)
973 reg = R600_BIOS_3_SCRATCH;
975 reg = RADEON_BIOS_3_SCRATCH;
977 /* XXX: fix up scratch reg handling */
979 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
980 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
981 (radeon_crtc->crtc_id << 18)));
982 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
983 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
988 args.ucEnable = ATOM_ENABLE;
989 args.ucCRTC = radeon_crtc->crtc_id;
991 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
997 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
999 struct drm_device *dev = encoder->dev;
1000 struct radeon_device *rdev = dev->dev_private;
1001 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1002 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1004 bool is_dig = false;
1006 memset(&args, 0, sizeof(args));
1008 DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1009 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1010 radeon_encoder->active_device);
1011 switch (radeon_encoder->encoder_id) {
1012 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1013 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1014 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1016 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1017 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1018 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1019 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1022 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1023 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1024 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1025 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1027 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1028 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1030 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1031 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1032 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1034 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1036 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1037 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1038 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1039 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1040 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1041 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1043 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1045 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1046 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1047 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1048 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1049 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1050 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1052 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1058 case DRM_MODE_DPMS_ON:
1059 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1061 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1062 dp_link_train(encoder, connector);
1065 case DRM_MODE_DPMS_STANDBY:
1066 case DRM_MODE_DPMS_SUSPEND:
1067 case DRM_MODE_DPMS_OFF:
1068 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1073 case DRM_MODE_DPMS_ON:
1074 args.ucAction = ATOM_ENABLE;
1076 case DRM_MODE_DPMS_STANDBY:
1077 case DRM_MODE_DPMS_SUSPEND:
1078 case DRM_MODE_DPMS_OFF:
1079 args.ucAction = ATOM_DISABLE;
1082 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1084 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1086 /* adjust pm to dpms change */
1087 radeon_pm_compute_clocks(rdev);
1090 union crtc_source_param {
1091 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1092 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1096 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1098 struct drm_device *dev = encoder->dev;
1099 struct radeon_device *rdev = dev->dev_private;
1100 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1101 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1102 union crtc_source_param args;
1103 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1105 struct radeon_encoder_atom_dig *dig;
1107 memset(&args, 0, sizeof(args));
1109 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1117 if (ASIC_IS_AVIVO(rdev))
1118 args.v1.ucCRTC = radeon_crtc->crtc_id;
1120 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1121 args.v1.ucCRTC = radeon_crtc->crtc_id;
1123 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1126 switch (radeon_encoder->encoder_id) {
1127 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1128 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1129 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1131 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1132 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1133 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1134 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1136 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1138 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1139 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1140 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1141 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1143 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1144 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1145 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1146 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1147 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1148 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1150 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1152 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1153 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1154 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1155 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1156 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1157 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1159 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1164 args.v2.ucCRTC = radeon_crtc->crtc_id;
1165 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1166 switch (radeon_encoder->encoder_id) {
1167 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1168 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1169 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1170 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1171 dig = radeon_encoder->enc_priv;
1172 switch (dig->dig_encoder) {
1174 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1177 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1180 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1183 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1186 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1189 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1193 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1194 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1196 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1197 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1198 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1199 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1200 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1202 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1204 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1205 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1206 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1207 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1208 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1210 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1217 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1221 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1223 /* update scratch regs with new routing */
1224 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1228 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1229 struct drm_display_mode *mode)
1231 struct drm_device *dev = encoder->dev;
1232 struct radeon_device *rdev = dev->dev_private;
1233 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1234 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1236 /* Funky macbooks */
1237 if ((dev->pdev->device == 0x71C5) &&
1238 (dev->pdev->subsystem_vendor == 0x106b) &&
1239 (dev->pdev->subsystem_device == 0x0080)) {
1240 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1241 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1243 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1244 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1246 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1250 /* set scaler clears this on some chips */
1251 /* XXX check DCE4 */
1252 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1253 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1254 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1255 AVIVO_D1MODE_INTERLEAVE_EN);
1259 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1261 struct drm_device *dev = encoder->dev;
1262 struct radeon_device *rdev = dev->dev_private;
1263 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1264 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1265 struct drm_encoder *test_encoder;
1266 struct radeon_encoder_atom_dig *dig;
1267 uint32_t dig_enc_in_use = 0;
1269 if (ASIC_IS_DCE4(rdev)) {
1270 struct radeon_connector_atom_dig *dig_connector =
1271 radeon_get_atom_connector_priv_from_encoder(encoder);
1273 switch (radeon_encoder->encoder_id) {
1274 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1275 if (dig_connector->linkb)
1280 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1281 if (dig_connector->linkb)
1286 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1287 if (dig_connector->linkb)
1295 /* on DCE32 and encoder can driver any block so just crtc id */
1296 if (ASIC_IS_DCE32(rdev)) {
1297 return radeon_crtc->crtc_id;
1300 /* on DCE3 - LVTMA can only be driven by DIGB */
1301 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1302 struct radeon_encoder *radeon_test_encoder;
1304 if (encoder == test_encoder)
1307 if (!radeon_encoder_is_digital(test_encoder))
1310 radeon_test_encoder = to_radeon_encoder(test_encoder);
1311 dig = radeon_test_encoder->enc_priv;
1313 if (dig->dig_encoder >= 0)
1314 dig_enc_in_use |= (1 << dig->dig_encoder);
1317 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1318 if (dig_enc_in_use & 0x2)
1319 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1322 if (!(dig_enc_in_use & 1))
1328 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1329 struct drm_display_mode *mode,
1330 struct drm_display_mode *adjusted_mode)
1332 struct drm_device *dev = encoder->dev;
1333 struct radeon_device *rdev = dev->dev_private;
1334 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1336 radeon_encoder->pixel_clock = adjusted_mode->clock;
1338 if (ASIC_IS_AVIVO(rdev)) {
1339 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1340 atombios_yuv_setup(encoder, true);
1342 atombios_yuv_setup(encoder, false);
1345 switch (radeon_encoder->encoder_id) {
1346 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1347 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1348 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1349 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1350 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1352 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1353 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1354 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1355 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1356 if (ASIC_IS_DCE4(rdev)) {
1357 /* disable the transmitter */
1358 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1359 /* setup and enable the encoder */
1360 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1362 /* init and enable the transmitter */
1363 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1364 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1366 /* disable the encoder and transmitter */
1367 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1368 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1370 /* setup and enable the encoder and transmitter */
1371 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1372 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1373 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1374 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1377 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1378 atombios_ddia_setup(encoder, ATOM_ENABLE);
1380 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1381 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1382 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1384 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1385 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1386 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1387 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1388 atombios_dac_setup(encoder, ATOM_ENABLE);
1389 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1390 atombios_tv_setup(encoder, ATOM_ENABLE);
1393 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1395 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1396 r600_hdmi_enable(encoder);
1397 r600_hdmi_setmode(encoder, adjusted_mode);
1402 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1404 struct drm_device *dev = encoder->dev;
1405 struct radeon_device *rdev = dev->dev_private;
1406 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1407 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1409 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1410 ATOM_DEVICE_CV_SUPPORT |
1411 ATOM_DEVICE_CRT_SUPPORT)) {
1412 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1413 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1416 memset(&args, 0, sizeof(args));
1418 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1421 args.sDacload.ucMisc = 0;
1423 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1424 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1425 args.sDacload.ucDacType = ATOM_DAC_A;
1427 args.sDacload.ucDacType = ATOM_DAC_B;
1429 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1430 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1431 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1432 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1433 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1434 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1436 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1437 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1438 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1440 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1443 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1450 static enum drm_connector_status
1451 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1453 struct drm_device *dev = encoder->dev;
1454 struct radeon_device *rdev = dev->dev_private;
1455 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1456 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1457 uint32_t bios_0_scratch;
1459 if (!atombios_dac_load_detect(encoder, connector)) {
1460 DRM_DEBUG("detect returned false \n");
1461 return connector_status_unknown;
1464 if (rdev->family >= CHIP_R600)
1465 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1467 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1469 DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1470 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1471 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1472 return connector_status_connected;
1474 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1475 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1476 return connector_status_connected;
1478 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1479 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1480 return connector_status_connected;
1482 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1483 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1484 return connector_status_connected; /* CTV */
1485 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1486 return connector_status_connected; /* STV */
1488 return connector_status_disconnected;
1491 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1493 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1495 if (radeon_encoder->active_device &
1496 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1497 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1499 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1502 radeon_atom_output_lock(encoder, true);
1503 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1505 /* this is needed for the pll/ss setup to work correctly in some cases */
1506 atombios_set_encoder_crtc_source(encoder);
1509 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1511 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1512 radeon_atom_output_lock(encoder, false);
1515 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1517 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1518 struct radeon_encoder_atom_dig *dig;
1519 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1521 if (radeon_encoder_is_digital(encoder)) {
1522 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1523 r600_hdmi_disable(encoder);
1524 dig = radeon_encoder->enc_priv;
1525 dig->dig_encoder = -1;
1527 radeon_encoder->active_device = 0;
1530 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1531 .dpms = radeon_atom_encoder_dpms,
1532 .mode_fixup = radeon_atom_mode_fixup,
1533 .prepare = radeon_atom_encoder_prepare,
1534 .mode_set = radeon_atom_encoder_mode_set,
1535 .commit = radeon_atom_encoder_commit,
1536 .disable = radeon_atom_encoder_disable,
1537 /* no detect for TMDS/LVDS yet */
1540 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1541 .dpms = radeon_atom_encoder_dpms,
1542 .mode_fixup = radeon_atom_mode_fixup,
1543 .prepare = radeon_atom_encoder_prepare,
1544 .mode_set = radeon_atom_encoder_mode_set,
1545 .commit = radeon_atom_encoder_commit,
1546 .detect = radeon_atom_dac_detect,
1549 void radeon_enc_destroy(struct drm_encoder *encoder)
1551 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1552 kfree(radeon_encoder->enc_priv);
1553 drm_encoder_cleanup(encoder);
1554 kfree(radeon_encoder);
1557 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1558 .destroy = radeon_enc_destroy,
1561 struct radeon_encoder_atom_dac *
1562 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1564 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1569 dac->tv_std = TV_STD_NTSC;
1573 struct radeon_encoder_atom_dig *
1574 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1576 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1581 /* coherent mode by default */
1582 dig->coherent_mode = true;
1583 dig->dig_encoder = -1;
1589 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1591 struct radeon_device *rdev = dev->dev_private;
1592 struct drm_encoder *encoder;
1593 struct radeon_encoder *radeon_encoder;
1595 /* see if we already added it */
1596 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1597 radeon_encoder = to_radeon_encoder(encoder);
1598 if (radeon_encoder->encoder_id == encoder_id) {
1599 radeon_encoder->devices |= supported_device;
1606 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1607 if (!radeon_encoder)
1610 encoder = &radeon_encoder->base;
1611 switch (rdev->num_crtc) {
1613 encoder->possible_crtcs = 0x1;
1617 encoder->possible_crtcs = 0x3;
1620 encoder->possible_crtcs = 0x3f;
1624 radeon_encoder->enc_priv = NULL;
1626 radeon_encoder->encoder_id = encoder_id;
1627 radeon_encoder->devices = supported_device;
1628 radeon_encoder->rmx_type = RMX_OFF;
1630 switch (radeon_encoder->encoder_id) {
1631 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1632 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1633 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1634 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1635 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1636 radeon_encoder->rmx_type = RMX_FULL;
1637 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1638 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1640 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1641 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1643 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1645 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1646 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1647 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1649 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1650 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1651 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1652 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1653 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1654 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1656 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1657 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1658 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1659 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1660 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1661 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1662 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1663 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1664 radeon_encoder->rmx_type = RMX_FULL;
1665 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1666 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1668 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1669 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1671 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);