drivers/gpu/drm/radeon/radeon_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
  39 {
  40         struct drm_device *dev = encoder->dev;
  41         struct radeon_device *rdev = dev->dev_private;
  42         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  43         struct drm_encoder *clone_encoder;
  44         uint32_t index_mask = 0;
  45         int count;
  46
  47         /* DIG routing gets problematic */
  48         if (rdev->family >= CHIP_R600)
  49                 return index_mask;
  50         /* LVDS/TV are too wacky */
  51         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
  52                 return index_mask;
  53         /* DVO requires 2x ppll clocks depending on tmds chip */
  54         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
  55                 return index_mask;
  56
  57         count = -1;
  58         list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
  59                 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
  60                 count++;
  61
  62                 if (clone_encoder == encoder)
  63                         continue;
  64                 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
  65                         continue;
  66                 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
  67                         continue;
  68                 else
  69                         index_mask |= (1 << count);
  70         }
  71         return index_mask;
  72 }
  73
  74 void radeon_setup_encoder_clones(struct drm_device *dev)
  75 {
  76         struct drm_encoder *encoder;
  77
  78         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  79                 encoder->possible_clones = radeon_encoder_clones(encoder);
  80         }
  81 }
  82
  83 uint32_t
  84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
  85 {
  86         struct radeon_device *rdev = dev->dev_private;
  87         uint32_t ret = 0;
  88
  89         switch (supported_device) {
  90         case ATOM_DEVICE_CRT1_SUPPORT:
  91         case ATOM_DEVICE_TV1_SUPPORT:
  92         case ATOM_DEVICE_TV2_SUPPORT:
  93         case ATOM_DEVICE_CRT2_SUPPORT:
  94         case ATOM_DEVICE_CV_SUPPORT:
  95                 switch (dac) {
  96                 case 1: /* dac a */
  97                         if ((rdev->family == CHIP_RS300) ||
  98                             (rdev->family == CHIP_RS400) ||
  99                             (rdev->family == CHIP_RS480))
 100                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 101                         else if (ASIC_IS_AVIVO(rdev))
 102                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
 103                         else
 104                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
 105                         break;
 106                 case 2: /* dac b */
 107                         if (ASIC_IS_AVIVO(rdev))
 108                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
 109                         else {
 110                                 /*if (rdev->family == CHIP_R200)
 111                                   ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 112                                   else*/
 113                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 114                         }
 115                         break;
 116                 case 3: /* external dac */
 117                         if (ASIC_IS_AVIVO(rdev))
 118                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 119                         else
 120                                 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 121                         break;
 122                 }
 123                 break;
 124         case ATOM_DEVICE_LCD1_SUPPORT:
 125                 if (ASIC_IS_AVIVO(rdev))
 126                         ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 127                 else
 128                         ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
 129                 break;
 130         case ATOM_DEVICE_DFP1_SUPPORT:
 131                 if ((rdev->family == CHIP_RS300) ||
 132                     (rdev->family == CHIP_RS400) ||
 133                     (rdev->family == CHIP_RS480))
 134                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 135                 else if (ASIC_IS_AVIVO(rdev))
 136                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
 137                 else
 138                         ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
 139                 break;
 140         case ATOM_DEVICE_LCD2_SUPPORT:
 141         case ATOM_DEVICE_DFP2_SUPPORT:
 142                 if ((rdev->family == CHIP_RS600) ||
 143                     (rdev->family == CHIP_RS690) ||
 144                     (rdev->family == CHIP_RS740))
 145                         ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
 146                 else if (ASIC_IS_AVIVO(rdev))
 147                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 148                 else
 149                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 150                 break;
 151         case ATOM_DEVICE_DFP3_SUPPORT:
 152                 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 153                 break;
 154         }
 155
 156         return ret;
 157 }
 158
 159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
 160 {
 161         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 162         switch (radeon_encoder->encoder_id) {
 163         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 164         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 165         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 166         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 167         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 168         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 169         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 170         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 171         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 172         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 173         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 174                 return true;
 175         default:
 176                 return false;
 177         }
 178 }
 179 void
 180 radeon_link_encoder_connector(struct drm_device *dev)
 181 {
 182         struct drm_connector *connector;
 183         struct radeon_connector *radeon_connector;
 184         struct drm_encoder *encoder;
 185         struct radeon_encoder *radeon_encoder;
 186
 187         /* walk the list and link encoders to connectors */
 188         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 189                 radeon_connector = to_radeon_connector(connector);
 190                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 191                         radeon_encoder = to_radeon_encoder(encoder);
 192                         if (radeon_encoder->devices & radeon_connector->devices)
 193                                 drm_mode_connector_attach_encoder(connector, encoder);
 194                 }
 195         }
 196 }
 197
 198 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
 199 {
 200         struct drm_device *dev = encoder->dev;
 201         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 202         struct drm_connector *connector;
 203
 204         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 205                 if (connector->encoder == encoder) {
 206                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 207                         radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
 208                         DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
 209                                   radeon_encoder->active_device, radeon_encoder->devices,
 210                                   radeon_connector->devices, encoder->encoder_type);
 211                 }
 212         }
 213 }
 214
 215 static struct drm_connector *
 216 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
 217 {
 218         struct drm_device *dev = encoder->dev;
 219         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 220         struct drm_connector *connector;
 221         struct radeon_connector *radeon_connector;
 222
 223         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 224                 radeon_connector = to_radeon_connector(connector);
 225                 if (radeon_encoder->active_device & radeon_connector->devices)
 226                         return connector;
 227         }
 228         return NULL;
 229 }
 230
 231 static struct radeon_connector_atom_dig *
 232 radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder)
 233 {
 234         struct drm_device *dev = encoder->dev;
 235         struct radeon_device *rdev = dev->dev_private;
 236         struct drm_connector *connector;
 237         struct radeon_connector *radeon_connector;
 238         struct radeon_connector_atom_dig *dig_connector;
 239
 240         if (!rdev->is_atom_bios)
 241                 return NULL;
 242
 243         connector = radeon_get_connector_for_encoder(encoder);
 244         if (!connector)
 245                 return NULL;
 246
 247         radeon_connector = to_radeon_connector(connector);
 248
 249         if (!radeon_connector->con_priv)
 250                 return NULL;
 251
 252         dig_connector = radeon_connector->con_priv;
 253
 254         return dig_connector;
 255 }
 256
 257 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 258                                    struct drm_display_mode *mode,
 259                                    struct drm_display_mode *adjusted_mode)
 260 {
 261         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 262         struct drm_device *dev = encoder->dev;
 263         struct radeon_device *rdev = dev->dev_private;
 264
 265         /* adjust pm to upcoming mode change */
 266         radeon_pm_compute_clocks(rdev);
 267
 268         /* set the active encoder to connector routing */
 269         radeon_encoder_set_active_device(encoder);
 270         drm_mode_set_crtcinfo(adjusted_mode, 0);
 271
 272         /* hw bug */
 273         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 274             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 275                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 276
 277         /* get the native mode for LVDS */
 278         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 279                 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 280                 int mode_id = adjusted_mode->base.id;
 281                 *adjusted_mode = *native_mode;
 282                 if (!ASIC_IS_AVIVO(rdev)) {
 283                         adjusted_mode->hdisplay = mode->hdisplay;
 284                         adjusted_mode->vdisplay = mode->vdisplay;
 285                         adjusted_mode->crtc_hdisplay = mode->hdisplay;
 286                         adjusted_mode->crtc_vdisplay = mode->vdisplay;
 287                 }
 288                 adjusted_mode->base.id = mode_id;
 289         }
 290
 291         /* get the native mode for TV */
 292         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 293                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 294                 if (tv_dac) {
 295                         if (tv_dac->tv_std == TV_STD_NTSC ||
 296                             tv_dac->tv_std == TV_STD_NTSC_J ||
 297                             tv_dac->tv_std == TV_STD_PAL_M)
 298                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 299                         else
 300                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 301                 }
 302         }
 303
 304         if (ASIC_IS_DCE3(rdev) &&
 305             (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
 306                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 307                 radeon_dp_set_link_config(connector, mode);
 308         }
 309
 310         return true;
 311 }
 312
 313 static void
 314 atombios_dac_setup(struct drm_encoder *encoder, int action)
 315 {
 316         struct drm_device *dev = encoder->dev;
 317         struct radeon_device *rdev = dev->dev_private;
 318         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 319         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 320         int index = 0;
 321         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 322
 323         memset(&args, 0, sizeof(args));
 324
 325         switch (radeon_encoder->encoder_id) {
 326         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 327         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 328                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 329                 break;
 330         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 331         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 332                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 333                 break;
 334         }
 335
 336         args.ucAction = action;
 337
 338         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 339                 args.ucDacStandard = ATOM_DAC1_PS2;
 340         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 341                 args.ucDacStandard = ATOM_DAC1_CV;
 342         else {
 343                 switch (dac_info->tv_std) {
 344                 case TV_STD_PAL:
 345                 case TV_STD_PAL_M:
 346                 case TV_STD_SCART_PAL:
 347                 case TV_STD_SECAM:
 348                 case TV_STD_PAL_CN:
 349                         args.ucDacStandard = ATOM_DAC1_PAL;
 350                         break;
 351                 case TV_STD_NTSC:
 352                 case TV_STD_NTSC_J:
 353                 case TV_STD_PAL_60:
 354                 default:
 355                         args.ucDacStandard = ATOM_DAC1_NTSC;
 356                         break;
 357                 }
 358         }
 359         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 360
 361         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 362
 363 }
 364
 365 static void
 366 atombios_tv_setup(struct drm_encoder *encoder, int action)
 367 {
 368         struct drm_device *dev = encoder->dev;
 369         struct radeon_device *rdev = dev->dev_private;
 370         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 371         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 372         int index = 0;
 373         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 374
 375         memset(&args, 0, sizeof(args));
 376
 377         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 378
 379         args.sTVEncoder.ucAction = action;
 380
 381         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 382                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 383         else {
 384                 switch (dac_info->tv_std) {
 385                 case TV_STD_NTSC:
 386                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 387                         break;
 388                 case TV_STD_PAL:
 389                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 390                         break;
 391                 case TV_STD_PAL_M:
 392                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 393                         break;
 394                 case TV_STD_PAL_60:
 395                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 396                         break;
 397                 case TV_STD_NTSC_J:
 398                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 399                         break;
 400                 case TV_STD_SCART_PAL:
 401                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 402                         break;
 403                 case TV_STD_SECAM:
 404                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 405                         break;
 406                 case TV_STD_PAL_CN:
 407                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 408                         break;
 409                 default:
 410                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 411                         break;
 412                 }
 413         }
 414
 415         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 416
 417         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 418
 419 }
 420
 421 void
 422 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
 423 {
 424         struct drm_device *dev = encoder->dev;
 425         struct radeon_device *rdev = dev->dev_private;
 426         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 427         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
 428         int index = 0;
 429
 430         memset(&args, 0, sizeof(args));
 431
 432         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 433
 434         args.sXTmdsEncoder.ucEnable = action;
 435
 436         if (radeon_encoder->pixel_clock > 165000)
 437                 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
 438
 439         /*if (pScrn->rgbBits == 8)*/
 440         args.sXTmdsEncoder.ucMisc |= (1 << 1);
 441
 442         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 443
 444 }
 445
 446 static void
 447 atombios_ddia_setup(struct drm_encoder *encoder, int action)
 448 {
 449         struct drm_device *dev = encoder->dev;
 450         struct radeon_device *rdev = dev->dev_private;
 451         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 452         DVO_ENCODER_CONTROL_PS_ALLOCATION args;
 453         int index = 0;
 454
 455         memset(&args, 0, sizeof(args));
 456
 457         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 458
 459         args.sDVOEncoder.ucAction = action;
 460         args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 461
 462         if (radeon_encoder->pixel_clock > 165000)
 463                 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
 464
 465         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 466
 467 }
 468
 469 union lvds_encoder_control {
 470         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 471         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 472 };
 473
 474 void
 475 atombios_digital_setup(struct drm_encoder *encoder, int action)
 476 {
 477         struct drm_device *dev = encoder->dev;
 478         struct radeon_device *rdev = dev->dev_private;
 479         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 480         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 481         struct radeon_connector_atom_dig *dig_connector =
 482                 radeon_get_atom_connector_priv_from_encoder(encoder);
 483         union lvds_encoder_control args;
 484         int index = 0;
 485         int hdmi_detected = 0;
 486         uint8_t frev, crev;
 487
 488         if (!dig || !dig_connector)
 489                 return;
 490
 491         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 492                 hdmi_detected = 1;
 493
 494         memset(&args, 0, sizeof(args));
 495
 496         switch (radeon_encoder->encoder_id) {
 497         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 498                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 499                 break;
 500         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 501         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 502                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 503                 break;
 504         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 505                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 506                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 507                 else
 508                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 509                 break;
 510         }
 511
 512         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 513                 return;
 514
 515         switch (frev) {
 516         case 1:
 517         case 2:
 518                 switch (crev) {
 519                 case 1:
 520                         args.v1.ucMisc = 0;
 521                         args.v1.ucAction = action;
 522                         if (hdmi_detected)
 523                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 524                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 525                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 526                                 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
 527                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 528                                 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 529                                         args.v1.ucMisc |= (1 << 1);
 530                         } else {
 531                                 if (dig_connector->linkb)
 532                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 533                                 if (radeon_encoder->pixel_clock > 165000)
 534                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 535                                 /*if (pScrn->rgbBits == 8) */
 536                                 args.v1.ucMisc |= (1 << 1);
 537                         }
 538                         break;
 539                 case 2:
 540                 case 3:
 541                         args.v2.ucMisc = 0;
 542                         args.v2.ucAction = action;
 543                         if (crev == 3) {
 544                                 if (dig->coherent_mode)
 545                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 546                         }
 547                         if (hdmi_detected)
 548                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 549                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 550                         args.v2.ucTruncate = 0;
 551                         args.v2.ucSpatial = 0;
 552                         args.v2.ucTemporal = 0;
 553                         args.v2.ucFRC = 0;
 554                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 555                                 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
 556                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 557                                 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
 558                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 559                                         if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 560                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 561                                 }
 562                                 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
 563                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 564                                         if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 565                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 566                                         if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 567                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 568                                 }
 569                         } else {
 570                                 if (dig_connector->linkb)
 571                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 572                                 if (radeon_encoder->pixel_clock > 165000)
 573                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 574                         }
 575                         break;
 576                 default:
 577                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 578                         break;
 579                 }
 580                 break;
 581         default:
 582                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 583                 break;
 584         }
 585
 586         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 587 }
 588
 589 int
 590 atombios_get_encoder_mode(struct drm_encoder *encoder)
 591 {
 592         struct drm_connector *connector;
 593         struct radeon_connector *radeon_connector;
 594         struct radeon_connector_atom_dig *dig_connector;
 595
 596         connector = radeon_get_connector_for_encoder(encoder);
 597         if (!connector)
 598                 return 0;
 599
 600         radeon_connector = to_radeon_connector(connector);
 601
 602         switch (connector->connector_type) {
 603         case DRM_MODE_CONNECTOR_DVII:
 604         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 605                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 606                         return ATOM_ENCODER_MODE_HDMI;
 607                 else if (radeon_connector->use_digital)
 608                         return ATOM_ENCODER_MODE_DVI;
 609                 else
 610                         return ATOM_ENCODER_MODE_CRT;
 611                 break;
 612         case DRM_MODE_CONNECTOR_DVID:
 613         case DRM_MODE_CONNECTOR_HDMIA:
 614         default:
 615                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 616                         return ATOM_ENCODER_MODE_HDMI;
 617                 else
 618                         return ATOM_ENCODER_MODE_DVI;
 619                 break;
 620         case DRM_MODE_CONNECTOR_LVDS:
 621                 return ATOM_ENCODER_MODE_LVDS;
 622                 break;
 623         case DRM_MODE_CONNECTOR_DisplayPort:
 624         case DRM_MODE_CONNECTOR_eDP:
 625                 dig_connector = radeon_connector->con_priv;
 626                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 627                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 628                         return ATOM_ENCODER_MODE_DP;
 629                 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
 630                         return ATOM_ENCODER_MODE_HDMI;
 631                 else
 632                         return ATOM_ENCODER_MODE_DVI;
 633                 break;
 634         case DRM_MODE_CONNECTOR_DVIA:
 635         case DRM_MODE_CONNECTOR_VGA:
 636                 return ATOM_ENCODER_MODE_CRT;
 637                 break;
 638         case DRM_MODE_CONNECTOR_Composite:
 639         case DRM_MODE_CONNECTOR_SVIDEO:
 640         case DRM_MODE_CONNECTOR_9PinDIN:
 641                 /* fix me */
 642                 return ATOM_ENCODER_MODE_TV;
 643                 /*return ATOM_ENCODER_MODE_CV;*/
 644                 break;
 645         }
 646 }
 647
 648 /*
 649  * DIG Encoder/Transmitter Setup
 650  *
 651  * DCE 3.0/3.1
 652  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 653  * Supports up to 3 digital outputs
 654  * - 2 DIG encoder blocks.
 655  * DIG1 can drive UNIPHY link A or link B
 656  * DIG2 can drive UNIPHY link B or LVTMA
 657  *
 658  * DCE 3.2
 659  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 660  * Supports up to 5 digital outputs
 661  * - 2 DIG encoder blocks.
 662  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 663  *
 664  * DCE 4.0
 665  * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
 666  * Supports up to 6 digital outputs
 667  * - 6 DIG encoder blocks.
 668  * - DIG to PHY mapping is hardcoded
 669  * DIG1 drives UNIPHY0 link A, A+B
 670  * DIG2 drives UNIPHY0 link B
 671  * DIG3 drives UNIPHY1 link A, A+B
 672  * DIG4 drives UNIPHY1 link B
 673  * DIG5 drives UNIPHY2 link A, A+B
 674  * DIG6 drives UNIPHY2 link B
 675  *
 676  * Routing
 677  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 678  * Examples:
 679  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 680  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 681  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 682  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 683  */
 684
 685 union dig_encoder_control {
 686         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 687         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 688         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 689 };
 690
 691 void
 692 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 693 {
 694         struct drm_device *dev = encoder->dev;
 695         struct radeon_device *rdev = dev->dev_private;
 696         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 697         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 698         struct radeon_connector_atom_dig *dig_connector =
 699                 radeon_get_atom_connector_priv_from_encoder(encoder);
 700         union dig_encoder_control args;
 701         int index = 0;
 702         uint8_t frev, crev;
 703
 704         if (!dig || !dig_connector)
 705                 return;
 706
 707         memset(&args, 0, sizeof(args));
 708
 709         if (ASIC_IS_DCE4(rdev))
 710                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 711         else {
 712                 if (dig->dig_encoder)
 713                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 714                 else
 715                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 716         }
 717
 718         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 719                 return;
 720
 721         args.v1.ucAction = action;
 722         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 723         args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 724
 725         if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
 726                 if (dig_connector->dp_clock == 270000)
 727                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 728                 args.v1.ucLaneNum = dig_connector->dp_lane_count;
 729         } else if (radeon_encoder->pixel_clock > 165000)
 730                 args.v1.ucLaneNum = 8;
 731         else
 732                 args.v1.ucLaneNum = 4;
 733
 734         if (ASIC_IS_DCE4(rdev)) {
 735                 args.v3.acConfig.ucDigSel = dig->dig_encoder;
 736                 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 737         } else {
 738                 switch (radeon_encoder->encoder_id) {
 739                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 740                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 741                         break;
 742                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 743                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 744                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 745                         break;
 746                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 747                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 748                         break;
 749                 }
 750                 if (dig_connector->linkb)
 751                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 752                 else
 753                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 754         }
 755
 756         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 757
 758 }
 759
 760 union dig_transmitter_control {
 761         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 762         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 763         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 764 };
 765
 766 void
 767 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 768 {
 769         struct drm_device *dev = encoder->dev;
 770         struct radeon_device *rdev = dev->dev_private;
 771         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 772         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 773         struct radeon_connector_atom_dig *dig_connector =
 774                 radeon_get_atom_connector_priv_from_encoder(encoder);
 775         struct drm_connector *connector;
 776         struct radeon_connector *radeon_connector;
 777         union dig_transmitter_control args;
 778         int index = 0;
 779         uint8_t frev, crev;
 780         bool is_dp = false;
 781         int pll_id = 0;
 782
 783         if (!dig || !dig_connector)
 784                 return;
 785
 786         connector = radeon_get_connector_for_encoder(encoder);
 787         radeon_connector = to_radeon_connector(connector);
 788
 789         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
 790                 is_dp = true;
 791
 792         memset(&args, 0, sizeof(args));
 793
 794         if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev))
 795                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 796         else {
 797                 switch (radeon_encoder->encoder_id) {
 798                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 799                         index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
 800                         break;
 801                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 802                         index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
 803                         break;
 804                 }
 805         }
 806
 807         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 808                 return;
 809
 810         args.v1.ucAction = action;
 811         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 812                 args.v1.usInitInfo = radeon_connector->connector_object_id;
 813         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 814                 args.v1.asMode.ucLaneSel = lane_num;
 815                 args.v1.asMode.ucLaneSet = lane_set;
 816         } else {
 817                 if (is_dp)
 818                         args.v1.usPixelClock =
 819                                 cpu_to_le16(dig_connector->dp_clock / 10);
 820                 else if (radeon_encoder->pixel_clock > 165000)
 821                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 822                 else
 823                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 824         }
 825         if (ASIC_IS_DCE4(rdev)) {
 826                 if (is_dp)
 827                         args.v3.ucLaneNum = dig_connector->dp_lane_count;
 828                 else if (radeon_encoder->pixel_clock > 165000)
 829                         args.v3.ucLaneNum = 8;
 830                 else
 831                         args.v3.ucLaneNum = 4;
 832
 833                 if (dig_connector->linkb) {
 834                         args.v3.acConfig.ucLinkSel = 1;
 835                         args.v3.acConfig.ucEncoderSel = 1;
 836                 }
 837
 838                 /* Select the PLL for the PHY
 839                  * DP PHY should be clocked from external src if there is
 840                  * one.
 841                  */
 842                 if (encoder->crtc) {
 843                         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 844                         pll_id = radeon_crtc->pll_id;
 845                 }
 846                 if (is_dp && rdev->clock.dp_extclk)
 847                         args.v3.acConfig.ucRefClkSource = 2; /* external src */
 848                 else
 849                         args.v3.acConfig.ucRefClkSource = pll_id;
 850
 851                 switch (radeon_encoder->encoder_id) {
 852                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 853                         args.v3.acConfig.ucTransmitterSel = 0;
 854                         break;
 855                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 856                         args.v3.acConfig.ucTransmitterSel = 1;
 857                         break;
 858                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 859                         args.v3.acConfig.ucTransmitterSel = 2;
 860                         break;
 861                 }
 862
 863                 if (is_dp)
 864                         args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
 865                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 866                         if (dig->coherent_mode)
 867                                 args.v3.acConfig.fCoherentMode = 1;
 868                 }
 869         } else if (ASIC_IS_DCE32(rdev)) {
 870                 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
 871                 if (dig_connector->linkb)
 872                         args.v2.acConfig.ucLinkSel = 1;
 873
 874                 switch (radeon_encoder->encoder_id) {
 875                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 876                         args.v2.acConfig.ucTransmitterSel = 0;
 877                         break;
 878                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 879                         args.v2.acConfig.ucTransmitterSel = 1;
 880                         break;
 881                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 882                         args.v2.acConfig.ucTransmitterSel = 2;
 883                         break;
 884                 }
 885
 886                 if (is_dp)
 887                         args.v2.acConfig.fCoherentMode = 1;
 888                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 889                         if (dig->coherent_mode)
 890                                 args.v2.acConfig.fCoherentMode = 1;
 891                 }
 892         } else {
 893                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 894
 895                 if (dig->dig_encoder)
 896                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 897                 else
 898                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 899
 900                 if ((rdev->flags & RADEON_IS_IGP) &&
 901                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
 902                         if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
 903                                 if (dig_connector->igp_lane_info & 0x1)
 904                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 905                                 else if (dig_connector->igp_lane_info & 0x2)
 906                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 907                                 else if (dig_connector->igp_lane_info & 0x4)
 908                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 909                                 else if (dig_connector->igp_lane_info & 0x8)
 910                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 911                         } else {
 912                                 if (dig_connector->igp_lane_info & 0x3)
 913                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 914                                 else if (dig_connector->igp_lane_info & 0xc)
 915                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
 916                         }
 917                 }
 918
 919                 if (dig_connector->linkb)
 920                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
 921                 else
 922                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
 923
 924                 if (is_dp)
 925                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 926                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 927                         if (dig->coherent_mode)
 928                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 929                         if (radeon_encoder->pixel_clock > 165000)
 930                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
 931                 }
 932         }
 933
 934         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 935 }
 936
 937 static void
 938 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
 939 {
 940         struct drm_device *dev = encoder->dev;
 941         struct radeon_device *rdev = dev->dev_private;
 942         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 943         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 944         ENABLE_YUV_PS_ALLOCATION args;
 945         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
 946         uint32_t temp, reg;
 947
 948         memset(&args, 0, sizeof(args));
 949
 950         if (rdev->family >= CHIP_R600)
 951                 reg = R600_BIOS_3_SCRATCH;
 952         else
 953                 reg = RADEON_BIOS_3_SCRATCH;
 954
 955         /* XXX: fix up scratch reg handling */
 956         temp = RREG32(reg);
 957         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 958                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
 959                              (radeon_crtc->crtc_id << 18)));
 960         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 961                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
 962         else
 963                 WREG32(reg, 0);
 964
 965         if (enable)
 966                 args.ucEnable = ATOM_ENABLE;
 967         args.ucCRTC = radeon_crtc->crtc_id;
 968
 969         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 970
 971         WREG32(reg, temp);
 972 }
 973
 974 static void
 975 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
 976 {
 977         struct drm_device *dev = encoder->dev;
 978         struct radeon_device *rdev = dev->dev_private;
 979         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 980         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
 981         int index = 0;
 982         bool is_dig = false;
 983
 984         memset(&args, 0, sizeof(args));
 985
 986         DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
 987                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
 988                   radeon_encoder->active_device);
 989         switch (radeon_encoder->encoder_id) {
 990         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 991         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 992                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
 993                 break;
 994         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 995         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 996         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 997         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 998                 is_dig = true;
 999                 break;
1000         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1001         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1002         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1003                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1004                 break;
1005         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1006                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1007                 break;
1008         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1009                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1010                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1011                 else
1012                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1013                 break;
1014         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1015         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1016                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1017                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1018                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1019                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1020                 else
1021                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1022                 break;
1023         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1024         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1025                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1026                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1027                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1028                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1029                 else
1030                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1031                 break;
1032         }
1033
1034         if (is_dig) {
1035                 switch (mode) {
1036                 case DRM_MODE_DPMS_ON:
1037                         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1038                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1039
1040                                 dp_link_train(encoder, connector);
1041                                 if (ASIC_IS_DCE4(rdev))
1042                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
1043                         }
1044                         if (!ASIC_IS_DCE4(rdev))
1045                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1046                         break;
1047                 case DRM_MODE_DPMS_STANDBY:
1048                 case DRM_MODE_DPMS_SUSPEND:
1049                 case DRM_MODE_DPMS_OFF:
1050                         if (!ASIC_IS_DCE4(rdev))
1051                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1052                         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1053                                 if (ASIC_IS_DCE4(rdev))
1054                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1055                         }
1056                         break;
1057                 }
1058         } else {
1059                 switch (mode) {
1060                 case DRM_MODE_DPMS_ON:
1061                         args.ucAction = ATOM_ENABLE;
1062                         break;
1063                 case DRM_MODE_DPMS_STANDBY:
1064                 case DRM_MODE_DPMS_SUSPEND:
1065                 case DRM_MODE_DPMS_OFF:
1066                         args.ucAction = ATOM_DISABLE;
1067                         break;
1068                 }
1069                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1070         }
1071         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1072
1073         /* adjust pm to dpms change */
1074         radeon_pm_compute_clocks(rdev);
1075 }
1076
1077 union crtc_source_param {
1078         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1079         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1080 };
1081
1082 static void
1083 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1084 {
1085         struct drm_device *dev = encoder->dev;
1086         struct radeon_device *rdev = dev->dev_private;
1087         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1088         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1089         union crtc_source_param args;
1090         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1091         uint8_t frev, crev;
1092         struct radeon_encoder_atom_dig *dig;
1093
1094         memset(&args, 0, sizeof(args));
1095
1096         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1097                 return;
1098
1099         switch (frev) {
1100         case 1:
1101                 switch (crev) {
1102                 case 1:
1103                 default:
1104                         if (ASIC_IS_AVIVO(rdev))
1105                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1106                         else {
1107                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1108                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1109                                 } else {
1110                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1111                                 }
1112                         }
1113                         switch (radeon_encoder->encoder_id) {
1114                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1115                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1116                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1117                                 break;
1118                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1119                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1120                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1121                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1122                                 else
1123                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1124                                 break;
1125                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1126                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1127                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1128                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1129                                 break;
1130                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1131                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1132                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1133                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1134                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1135                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1136                                 else
1137                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1138                                 break;
1139                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1140                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1141                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1142                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1143                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1144                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1145                                 else
1146                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1147                                 break;
1148                         }
1149                         break;
1150                 case 2:
1151                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1152                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1153                         switch (radeon_encoder->encoder_id) {
1154                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1155                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1156                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1157                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1158                                 dig = radeon_encoder->enc_priv;
1159                                 switch (dig->dig_encoder) {
1160                                 case 0:
1161                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1162                                         break;
1163                                 case 1:
1164                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1165                                         break;
1166                                 case 2:
1167                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1168                                         break;
1169                                 case 3:
1170                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1171                                         break;
1172                                 case 4:
1173                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1174                                         break;
1175                                 case 5:
1176                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1177                                         break;
1178                                 }
1179                                 break;
1180                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1181                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1182                                 break;
1183                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1184                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1185                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1186                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1187                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1188                                 else
1189                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1190                                 break;
1191                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1192                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1193                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1194                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1195                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1196                                 else
1197                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1198                                 break;
1199                         }
1200                         break;
1201                 }
1202                 break;
1203         default:
1204                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1205                 break;
1206         }
1207
1208         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1209
1210         /* update scratch regs with new routing */
1211         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1212 }
1213
1214 static void
1215 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1216                               struct drm_display_mode *mode)
1217 {
1218         struct drm_device *dev = encoder->dev;
1219         struct radeon_device *rdev = dev->dev_private;
1220         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1221         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1222
1223         /* Funky macbooks */
1224         if ((dev->pdev->device == 0x71C5) &&
1225             (dev->pdev->subsystem_vendor == 0x106b) &&
1226             (dev->pdev->subsystem_device == 0x0080)) {
1227                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1228                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1229
1230                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1231                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1232
1233                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1234                 }
1235         }
1236
1237         /* set scaler clears this on some chips */
1238         /* XXX check DCE4 */
1239         if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1240                 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1241                         WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1242                                AVIVO_D1MODE_INTERLEAVE_EN);
1243         }
1244 }
1245
1246 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1247 {
1248         struct drm_device *dev = encoder->dev;
1249         struct radeon_device *rdev = dev->dev_private;
1250         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1251         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1252         struct drm_encoder *test_encoder;
1253         struct radeon_encoder_atom_dig *dig;
1254         uint32_t dig_enc_in_use = 0;
1255
1256         if (ASIC_IS_DCE4(rdev)) {
1257                 struct radeon_connector_atom_dig *dig_connector =
1258                         radeon_get_atom_connector_priv_from_encoder(encoder);
1259
1260                 switch (radeon_encoder->encoder_id) {
1261                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1262                         if (dig_connector->linkb)
1263                                 return 1;
1264                         else
1265                                 return 0;
1266                         break;
1267                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1268                         if (dig_connector->linkb)
1269                                 return 3;
1270                         else
1271                                 return 2;
1272                         break;
1273                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1274                         if (dig_connector->linkb)
1275                                 return 5;
1276                         else
1277                                 return 4;
1278                         break;
1279                 }
1280         }
1281
1282         /* on DCE32 and encoder can driver any block so just crtc id */
1283         if (ASIC_IS_DCE32(rdev)) {
1284                 return radeon_crtc->crtc_id;
1285         }
1286
1287         /* on DCE3 - LVTMA can only be driven by DIGB */
1288         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1289                 struct radeon_encoder *radeon_test_encoder;
1290
1291                 if (encoder == test_encoder)
1292                         continue;
1293
1294                 if (!radeon_encoder_is_digital(test_encoder))
1295                         continue;
1296
1297                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1298                 dig = radeon_test_encoder->enc_priv;
1299
1300                 if (dig->dig_encoder >= 0)
1301                         dig_enc_in_use |= (1 << dig->dig_encoder);
1302         }
1303
1304         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1305                 if (dig_enc_in_use & 0x2)
1306                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1307                 return 1;
1308         }
1309         if (!(dig_enc_in_use & 1))
1310                 return 0;
1311         return 1;
1312 }
1313
1314 static void
1315 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1316                              struct drm_display_mode *mode,
1317                              struct drm_display_mode *adjusted_mode)
1318 {
1319         struct drm_device *dev = encoder->dev;
1320         struct radeon_device *rdev = dev->dev_private;
1321         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1322
1323         radeon_encoder->pixel_clock = adjusted_mode->clock;
1324
1325         if (ASIC_IS_AVIVO(rdev)) {
1326                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1327                         atombios_yuv_setup(encoder, true);
1328                 else
1329                         atombios_yuv_setup(encoder, false);
1330         }
1331
1332         switch (radeon_encoder->encoder_id) {
1333         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1334         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1335         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1336         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1337                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1338                 break;
1339         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1340         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1341         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1342         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1343                 if (ASIC_IS_DCE4(rdev)) {
1344                         /* disable the transmitter */
1345                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1346                         /* setup and enable the encoder */
1347                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1348
1349                         /* init and enable the transmitter */
1350                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1351                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1352                 } else {
1353                         /* disable the encoder and transmitter */
1354                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1355                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1356
1357                         /* setup and enable the encoder and transmitter */
1358                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1359                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1360                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1361                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1362                 }
1363                 break;
1364         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1365                 atombios_ddia_setup(encoder, ATOM_ENABLE);
1366                 break;
1367         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1368         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1369                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1370                 break;
1371         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1372         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1373         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1374         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1375                 atombios_dac_setup(encoder, ATOM_ENABLE);
1376                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1377                         atombios_tv_setup(encoder, ATOM_ENABLE);
1378                 break;
1379         }
1380         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1381
1382         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1383                 r600_hdmi_enable(encoder);
1384                 r600_hdmi_setmode(encoder, adjusted_mode);
1385         }
1386 }
1387
1388 static bool
1389 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1390 {
1391         struct drm_device *dev = encoder->dev;
1392         struct radeon_device *rdev = dev->dev_private;
1393         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1394         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1395
1396         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1397                                        ATOM_DEVICE_CV_SUPPORT |
1398                                        ATOM_DEVICE_CRT_SUPPORT)) {
1399                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1400                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1401                 uint8_t frev, crev;
1402
1403                 memset(&args, 0, sizeof(args));
1404
1405                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1406                         return false;
1407
1408                 args.sDacload.ucMisc = 0;
1409
1410                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1411                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1412                         args.sDacload.ucDacType = ATOM_DAC_A;
1413                 else
1414                         args.sDacload.ucDacType = ATOM_DAC_B;
1415
1416                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1417                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1418                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1419                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1420                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1421                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1422                         if (crev >= 3)
1423                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1424                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1425                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1426                         if (crev >= 3)
1427                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1428                 }
1429
1430                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1431
1432                 return true;
1433         } else
1434                 return false;
1435 }
1436
1437 static enum drm_connector_status
1438 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1439 {
1440         struct drm_device *dev = encoder->dev;
1441         struct radeon_device *rdev = dev->dev_private;
1442         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1443         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1444         uint32_t bios_0_scratch;
1445
1446         if (!atombios_dac_load_detect(encoder, connector)) {
1447                 DRM_DEBUG("detect returned false \n");
1448                 return connector_status_unknown;
1449         }
1450
1451         if (rdev->family >= CHIP_R600)
1452                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1453         else
1454                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1455
1456         DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1457         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1458                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1459                         return connector_status_connected;
1460         }
1461         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1462                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1463                         return connector_status_connected;
1464         }
1465         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1466                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1467                         return connector_status_connected;
1468         }
1469         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1470                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1471                         return connector_status_connected; /* CTV */
1472                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1473                         return connector_status_connected; /* STV */
1474         }
1475         return connector_status_disconnected;
1476 }
1477
1478 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1479 {
1480         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1481
1482         if (radeon_encoder->active_device &
1483             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1484                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1485                 if (dig)
1486                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1487         }
1488
1489         radeon_atom_output_lock(encoder, true);
1490         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1491
1492         /* this is needed for the pll/ss setup to work correctly in some cases */
1493         atombios_set_encoder_crtc_source(encoder);
1494 }
1495
1496 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1497 {
1498         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1499         radeon_atom_output_lock(encoder, false);
1500 }
1501
1502 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1503 {
1504         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1505         struct radeon_encoder_atom_dig *dig;
1506         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1507
1508         if (radeon_encoder_is_digital(encoder)) {
1509                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1510                         r600_hdmi_disable(encoder);
1511                 dig = radeon_encoder->enc_priv;
1512                 dig->dig_encoder = -1;
1513         }
1514         radeon_encoder->active_device = 0;
1515 }
1516
1517 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1518         .dpms = radeon_atom_encoder_dpms,
1519         .mode_fixup = radeon_atom_mode_fixup,
1520         .prepare = radeon_atom_encoder_prepare,
1521         .mode_set = radeon_atom_encoder_mode_set,
1522         .commit = radeon_atom_encoder_commit,
1523         .disable = radeon_atom_encoder_disable,
1524         /* no detect for TMDS/LVDS yet */
1525 };
1526
1527 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1528         .dpms = radeon_atom_encoder_dpms,
1529         .mode_fixup = radeon_atom_mode_fixup,
1530         .prepare = radeon_atom_encoder_prepare,
1531         .mode_set = radeon_atom_encoder_mode_set,
1532         .commit = radeon_atom_encoder_commit,
1533         .detect = radeon_atom_dac_detect,
1534 };
1535
1536 void radeon_enc_destroy(struct drm_encoder *encoder)
1537 {
1538         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1539         kfree(radeon_encoder->enc_priv);
1540         drm_encoder_cleanup(encoder);
1541         kfree(radeon_encoder);
1542 }
1543
1544 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1545         .destroy = radeon_enc_destroy,
1546 };
1547
1548 struct radeon_encoder_atom_dac *
1549 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1550 {
1551         struct drm_device *dev = radeon_encoder->base.dev;
1552         struct radeon_device *rdev = dev->dev_private;
1553         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1554
1555         if (!dac)
1556                 return NULL;
1557
1558         dac->tv_std = radeon_atombios_get_tv_info(rdev);
1559         return dac;
1560 }
1561
1562 struct radeon_encoder_atom_dig *
1563 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1564 {
1565         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1566
1567         if (!dig)
1568                 return NULL;
1569
1570         /* coherent mode by default */
1571         dig->coherent_mode = true;
1572         dig->dig_encoder = -1;
1573
1574         return dig;
1575 }
1576
1577 void
1578 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1579 {
1580         struct radeon_device *rdev = dev->dev_private;
1581         struct drm_encoder *encoder;
1582         struct radeon_encoder *radeon_encoder;
1583
1584         /* see if we already added it */
1585         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1586                 radeon_encoder = to_radeon_encoder(encoder);
1587                 if (radeon_encoder->encoder_id == encoder_id) {
1588                         radeon_encoder->devices |= supported_device;
1589                         return;
1590                 }
1591
1592         }
1593
1594         /* add a new one */
1595         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1596         if (!radeon_encoder)
1597                 return;
1598
1599         encoder = &radeon_encoder->base;
1600         switch (rdev->num_crtc) {
1601         case 1:
1602                 encoder->possible_crtcs = 0x1;
1603                 break;
1604         case 2:
1605         default:
1606                 encoder->possible_crtcs = 0x3;
1607                 break;
1608         case 6:
1609                 encoder->possible_crtcs = 0x3f;
1610                 break;
1611         }
1612
1613         radeon_encoder->enc_priv = NULL;
1614
1615         radeon_encoder->encoder_id = encoder_id;
1616         radeon_encoder->devices = supported_device;
1617         radeon_encoder->rmx_type = RMX_OFF;
1618
1619         switch (radeon_encoder->encoder_id) {
1620         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1621         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1622         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1623         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1624                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1625                         radeon_encoder->rmx_type = RMX_FULL;
1626                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1627                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1628                 } else {
1629                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1630                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1631                 }
1632                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1633                 break;
1634         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1635                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1636                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1637                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1638                 break;
1639         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1640         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1641         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1642                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1643                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1644                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1645                 break;
1646         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1647         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1648         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1649         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1650         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1651         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1652         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1653                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1654                         radeon_encoder->rmx_type = RMX_FULL;
1655                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1656                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1657                 } else {
1658                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1659                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1660                 }
1661                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1662                 break;
1663         }
1664 }