drivers/gpu/drm/radeon/radeon_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
  39 {
  40         struct drm_device *dev = encoder->dev;
  41         struct radeon_device *rdev = dev->dev_private;
  42         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  43         struct drm_encoder *clone_encoder;
  44         uint32_t index_mask = 0;
  45         int count;
  46
  47         /* DIG routing gets problematic */
  48         if (rdev->family >= CHIP_R600)
  49                 return index_mask;
  50         /* LVDS/TV are too wacky */
  51         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
  52                 return index_mask;
  53         /* DVO requires 2x ppll clocks depending on tmds chip */
  54         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
  55                 return index_mask;
  56
  57         count = -1;
  58         list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
  59                 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
  60                 count++;
  61
  62                 if (clone_encoder == encoder)
  63                         continue;
  64                 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
  65                         continue;
  66                 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
  67                         continue;
  68                 else
  69                         index_mask |= (1 << count);
  70         }
  71         return index_mask;
  72 }
  73
  74 void radeon_setup_encoder_clones(struct drm_device *dev)
  75 {
  76         struct drm_encoder *encoder;
  77
  78         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  79                 encoder->possible_clones = radeon_encoder_clones(encoder);
  80         }
  81 }
  82
  83 uint32_t
  84 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
  85 {
  86         struct radeon_device *rdev = dev->dev_private;
  87         uint32_t ret = 0;
  88
  89         switch (supported_device) {
  90         case ATOM_DEVICE_CRT1_SUPPORT:
  91         case ATOM_DEVICE_TV1_SUPPORT:
  92         case ATOM_DEVICE_TV2_SUPPORT:
  93         case ATOM_DEVICE_CRT2_SUPPORT:
  94         case ATOM_DEVICE_CV_SUPPORT:
  95                 switch (dac) {
  96                 case 1: /* dac a */
  97                         if ((rdev->family == CHIP_RS300) ||
  98                             (rdev->family == CHIP_RS400) ||
  99                             (rdev->family == CHIP_RS480))
 100                                 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
 101                         else if (ASIC_IS_AVIVO(rdev))
 102                                 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
 103                         else
 104                                 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
 105                         break;
 106                 case 2: /* dac b */
 107                         if (ASIC_IS_AVIVO(rdev))
 108                                 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
 109                         else {
 110                                 /*if (rdev->family == CHIP_R200)
 111                                   ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 112                                   else*/
 113                                 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
 114                         }
 115                         break;
 116                 case 3: /* external dac */
 117                         if (ASIC_IS_AVIVO(rdev))
 118                                 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
 119                         else
 120                                 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 121                         break;
 122                 }
 123                 break;
 124         case ATOM_DEVICE_LCD1_SUPPORT:
 125                 if (ASIC_IS_AVIVO(rdev))
 126                         ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
 127                 else
 128                         ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
 129                 break;
 130         case ATOM_DEVICE_DFP1_SUPPORT:
 131                 if ((rdev->family == CHIP_RS300) ||
 132                     (rdev->family == CHIP_RS400) ||
 133                     (rdev->family == CHIP_RS480))
 134                         ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 135                 else if (ASIC_IS_AVIVO(rdev))
 136                         ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
 137                 else
 138                         ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
 139                 break;
 140         case ATOM_DEVICE_LCD2_SUPPORT:
 141         case ATOM_DEVICE_DFP2_SUPPORT:
 142                 if ((rdev->family == CHIP_RS600) ||
 143                     (rdev->family == CHIP_RS690) ||
 144                     (rdev->family == CHIP_RS740))
 145                         ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
 146                 else if (ASIC_IS_AVIVO(rdev))
 147                         ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
 148                 else
 149                         ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 150                 break;
 151         case ATOM_DEVICE_DFP3_SUPPORT:
 152                 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
 153                 break;
 154         }
 155
 156         return ret;
 157 }
 158
 159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
 160 {
 161         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 162         switch (radeon_encoder->encoder_id) {
 163         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 164         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 165         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 166         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 167         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 168         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 169         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 170         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 171         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 172         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 173         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 174                 return true;
 175         default:
 176                 return false;
 177         }
 178 }
 179
 180 void
 181 radeon_link_encoder_connector(struct drm_device *dev)
 182 {
 183         struct drm_connector *connector;
 184         struct radeon_connector *radeon_connector;
 185         struct drm_encoder *encoder;
 186         struct radeon_encoder *radeon_encoder;
 187
 188         /* walk the list and link encoders to connectors */
 189         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 190                 radeon_connector = to_radeon_connector(connector);
 191                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 192                         radeon_encoder = to_radeon_encoder(encoder);
 193                         if (radeon_encoder->devices & radeon_connector->devices)
 194                                 drm_mode_connector_attach_encoder(connector, encoder);
 195                 }
 196         }
 197 }
 198
 199 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
 200 {
 201         struct drm_device *dev = encoder->dev;
 202         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 203         struct drm_connector *connector;
 204
 205         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 206                 if (connector->encoder == encoder) {
 207                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 208                         radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
 209                         DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
 210                                   radeon_encoder->active_device, radeon_encoder->devices,
 211                                   radeon_connector->devices, encoder->encoder_type);
 212                 }
 213         }
 214 }
 215
 216 struct drm_connector *
 217 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
 218 {
 219         struct drm_device *dev = encoder->dev;
 220         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 221         struct drm_connector *connector;
 222         struct radeon_connector *radeon_connector;
 223
 224         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 225                 radeon_connector = to_radeon_connector(connector);
 226                 if (radeon_encoder->active_device & radeon_connector->devices)
 227                         return connector;
 228         }
 229         return NULL;
 230 }
 231
 232 struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder)
 233 {
 234         struct drm_device *dev = encoder->dev;
 235         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 236         struct drm_encoder *other_encoder;
 237         struct radeon_encoder *other_radeon_encoder;
 238
 239         if (radeon_encoder->is_ext_encoder)
 240                 return NULL;
 241
 242         list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
 243                 if (other_encoder == encoder)
 244                         continue;
 245                 other_radeon_encoder = to_radeon_encoder(other_encoder);
 246                 if (other_radeon_encoder->is_ext_encoder &&
 247                     (radeon_encoder->devices & other_radeon_encoder->devices))
 248                         return other_encoder;
 249         }
 250         return NULL;
 251 }
 252
 253 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
 254                              struct drm_display_mode *adjusted_mode)
 255 {
 256         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 257         struct drm_device *dev = encoder->dev;
 258         struct radeon_device *rdev = dev->dev_private;
 259         struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 260         unsigned hblank = native_mode->htotal - native_mode->hdisplay;
 261         unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
 262         unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
 263         unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
 264         unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
 265         unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
 266
 267         adjusted_mode->clock = native_mode->clock;
 268         adjusted_mode->flags = native_mode->flags;
 269
 270         if (ASIC_IS_AVIVO(rdev)) {
 271                 adjusted_mode->hdisplay = native_mode->hdisplay;
 272                 adjusted_mode->vdisplay = native_mode->vdisplay;
 273         }
 274
 275         adjusted_mode->htotal = native_mode->hdisplay + hblank;
 276         adjusted_mode->hsync_start = native_mode->hdisplay + hover;
 277         adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
 278
 279         adjusted_mode->vtotal = native_mode->vdisplay + vblank;
 280         adjusted_mode->vsync_start = native_mode->vdisplay + vover;
 281         adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
 282
 283         drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
 284
 285         if (ASIC_IS_AVIVO(rdev)) {
 286                 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
 287                 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
 288         }
 289
 290         adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
 291         adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
 292         adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
 293
 294         adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
 295         adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
 296         adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
 297
 298 }
 299
 300 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 301                                    struct drm_display_mode *mode,
 302                                    struct drm_display_mode *adjusted_mode)
 303 {
 304         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 305         struct drm_device *dev = encoder->dev;
 306         struct radeon_device *rdev = dev->dev_private;
 307
 308         /* set the active encoder to connector routing */
 309         radeon_encoder_set_active_device(encoder);
 310         drm_mode_set_crtcinfo(adjusted_mode, 0);
 311
 312         /* hw bug */
 313         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 314             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 315                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 316
 317         /* get the native mode for LVDS */
 318         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
 319                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 320
 321         /* get the native mode for TV */
 322         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 323                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 324                 if (tv_dac) {
 325                         if (tv_dac->tv_std == TV_STD_NTSC ||
 326                             tv_dac->tv_std == TV_STD_NTSC_J ||
 327                             tv_dac->tv_std == TV_STD_PAL_M)
 328                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 329                         else
 330                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 331                 }
 332         }
 333
 334         if (ASIC_IS_DCE3(rdev) &&
 335             (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
 336                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 337                 radeon_dp_set_link_config(connector, mode);
 338         }
 339
 340         return true;
 341 }
 342
 343 static void
 344 atombios_dac_setup(struct drm_encoder *encoder, int action)
 345 {
 346         struct drm_device *dev = encoder->dev;
 347         struct radeon_device *rdev = dev->dev_private;
 348         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 349         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 350         int index = 0;
 351         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 352
 353         memset(&args, 0, sizeof(args));
 354
 355         switch (radeon_encoder->encoder_id) {
 356         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 357         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 358                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 359                 break;
 360         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 361         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 362                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 363                 break;
 364         }
 365
 366         args.ucAction = action;
 367
 368         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 369                 args.ucDacStandard = ATOM_DAC1_PS2;
 370         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 371                 args.ucDacStandard = ATOM_DAC1_CV;
 372         else {
 373                 switch (dac_info->tv_std) {
 374                 case TV_STD_PAL:
 375                 case TV_STD_PAL_M:
 376                 case TV_STD_SCART_PAL:
 377                 case TV_STD_SECAM:
 378                 case TV_STD_PAL_CN:
 379                         args.ucDacStandard = ATOM_DAC1_PAL;
 380                         break;
 381                 case TV_STD_NTSC:
 382                 case TV_STD_NTSC_J:
 383                 case TV_STD_PAL_60:
 384                 default:
 385                         args.ucDacStandard = ATOM_DAC1_NTSC;
 386                         break;
 387                 }
 388         }
 389         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 390
 391         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 392
 393 }
 394
 395 static void
 396 atombios_tv_setup(struct drm_encoder *encoder, int action)
 397 {
 398         struct drm_device *dev = encoder->dev;
 399         struct radeon_device *rdev = dev->dev_private;
 400         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 401         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 402         int index = 0;
 403         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 404
 405         memset(&args, 0, sizeof(args));
 406
 407         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 408
 409         args.sTVEncoder.ucAction = action;
 410
 411         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 412                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 413         else {
 414                 switch (dac_info->tv_std) {
 415                 case TV_STD_NTSC:
 416                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 417                         break;
 418                 case TV_STD_PAL:
 419                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 420                         break;
 421                 case TV_STD_PAL_M:
 422                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 423                         break;
 424                 case TV_STD_PAL_60:
 425                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 426                         break;
 427                 case TV_STD_NTSC_J:
 428                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 429                         break;
 430                 case TV_STD_SCART_PAL:
 431                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 432                         break;
 433                 case TV_STD_SECAM:
 434                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 435                         break;
 436                 case TV_STD_PAL_CN:
 437                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 438                         break;
 439                 default:
 440                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 441                         break;
 442                 }
 443         }
 444
 445         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 446
 447         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 448
 449 }
 450
 451 union dvo_encoder_control {
 452         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 453         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 454         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 455 };
 456
 457 void
 458 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 459 {
 460         struct drm_device *dev = encoder->dev;
 461         struct radeon_device *rdev = dev->dev_private;
 462         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 463         union dvo_encoder_control args;
 464         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 465
 466         memset(&args, 0, sizeof(args));
 467
 468         if (ASIC_IS_DCE3(rdev)) {
 469                 /* DCE3+ */
 470                 args.dvo_v3.ucAction = action;
 471                 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 472                 args.dvo_v3.ucDVOConfig = 0; /* XXX */
 473         } else if (ASIC_IS_DCE2(rdev)) {
 474                 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
 475                 args.dvo.sDVOEncoder.ucAction = action;
 476                 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 477                 /* DFP1, CRT1, TV1 depending on the type of port */
 478                 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 479
 480                 if (radeon_encoder->pixel_clock > 165000)
 481                         args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 482         } else {
 483                 /* R4xx, R5xx */
 484                 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 485
 486                 if (radeon_encoder->pixel_clock > 165000)
 487                         args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 488
 489                 /*if (pScrn->rgbBits == 8)*/
 490                 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 491         }
 492
 493         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 494 }
 495
 496 union lvds_encoder_control {
 497         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 498         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 499 };
 500
 501 void
 502 atombios_digital_setup(struct drm_encoder *encoder, int action)
 503 {
 504         struct drm_device *dev = encoder->dev;
 505         struct radeon_device *rdev = dev->dev_private;
 506         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 507         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 508         union lvds_encoder_control args;
 509         int index = 0;
 510         int hdmi_detected = 0;
 511         uint8_t frev, crev;
 512
 513         if (!dig)
 514                 return;
 515
 516         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 517                 hdmi_detected = 1;
 518
 519         memset(&args, 0, sizeof(args));
 520
 521         switch (radeon_encoder->encoder_id) {
 522         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 523                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 524                 break;
 525         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 526         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 527                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 528                 break;
 529         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 530                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 531                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 532                 else
 533                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 534                 break;
 535         }
 536
 537         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 538                 return;
 539
 540         switch (frev) {
 541         case 1:
 542         case 2:
 543                 switch (crev) {
 544                 case 1:
 545                         args.v1.ucMisc = 0;
 546                         args.v1.ucAction = action;
 547                         if (hdmi_detected)
 548                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 549                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 550                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 551                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 552                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 553                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 554                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 555                         } else {
 556                                 if (dig->linkb)
 557                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 558                                 if (radeon_encoder->pixel_clock > 165000)
 559                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 560                                 /*if (pScrn->rgbBits == 8) */
 561                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 562                         }
 563                         break;
 564                 case 2:
 565                 case 3:
 566                         args.v2.ucMisc = 0;
 567                         args.v2.ucAction = action;
 568                         if (crev == 3) {
 569                                 if (dig->coherent_mode)
 570                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 571                         }
 572                         if (hdmi_detected)
 573                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 574                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 575                         args.v2.ucTruncate = 0;
 576                         args.v2.ucSpatial = 0;
 577                         args.v2.ucTemporal = 0;
 578                         args.v2.ucFRC = 0;
 579                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 580                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 581                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 582                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 583                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 584                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 585                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 586                                 }
 587                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 588                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 589                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 590                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 591                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 592                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 593                                 }
 594                         } else {
 595                                 if (dig->linkb)
 596                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 597                                 if (radeon_encoder->pixel_clock > 165000)
 598                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 599                         }
 600                         break;
 601                 default:
 602                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 603                         break;
 604                 }
 605                 break;
 606         default:
 607                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 608                 break;
 609         }
 610
 611         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 612 }
 613
 614 int
 615 atombios_get_encoder_mode(struct drm_encoder *encoder)
 616 {
 617         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 618         struct drm_device *dev = encoder->dev;
 619         struct radeon_device *rdev = dev->dev_private;
 620         struct drm_connector *connector;
 621         struct radeon_connector *radeon_connector;
 622         struct radeon_connector_atom_dig *dig_connector;
 623
 624         connector = radeon_get_connector_for_encoder(encoder);
 625         if (!connector) {
 626                 switch (radeon_encoder->encoder_id) {
 627                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 628                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 629                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 630                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 631                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 632                         return ATOM_ENCODER_MODE_DVI;
 633                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 634                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 635                 default:
 636                         return ATOM_ENCODER_MODE_CRT;
 637                 }
 638         }
 639         radeon_connector = to_radeon_connector(connector);
 640
 641         switch (connector->connector_type) {
 642         case DRM_MODE_CONNECTOR_DVII:
 643         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 644                 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
 645                         /* fix me */
 646                         if (ASIC_IS_DCE4(rdev))
 647                                 return ATOM_ENCODER_MODE_DVI;
 648                         else
 649                                 return ATOM_ENCODER_MODE_HDMI;
 650                 } else if (radeon_connector->use_digital)
 651                         return ATOM_ENCODER_MODE_DVI;
 652                 else
 653                         return ATOM_ENCODER_MODE_CRT;
 654                 break;
 655         case DRM_MODE_CONNECTOR_DVID:
 656         case DRM_MODE_CONNECTOR_HDMIA:
 657         default:
 658                 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
 659                         /* fix me */
 660                         if (ASIC_IS_DCE4(rdev))
 661                                 return ATOM_ENCODER_MODE_DVI;
 662                         else
 663                                 return ATOM_ENCODER_MODE_HDMI;
 664                 } else
 665                         return ATOM_ENCODER_MODE_DVI;
 666                 break;
 667         case DRM_MODE_CONNECTOR_LVDS:
 668                 return ATOM_ENCODER_MODE_LVDS;
 669                 break;
 670         case DRM_MODE_CONNECTOR_DisplayPort:
 671                 dig_connector = radeon_connector->con_priv;
 672                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 673                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 674                         return ATOM_ENCODER_MODE_DP;
 675                 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
 676                         /* fix me */
 677                         if (ASIC_IS_DCE4(rdev))
 678                                 return ATOM_ENCODER_MODE_DVI;
 679                         else
 680                                 return ATOM_ENCODER_MODE_HDMI;
 681                 } else
 682                         return ATOM_ENCODER_MODE_DVI;
 683                 break;
 684         case DRM_MODE_CONNECTOR_eDP:
 685                 return ATOM_ENCODER_MODE_DP;
 686         case DRM_MODE_CONNECTOR_DVIA:
 687         case DRM_MODE_CONNECTOR_VGA:
 688                 return ATOM_ENCODER_MODE_CRT;
 689                 break;
 690         case DRM_MODE_CONNECTOR_Composite:
 691         case DRM_MODE_CONNECTOR_SVIDEO:
 692         case DRM_MODE_CONNECTOR_9PinDIN:
 693                 /* fix me */
 694                 return ATOM_ENCODER_MODE_TV;
 695                 /*return ATOM_ENCODER_MODE_CV;*/
 696                 break;
 697         }
 698 }
 699
 700 /*
 701  * DIG Encoder/Transmitter Setup
 702  *
 703  * DCE 3.0/3.1
 704  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 705  * Supports up to 3 digital outputs
 706  * - 2 DIG encoder blocks.
 707  * DIG1 can drive UNIPHY link A or link B
 708  * DIG2 can drive UNIPHY link B or LVTMA
 709  *
 710  * DCE 3.2
 711  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 712  * Supports up to 5 digital outputs
 713  * - 2 DIG encoder blocks.
 714  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 715  *
 716  * DCE 4.0/5.0
 717  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 718  * Supports up to 6 digital outputs
 719  * - 6 DIG encoder blocks.
 720  * - DIG to PHY mapping is hardcoded
 721  * DIG1 drives UNIPHY0 link A, A+B
 722  * DIG2 drives UNIPHY0 link B
 723  * DIG3 drives UNIPHY1 link A, A+B
 724  * DIG4 drives UNIPHY1 link B
 725  * DIG5 drives UNIPHY2 link A, A+B
 726  * DIG6 drives UNIPHY2 link B
 727  *
 728  * DCE 4.1
 729  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 730  * Supports up to 6 digital outputs
 731  * - 2 DIG encoder blocks.
 732  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 733  *
 734  * Routing
 735  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 736  * Examples:
 737  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 738  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 739  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 740  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 741  */
 742
 743 union dig_encoder_control {
 744         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 745         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 746         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 747         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 748 };
 749
 750 void
 751 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 752 {
 753         struct drm_device *dev = encoder->dev;
 754         struct radeon_device *rdev = dev->dev_private;
 755         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 756         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 757         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 758         union dig_encoder_control args;
 759         int index = 0;
 760         uint8_t frev, crev;
 761         int dp_clock = 0;
 762         int dp_lane_count = 0;
 763         int hpd_id = RADEON_HPD_NONE;
 764         int bpc = 8;
 765
 766         if (connector) {
 767                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 768                 struct radeon_connector_atom_dig *dig_connector =
 769                         radeon_connector->con_priv;
 770
 771                 dp_clock = dig_connector->dp_clock;
 772                 dp_lane_count = dig_connector->dp_lane_count;
 773                 hpd_id = radeon_connector->hpd.hpd;
 774                 bpc = connector->display_info.bpc;
 775         }
 776
 777         /* no dig encoder assigned */
 778         if (dig->dig_encoder == -1)
 779                 return;
 780
 781         memset(&args, 0, sizeof(args));
 782
 783         if (ASIC_IS_DCE4(rdev))
 784                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 785         else {
 786                 if (dig->dig_encoder)
 787                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 788                 else
 789                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 790         }
 791
 792         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 793                 return;
 794
 795         args.v1.ucAction = action;
 796         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 797         args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 798
 799         if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
 800             (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST))
 801                 args.v1.ucLaneNum = dp_lane_count;
 802         else if (radeon_encoder->pixel_clock > 165000)
 803                 args.v1.ucLaneNum = 8;
 804         else
 805                 args.v1.ucLaneNum = 4;
 806
 807         if (ASIC_IS_DCE5(rdev)) {
 808                 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
 809                     (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) {
 810                         if (dp_clock == 270000)
 811                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 812                         else if (dp_clock == 540000)
 813                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 814                 }
 815                 args.v4.acConfig.ucDigSel = dig->dig_encoder;
 816                 switch (bpc) {
 817                 case 0:
 818                         args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
 819                         break;
 820                 case 6:
 821                         args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
 822                         break;
 823                 case 8:
 824                 default:
 825                         args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 826                         break;
 827                 case 10:
 828                         args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
 829                         break;
 830                 case 12:
 831                         args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
 832                         break;
 833                 case 16:
 834                         args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
 835                         break;
 836                 }
 837                 if (hpd_id == RADEON_HPD_NONE)
 838                         args.v4.ucHPD_ID = 0;
 839                 else
 840                         args.v4.ucHPD_ID = hpd_id + 1;
 841         } else if (ASIC_IS_DCE4(rdev)) {
 842                 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
 843                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 844                 args.v3.acConfig.ucDigSel = dig->dig_encoder;
 845                 switch (bpc) {
 846                 case 0:
 847                         args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
 848                         break;
 849                 case 6:
 850                         args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
 851                         break;
 852                 case 8:
 853                 default:
 854                         args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 855                         break;
 856                 case 10:
 857                         args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
 858                         break;
 859                 case 12:
 860                         args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
 861                         break;
 862                 case 16:
 863                         args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
 864                         break;
 865                 }
 866         } else {
 867                 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
 868                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 869                 switch (radeon_encoder->encoder_id) {
 870                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 871                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 872                         break;
 873                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 874                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 875                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 876                         break;
 877                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 878                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 879                         break;
 880                 }
 881                 if (dig->linkb)
 882                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 883                 else
 884                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 885         }
 886
 887         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 888
 889 }
 890
 891 union dig_transmitter_control {
 892         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 893         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 894         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 895         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
 896 };
 897
 898 void
 899 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 900 {
 901         struct drm_device *dev = encoder->dev;
 902         struct radeon_device *rdev = dev->dev_private;
 903         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 904         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 905         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 906         union dig_transmitter_control args;
 907         int index = 0;
 908         uint8_t frev, crev;
 909         bool is_dp = false;
 910         int pll_id = 0;
 911         int dp_clock = 0;
 912         int dp_lane_count = 0;
 913         int connector_object_id = 0;
 914         int igp_lane_info = 0;
 915
 916         if (connector) {
 917                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 918                 struct radeon_connector_atom_dig *dig_connector =
 919                         radeon_connector->con_priv;
 920
 921                 dp_clock = dig_connector->dp_clock;
 922                 dp_lane_count = dig_connector->dp_lane_count;
 923                 connector_object_id =
 924                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 925                 igp_lane_info = dig_connector->igp_lane_info;
 926         }
 927
 928         /* no dig encoder assigned */
 929         if (dig->dig_encoder == -1)
 930                 return;
 931
 932         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
 933                 is_dp = true;
 934
 935         memset(&args, 0, sizeof(args));
 936
 937         switch (radeon_encoder->encoder_id) {
 938         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 939                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
 940                 break;
 941         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 942         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 943         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 944                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 945                 break;
 946         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 947                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
 948                 break;
 949         }
 950
 951         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 952                 return;
 953
 954         args.v1.ucAction = action;
 955         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 956                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
 957         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 958                 args.v1.asMode.ucLaneSel = lane_num;
 959                 args.v1.asMode.ucLaneSet = lane_set;
 960         } else {
 961                 if (is_dp)
 962                         args.v1.usPixelClock =
 963                                 cpu_to_le16(dp_clock / 10);
 964                 else if (radeon_encoder->pixel_clock > 165000)
 965                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 966                 else
 967                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 968         }
 969         if (ASIC_IS_DCE4(rdev)) {
 970                 if (is_dp)
 971                         args.v3.ucLaneNum = dp_lane_count;
 972                 else if (radeon_encoder->pixel_clock > 165000)
 973                         args.v3.ucLaneNum = 8;
 974                 else
 975                         args.v3.ucLaneNum = 4;
 976
 977                 if (dig->linkb)
 978                         args.v3.acConfig.ucLinkSel = 1;
 979                 if (dig->dig_encoder & 1)
 980                         args.v3.acConfig.ucEncoderSel = 1;
 981
 982                 /* Select the PLL for the PHY
 983                  * DP PHY should be clocked from external src if there is
 984                  * one.
 985                  */
 986                 if (encoder->crtc) {
 987                         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 988                         pll_id = radeon_crtc->pll_id;
 989                 }
 990
 991                 if (ASIC_IS_DCE5(rdev)) {
 992                         /* On DCE5 DCPLL usually generates the DP ref clock */
 993                         if (is_dp) {
 994                                 if (rdev->clock.dp_extclk)
 995                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
 996                                 else
 997                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
 998                         } else
 999                                 args.v4.acConfig.ucRefClkSource = pll_id;
1000                 } else {
1001                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
1002                         if (is_dp && rdev->clock.dp_extclk)
1003                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1004                         else
1005                                 args.v3.acConfig.ucRefClkSource = pll_id;
1006                 }
1007
1008                 switch (radeon_encoder->encoder_id) {
1009                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1010                         args.v3.acConfig.ucTransmitterSel = 0;
1011                         break;
1012                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1013                         args.v3.acConfig.ucTransmitterSel = 1;
1014                         break;
1015                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1016                         args.v3.acConfig.ucTransmitterSel = 2;
1017                         break;
1018                 }
1019
1020                 if (is_dp)
1021                         args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1022                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1023                         if (dig->coherent_mode)
1024                                 args.v3.acConfig.fCoherentMode = 1;
1025                         if (radeon_encoder->pixel_clock > 165000)
1026                                 args.v3.acConfig.fDualLinkConnector = 1;
1027                 }
1028         } else if (ASIC_IS_DCE32(rdev)) {
1029                 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
1030                 if (dig->linkb)
1031                         args.v2.acConfig.ucLinkSel = 1;
1032
1033                 switch (radeon_encoder->encoder_id) {
1034                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1035                         args.v2.acConfig.ucTransmitterSel = 0;
1036                         break;
1037                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1038                         args.v2.acConfig.ucTransmitterSel = 1;
1039                         break;
1040                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1041                         args.v2.acConfig.ucTransmitterSel = 2;
1042                         break;
1043                 }
1044
1045                 if (is_dp)
1046                         args.v2.acConfig.fCoherentMode = 1;
1047                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1048                         if (dig->coherent_mode)
1049                                 args.v2.acConfig.fCoherentMode = 1;
1050                         if (radeon_encoder->pixel_clock > 165000)
1051                                 args.v2.acConfig.fDualLinkConnector = 1;
1052                 }
1053         } else {
1054                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1055
1056                 if (dig->dig_encoder)
1057                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1058                 else
1059                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1060
1061                 if ((rdev->flags & RADEON_IS_IGP) &&
1062                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1063                         if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
1064                                 if (igp_lane_info & 0x1)
1065                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1066                                 else if (igp_lane_info & 0x2)
1067                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1068                                 else if (igp_lane_info & 0x4)
1069                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1070                                 else if (igp_lane_info & 0x8)
1071                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1072                         } else {
1073                                 if (igp_lane_info & 0x3)
1074                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1075                                 else if (igp_lane_info & 0xc)
1076                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1077                         }
1078                 }
1079
1080                 if (dig->linkb)
1081                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1082                 else
1083                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1084
1085                 if (is_dp)
1086                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1087                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1088                         if (dig->coherent_mode)
1089                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1090                         if (radeon_encoder->pixel_clock > 165000)
1091                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1092                 }
1093         }
1094
1095         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1096 }
1097
1098 void
1099 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1100 {
1101         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1102         struct drm_device *dev = radeon_connector->base.dev;
1103         struct radeon_device *rdev = dev->dev_private;
1104         union dig_transmitter_control args;
1105         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1106         uint8_t frev, crev;
1107
1108         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1109                 return;
1110
1111         if (!ASIC_IS_DCE4(rdev))
1112                 return;
1113
1114         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1115             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1116                 return;
1117
1118         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1119                 return;
1120
1121         memset(&args, 0, sizeof(args));
1122
1123         args.v1.ucAction = action;
1124
1125         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1126 }
1127
1128 union external_encoder_control {
1129         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1130         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1131 };
1132
1133 static void
1134 atombios_external_encoder_setup(struct drm_encoder *encoder,
1135                                 struct drm_encoder *ext_encoder,
1136                                 int action)
1137 {
1138         struct drm_device *dev = encoder->dev;
1139         struct radeon_device *rdev = dev->dev_private;
1140         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1141         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1142         union external_encoder_control args;
1143         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1144         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1145         u8 frev, crev;
1146         int dp_clock = 0;
1147         int dp_lane_count = 0;
1148         int connector_object_id = 0;
1149         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1150         int bpc = 8;
1151
1152         if (connector) {
1153                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1154                 struct radeon_connector_atom_dig *dig_connector =
1155                         radeon_connector->con_priv;
1156
1157                 dp_clock = dig_connector->dp_clock;
1158                 dp_lane_count = dig_connector->dp_lane_count;
1159                 connector_object_id =
1160                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1161                 bpc = connector->display_info.bpc;
1162         }
1163
1164         memset(&args, 0, sizeof(args));
1165
1166         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1167                 return;
1168
1169         switch (frev) {
1170         case 1:
1171                 /* no params on frev 1 */
1172                 break;
1173         case 2:
1174                 switch (crev) {
1175                 case 1:
1176                 case 2:
1177                         args.v1.sDigEncoder.ucAction = action;
1178                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1179                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1180
1181                         if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1182                                 if (dp_clock == 270000)
1183                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1184                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1185                         } else if (radeon_encoder->pixel_clock > 165000)
1186                                 args.v1.sDigEncoder.ucLaneNum = 8;
1187                         else
1188                                 args.v1.sDigEncoder.ucLaneNum = 4;
1189                         break;
1190                 case 3:
1191                         args.v3.sExtEncoder.ucAction = action;
1192                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1193                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1194                         else
1195                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1196                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1197
1198                         if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1199                                 if (dp_clock == 270000)
1200                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1201                                 else if (dp_clock == 540000)
1202                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1203                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1204                         } else if (radeon_encoder->pixel_clock > 165000)
1205                                 args.v3.sExtEncoder.ucLaneNum = 8;
1206                         else
1207                                 args.v3.sExtEncoder.ucLaneNum = 4;
1208                         switch (ext_enum) {
1209                         case GRAPH_OBJECT_ENUM_ID1:
1210                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1211                                 break;
1212                         case GRAPH_OBJECT_ENUM_ID2:
1213                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1214                                 break;
1215                         case GRAPH_OBJECT_ENUM_ID3:
1216                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1217                                 break;
1218                         }
1219                         switch (bpc) {
1220                         case 0:
1221                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1222                                 break;
1223                         case 6:
1224                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1225                                 break;
1226                         case 8:
1227                         default:
1228                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1229                                 break;
1230                         case 10:
1231                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1232                                 break;
1233                         case 12:
1234                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1235                                 break;
1236                         case 16:
1237                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1238                                 break;
1239                         }
1240                         break;
1241                 default:
1242                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1243                         return;
1244                 }
1245                 break;
1246         default:
1247                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1248                 return;
1249         }
1250         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1251 }
1252
1253 static void
1254 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1255 {
1256         struct drm_device *dev = encoder->dev;
1257         struct radeon_device *rdev = dev->dev_private;
1258         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1259         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1260         ENABLE_YUV_PS_ALLOCATION args;
1261         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1262         uint32_t temp, reg;
1263
1264         memset(&args, 0, sizeof(args));
1265
1266         if (rdev->family >= CHIP_R600)
1267                 reg = R600_BIOS_3_SCRATCH;
1268         else
1269                 reg = RADEON_BIOS_3_SCRATCH;
1270
1271         /* XXX: fix up scratch reg handling */
1272         temp = RREG32(reg);
1273         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1274                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1275                              (radeon_crtc->crtc_id << 18)));
1276         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1277                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1278         else
1279                 WREG32(reg, 0);
1280
1281         if (enable)
1282                 args.ucEnable = ATOM_ENABLE;
1283         args.ucCRTC = radeon_crtc->crtc_id;
1284
1285         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1286
1287         WREG32(reg, temp);
1288 }
1289
1290 static void
1291 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1292 {
1293         struct drm_device *dev = encoder->dev;
1294         struct radeon_device *rdev = dev->dev_private;
1295         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1296         struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1297         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1298         int index = 0;
1299         bool is_dig = false;
1300         bool is_dce5_dac = false;
1301         bool is_dce5_dvo = false;
1302
1303         memset(&args, 0, sizeof(args));
1304
1305         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1306                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1307                   radeon_encoder->active_device);
1308         switch (radeon_encoder->encoder_id) {
1309         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1310         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1311                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1312                 break;
1313         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1314         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1315         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1316         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1317                 is_dig = true;
1318                 break;
1319         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1320         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1321                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1322                 break;
1323         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1324                 if (ASIC_IS_DCE5(rdev))
1325                         is_dce5_dvo = true;
1326                 else if (ASIC_IS_DCE3(rdev))
1327                         is_dig = true;
1328                 else
1329                         index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1330                 break;
1331         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1332                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1333                 break;
1334         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1335                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1336                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1337                 else
1338                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1339                 break;
1340         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1341         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1342                 if (ASIC_IS_DCE5(rdev))
1343                         is_dce5_dac = true;
1344                 else {
1345                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1346                                 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1347                         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1348                                 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1349                         else
1350                                 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1351                 }
1352                 break;
1353         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1354         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1355                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1356                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1357                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1358                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1359                 else
1360                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1361                 break;
1362         }
1363
1364         if (is_dig) {
1365                 switch (mode) {
1366                 case DRM_MODE_DPMS_ON:
1367                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1368                         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1369                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1370
1371                                 if (connector &&
1372                                     (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1373                                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1374                                         struct radeon_connector_atom_dig *radeon_dig_connector =
1375                                                 radeon_connector->con_priv;
1376                                         atombios_set_edp_panel_power(connector,
1377                                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
1378                                         radeon_dig_connector->edp_on = true;
1379                                 }
1380                                 dp_link_train(encoder, connector);
1381                                 if (ASIC_IS_DCE4(rdev))
1382                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
1383                         }
1384                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1385                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1386                         break;
1387                 case DRM_MODE_DPMS_STANDBY:
1388                 case DRM_MODE_DPMS_SUSPEND:
1389                 case DRM_MODE_DPMS_OFF:
1390                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1391                         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1392                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1393
1394                                 if (ASIC_IS_DCE4(rdev))
1395                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1396                                 if (connector &&
1397                                     (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1398                                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1399                                         struct radeon_connector_atom_dig *radeon_dig_connector =
1400                                                 radeon_connector->con_priv;
1401                                         atombios_set_edp_panel_power(connector,
1402                                                                      ATOM_TRANSMITTER_ACTION_POWER_OFF);
1403                                         radeon_dig_connector->edp_on = false;
1404                                 }
1405                         }
1406                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1407                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1408                         break;
1409                 }
1410         } else if (is_dce5_dac) {
1411                 switch (mode) {
1412                 case DRM_MODE_DPMS_ON:
1413                         atombios_dac_setup(encoder, ATOM_ENABLE);
1414                         break;
1415                 case DRM_MODE_DPMS_STANDBY:
1416                 case DRM_MODE_DPMS_SUSPEND:
1417                 case DRM_MODE_DPMS_OFF:
1418                         atombios_dac_setup(encoder, ATOM_DISABLE);
1419                         break;
1420                 }
1421         } else if (is_dce5_dvo) {
1422                 switch (mode) {
1423                 case DRM_MODE_DPMS_ON:
1424                         atombios_dvo_setup(encoder, ATOM_ENABLE);
1425                         break;
1426                 case DRM_MODE_DPMS_STANDBY:
1427                 case DRM_MODE_DPMS_SUSPEND:
1428                 case DRM_MODE_DPMS_OFF:
1429                         atombios_dvo_setup(encoder, ATOM_DISABLE);
1430                         break;
1431                 }
1432         } else {
1433                 switch (mode) {
1434                 case DRM_MODE_DPMS_ON:
1435                         args.ucAction = ATOM_ENABLE;
1436                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1437                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1438                                 args.ucAction = ATOM_LCD_BLON;
1439                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1440                         }
1441                         break;
1442                 case DRM_MODE_DPMS_STANDBY:
1443                 case DRM_MODE_DPMS_SUSPEND:
1444                 case DRM_MODE_DPMS_OFF:
1445                         args.ucAction = ATOM_DISABLE;
1446                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1447                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1448                                 args.ucAction = ATOM_LCD_BLOFF;
1449                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1450                         }
1451                         break;
1452                 }
1453         }
1454
1455         if (ext_encoder) {
1456                 int action;
1457
1458                 switch (mode) {
1459                 case DRM_MODE_DPMS_ON:
1460                 default:
1461                         if (ASIC_IS_DCE41(rdev))
1462                                 action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT;
1463                         else
1464                                 action = ATOM_ENABLE;
1465                         break;
1466                 case DRM_MODE_DPMS_STANDBY:
1467                 case DRM_MODE_DPMS_SUSPEND:
1468                 case DRM_MODE_DPMS_OFF:
1469                         if (ASIC_IS_DCE41(rdev))
1470                                 action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT;
1471                         else
1472                                 action = ATOM_DISABLE;
1473                         break;
1474                 }
1475                 atombios_external_encoder_setup(encoder, ext_encoder, action);
1476         }
1477
1478         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1479
1480 }
1481
1482 union crtc_source_param {
1483         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1484         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1485 };
1486
1487 static void
1488 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1489 {
1490         struct drm_device *dev = encoder->dev;
1491         struct radeon_device *rdev = dev->dev_private;
1492         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1493         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1494         union crtc_source_param args;
1495         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1496         uint8_t frev, crev;
1497         struct radeon_encoder_atom_dig *dig;
1498
1499         memset(&args, 0, sizeof(args));
1500
1501         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1502                 return;
1503
1504         switch (frev) {
1505         case 1:
1506                 switch (crev) {
1507                 case 1:
1508                 default:
1509                         if (ASIC_IS_AVIVO(rdev))
1510                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1511                         else {
1512                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1513                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1514                                 } else {
1515                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1516                                 }
1517                         }
1518                         switch (radeon_encoder->encoder_id) {
1519                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1520                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1521                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1522                                 break;
1523                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1524                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1525                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1526                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1527                                 else
1528                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1529                                 break;
1530                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1531                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1532                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1533                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1534                                 break;
1535                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1536                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1537                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1538                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1539                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1540                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1541                                 else
1542                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1543                                 break;
1544                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1545                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1546                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1547                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1548                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1549                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1550                                 else
1551                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1552                                 break;
1553                         }
1554                         break;
1555                 case 2:
1556                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1557                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1558                         switch (radeon_encoder->encoder_id) {
1559                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1560                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1561                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1562                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1563                                 dig = radeon_encoder->enc_priv;
1564                                 switch (dig->dig_encoder) {
1565                                 case 0:
1566                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1567                                         break;
1568                                 case 1:
1569                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1570                                         break;
1571                                 case 2:
1572                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1573                                         break;
1574                                 case 3:
1575                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1576                                         break;
1577                                 case 4:
1578                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1579                                         break;
1580                                 case 5:
1581                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1582                                         break;
1583                                 }
1584                                 break;
1585                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1586                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1587                                 break;
1588                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1589                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1590                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1591                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1592                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1593                                 else
1594                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1595                                 break;
1596                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1597                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1598                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1599                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1600                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1601                                 else
1602                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1603                                 break;
1604                         }
1605                         break;
1606                 }
1607                 break;
1608         default:
1609                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1610                 return;
1611         }
1612
1613         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1614
1615         /* update scratch regs with new routing */
1616         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1617 }
1618
1619 static void
1620 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1621                               struct drm_display_mode *mode)
1622 {
1623         struct drm_device *dev = encoder->dev;
1624         struct radeon_device *rdev = dev->dev_private;
1625         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1626         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1627
1628         /* Funky macbooks */
1629         if ((dev->pdev->device == 0x71C5) &&
1630             (dev->pdev->subsystem_vendor == 0x106b) &&
1631             (dev->pdev->subsystem_device == 0x0080)) {
1632                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1633                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1634
1635                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1636                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1637
1638                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1639                 }
1640         }
1641
1642         /* set scaler clears this on some chips */
1643         if (ASIC_IS_AVIVO(rdev) &&
1644             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1645                 if (ASIC_IS_DCE4(rdev)) {
1646                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1647                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1648                                        EVERGREEN_INTERLEAVE_EN);
1649                         else
1650                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1651                 } else {
1652                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1653                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1654                                        AVIVO_D1MODE_INTERLEAVE_EN);
1655                         else
1656                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1657                 }
1658         }
1659 }
1660
1661 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1662 {
1663         struct drm_device *dev = encoder->dev;
1664         struct radeon_device *rdev = dev->dev_private;
1665         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1666         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1667         struct drm_encoder *test_encoder;
1668         struct radeon_encoder_atom_dig *dig;
1669         uint32_t dig_enc_in_use = 0;
1670
1671         /* DCE4/5 */
1672         if (ASIC_IS_DCE4(rdev)) {
1673                 dig = radeon_encoder->enc_priv;
1674                 if (ASIC_IS_DCE41(rdev))
1675                         return radeon_crtc->crtc_id;
1676                 else {
1677                         switch (radeon_encoder->encoder_id) {
1678                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1679                                 if (dig->linkb)
1680                                         return 1;
1681                                 else
1682                                         return 0;
1683                                 break;
1684                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1685                                 if (dig->linkb)
1686                                         return 3;
1687                                 else
1688                                         return 2;
1689                                 break;
1690                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1691                                 if (dig->linkb)
1692                                         return 5;
1693                                 else
1694                                         return 4;
1695                                 break;
1696                         }
1697                 }
1698         }
1699
1700         /* on DCE32 and encoder can driver any block so just crtc id */
1701         if (ASIC_IS_DCE32(rdev)) {
1702                 return radeon_crtc->crtc_id;
1703         }
1704
1705         /* on DCE3 - LVTMA can only be driven by DIGB */
1706         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1707                 struct radeon_encoder *radeon_test_encoder;
1708
1709                 if (encoder == test_encoder)
1710                         continue;
1711
1712                 if (!radeon_encoder_is_digital(test_encoder))
1713                         continue;
1714
1715                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1716                 dig = radeon_test_encoder->enc_priv;
1717
1718                 if (dig->dig_encoder >= 0)
1719                         dig_enc_in_use |= (1 << dig->dig_encoder);
1720         }
1721
1722         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1723                 if (dig_enc_in_use & 0x2)
1724                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1725                 return 1;
1726         }
1727         if (!(dig_enc_in_use & 1))
1728                 return 0;
1729         return 1;
1730 }
1731
1732 static void
1733 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1734                              struct drm_display_mode *mode,
1735                              struct drm_display_mode *adjusted_mode)
1736 {
1737         struct drm_device *dev = encoder->dev;
1738         struct radeon_device *rdev = dev->dev_private;
1739         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1740         struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1741
1742         radeon_encoder->pixel_clock = adjusted_mode->clock;
1743
1744         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1745                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1746                         atombios_yuv_setup(encoder, true);
1747                 else
1748                         atombios_yuv_setup(encoder, false);
1749         }
1750
1751         switch (radeon_encoder->encoder_id) {
1752         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1753         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1754         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1755         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1756                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1757                 break;
1758         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1759         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1760         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1761         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1762                 if (ASIC_IS_DCE4(rdev)) {
1763                         /* disable the transmitter */
1764                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1765                         /* setup and enable the encoder */
1766                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1767
1768                         /* init and enable the transmitter */
1769                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1770                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1771                 } else {
1772                         /* disable the encoder and transmitter */
1773                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1774                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1775
1776                         /* setup and enable the encoder and transmitter */
1777                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1778                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1779                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1780                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1781                 }
1782                 break;
1783         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1784         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1785         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1786                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1787                 break;
1788         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1789         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1790         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1791         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1792                 atombios_dac_setup(encoder, ATOM_ENABLE);
1793                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1794                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1795                                 atombios_tv_setup(encoder, ATOM_ENABLE);
1796                         else
1797                                 atombios_tv_setup(encoder, ATOM_DISABLE);
1798                 }
1799                 break;
1800         }
1801
1802         if (ext_encoder) {
1803                 if (ASIC_IS_DCE41(rdev)) {
1804                         atombios_external_encoder_setup(encoder, ext_encoder,
1805                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1806                         atombios_external_encoder_setup(encoder, ext_encoder,
1807                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1808                 } else
1809                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1810         }
1811
1812         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1813
1814         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1815                 r600_hdmi_enable(encoder);
1816                 r600_hdmi_setmode(encoder, adjusted_mode);
1817         }
1818 }
1819
1820 static bool
1821 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1822 {
1823         struct drm_device *dev = encoder->dev;
1824         struct radeon_device *rdev = dev->dev_private;
1825         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1826         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1827
1828         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1829                                        ATOM_DEVICE_CV_SUPPORT |
1830                                        ATOM_DEVICE_CRT_SUPPORT)) {
1831                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1832                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1833                 uint8_t frev, crev;
1834
1835                 memset(&args, 0, sizeof(args));
1836
1837                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1838                         return false;
1839
1840                 args.sDacload.ucMisc = 0;
1841
1842                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1843                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1844                         args.sDacload.ucDacType = ATOM_DAC_A;
1845                 else
1846                         args.sDacload.ucDacType = ATOM_DAC_B;
1847
1848                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1849                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1850                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1851                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1852                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1853                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1854                         if (crev >= 3)
1855                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1856                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1857                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1858                         if (crev >= 3)
1859                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1860                 }
1861
1862                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1863
1864                 return true;
1865         } else
1866                 return false;
1867 }
1868
1869 static enum drm_connector_status
1870 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1871 {
1872         struct drm_device *dev = encoder->dev;
1873         struct radeon_device *rdev = dev->dev_private;
1874         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1875         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1876         uint32_t bios_0_scratch;
1877
1878         if (!atombios_dac_load_detect(encoder, connector)) {
1879                 DRM_DEBUG_KMS("detect returned false \n");
1880                 return connector_status_unknown;
1881         }
1882
1883         if (rdev->family >= CHIP_R600)
1884                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1885         else
1886                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1887
1888         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1889         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1890                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1891                         return connector_status_connected;
1892         }
1893         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1894                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1895                         return connector_status_connected;
1896         }
1897         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1898                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1899                         return connector_status_connected;
1900         }
1901         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1902                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1903                         return connector_status_connected; /* CTV */
1904                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1905                         return connector_status_connected; /* STV */
1906         }
1907         return connector_status_disconnected;
1908 }
1909
1910 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1911 {
1912         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1913         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1914
1915         if (radeon_encoder->active_device &
1916             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1917                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1918                 if (dig)
1919                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1920         }
1921
1922         radeon_atom_output_lock(encoder, true);
1923         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1924
1925         /* select the clock/data port if it uses a router */
1926         if (connector) {
1927                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1928                 if (radeon_connector->router.cd_valid)
1929                         radeon_router_select_cd_port(radeon_connector);
1930         }
1931
1932         /* this is needed for the pll/ss setup to work correctly in some cases */
1933         atombios_set_encoder_crtc_source(encoder);
1934 }
1935
1936 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1937 {
1938         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1939         radeon_atom_output_lock(encoder, false);
1940 }
1941
1942 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1943 {
1944         struct drm_device *dev = encoder->dev;
1945         struct radeon_device *rdev = dev->dev_private;
1946         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1947         struct radeon_encoder_atom_dig *dig;
1948
1949         /* check for pre-DCE3 cards with shared encoders;
1950          * can't really use the links individually, so don't disable
1951          * the encoder if it's in use by another connector
1952          */
1953         if (!ASIC_IS_DCE3(rdev)) {
1954                 struct drm_encoder *other_encoder;
1955                 struct radeon_encoder *other_radeon_encoder;
1956
1957                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
1958                         other_radeon_encoder = to_radeon_encoder(other_encoder);
1959                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
1960                             drm_helper_encoder_in_use(other_encoder))
1961                                 goto disable_done;
1962                 }
1963         }
1964
1965         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1966
1967         switch (radeon_encoder->encoder_id) {
1968         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1969         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1970         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1971         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1972                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
1973                 break;
1974         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1975         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1976         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1977         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1978                 if (ASIC_IS_DCE4(rdev))
1979                         /* disable the transmitter */
1980                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1981                 else {
1982                         /* disable the encoder and transmitter */
1983                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1984                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1985                 }
1986                 break;
1987         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1988         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1989         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1990                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1991                 break;
1992         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1993         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1994         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1995         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1996                 atombios_dac_setup(encoder, ATOM_DISABLE);
1997                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1998                         atombios_tv_setup(encoder, ATOM_DISABLE);
1999                 break;
2000         }
2001
2002 disable_done:
2003         if (radeon_encoder_is_digital(encoder)) {
2004                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2005                         r600_hdmi_disable(encoder);
2006                 dig = radeon_encoder->enc_priv;
2007                 dig->dig_encoder = -1;
2008         }
2009         radeon_encoder->active_device = 0;
2010 }
2011
2012 /* these are handled by the primary encoders */
2013 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2014 {
2015
2016 }
2017
2018 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2019 {
2020
2021 }
2022
2023 static void
2024 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2025                          struct drm_display_mode *mode,
2026                          struct drm_display_mode *adjusted_mode)
2027 {
2028
2029 }
2030
2031 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2032 {
2033
2034 }
2035
2036 static void
2037 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2038 {
2039
2040 }
2041
2042 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2043                                        struct drm_display_mode *mode,
2044                                        struct drm_display_mode *adjusted_mode)
2045 {
2046         return true;
2047 }
2048
2049 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2050         .dpms = radeon_atom_ext_dpms,
2051         .mode_fixup = radeon_atom_ext_mode_fixup,
2052         .prepare = radeon_atom_ext_prepare,
2053         .mode_set = radeon_atom_ext_mode_set,
2054         .commit = radeon_atom_ext_commit,
2055         .disable = radeon_atom_ext_disable,
2056         /* no detect for TMDS/LVDS yet */
2057 };
2058
2059 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2060         .dpms = radeon_atom_encoder_dpms,
2061         .mode_fixup = radeon_atom_mode_fixup,
2062         .prepare = radeon_atom_encoder_prepare,
2063         .mode_set = radeon_atom_encoder_mode_set,
2064         .commit = radeon_atom_encoder_commit,
2065         .disable = radeon_atom_encoder_disable,
2066         /* no detect for TMDS/LVDS yet */
2067 };
2068
2069 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2070         .dpms = radeon_atom_encoder_dpms,
2071         .mode_fixup = radeon_atom_mode_fixup,
2072         .prepare = radeon_atom_encoder_prepare,
2073         .mode_set = radeon_atom_encoder_mode_set,
2074         .commit = radeon_atom_encoder_commit,
2075         .detect = radeon_atom_dac_detect,
2076 };
2077
2078 void radeon_enc_destroy(struct drm_encoder *encoder)
2079 {
2080         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2081         kfree(radeon_encoder->enc_priv);
2082         drm_encoder_cleanup(encoder);
2083         kfree(radeon_encoder);
2084 }
2085
2086 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2087         .destroy = radeon_enc_destroy,
2088 };
2089
2090 struct radeon_encoder_atom_dac *
2091 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2092 {
2093         struct drm_device *dev = radeon_encoder->base.dev;
2094         struct radeon_device *rdev = dev->dev_private;
2095         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2096
2097         if (!dac)
2098                 return NULL;
2099
2100         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2101         return dac;
2102 }
2103
2104 struct radeon_encoder_atom_dig *
2105 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2106 {
2107         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2108         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2109
2110         if (!dig)
2111                 return NULL;
2112
2113         /* coherent mode by default */
2114         dig->coherent_mode = true;
2115         dig->dig_encoder = -1;
2116
2117         if (encoder_enum == 2)
2118                 dig->linkb = true;
2119         else
2120                 dig->linkb = false;
2121
2122         return dig;
2123 }
2124
2125 void
2126 radeon_add_atom_encoder(struct drm_device *dev,
2127                         uint32_t encoder_enum,
2128                         uint32_t supported_device,
2129                         u16 caps)
2130 {
2131         struct radeon_device *rdev = dev->dev_private;
2132         struct drm_encoder *encoder;
2133         struct radeon_encoder *radeon_encoder;
2134
2135         /* see if we already added it */
2136         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2137                 radeon_encoder = to_radeon_encoder(encoder);
2138                 if (radeon_encoder->encoder_enum == encoder_enum) {
2139                         radeon_encoder->devices |= supported_device;
2140                         return;
2141                 }
2142
2143         }
2144
2145         /* add a new one */
2146         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2147         if (!radeon_encoder)
2148                 return;
2149
2150         encoder = &radeon_encoder->base;
2151         switch (rdev->num_crtc) {
2152         case 1:
2153                 encoder->possible_crtcs = 0x1;
2154                 break;
2155         case 2:
2156         default:
2157                 encoder->possible_crtcs = 0x3;
2158                 break;
2159         case 6:
2160                 encoder->possible_crtcs = 0x3f;
2161                 break;
2162         }
2163
2164         radeon_encoder->enc_priv = NULL;
2165
2166         radeon_encoder->encoder_enum = encoder_enum;
2167         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2168         radeon_encoder->devices = supported_device;
2169         radeon_encoder->rmx_type = RMX_OFF;
2170         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2171         radeon_encoder->is_ext_encoder = false;
2172         radeon_encoder->caps = caps;
2173
2174         switch (radeon_encoder->encoder_id) {
2175         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2176         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2177         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2178         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2179                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2180                         radeon_encoder->rmx_type = RMX_FULL;
2181                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2182                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2183                 } else {
2184                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2185                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2186                 }
2187                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2188                 break;
2189         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2190                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2191                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2192                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2193                 break;
2194         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2195         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2196         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2197                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2198                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2199                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2200                 break;
2201         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2202         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2203         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2204         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2205         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2206         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2207         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2208                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2209                         radeon_encoder->rmx_type = RMX_FULL;
2210                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2211                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2212                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2213                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2214                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2215                 } else {
2216                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2217                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2218                 }
2219                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2220                 break;
2221         case ENCODER_OBJECT_ID_SI170B:
2222         case ENCODER_OBJECT_ID_CH7303:
2223         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2224         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2225         case ENCODER_OBJECT_ID_TITFP513:
2226         case ENCODER_OBJECT_ID_VT1623:
2227         case ENCODER_OBJECT_ID_HDMI_SI1930:
2228         case ENCODER_OBJECT_ID_TRAVIS:
2229         case ENCODER_OBJECT_ID_NUTMEG:
2230                 /* these are handled by the primary encoders */
2231                 radeon_encoder->is_ext_encoder = true;
2232                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2233                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2234                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2235                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2236                 else
2237                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2238                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2239                 break;
2240         }
2241 }