drivers/gpu/drm/radeon/radeon_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
  39 {
  40         struct drm_device *dev = encoder->dev;
  41         struct radeon_device *rdev = dev->dev_private;
  42         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  43         struct drm_encoder *clone_encoder;
  44         uint32_t index_mask = 0;
  45         int count;
  46
  47         /* DIG routing gets problematic */
  48         if (rdev->family >= CHIP_R600)
  49                 return index_mask;
  50         /* LVDS/TV are too wacky */
  51         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
  52                 return index_mask;
  53         /* DVO requires 2x ppll clocks depending on tmds chip */
  54         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
  55                 return index_mask;
  56
  57         count = -1;
  58         list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
  59                 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
  60                 count++;
  61
  62                 if (clone_encoder == encoder)
  63                         continue;
  64                 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
  65                         continue;
  66                 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
  67                         continue;
  68                 else
  69                         index_mask |= (1 << count);
  70         }
  71         return index_mask;
  72 }
  73
  74 void radeon_setup_encoder_clones(struct drm_device *dev)
  75 {
  76         struct drm_encoder *encoder;
  77
  78         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  79                 encoder->possible_clones = radeon_encoder_clones(encoder);
  80         }
  81 }
  82
  83 uint32_t
  84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
  85 {
  86         struct radeon_device *rdev = dev->dev_private;
  87         uint32_t ret = 0;
  88
  89         switch (supported_device) {
  90         case ATOM_DEVICE_CRT1_SUPPORT:
  91         case ATOM_DEVICE_TV1_SUPPORT:
  92         case ATOM_DEVICE_TV2_SUPPORT:
  93         case ATOM_DEVICE_CRT2_SUPPORT:
  94         case ATOM_DEVICE_CV_SUPPORT:
  95                 switch (dac) {
  96                 case 1: /* dac a */
  97                         if ((rdev->family == CHIP_RS300) ||
  98                             (rdev->family == CHIP_RS400) ||
  99                             (rdev->family == CHIP_RS480))
 100                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 101                         else if (ASIC_IS_AVIVO(rdev))
 102                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
 103                         else
 104                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
 105                         break;
 106                 case 2: /* dac b */
 107                         if (ASIC_IS_AVIVO(rdev))
 108                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
 109                         else {
 110                                 /*if (rdev->family == CHIP_R200)
 111                                   ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 112                                   else*/
 113                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 114                         }
 115                         break;
 116                 case 3: /* external dac */
 117                         if (ASIC_IS_AVIVO(rdev))
 118                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 119                         else
 120                                 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 121                         break;
 122                 }
 123                 break;
 124         case ATOM_DEVICE_LCD1_SUPPORT:
 125                 if (ASIC_IS_AVIVO(rdev))
 126                         ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 127                 else
 128                         ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
 129                 break;
 130         case ATOM_DEVICE_DFP1_SUPPORT:
 131                 if ((rdev->family == CHIP_RS300) ||
 132                     (rdev->family == CHIP_RS400) ||
 133                     (rdev->family == CHIP_RS480))
 134                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 135                 else if (ASIC_IS_AVIVO(rdev))
 136                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
 137                 else
 138                         ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
 139                 break;
 140         case ATOM_DEVICE_LCD2_SUPPORT:
 141         case ATOM_DEVICE_DFP2_SUPPORT:
 142                 if ((rdev->family == CHIP_RS600) ||
 143                     (rdev->family == CHIP_RS690) ||
 144                     (rdev->family == CHIP_RS740))
 145                         ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
 146                 else if (ASIC_IS_AVIVO(rdev))
 147                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 148                 else
 149                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 150                 break;
 151         case ATOM_DEVICE_DFP3_SUPPORT:
 152                 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 153                 break;
 154         }
 155
 156         return ret;
 157 }
 158
 159 void
 160 radeon_link_encoder_connector(struct drm_device *dev)
 161 {
 162         struct drm_connector *connector;
 163         struct radeon_connector *radeon_connector;
 164         struct drm_encoder *encoder;
 165         struct radeon_encoder *radeon_encoder;
 166
 167         /* walk the list and link encoders to connectors */
 168         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 169                 radeon_connector = to_radeon_connector(connector);
 170                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 171                         radeon_encoder = to_radeon_encoder(encoder);
 172                         if (radeon_encoder->devices & radeon_connector->devices)
 173                                 drm_mode_connector_attach_encoder(connector, encoder);
 174                 }
 175         }
 176 }
 177
 178 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
 179 {
 180         struct drm_device *dev = encoder->dev;
 181         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 182         struct drm_connector *connector;
 183
 184         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 185                 if (connector->encoder == encoder) {
 186                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 187                         radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
 188                         DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
 189                                   radeon_encoder->active_device, radeon_encoder->devices,
 190                                   radeon_connector->devices, encoder->encoder_type);
 191                 }
 192         }
 193 }
 194
 195 static struct drm_connector *
 196 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
 197 {
 198         struct drm_device *dev = encoder->dev;
 199         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 200         struct drm_connector *connector;
 201         struct radeon_connector *radeon_connector;
 202
 203         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 204                 radeon_connector = to_radeon_connector(connector);
 205                 if (radeon_encoder->devices & radeon_connector->devices)
 206                         return connector;
 207         }
 208         return NULL;
 209 }
 210
 211 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 212                                    struct drm_display_mode *mode,
 213                                    struct drm_display_mode *adjusted_mode)
 214 {
 215         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 216         struct drm_device *dev = encoder->dev;
 217         struct radeon_device *rdev = dev->dev_private;
 218
 219         /* set the active encoder to connector routing */
 220         radeon_encoder_set_active_device(encoder);
 221         drm_mode_set_crtcinfo(adjusted_mode, 0);
 222
 223         /* hw bug */
 224         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 225             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 226                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 227
 228         /* get the native mode for LVDS */
 229         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 230                 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 231                 int mode_id = adjusted_mode->base.id;
 232                 *adjusted_mode = *native_mode;
 233                 if (!ASIC_IS_AVIVO(rdev)) {
 234                         adjusted_mode->hdisplay = mode->hdisplay;
 235                         adjusted_mode->vdisplay = mode->vdisplay;
 236                 }
 237                 adjusted_mode->base.id = mode_id;
 238         }
 239
 240         /* get the native mode for TV */
 241         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 242                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 243                 if (tv_dac) {
 244                         if (tv_dac->tv_std == TV_STD_NTSC ||
 245                             tv_dac->tv_std == TV_STD_NTSC_J ||
 246                             tv_dac->tv_std == TV_STD_PAL_M)
 247                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 248                         else
 249                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 250                 }
 251         }
 252
 253         if (ASIC_IS_DCE3(rdev) &&
 254             (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT))) {
 255                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 256                 radeon_dp_set_link_config(connector, mode);
 257         }
 258
 259         return true;
 260 }
 261
 262 static void
 263 atombios_dac_setup(struct drm_encoder *encoder, int action)
 264 {
 265         struct drm_device *dev = encoder->dev;
 266         struct radeon_device *rdev = dev->dev_private;
 267         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 268         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 269         int index = 0, num = 0;
 270         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 271         enum radeon_tv_std tv_std = TV_STD_NTSC;
 272
 273         if (dac_info->tv_std)
 274                 tv_std = dac_info->tv_std;
 275
 276         memset(&args, 0, sizeof(args));
 277
 278         switch (radeon_encoder->encoder_id) {
 279         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 280         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 281                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 282                 num = 1;
 283                 break;
 284         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 285         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 286                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 287                 num = 2;
 288                 break;
 289         }
 290
 291         args.ucAction = action;
 292
 293         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 294                 args.ucDacStandard = ATOM_DAC1_PS2;
 295         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 296                 args.ucDacStandard = ATOM_DAC1_CV;
 297         else {
 298                 switch (tv_std) {
 299                 case TV_STD_PAL:
 300                 case TV_STD_PAL_M:
 301                 case TV_STD_SCART_PAL:
 302                 case TV_STD_SECAM:
 303                 case TV_STD_PAL_CN:
 304                         args.ucDacStandard = ATOM_DAC1_PAL;
 305                         break;
 306                 case TV_STD_NTSC:
 307                 case TV_STD_NTSC_J:
 308                 case TV_STD_PAL_60:
 309                 default:
 310                         args.ucDacStandard = ATOM_DAC1_NTSC;
 311                         break;
 312                 }
 313         }
 314         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 315
 316         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 317
 318 }
 319
 320 static void
 321 atombios_tv_setup(struct drm_encoder *encoder, int action)
 322 {
 323         struct drm_device *dev = encoder->dev;
 324         struct radeon_device *rdev = dev->dev_private;
 325         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 326         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 327         int index = 0;
 328         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 329         enum radeon_tv_std tv_std = TV_STD_NTSC;
 330
 331         if (dac_info->tv_std)
 332                 tv_std = dac_info->tv_std;
 333
 334         memset(&args, 0, sizeof(args));
 335
 336         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 337
 338         args.sTVEncoder.ucAction = action;
 339
 340         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 341                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 342         else {
 343                 switch (tv_std) {
 344                 case TV_STD_NTSC:
 345                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 346                         break;
 347                 case TV_STD_PAL:
 348                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 349                         break;
 350                 case TV_STD_PAL_M:
 351                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 352                         break;
 353                 case TV_STD_PAL_60:
 354                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 355                         break;
 356                 case TV_STD_NTSC_J:
 357                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 358                         break;
 359                 case TV_STD_SCART_PAL:
 360                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 361                         break;
 362                 case TV_STD_SECAM:
 363                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 364                         break;
 365                 case TV_STD_PAL_CN:
 366                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 367                         break;
 368                 default:
 369                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 370                         break;
 371                 }
 372         }
 373
 374         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 375
 376         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 377
 378 }
 379
 380 void
 381 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
 382 {
 383         struct drm_device *dev = encoder->dev;
 384         struct radeon_device *rdev = dev->dev_private;
 385         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 386         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
 387         int index = 0;
 388
 389         memset(&args, 0, sizeof(args));
 390
 391         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 392
 393         args.sXTmdsEncoder.ucEnable = action;
 394
 395         if (radeon_encoder->pixel_clock > 165000)
 396                 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
 397
 398         /*if (pScrn->rgbBits == 8)*/
 399         args.sXTmdsEncoder.ucMisc |= (1 << 1);
 400
 401         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 402
 403 }
 404
 405 static void
 406 atombios_ddia_setup(struct drm_encoder *encoder, int action)
 407 {
 408         struct drm_device *dev = encoder->dev;
 409         struct radeon_device *rdev = dev->dev_private;
 410         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 411         DVO_ENCODER_CONTROL_PS_ALLOCATION args;
 412         int index = 0;
 413
 414         memset(&args, 0, sizeof(args));
 415
 416         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 417
 418         args.sDVOEncoder.ucAction = action;
 419         args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 420
 421         if (radeon_encoder->pixel_clock > 165000)
 422                 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
 423
 424         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 425
 426 }
 427
 428 union lvds_encoder_control {
 429         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 430         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 431 };
 432
 433 void
 434 atombios_digital_setup(struct drm_encoder *encoder, int action)
 435 {
 436         struct drm_device *dev = encoder->dev;
 437         struct radeon_device *rdev = dev->dev_private;
 438         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 439         union lvds_encoder_control args;
 440         int index = 0;
 441         int hdmi_detected = 0;
 442         uint8_t frev, crev;
 443         struct radeon_encoder_atom_dig *dig;
 444         struct drm_connector *connector;
 445         struct radeon_connector *radeon_connector;
 446         struct radeon_connector_atom_dig *dig_connector;
 447
 448         connector = radeon_get_connector_for_encoder(encoder);
 449         if (!connector)
 450                 return;
 451
 452         radeon_connector = to_radeon_connector(connector);
 453
 454         if (!radeon_encoder->enc_priv)
 455                 return;
 456
 457         dig = radeon_encoder->enc_priv;
 458
 459         if (!radeon_connector->con_priv)
 460                 return;
 461
 462         if (drm_detect_hdmi_monitor(radeon_connector->edid))
 463                 hdmi_detected = 1;
 464
 465         dig_connector = radeon_connector->con_priv;
 466
 467         memset(&args, 0, sizeof(args));
 468
 469         switch (radeon_encoder->encoder_id) {
 470         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 471                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 472                 break;
 473         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 474         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 475                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 476                 break;
 477         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 478                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 479                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 480                 else
 481                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 482                 break;
 483         }
 484
 485         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 486
 487         switch (frev) {
 488         case 1:
 489         case 2:
 490                 switch (crev) {
 491                 case 1:
 492                         args.v1.ucMisc = 0;
 493                         args.v1.ucAction = action;
 494                         if (hdmi_detected)
 495                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 496                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 497                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 498                                 if (dig->lvds_misc & (1 << 0))
 499                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 500                                 if (dig->lvds_misc & (1 << 1))
 501                                         args.v1.ucMisc |= (1 << 1);
 502                         } else {
 503                                 if (dig_connector->linkb)
 504                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 505                                 if (radeon_encoder->pixel_clock > 165000)
 506                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 507                                 /*if (pScrn->rgbBits == 8) */
 508                                 args.v1.ucMisc |= (1 << 1);
 509                         }
 510                         break;
 511                 case 2:
 512                 case 3:
 513                         args.v2.ucMisc = 0;
 514                         args.v2.ucAction = action;
 515                         if (crev == 3) {
 516                                 if (dig->coherent_mode)
 517                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 518                         }
 519                         if (hdmi_detected)
 520                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 521                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 522                         args.v2.ucTruncate = 0;
 523                         args.v2.ucSpatial = 0;
 524                         args.v2.ucTemporal = 0;
 525                         args.v2.ucFRC = 0;
 526                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 527                                 if (dig->lvds_misc & (1 << 0))
 528                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 529                                 if (dig->lvds_misc & (1 << 5)) {
 530                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 531                                         if (dig->lvds_misc & (1 << 1))
 532                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 533                                 }
 534                                 if (dig->lvds_misc & (1 << 6)) {
 535                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 536                                         if (dig->lvds_misc & (1 << 1))
 537                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 538                                         if (((dig->lvds_misc >> 2) & 0x3) == 2)
 539                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 540                                 }
 541                         } else {
 542                                 if (dig_connector->linkb)
 543                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 544                                 if (radeon_encoder->pixel_clock > 165000)
 545                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 546                         }
 547                         break;
 548                 default:
 549                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 550                         break;
 551                 }
 552                 break;
 553         default:
 554                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 555                 break;
 556         }
 557
 558         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 559         r600_hdmi_enable(encoder, hdmi_detected);
 560 }
 561
 562 int
 563 atombios_get_encoder_mode(struct drm_encoder *encoder)
 564 {
 565         struct drm_connector *connector;
 566         struct radeon_connector *radeon_connector;
 567         struct radeon_connector_atom_dig *radeon_dig_connector;
 568
 569         connector = radeon_get_connector_for_encoder(encoder);
 570         if (!connector)
 571                 return 0;
 572
 573         radeon_connector = to_radeon_connector(connector);
 574
 575         switch (connector->connector_type) {
 576         case DRM_MODE_CONNECTOR_DVII:
 577         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 578                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 579                         return ATOM_ENCODER_MODE_HDMI;
 580                 else if (radeon_connector->use_digital)
 581                         return ATOM_ENCODER_MODE_DVI;
 582                 else
 583                         return ATOM_ENCODER_MODE_CRT;
 584                 break;
 585         case DRM_MODE_CONNECTOR_DVID:
 586         case DRM_MODE_CONNECTOR_HDMIA:
 587         default:
 588                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 589                         return ATOM_ENCODER_MODE_HDMI;
 590                 else
 591                         return ATOM_ENCODER_MODE_DVI;
 592                 break;
 593         case DRM_MODE_CONNECTOR_LVDS:
 594                 return ATOM_ENCODER_MODE_LVDS;
 595                 break;
 596         case DRM_MODE_CONNECTOR_DisplayPort:
 597                 radeon_dig_connector = radeon_connector->con_priv;
 598                 if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
 599                         return ATOM_ENCODER_MODE_DP;
 600                 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
 601                         return ATOM_ENCODER_MODE_HDMI;
 602                 else
 603                         return ATOM_ENCODER_MODE_DVI;
 604                 break;
 605         case CONNECTOR_DVI_A:
 606         case CONNECTOR_VGA:
 607                 return ATOM_ENCODER_MODE_CRT;
 608                 break;
 609         case CONNECTOR_STV:
 610         case CONNECTOR_CTV:
 611         case CONNECTOR_DIN:
 612                 /* fix me */
 613                 return ATOM_ENCODER_MODE_TV;
 614                 /*return ATOM_ENCODER_MODE_CV;*/
 615                 break;
 616         }
 617 }
 618
 619 /*
 620  * DIG Encoder/Transmitter Setup
 621  *
 622  * DCE 3.0/3.1
 623  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 624  * Supports up to 3 digital outputs
 625  * - 2 DIG encoder blocks.
 626  * DIG1 can drive UNIPHY link A or link B
 627  * DIG2 can drive UNIPHY link B or LVTMA
 628  *
 629  * DCE 3.2
 630  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 631  * Supports up to 5 digital outputs
 632  * - 2 DIG encoder blocks.
 633  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 634  *
 635  * Routing
 636  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 637  * Examples:
 638  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 639  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 640  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 641  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 642  */
 643 static void
 644 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 645 {
 646         struct drm_device *dev = encoder->dev;
 647         struct radeon_device *rdev = dev->dev_private;
 648         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 649         DIG_ENCODER_CONTROL_PS_ALLOCATION args;
 650         int index = 0, num = 0;
 651         uint8_t frev, crev;
 652         struct radeon_encoder_atom_dig *dig;
 653         struct drm_connector *connector;
 654         struct radeon_connector *radeon_connector;
 655         struct radeon_connector_atom_dig *dig_connector;
 656
 657         connector = radeon_get_connector_for_encoder(encoder);
 658         if (!connector)
 659                 return;
 660
 661         radeon_connector = to_radeon_connector(connector);
 662
 663         if (!radeon_connector->con_priv)
 664                 return;
 665
 666         dig_connector = radeon_connector->con_priv;
 667
 668         if (!radeon_encoder->enc_priv)
 669                 return;
 670
 671         dig = radeon_encoder->enc_priv;
 672
 673         memset(&args, 0, sizeof(args));
 674
 675         if (ASIC_IS_DCE32(rdev)) {
 676                 if (dig->dig_block)
 677                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 678                 else
 679                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 680                 num = dig->dig_block + 1;
 681         } else {
 682                 switch (radeon_encoder->encoder_id) {
 683                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 684                         /* XXX doesn't really matter which dig encoder we pick as long as it's
 685                          * not already in use
 686                          */
 687                         if (dig_connector->linkb)
 688                                 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 689                         else
 690                                 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 691                         num = 1;
 692                         break;
 693                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 694                         /* Only dig2 encoder can drive LVTMA */
 695                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 696                         num = 2;
 697                         break;
 698                 }
 699         }
 700
 701         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 702
 703         args.ucAction = action;
 704         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 705
 706         if (ASIC_IS_DCE32(rdev)) {
 707                 switch (radeon_encoder->encoder_id) {
 708                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 709                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 710                         break;
 711                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 712                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 713                         break;
 714                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 715                         args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 716                         break;
 717                 }
 718         } else {
 719                 switch (radeon_encoder->encoder_id) {
 720                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 721                         args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
 722                         break;
 723                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 724                         args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2;
 725                         break;
 726                 }
 727         }
 728
 729         args.ucEncoderMode = atombios_get_encoder_mode(encoder);
 730
 731         if (args.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
 732                 if (dig_connector->dp_clock == 270000)
 733                         args.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 734                 args.ucLaneNum = dig_connector->dp_lane_count;
 735         } else if (radeon_encoder->pixel_clock > 165000)
 736                 args.ucLaneNum = 8;
 737         else
 738                 args.ucLaneNum = 4;
 739
 740         if (dig_connector->linkb)
 741                 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 742         else
 743                 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 744
 745         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 746
 747 }
 748
 749 union dig_transmitter_control {
 750         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 751         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 752 };
 753
 754 void
 755 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 756 {
 757         struct drm_device *dev = encoder->dev;
 758         struct radeon_device *rdev = dev->dev_private;
 759         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 760         union dig_transmitter_control args;
 761         int index = 0, num = 0;
 762         uint8_t frev, crev;
 763         struct radeon_encoder_atom_dig *dig;
 764         struct drm_connector *connector;
 765         struct radeon_connector *radeon_connector;
 766         struct radeon_connector_atom_dig *dig_connector;
 767         bool is_dp = false;
 768
 769         connector = radeon_get_connector_for_encoder(encoder);
 770         if (!connector)
 771                 return;
 772
 773         radeon_connector = to_radeon_connector(connector);
 774
 775         if (!radeon_encoder->enc_priv)
 776                 return;
 777
 778         dig = radeon_encoder->enc_priv;
 779
 780         if (!radeon_connector->con_priv)
 781                 return;
 782
 783         dig_connector = radeon_connector->con_priv;
 784
 785         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
 786                 is_dp = true;
 787
 788         memset(&args, 0, sizeof(args));
 789
 790         if (ASIC_IS_DCE32(rdev))
 791                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 792         else {
 793                 switch (radeon_encoder->encoder_id) {
 794                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 795                         index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
 796                         break;
 797                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 798                         index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
 799                         break;
 800                 }
 801         }
 802
 803         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 804
 805         args.v1.ucAction = action;
 806         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 807                 args.v1.usInitInfo = radeon_connector->connector_object_id;
 808         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 809                 args.v1.asMode.ucLaneSel = lane_num;
 810                 args.v1.asMode.ucLaneSet = lane_set;
 811         } else {
 812                 if (is_dp)
 813                         args.v1.usPixelClock =
 814                                 cpu_to_le16(dig_connector->dp_clock / 10);
 815                 else if (radeon_encoder->pixel_clock > 165000)
 816                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 817                 else
 818                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 819         }
 820         if (ASIC_IS_DCE32(rdev)) {
 821                 if (dig->dig_block)
 822                         args.v2.acConfig.ucEncoderSel = 1;
 823                 if (dig_connector->linkb)
 824                         args.v2.acConfig.ucLinkSel = 1;
 825
 826                 switch (radeon_encoder->encoder_id) {
 827                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 828                         args.v2.acConfig.ucTransmitterSel = 0;
 829                         num = 0;
 830                         break;
 831                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 832                         args.v2.acConfig.ucTransmitterSel = 1;
 833                         num = 1;
 834                         break;
 835                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 836                         args.v2.acConfig.ucTransmitterSel = 2;
 837                         num = 2;
 838                         break;
 839                 }
 840
 841                 if (is_dp)
 842                         args.v2.acConfig.fCoherentMode = 1;
 843                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 844                         if (dig->coherent_mode)
 845                                 args.v2.acConfig.fCoherentMode = 1;
 846                 }
 847         } else {
 848                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 849
 850                 switch (radeon_encoder->encoder_id) {
 851                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 852                         /* XXX doesn't really matter which dig encoder we pick as long as it's
 853                          * not already in use
 854                          */
 855                         if (dig_connector->linkb)
 856                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 857                         else
 858                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 859                         if (rdev->flags & RADEON_IS_IGP) {
 860                                 if (radeon_encoder->pixel_clock > 165000) {
 861                                         if (dig_connector->igp_lane_info & 0x3)
 862                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 863                                         else if (dig_connector->igp_lane_info & 0xc)
 864                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
 865                                 } else {
 866                                         if (dig_connector->igp_lane_info & 0x1)
 867                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 868                                         else if (dig_connector->igp_lane_info & 0x2)
 869                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 870                                         else if (dig_connector->igp_lane_info & 0x4)
 871                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 872                                         else if (dig_connector->igp_lane_info & 0x8)
 873                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 874                                 }
 875                         }
 876                         break;
 877                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 878                         /* Only dig2 encoder can drive LVTMA */
 879                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 880                         break;
 881                 }
 882
 883                 if (radeon_encoder->pixel_clock > 165000)
 884                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
 885
 886                 if (dig_connector->linkb)
 887                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
 888                 else
 889                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
 890
 891                 if (is_dp)
 892                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 893                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 894                         if (dig->coherent_mode)
 895                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 896                 }
 897         }
 898
 899         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 900 }
 901
 902 static void
 903 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
 904 {
 905         struct drm_device *dev = encoder->dev;
 906         struct radeon_device *rdev = dev->dev_private;
 907         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 908         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 909         ENABLE_YUV_PS_ALLOCATION args;
 910         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
 911         uint32_t temp, reg;
 912
 913         memset(&args, 0, sizeof(args));
 914
 915         if (rdev->family >= CHIP_R600)
 916                 reg = R600_BIOS_3_SCRATCH;
 917         else
 918                 reg = RADEON_BIOS_3_SCRATCH;
 919
 920         /* XXX: fix up scratch reg handling */
 921         temp = RREG32(reg);
 922         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 923                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
 924                              (radeon_crtc->crtc_id << 18)));
 925         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 926                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
 927         else
 928                 WREG32(reg, 0);
 929
 930         if (enable)
 931                 args.ucEnable = ATOM_ENABLE;
 932         args.ucCRTC = radeon_crtc->crtc_id;
 933
 934         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 935
 936         WREG32(reg, temp);
 937 }
 938
 939 static void
 940 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
 941 {
 942         struct drm_device *dev = encoder->dev;
 943         struct radeon_device *rdev = dev->dev_private;
 944         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 945         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
 946         int index = 0;
 947         bool is_dig = false;
 948
 949         memset(&args, 0, sizeof(args));
 950
 951         DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
 952                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
 953                   radeon_encoder->active_device);
 954         switch (radeon_encoder->encoder_id) {
 955         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 956         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 957                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
 958                 break;
 959         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 960         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 961         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 962         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 963                 is_dig = true;
 964                 break;
 965         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 966         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 967         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 968                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
 969                 break;
 970         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 971                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 972                 break;
 973         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 974                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 975                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 976                 else
 977                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
 978                 break;
 979         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 980         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 981                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 982                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
 983                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 984                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
 985                 else
 986                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
 987                 break;
 988         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 989         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 990                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 991                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
 992                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 993                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
 994                 else
 995                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
 996                 break;
 997         }
 998
 999         if (is_dig) {
1000                 switch (mode) {
1001                 case DRM_MODE_DPMS_ON:
1002                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1003                         {
1004                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1005                                 dp_link_train(encoder, connector);
1006                         }
1007                         break;
1008                 case DRM_MODE_DPMS_STANDBY:
1009                 case DRM_MODE_DPMS_SUSPEND:
1010                 case DRM_MODE_DPMS_OFF:
1011                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1012                         break;
1013                 }
1014         } else {
1015                 switch (mode) {
1016                 case DRM_MODE_DPMS_ON:
1017                         args.ucAction = ATOM_ENABLE;
1018                         break;
1019                 case DRM_MODE_DPMS_STANDBY:
1020                 case DRM_MODE_DPMS_SUSPEND:
1021                 case DRM_MODE_DPMS_OFF:
1022                         args.ucAction = ATOM_DISABLE;
1023                         break;
1024                 }
1025                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1026         }
1027         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1028 }
1029
1030 union crtc_sourc_param {
1031         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1032         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1033 };
1034
1035 static void
1036 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1037 {
1038         struct drm_device *dev = encoder->dev;
1039         struct radeon_device *rdev = dev->dev_private;
1040         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1041         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1042         union crtc_sourc_param args;
1043         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1044         uint8_t frev, crev;
1045
1046         memset(&args, 0, sizeof(args));
1047
1048         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1049
1050         switch (frev) {
1051         case 1:
1052                 switch (crev) {
1053                 case 1:
1054                 default:
1055                         if (ASIC_IS_AVIVO(rdev))
1056                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1057                         else {
1058                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1059                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1060                                 } else {
1061                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1062                                 }
1063                         }
1064                         switch (radeon_encoder->encoder_id) {
1065                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1066                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1067                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1068                                 break;
1069                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1070                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1071                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1072                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1073                                 else
1074                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1075                                 break;
1076                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1077                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1078                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1079                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1080                                 break;
1081                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1082                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1083                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1084                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1085                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1086                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1087                                 else
1088                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1089                                 break;
1090                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1091                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1092                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1093                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1094                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1095                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1096                                 else
1097                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1098                                 break;
1099                         }
1100                         break;
1101                 case 2:
1102                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1103                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1104                         switch (radeon_encoder->encoder_id) {
1105                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1106                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1107                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1108                                 if (ASIC_IS_DCE32(rdev)) {
1109                                         if (radeon_crtc->crtc_id)
1110                                                 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1111                                         else
1112                                                 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1113                                 } else {
1114                                         struct drm_connector *connector;
1115                                         struct radeon_connector *radeon_connector;
1116                                         struct radeon_connector_atom_dig *dig_connector;
1117
1118                                         connector = radeon_get_connector_for_encoder(encoder);
1119                                         if (!connector)
1120                                                 return;
1121                                         radeon_connector = to_radeon_connector(connector);
1122                                         if (!radeon_connector->con_priv)
1123                                                 return;
1124                                         dig_connector = radeon_connector->con_priv;
1125
1126                                         /* XXX doesn't really matter which dig encoder we pick as long as it's
1127                                          * not already in use
1128                                          */
1129                                         if (dig_connector->linkb)
1130                                                 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1131                                         else
1132                                                 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1133                                 }
1134                                 break;
1135                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1136                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1137                                 break;
1138                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1139                                 /* Only dig2 encoder can drive LVTMA */
1140                                 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1141                                 break;
1142                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1143                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1144                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1145                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1146                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1147                                 else
1148                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1149                                 break;
1150                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1151                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1152                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1153                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1154                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1155                                 else
1156                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1157                                 break;
1158                         }
1159                         break;
1160                 }
1161                 break;
1162         default:
1163                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1164                 break;
1165         }
1166
1167         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1168 }
1169
1170 static void
1171 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1172                               struct drm_display_mode *mode)
1173 {
1174         struct drm_device *dev = encoder->dev;
1175         struct radeon_device *rdev = dev->dev_private;
1176         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1177         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1178
1179         /* Funky macbooks */
1180         if ((dev->pdev->device == 0x71C5) &&
1181             (dev->pdev->subsystem_vendor == 0x106b) &&
1182             (dev->pdev->subsystem_device == 0x0080)) {
1183                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1184                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1185
1186                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1187                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1188
1189                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1190                 }
1191         }
1192
1193         /* set scaler clears this on some chips */
1194         if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1195                 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1196                         WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1197                                AVIVO_D1MODE_INTERLEAVE_EN);
1198         }
1199 }
1200
1201 static void
1202 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1203                              struct drm_display_mode *mode,
1204                              struct drm_display_mode *adjusted_mode)
1205 {
1206         struct drm_device *dev = encoder->dev;
1207         struct radeon_device *rdev = dev->dev_private;
1208         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1209         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1210
1211         if (radeon_encoder->active_device &
1212             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1213                 if (radeon_encoder->enc_priv) {
1214                         struct radeon_encoder_atom_dig *dig;
1215
1216                         dig = radeon_encoder->enc_priv;
1217                         dig->dig_block = radeon_crtc->crtc_id;
1218                 }
1219         }
1220         radeon_encoder->pixel_clock = adjusted_mode->clock;
1221
1222         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1223         atombios_set_encoder_crtc_source(encoder);
1224
1225         if (ASIC_IS_AVIVO(rdev)) {
1226                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1227                         atombios_yuv_setup(encoder, true);
1228                 else
1229                         atombios_yuv_setup(encoder, false);
1230         }
1231
1232         switch (radeon_encoder->encoder_id) {
1233         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1234         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1235         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1236         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1237                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1238                 break;
1239         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1240         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1241         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1242         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1243                 /* disable the encoder and transmitter */
1244                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1245                 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1246
1247                 /* setup and enable the encoder and transmitter */
1248                 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1249                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1250                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1251                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1252                 break;
1253         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1254                 atombios_ddia_setup(encoder, ATOM_ENABLE);
1255                 break;
1256         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1257         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1258                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1259                 break;
1260         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1261         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1262         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1263         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1264                 atombios_dac_setup(encoder, ATOM_ENABLE);
1265                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1266                         atombios_tv_setup(encoder, ATOM_ENABLE);
1267                 break;
1268         }
1269         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1270
1271         r600_hdmi_setmode(encoder, adjusted_mode);
1272 }
1273
1274 static bool
1275 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1276 {
1277         struct drm_device *dev = encoder->dev;
1278         struct radeon_device *rdev = dev->dev_private;
1279         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1280         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1281
1282         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1283                                        ATOM_DEVICE_CV_SUPPORT |
1284                                        ATOM_DEVICE_CRT_SUPPORT)) {
1285                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1286                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1287                 uint8_t frev, crev;
1288
1289                 memset(&args, 0, sizeof(args));
1290
1291                 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1292
1293                 args.sDacload.ucMisc = 0;
1294
1295                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1296                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1297                         args.sDacload.ucDacType = ATOM_DAC_A;
1298                 else
1299                         args.sDacload.ucDacType = ATOM_DAC_B;
1300
1301                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1302                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1303                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1304                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1305                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1306                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1307                         if (crev >= 3)
1308                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1309                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1310                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1311                         if (crev >= 3)
1312                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1313                 }
1314
1315                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1316
1317                 return true;
1318         } else
1319                 return false;
1320 }
1321
1322 static enum drm_connector_status
1323 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1324 {
1325         struct drm_device *dev = encoder->dev;
1326         struct radeon_device *rdev = dev->dev_private;
1327         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1328         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1329         uint32_t bios_0_scratch;
1330
1331         if (!atombios_dac_load_detect(encoder, connector)) {
1332                 DRM_DEBUG("detect returned false \n");
1333                 return connector_status_unknown;
1334         }
1335
1336         if (rdev->family >= CHIP_R600)
1337                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1338         else
1339                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1340
1341         DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1342         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1343                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1344                         return connector_status_connected;
1345         }
1346         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1347                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1348                         return connector_status_connected;
1349         }
1350         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1351                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1352                         return connector_status_connected;
1353         }
1354         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1355                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1356                         return connector_status_connected; /* CTV */
1357                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1358                         return connector_status_connected; /* STV */
1359         }
1360         return connector_status_disconnected;
1361 }
1362
1363 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1364 {
1365         radeon_atom_output_lock(encoder, true);
1366         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1367 }
1368
1369 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1370 {
1371         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1372         radeon_atom_output_lock(encoder, false);
1373 }
1374
1375 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1376 {
1377         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1378         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1379         radeon_encoder->active_device = 0;
1380 }
1381
1382 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1383         .dpms = radeon_atom_encoder_dpms,
1384         .mode_fixup = radeon_atom_mode_fixup,
1385         .prepare = radeon_atom_encoder_prepare,
1386         .mode_set = radeon_atom_encoder_mode_set,
1387         .commit = radeon_atom_encoder_commit,
1388         .disable = radeon_atom_encoder_disable,
1389         /* no detect for TMDS/LVDS yet */
1390 };
1391
1392 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1393         .dpms = radeon_atom_encoder_dpms,
1394         .mode_fixup = radeon_atom_mode_fixup,
1395         .prepare = radeon_atom_encoder_prepare,
1396         .mode_set = radeon_atom_encoder_mode_set,
1397         .commit = radeon_atom_encoder_commit,
1398         .detect = radeon_atom_dac_detect,
1399 };
1400
1401 void radeon_enc_destroy(struct drm_encoder *encoder)
1402 {
1403         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1404         kfree(radeon_encoder->enc_priv);
1405         drm_encoder_cleanup(encoder);
1406         kfree(radeon_encoder);
1407 }
1408
1409 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1410         .destroy = radeon_enc_destroy,
1411 };
1412
1413 struct radeon_encoder_atom_dac *
1414 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1415 {
1416         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1417
1418         if (!dac)
1419                 return NULL;
1420
1421         dac->tv_std = TV_STD_NTSC;
1422         return dac;
1423 }
1424
1425 struct radeon_encoder_atom_dig *
1426 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1427 {
1428         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1429
1430         if (!dig)
1431                 return NULL;
1432
1433         /* coherent mode by default */
1434         dig->coherent_mode = true;
1435
1436         return dig;
1437 }
1438
1439 void
1440 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1441 {
1442         struct radeon_device *rdev = dev->dev_private;
1443         struct drm_encoder *encoder;
1444         struct radeon_encoder *radeon_encoder;
1445
1446         /* see if we already added it */
1447         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1448                 radeon_encoder = to_radeon_encoder(encoder);
1449                 if (radeon_encoder->encoder_id == encoder_id) {
1450                         radeon_encoder->devices |= supported_device;
1451                         return;
1452                 }
1453
1454         }
1455
1456         /* add a new one */
1457         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1458         if (!radeon_encoder)
1459                 return;
1460
1461         encoder = &radeon_encoder->base;
1462         if (rdev->flags & RADEON_SINGLE_CRTC)
1463                 encoder->possible_crtcs = 0x1;
1464         else
1465                 encoder->possible_crtcs = 0x3;
1466
1467         radeon_encoder->enc_priv = NULL;
1468
1469         radeon_encoder->encoder_id = encoder_id;
1470         radeon_encoder->devices = supported_device;
1471         radeon_encoder->rmx_type = RMX_OFF;
1472
1473         switch (radeon_encoder->encoder_id) {
1474         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1475         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1476         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1477         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1478                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1479                         radeon_encoder->rmx_type = RMX_FULL;
1480                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1481                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1482                 } else {
1483                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1484                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1485                 }
1486                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1487                 break;
1488         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1489                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1490                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1491                 break;
1492         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1493         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1494         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1495                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1496                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1497                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1498                 break;
1499         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1500         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1501         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1502         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1503         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1504         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1505         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1506                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1507                         radeon_encoder->rmx_type = RMX_FULL;
1508                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1509                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1510                 } else {
1511                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1512                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1513                 }
1514                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1515                 break;
1516         }
1517
1518         r600_hdmi_init(encoder);
1519 }