drivers/gpu/drm/radeon/radeon_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/console.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include <linux/efi.h>
  36 #include "radeon_reg.h"
  37 #include "radeon.h"
  38 #include "atom.h"
  39
  40 static const char radeon_family_name[][16] = {
  41         "R100",
  42         "RV100",
  43         "RS100",
  44         "RV200",
  45         "RS200",
  46         "R200",
  47         "RV250",
  48         "RS300",
  49         "RV280",
  50         "R300",
  51         "R350",
  52         "RV350",
  53         "RV380",
  54         "R420",
  55         "R423",
  56         "RV410",
  57         "RS400",
  58         "RS480",
  59         "RS600",
  60         "RS690",
  61         "RS740",
  62         "RV515",
  63         "R520",
  64         "RV530",
  65         "RV560",
  66         "RV570",
  67         "R580",
  68         "R600",
  69         "RV610",
  70         "RV630",
  71         "RV670",
  72         "RV620",
  73         "RV635",
  74         "RS780",
  75         "RS880",
  76         "RV770",
  77         "RV730",
  78         "RV710",
  79         "RV740",
  80         "CEDAR",
  81         "REDWOOD",
  82         "JUNIPER",
  83         "CYPRESS",
  84         "HEMLOCK",
  85         "PALM",
  86         "SUMO",
  87         "SUMO2",
  88         "BARTS",
  89         "TURKS",
  90         "CAICOS",
  91         "CAYMAN",
  92         "LAST",
  93 };
  94
  95 /*
  96  * Clear GPU surface registers.
  97  */
  98 void radeon_surface_init(struct radeon_device *rdev)
  99 {
 100         /* FIXME: check this out */
 101         if (rdev->family < CHIP_R600) {
 102                 int i;
 103
 104                 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 105                         if (rdev->surface_regs[i].bo)
 106                                 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
 107                         else
 108                                 radeon_clear_surface_reg(rdev, i);
 109                 }
 110                 /* enable surfaces */
 111                 WREG32(RADEON_SURFACE_CNTL, 0);
 112         }
 113 }
 114
 115 /*
 116  * GPU scratch registers helpers function.
 117  */
 118 void radeon_scratch_init(struct radeon_device *rdev)
 119 {
 120         int i;
 121
 122         /* FIXME: check this out */
 123         if (rdev->family < CHIP_R300) {
 124                 rdev->scratch.num_reg = 5;
 125         } else {
 126                 rdev->scratch.num_reg = 7;
 127         }
 128         rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
 129         for (i = 0; i < rdev->scratch.num_reg; i++) {
 130                 rdev->scratch.free[i] = true;
 131                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
 132         }
 133 }
 134
 135 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
 136 {
 137         int i;
 138
 139         for (i = 0; i < rdev->scratch.num_reg; i++) {
 140                 if (rdev->scratch.free[i]) {
 141                         rdev->scratch.free[i] = false;
 142                         *reg = rdev->scratch.reg[i];
 143                         return 0;
 144                 }
 145         }
 146         return -EINVAL;
 147 }
 148
 149 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
 150 {
 151         int i;
 152
 153         for (i = 0; i < rdev->scratch.num_reg; i++) {
 154                 if (rdev->scratch.reg[i] == reg) {
 155                         rdev->scratch.free[i] = true;
 156                         return;
 157                 }
 158         }
 159 }
 160
 161 void radeon_wb_disable(struct radeon_device *rdev)
 162 {
 163         int r;
 164
 165         if (rdev->wb.wb_obj) {
 166                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 167                 if (unlikely(r != 0))
 168                         return;
 169                 radeon_bo_kunmap(rdev->wb.wb_obj);
 170                 radeon_bo_unpin(rdev->wb.wb_obj);
 171                 radeon_bo_unreserve(rdev->wb.wb_obj);
 172         }
 173         rdev->wb.enabled = false;
 174 }
 175
 176 void radeon_wb_fini(struct radeon_device *rdev)
 177 {
 178         radeon_wb_disable(rdev);
 179         if (rdev->wb.wb_obj) {
 180                 radeon_bo_unref(&rdev->wb.wb_obj);
 181                 rdev->wb.wb = NULL;
 182                 rdev->wb.wb_obj = NULL;
 183         }
 184 }
 185
 186 int radeon_wb_init(struct radeon_device *rdev)
 187 {
 188         int r;
 189
 190         if (rdev->wb.wb_obj == NULL) {
 191                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
 192                                 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
 193                 if (r) {
 194                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
 195                         return r;
 196                 }
 197         }
 198         r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 199         if (unlikely(r != 0)) {
 200                 radeon_wb_fini(rdev);
 201                 return r;
 202         }
 203         r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
 204                           &rdev->wb.gpu_addr);
 205         if (r) {
 206                 radeon_bo_unreserve(rdev->wb.wb_obj);
 207                 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
 208                 radeon_wb_fini(rdev);
 209                 return r;
 210         }
 211         r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 212         radeon_bo_unreserve(rdev->wb.wb_obj);
 213         if (r) {
 214                 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
 215                 radeon_wb_fini(rdev);
 216                 return r;
 217         }
 218
 219         /* clear wb memory */
 220         memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
 221         /* disable event_write fences */
 222         rdev->wb.use_event = false;
 223         /* disabled via module param */
 224         if (radeon_no_wb == 1)
 225                 rdev->wb.enabled = false;
 226         else {
 227                 if (rdev->flags & RADEON_IS_AGP) {
 228                         /* often unreliable on AGP */
 229                         rdev->wb.enabled = false;
 230                 } else if (rdev->family < CHIP_R300) {
 231                         /* often unreliable on pre-r300 */
 232                         rdev->wb.enabled = false;
 233                 } else {
 234                         rdev->wb.enabled = true;
 235                         /* event_write fences are only available on r600+ */
 236                         if (rdev->family >= CHIP_R600)
 237                                 rdev->wb.use_event = true;
 238                 }
 239         }
 240         /* always use writeback/events on NI */
 241         if (ASIC_IS_DCE5(rdev)) {
 242                 rdev->wb.enabled = true;
 243                 rdev->wb.use_event = true;
 244         }
 245
 246         dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
 247
 248         return 0;
 249 }
 250
 251 /**
 252  * radeon_vram_location - try to find VRAM location
 253  * @rdev: radeon device structure holding all necessary informations
 254  * @mc: memory controller structure holding memory informations
 255  * @base: base address at which to put VRAM
 256  *
 257  * Function will place try to place VRAM at base address provided
 258  * as parameter (which is so far either PCI aperture address or
 259  * for IGP TOM base address).
 260  *
 261  * If there is not enough space to fit the unvisible VRAM in the 32bits
 262  * address space then we limit the VRAM size to the aperture.
 263  *
 264  * If we are using AGP and if the AGP aperture doesn't allow us to have
 265  * room for all the VRAM than we restrict the VRAM to the PCI aperture
 266  * size and print a warning.
 267  *
 268  * This function will never fails, worst case are limiting VRAM.
 269  *
 270  * Note: GTT start, end, size should be initialized before calling this
 271  * function on AGP platform.
 272  *
 273  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 274  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 275  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 276  * not IGP.
 277  *
 278  * Note: we use mc_vram_size as on some board we need to program the mc to
 279  * cover the whole aperture even if VRAM size is inferior to aperture size
 280  * Novell bug 204882 + along with lots of ubuntu ones
 281  *
 282  * Note: when limiting vram it's safe to overwritte real_vram_size because
 283  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 284  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 285  * ones)
 286  *
 287  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 288  * explicitly check for that thought.
 289  *
 290  * FIXME: when reducing VRAM size align new size on power of 2.
 291  */
 292 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
 293 {
 294         mc->vram_start = base;
 295         if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
 296                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 297                 mc->real_vram_size = mc->aper_size;
 298                 mc->mc_vram_size = mc->aper_size;
 299         }
 300         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 301         if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
 302                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 303                 mc->real_vram_size = mc->aper_size;
 304                 mc->mc_vram_size = mc->aper_size;
 305         }
 306         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 307         if (radeon_vram_limit && radeon_vram_limit < mc->real_vram_size)
 308                 mc->real_vram_size = radeon_vram_limit;
 309         dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 310                         mc->mc_vram_size >> 20, mc->vram_start,
 311                         mc->vram_end, mc->real_vram_size >> 20);
 312 }
 313
 314 /**
 315  * radeon_gtt_location - try to find GTT location
 316  * @rdev: radeon device structure holding all necessary informations
 317  * @mc: memory controller structure holding memory informations
 318  *
 319  * Function will place try to place GTT before or after VRAM.
 320  *
 321  * If GTT size is bigger than space left then we ajust GTT size.
 322  * Thus function will never fails.
 323  *
 324  * FIXME: when reducing GTT size align new size on power of 2.
 325  */
 326 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 327 {
 328         u64 size_af, size_bf;
 329
 330         size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 331         size_bf = mc->vram_start & ~mc->gtt_base_align;
 332         if (size_bf > size_af) {
 333                 if (mc->gtt_size > size_bf) {
 334                         dev_warn(rdev->dev, "limiting GTT\n");
 335                         mc->gtt_size = size_bf;
 336                 }
 337                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 338         } else {
 339                 if (mc->gtt_size > size_af) {
 340                         dev_warn(rdev->dev, "limiting GTT\n");
 341                         mc->gtt_size = size_af;
 342                 }
 343                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 344         }
 345         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 346         dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 347                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 348 }
 349
 350 /*
 351  * GPU helpers function.
 352  */
 353
 354 /**
 355  * radeon_device_is_virtual - check if we are running is a virtual environment
 356  *
 357  * Check if the asic has been passed through to a VM (all asics).
 358  * Used at driver startup.
 359  * Returns true if virtual or false if not.
 360  */
 361 static bool radeon_device_is_virtual(void)
 362 {
 363 #ifdef CONFIG_X86
 364         return boot_cpu_has(X86_FEATURE_HYPERVISOR);
 365 #else
 366         return false;
 367 #endif
 368 }
 369
 370 bool radeon_card_posted(struct radeon_device *rdev)
 371 {
 372         uint32_t reg;
 373
 374         /* for pass through, always force asic_init */
 375         if (radeon_device_is_virtual())
 376                 return false;
 377
 378         if (efi_enabled(EFI_BOOT) &&
 379             rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE)
 380                 return false;
 381
 382         /* first check CRTCs */
 383         if (ASIC_IS_DCE4(rdev)) {
 384                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
 385                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
 386                         if (rdev->num_crtc >= 4) {
 387                                 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
 388                                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
 389                         }
 390                         if (rdev->num_crtc >= 6) {
 391                                 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
 392                                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 393                         }
 394                 if (reg & EVERGREEN_CRTC_MASTER_EN)
 395                         return true;
 396         } else if (ASIC_IS_AVIVO(rdev)) {
 397                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
 398                       RREG32(AVIVO_D2CRTC_CONTROL);
 399                 if (reg & AVIVO_CRTC_EN) {
 400                         return true;
 401                 }
 402         } else {
 403                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
 404                       RREG32(RADEON_CRTC2_GEN_CNTL);
 405                 if (reg & RADEON_CRTC_EN) {
 406                         return true;
 407                 }
 408         }
 409
 410         /* then check MEM_SIZE, in case the crtcs are off */
 411         if (rdev->family >= CHIP_R600)
 412                 reg = RREG32(R600_CONFIG_MEMSIZE);
 413         else
 414                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
 415
 416         if (reg)
 417                 return true;
 418
 419         return false;
 420
 421 }
 422
 423 void radeon_update_bandwidth_info(struct radeon_device *rdev)
 424 {
 425         fixed20_12 a;
 426         u32 sclk = rdev->pm.current_sclk;
 427         u32 mclk = rdev->pm.current_mclk;
 428
 429         /* sclk/mclk in Mhz */
 430         a.full = dfixed_const(100);
 431         rdev->pm.sclk.full = dfixed_const(sclk);
 432         rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
 433         rdev->pm.mclk.full = dfixed_const(mclk);
 434         rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
 435
 436         if (rdev->flags & RADEON_IS_IGP) {
 437                 a.full = dfixed_const(16);
 438                 /* core_bandwidth = sclk(Mhz) * 16 */
 439                 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
 440         }
 441 }
 442
 443 bool radeon_boot_test_post_card(struct radeon_device *rdev)
 444 {
 445         if (radeon_card_posted(rdev))
 446                 return true;
 447
 448         if (rdev->bios) {
 449                 DRM_INFO("GPU not posted. posting now...\n");
 450                 if (rdev->is_atom_bios)
 451                         atom_asic_init(rdev->mode_info.atom_context);
 452                 else
 453                         radeon_combios_asic_init(rdev->ddev);
 454                 return true;
 455         } else {
 456                 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
 457                 return false;
 458         }
 459 }
 460
 461 int radeon_dummy_page_init(struct radeon_device *rdev)
 462 {
 463         if (rdev->dummy_page.page)
 464                 return 0;
 465         rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 466         if (rdev->dummy_page.page == NULL)
 467                 return -ENOMEM;
 468         rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
 469                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 470         if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
 471                 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 472                 __free_page(rdev->dummy_page.page);
 473                 rdev->dummy_page.page = NULL;
 474                 return -ENOMEM;
 475         }
 476         return 0;
 477 }
 478
 479 void radeon_dummy_page_fini(struct radeon_device *rdev)
 480 {
 481         if (rdev->dummy_page.page == NULL)
 482                 return;
 483         pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
 484                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 485         __free_page(rdev->dummy_page.page);
 486         rdev->dummy_page.page = NULL;
 487 }
 488
 489
 490 /* ATOM accessor methods */
 491 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 492 {
 493         struct radeon_device *rdev = info->dev->dev_private;
 494         uint32_t r;
 495
 496         r = rdev->pll_rreg(rdev, reg);
 497         return r;
 498 }
 499
 500 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 501 {
 502         struct radeon_device *rdev = info->dev->dev_private;
 503
 504         rdev->pll_wreg(rdev, reg, val);
 505 }
 506
 507 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 508 {
 509         struct radeon_device *rdev = info->dev->dev_private;
 510         uint32_t r;
 511
 512         r = rdev->mc_rreg(rdev, reg);
 513         return r;
 514 }
 515
 516 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 517 {
 518         struct radeon_device *rdev = info->dev->dev_private;
 519
 520         rdev->mc_wreg(rdev, reg, val);
 521 }
 522
 523 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 524 {
 525         struct radeon_device *rdev = info->dev->dev_private;
 526
 527         WREG32(reg*4, val);
 528 }
 529
 530 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 531 {
 532         struct radeon_device *rdev = info->dev->dev_private;
 533         uint32_t r;
 534
 535         r = RREG32(reg*4);
 536         return r;
 537 }
 538
 539 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 540 {
 541         struct radeon_device *rdev = info->dev->dev_private;
 542
 543         WREG32_IO(reg*4, val);
 544 }
 545
 546 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 547 {
 548         struct radeon_device *rdev = info->dev->dev_private;
 549         uint32_t r;
 550
 551         r = RREG32_IO(reg*4);
 552         return r;
 553 }
 554
 555 int radeon_atombios_init(struct radeon_device *rdev)
 556 {
 557         struct card_info *atom_card_info =
 558             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 559
 560         if (!atom_card_info)
 561                 return -ENOMEM;
 562
 563         rdev->mode_info.atom_card_info = atom_card_info;
 564         atom_card_info->dev = rdev->ddev;
 565         atom_card_info->reg_read = cail_reg_read;
 566         atom_card_info->reg_write = cail_reg_write;
 567         /* needed for iio ops */
 568         if (rdev->rio_mem) {
 569                 atom_card_info->ioreg_read = cail_ioreg_read;
 570                 atom_card_info->ioreg_write = cail_ioreg_write;
 571         } else {
 572                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 573                 atom_card_info->ioreg_read = cail_reg_read;
 574                 atom_card_info->ioreg_write = cail_reg_write;
 575         }
 576         atom_card_info->mc_read = cail_mc_read;
 577         atom_card_info->mc_write = cail_mc_write;
 578         atom_card_info->pll_read = cail_pll_read;
 579         atom_card_info->pll_write = cail_pll_write;
 580
 581         rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
 582         mutex_init(&rdev->mode_info.atom_context->mutex);
 583         radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
 584         atom_allocate_fb_scratch(rdev->mode_info.atom_context);
 585         return 0;
 586 }
 587
 588 void radeon_atombios_fini(struct radeon_device *rdev)
 589 {
 590         if (rdev->mode_info.atom_context) {
 591                 kfree(rdev->mode_info.atom_context->scratch);
 592                 kfree(rdev->mode_info.atom_context);
 593         }
 594         kfree(rdev->mode_info.atom_card_info);
 595 }
 596
 597 int radeon_combios_init(struct radeon_device *rdev)
 598 {
 599         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
 600         return 0;
 601 }
 602
 603 void radeon_combios_fini(struct radeon_device *rdev)
 604 {
 605 }
 606
 607 /* if we get transitioned to only one device, tak VGA back */
 608 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
 609 {
 610         struct radeon_device *rdev = cookie;
 611         radeon_vga_set_state(rdev, state);
 612         if (state)
 613                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 614                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 615         else
 616                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 617 }
 618
 619 void radeon_check_arguments(struct radeon_device *rdev)
 620 {
 621         /* vramlimit must be a power of two */
 622         switch (radeon_vram_limit) {
 623         case 0:
 624         case 4:
 625         case 8:
 626         case 16:
 627         case 32:
 628         case 64:
 629         case 128:
 630         case 256:
 631         case 512:
 632         case 1024:
 633         case 2048:
 634         case 4096:
 635                 break;
 636         default:
 637                 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
 638                                 radeon_vram_limit);
 639                 radeon_vram_limit = 0;
 640                 break;
 641         }
 642         radeon_vram_limit = radeon_vram_limit << 20;
 643         /* gtt size must be power of two and greater or equal to 32M */
 644         switch (radeon_gart_size) {
 645         case 4:
 646         case 8:
 647         case 16:
 648                 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
 649                                 radeon_gart_size);
 650                 radeon_gart_size = 512;
 651                 break;
 652         case 32:
 653         case 64:
 654         case 128:
 655         case 256:
 656         case 512:
 657         case 1024:
 658         case 2048:
 659         case 4096:
 660                 break;
 661         default:
 662                 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
 663                                 radeon_gart_size);
 664                 radeon_gart_size = 512;
 665                 break;
 666         }
 667         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 668         /* AGP mode can only be -1, 1, 2, 4, 8 */
 669         switch (radeon_agpmode) {
 670         case -1:
 671         case 0:
 672         case 1:
 673         case 2:
 674         case 4:
 675         case 8:
 676                 break;
 677         default:
 678                 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
 679                                 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
 680                 radeon_agpmode = 0;
 681                 break;
 682         }
 683 }
 684
 685 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 686 {
 687         struct drm_device *dev = pci_get_drvdata(pdev);
 688         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 689         if (state == VGA_SWITCHEROO_ON) {
 690                 printk(KERN_INFO "radeon: switched on\n");
 691                 /* don't suspend or resume card normally */
 692                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 693                 radeon_resume_kms(dev);
 694                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 695                 drm_kms_helper_poll_enable(dev);
 696         } else {
 697                 printk(KERN_INFO "radeon: switched off\n");
 698                 drm_kms_helper_poll_disable(dev);
 699                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 700                 radeon_suspend_kms(dev, pmm);
 701                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 702         }
 703 }
 704
 705 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
 706 {
 707         struct drm_device *dev = pci_get_drvdata(pdev);
 708         bool can_switch;
 709
 710         spin_lock(&dev->count_lock);
 711         can_switch = (dev->open_count == 0);
 712         spin_unlock(&dev->count_lock);
 713         return can_switch;
 714 }
 715
 716
 717 int radeon_device_init(struct radeon_device *rdev,
 718                        struct drm_device *ddev,
 719                        struct pci_dev *pdev,
 720                        uint32_t flags)
 721 {
 722         int r, i;
 723         int dma_bits;
 724
 725         rdev->shutdown = false;
 726         rdev->dev = &pdev->dev;
 727         rdev->ddev = ddev;
 728         rdev->pdev = pdev;
 729         rdev->flags = flags;
 730         rdev->family = flags & RADEON_FAMILY_MASK;
 731         rdev->is_atom_bios = false;
 732         rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
 733         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 734         rdev->gpu_lockup = false;
 735         rdev->accel_working = false;
 736
 737         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
 738                 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
 739                 pdev->subsystem_vendor, pdev->subsystem_device);
 740
 741         /* mutex initialization are all done here so we
 742          * can recall function without having locking issues */
 743         radeon_mutex_init(&rdev->cs_mutex);
 744         mutex_init(&rdev->ib_pool.mutex);
 745         mutex_init(&rdev->cp.mutex);
 746         mutex_init(&rdev->dc_hw_i2c_mutex);
 747         if (rdev->family >= CHIP_R600)
 748                 spin_lock_init(&rdev->ih.lock);
 749         mutex_init(&rdev->gem.mutex);
 750         mutex_init(&rdev->pm.mutex);
 751         mutex_init(&rdev->vram_mutex);
 752         rwlock_init(&rdev->fence_drv.lock);
 753         INIT_LIST_HEAD(&rdev->gem.objects);
 754         init_waitqueue_head(&rdev->irq.vblank_queue);
 755         init_waitqueue_head(&rdev->irq.idle_queue);
 756
 757         /* Set asic functions */
 758         r = radeon_asic_init(rdev);
 759         if (r)
 760                 return r;
 761         radeon_check_arguments(rdev);
 762
 763         /* all of the newer IGP chips have an internal gart
 764          * However some rs4xx report as AGP, so remove that here.
 765          */
 766         if ((rdev->family >= CHIP_RS400) &&
 767             (rdev->flags & RADEON_IS_IGP)) {
 768                 rdev->flags &= ~RADEON_IS_AGP;
 769         }
 770
 771         if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
 772                 radeon_agp_disable(rdev);
 773         }
 774
 775         /* set DMA mask + need_dma32 flags.
 776          * PCIE - can handle 40-bits.
 777          * IGP - can handle 40-bits
 778          * AGP - generally dma32 is safest
 779          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
 780          */
 781         rdev->need_dma32 = false;
 782         if (rdev->flags & RADEON_IS_AGP)
 783                 rdev->need_dma32 = true;
 784         if ((rdev->flags & RADEON_IS_PCI) &&
 785             (rdev->family <= CHIP_RS740))
 786                 rdev->need_dma32 = true;
 787
 788         dma_bits = rdev->need_dma32 ? 32 : 40;
 789         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
 790         if (r) {
 791                 rdev->need_dma32 = true;
 792                 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
 793         }
 794
 795         /* Registers mapping */
 796         /* TODO: block userspace mapping of io register */
 797         rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
 798         rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
 799         rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
 800         if (rdev->rmmio == NULL) {
 801                 return -ENOMEM;
 802         }
 803         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
 804         DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
 805
 806         /* io port mapping */
 807         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 808                 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
 809                         rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
 810                         rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
 811                         break;
 812                 }
 813         }
 814         if (rdev->rio_mem == NULL)
 815                 DRM_ERROR("Unable to find PCI I/O BAR\n");
 816
 817         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
 818         /* this will fail for cards that aren't VGA class devices, just
 819          * ignore it */
 820         vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
 821         vga_switcheroo_register_client(rdev->pdev,
 822                                        radeon_switcheroo_set_state,
 823                                        NULL,
 824                                        radeon_switcheroo_can_switch);
 825
 826         r = radeon_init(rdev);
 827         if (r)
 828                 return r;
 829
 830         if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
 831                 /* Acceleration not working on AGP card try again
 832                  * with fallback to PCI or PCIE GART
 833                  */
 834                 radeon_asic_reset(rdev);
 835                 radeon_fini(rdev);
 836                 radeon_agp_disable(rdev);
 837                 r = radeon_init(rdev);
 838                 if (r)
 839                         return r;
 840         }
 841         if (radeon_testing) {
 842                 if (rdev->accel_working)
 843                         radeon_test_moves(rdev);
 844                 else
 845                         DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
 846         }
 847         if (radeon_benchmarking) {
 848                 if (rdev->accel_working)
 849                         radeon_benchmark(rdev, radeon_benchmarking);
 850                 else
 851                         DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
 852         }
 853         return 0;
 854 }
 855
 856 void radeon_device_fini(struct radeon_device *rdev)
 857 {
 858         DRM_INFO("radeon: finishing device.\n");
 859         rdev->shutdown = true;
 860         /* evict vram memory */
 861         radeon_bo_evict_vram(rdev);
 862         radeon_fini(rdev);
 863         vga_switcheroo_unregister_client(rdev->pdev);
 864         vga_client_register(rdev->pdev, NULL, NULL, NULL);
 865         if (rdev->rio_mem)
 866                 pci_iounmap(rdev->pdev, rdev->rio_mem);
 867         rdev->rio_mem = NULL;
 868         iounmap(rdev->rmmio);
 869         rdev->rmmio = NULL;
 870 }
 871
 872
 873 /*
 874  * Suspend & resume.
 875  */
 876 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 877 {
 878         struct radeon_device *rdev;
 879         struct drm_crtc *crtc;
 880         struct drm_connector *connector;
 881         int r;
 882
 883         if (dev == NULL || dev->dev_private == NULL) {
 884                 return -ENODEV;
 885         }
 886         if (state.event == PM_EVENT_PRETHAW) {
 887                 return 0;
 888         }
 889         rdev = dev->dev_private;
 890
 891         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 892                 return 0;
 893
 894         drm_kms_helper_poll_disable(dev);
 895
 896         /* turn off display hw */
 897         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 898                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
 899         }
 900
 901         /* unpin the front buffers */
 902         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 903                 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
 904                 struct radeon_bo *robj;
 905
 906                 if (rfb == NULL || rfb->obj == NULL) {
 907                         continue;
 908                 }
 909                 robj = gem_to_radeon_bo(rfb->obj);
 910                 /* don't unpin kernel fb objects */
 911                 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
 912                         r = radeon_bo_reserve(robj, false);
 913                         if (r == 0) {
 914                                 radeon_bo_unpin(robj);
 915                                 radeon_bo_unreserve(robj);
 916                         }
 917                 }
 918         }
 919         /* evict vram memory */
 920         radeon_bo_evict_vram(rdev);
 921         /* wait for gpu to finish processing current batch */
 922         radeon_fence_wait_last(rdev);
 923
 924         radeon_save_bios_scratch_regs(rdev);
 925
 926         radeon_pm_suspend(rdev);
 927         radeon_suspend(rdev);
 928         radeon_hpd_fini(rdev);
 929         /* evict remaining vram memory */
 930         radeon_bo_evict_vram(rdev);
 931
 932         radeon_agp_suspend(rdev);
 933
 934         pci_save_state(dev->pdev);
 935         if (state.event == PM_EVENT_SUSPEND) {
 936                 /* Shut down the device */
 937                 pci_disable_device(dev->pdev);
 938                 pci_set_power_state(dev->pdev, PCI_D3hot);
 939         }
 940         console_lock();
 941         radeon_fbdev_set_suspend(rdev, 1);
 942         console_unlock();
 943         return 0;
 944 }
 945
 946 int radeon_resume_kms(struct drm_device *dev)
 947 {
 948         struct drm_connector *connector;
 949         struct radeon_device *rdev = dev->dev_private;
 950
 951         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 952                 return 0;
 953
 954         console_lock();
 955         pci_set_power_state(dev->pdev, PCI_D0);
 956         pci_restore_state(dev->pdev);
 957         if (pci_enable_device(dev->pdev)) {
 958                 console_unlock();
 959                 return -1;
 960         }
 961         pci_set_master(dev->pdev);
 962         /* resume AGP if in use */
 963         radeon_agp_resume(rdev);
 964         radeon_resume(rdev);
 965         radeon_pm_resume(rdev);
 966         radeon_restore_bios_scratch_regs(rdev);
 967
 968         radeon_fbdev_set_suspend(rdev, 0);
 969         console_unlock();
 970
 971         /* init dig PHYs */
 972         if (rdev->is_atom_bios)
 973                 radeon_atom_encoder_init(rdev);
 974         /* reset hpd state */
 975         radeon_hpd_init(rdev);
 976         /* blat the mode back in */
 977         drm_helper_resume_force_mode(dev);
 978         /* turn on display hw */
 979         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 980                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
 981         }
 982
 983         drm_kms_helper_poll_enable(dev);
 984         return 0;
 985 }
 986
 987 int radeon_gpu_reset(struct radeon_device *rdev)
 988 {
 989         int r;
 990         int resched;
 991
 992         /* Prevent CS ioctl from interfering */
 993         radeon_mutex_lock(&rdev->cs_mutex);
 994
 995         radeon_save_bios_scratch_regs(rdev);
 996         /* block TTM */
 997         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 998         radeon_suspend(rdev);
 999
1000         r = radeon_asic_reset(rdev);
1001         if (!r) {
1002                 dev_info(rdev->dev, "GPU reset succeed\n");
1003                 radeon_resume(rdev);
1004                 radeon_restore_bios_scratch_regs(rdev);
1005                 drm_helper_resume_force_mode(rdev->ddev);
1006                 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1007         }
1008
1009         radeon_mutex_unlock(&rdev->cs_mutex);
1010
1011         if (r) {
1012                 /* bad news, how to tell it to userspace ? */
1013                 dev_info(rdev->dev, "GPU reset failed\n");
1014         }
1015
1016         return r;
1017 }
1018
1019
1020 /*
1021  * Debugfs
1022  */
1023 struct radeon_debugfs {
1024         struct drm_info_list    *files;
1025         unsigned                num_files;
1026 };
1027 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1028 static unsigned _radeon_debugfs_count = 0;
1029
1030 int radeon_debugfs_add_files(struct radeon_device *rdev,
1031                              struct drm_info_list *files,
1032                              unsigned nfiles)
1033 {
1034         unsigned i;
1035
1036         for (i = 0; i < _radeon_debugfs_count; i++) {
1037                 if (_radeon_debugfs[i].files == files) {
1038                         /* Already registered */
1039                         return 0;
1040                 }
1041         }
1042
1043         i = _radeon_debugfs_count + 1;
1044         if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1045                 DRM_ERROR("Reached maximum number of debugfs components.\n");
1046                 DRM_ERROR("Report so we increase "
1047                           "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1048                 return -EINVAL;
1049         }
1050         _radeon_debugfs[_radeon_debugfs_count].files = files;
1051         _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
1052         _radeon_debugfs_count = i;
1053 #if defined(CONFIG_DEBUG_FS)
1054         drm_debugfs_create_files(files, nfiles,
1055                                  rdev->ddev->control->debugfs_root,
1056                                  rdev->ddev->control);
1057         drm_debugfs_create_files(files, nfiles,
1058                                  rdev->ddev->primary->debugfs_root,
1059                                  rdev->ddev->primary);
1060 #endif
1061         return 0;
1062 }
1063
1064 #if defined(CONFIG_DEBUG_FS)
1065 int radeon_debugfs_init(struct drm_minor *minor)
1066 {
1067         return 0;
1068 }
1069
1070 void radeon_debugfs_cleanup(struct drm_minor *minor)
1071 {
1072         unsigned i;
1073
1074         for (i = 0; i < _radeon_debugfs_count; i++) {
1075                 drm_debugfs_remove_files(_radeon_debugfs[i].files,
1076                                          _radeon_debugfs[i].num_files, minor);
1077         }
1078 }
1079 #endif