drivers/gpu/drm/radeon/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2007 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  */
  31
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "drm_sarea.h"
  35 #include "radeon_drm.h"
  36 #include "radeon_drv.h"
  37 #include "r300_reg.h"
  38
  39 #include "radeon_microcode.h"
  40
  41 #define RADEON_FIFO_DEBUG       0
  42
  43 static int radeon_do_cleanup_cp(struct drm_device * dev);
  44 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
  45
  46 static u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
  47 {
  48         u32 val;
  49
  50         if (dev_priv->flags & RADEON_IS_AGP) {
  51                 val = DRM_READ32(dev_priv->ring_rptr, off);
  52         } else {
  53                 val = *(((volatile u32 *)
  54                          dev_priv->ring_rptr->handle) +
  55                         (off / sizeof(u32)));
  56                 val = le32_to_cpu(val);
  57         }
  58         return val;
  59 }
  60
  61 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
  62 {
  63         if (dev_priv->writeback_works)
  64                 return radeon_read_ring_rptr(dev_priv, 0);
  65         else
  66                 return RADEON_READ(RADEON_CP_RB_RPTR);
  67 }
  68
  69 static void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
  70 {
  71         if (dev_priv->flags & RADEON_IS_AGP)
  72                 DRM_WRITE32(dev_priv->ring_rptr, off, val);
  73         else
  74                 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
  75                   (off / sizeof(u32))) = cpu_to_le32(val);
  76 }
  77
  78 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
  79 {
  80         radeon_write_ring_rptr(dev_priv, 0, val);
  81 }
  82
  83 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
  84 {
  85         if (dev_priv->writeback_works)
  86                 return radeon_read_ring_rptr(dev_priv,
  87                                              RADEON_SCRATCHOFF(index));
  88         else
  89                 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
  90 }
  91
  92 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  93 {
  94         u32 ret;
  95         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
  96         ret = RADEON_READ(R520_MC_IND_DATA);
  97         RADEON_WRITE(R520_MC_IND_INDEX, 0);
  98         return ret;
  99 }
 100
 101 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 102 {
 103         u32 ret;
 104         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
 105         ret = RADEON_READ(RS480_NB_MC_DATA);
 106         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
 107         return ret;
 108 }
 109
 110 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 111 {
 112         u32 ret;
 113         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
 114         ret = RADEON_READ(RS690_MC_DATA);
 115         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
 116         return ret;
 117 }
 118
 119 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 120 {
 121         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 122             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 123                 return RS690_READ_MCIND(dev_priv, addr);
 124         else
 125                 return RS480_READ_MCIND(dev_priv, addr);
 126 }
 127
 128 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 129 {
 130
 131         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 132                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
 133         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 134                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 135                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
 136         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 137                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
 138         else
 139                 return RADEON_READ(RADEON_MC_FB_LOCATION);
 140 }
 141
 142 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 143 {
 144         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 145                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
 146         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 147                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 148                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 149         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 150                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 151         else
 152                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 153 }
 154
 155 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 156 {
 157         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 158                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 159         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 160                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 161                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 162         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 163                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 164         else
 165                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 166 }
 167
 168 static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 169 {
 170         u32 agp_base_hi = upper_32_bits(agp_base);
 171         u32 agp_base_lo = agp_base & 0xffffffff;
 172
 173         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 174                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 175                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 176         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 177                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 178                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 179                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 180         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 181                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 182                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 183         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 184                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 185                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 186                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
 187         } else {
 188                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 189                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 190                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 191         }
 192 }
 193
 194 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 195 {
 196         drm_radeon_private_t *dev_priv = dev->dev_private;
 197
 198         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 199         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 200 }
 201
 202 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 203 {
 204         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 205         return RADEON_READ(RADEON_PCIE_DATA);
 206 }
 207
 208 #if RADEON_FIFO_DEBUG
 209 static void radeon_status(drm_radeon_private_t * dev_priv)
 210 {
 211         printk("%s:\n", __func__);
 212         printk("RBBM_STATUS = 0x%08x\n",
 213                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 214         printk("CP_RB_RTPR = 0x%08x\n",
 215                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 216         printk("CP_RB_WTPR = 0x%08x\n",
 217                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 218         printk("AIC_CNTL = 0x%08x\n",
 219                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 220         printk("AIC_STAT = 0x%08x\n",
 221                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 222         printk("AIC_PT_BASE = 0x%08x\n",
 223                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 224         printk("TLB_ADDR = 0x%08x\n",
 225                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 226         printk("TLB_DATA = 0x%08x\n",
 227                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 228 }
 229 #endif
 230
 231 /* ================================================================
 232  * Engine, FIFO control
 233  */
 234
 235 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 236 {
 237         u32 tmp;
 238         int i;
 239
 240         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 241
 242         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 243                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 244                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 245                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 246
 247                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 248                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 249                               & RADEON_RB3D_DC_BUSY)) {
 250                                 return 0;
 251                         }
 252                         DRM_UDELAY(1);
 253                 }
 254         } else {
 255                 /* don't flush or purge cache here or lockup */
 256                 return 0;
 257         }
 258
 259 #if RADEON_FIFO_DEBUG
 260         DRM_ERROR("failed!\n");
 261         radeon_status(dev_priv);
 262 #endif
 263         return -EBUSY;
 264 }
 265
 266 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 267 {
 268         int i;
 269
 270         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 271
 272         for (i = 0; i < dev_priv->usec_timeout; i++) {
 273                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 274                              & RADEON_RBBM_FIFOCNT_MASK);
 275                 if (slots >= entries)
 276                         return 0;
 277                 DRM_UDELAY(1);
 278         }
 279         DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
 280                  RADEON_READ(RADEON_RBBM_STATUS),
 281                  RADEON_READ(R300_VAP_CNTL_STATUS));
 282
 283 #if RADEON_FIFO_DEBUG
 284         DRM_ERROR("failed!\n");
 285         radeon_status(dev_priv);
 286 #endif
 287         return -EBUSY;
 288 }
 289
 290 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 291 {
 292         int i, ret;
 293
 294         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 295
 296         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 297         if (ret)
 298                 return ret;
 299
 300         for (i = 0; i < dev_priv->usec_timeout; i++) {
 301                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 302                       & RADEON_RBBM_ACTIVE)) {
 303                         radeon_do_pixcache_flush(dev_priv);
 304                         return 0;
 305                 }
 306                 DRM_UDELAY(1);
 307         }
 308         DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
 309                  RADEON_READ(RADEON_RBBM_STATUS),
 310                  RADEON_READ(R300_VAP_CNTL_STATUS));
 311
 312 #if RADEON_FIFO_DEBUG
 313         DRM_ERROR("failed!\n");
 314         radeon_status(dev_priv);
 315 #endif
 316         return -EBUSY;
 317 }
 318
 319 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
 320 {
 321         uint32_t gb_tile_config, gb_pipe_sel = 0;
 322
 323         /* RS4xx/RS6xx/R4xx/R5xx */
 324         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 325                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 326                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 327         } else {
 328                 /* R3xx */
 329                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 330                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
 331                         dev_priv->num_gb_pipes = 2;
 332                 } else {
 333                         /* R3Vxx */
 334                         dev_priv->num_gb_pipes = 1;
 335                 }
 336         }
 337         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 338
 339         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 340
 341         switch (dev_priv->num_gb_pipes) {
 342         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 343         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 344         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 345         default:
 346         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 347         }
 348
 349         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 350                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 351                 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 352         }
 353         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 354         radeon_do_wait_for_idle(dev_priv);
 355         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 356         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 357                                                R300_DC_AUTOFLUSH_ENABLE |
 358                                                R300_DC_DC_DISABLE_IGNORE_PE));
 359
 360
 361 }
 362
 363 /* ================================================================
 364  * CP control, initialization
 365  */
 366
 367 /* Load the microcode for the CP */
 368 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 369 {
 370         int i;
 371         DRM_DEBUG("\n");
 372
 373         radeon_do_wait_for_idle(dev_priv);
 374
 375         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 376         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 377             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 378             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 379             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 380             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 381                 DRM_INFO("Loading R100 Microcode\n");
 382                 for (i = 0; i < 256; i++) {
 383                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 384                                      R100_cp_microcode[i][1]);
 385                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 386                                      R100_cp_microcode[i][0]);
 387                 }
 388         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 389                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 390                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 391                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 392                 DRM_INFO("Loading R200 Microcode\n");
 393                 for (i = 0; i < 256; i++) {
 394                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 395                                      R200_cp_microcode[i][1]);
 396                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 397                                      R200_cp_microcode[i][0]);
 398                 }
 399         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 400                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 401                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 402                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 403                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 404                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 405                 DRM_INFO("Loading R300 Microcode\n");
 406                 for (i = 0; i < 256; i++) {
 407                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 408                                      R300_cp_microcode[i][1]);
 409                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 410                                      R300_cp_microcode[i][0]);
 411                 }
 412         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 413                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
 414                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 415                 DRM_INFO("Loading R400 Microcode\n");
 416                 for (i = 0; i < 256; i++) {
 417                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 418                                      R420_cp_microcode[i][1]);
 419                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 420                                      R420_cp_microcode[i][0]);
 421                 }
 422         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 423                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 424                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 425                 for (i = 0; i < 256; i++) {
 426                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 427                                      RS690_cp_microcode[i][1]);
 428                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 429                                      RS690_cp_microcode[i][0]);
 430                 }
 431         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 432                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 433                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 434                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 435                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 436                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 437                 DRM_INFO("Loading R500 Microcode\n");
 438                 for (i = 0; i < 256; i++) {
 439                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 440                                      R520_cp_microcode[i][1]);
 441                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 442                                      R520_cp_microcode[i][0]);
 443                 }
 444         }
 445 }
 446
 447 /* Flush any pending commands to the CP.  This should only be used just
 448  * prior to a wait for idle, as it informs the engine that the command
 449  * stream is ending.
 450  */
 451 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 452 {
 453         DRM_DEBUG("\n");
 454 #if 0
 455         u32 tmp;
 456
 457         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 458         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 459 #endif
 460 }
 461
 462 /* Wait for the CP to go idle.
 463  */
 464 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 465 {
 466         RING_LOCALS;
 467         DRM_DEBUG("\n");
 468
 469         BEGIN_RING(6);
 470
 471         RADEON_PURGE_CACHE();
 472         RADEON_PURGE_ZCACHE();
 473         RADEON_WAIT_UNTIL_IDLE();
 474
 475         ADVANCE_RING();
 476         COMMIT_RING();
 477
 478         return radeon_do_wait_for_idle(dev_priv);
 479 }
 480
 481 /* Start the Command Processor.
 482  */
 483 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 484 {
 485         RING_LOCALS;
 486         DRM_DEBUG("\n");
 487
 488         radeon_do_wait_for_idle(dev_priv);
 489
 490         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 491
 492         dev_priv->cp_running = 1;
 493
 494         BEGIN_RING(8);
 495         /* isync can only be written through cp on r5xx write it here */
 496         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
 497         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
 498                  RADEON_ISYNC_ANY3D_IDLE2D |
 499                  RADEON_ISYNC_WAIT_IDLEGUI |
 500                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 501         RADEON_PURGE_CACHE();
 502         RADEON_PURGE_ZCACHE();
 503         RADEON_WAIT_UNTIL_IDLE();
 504         ADVANCE_RING();
 505         COMMIT_RING();
 506
 507         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 508 }
 509
 510 /* Reset the Command Processor.  This will not flush any pending
 511  * commands, so you must wait for the CP command stream to complete
 512  * before calling this routine.
 513  */
 514 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 515 {
 516         u32 cur_read_ptr;
 517         DRM_DEBUG("\n");
 518
 519         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 520         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 521         SET_RING_HEAD(dev_priv, cur_read_ptr);
 522         dev_priv->ring.tail = cur_read_ptr;
 523 }
 524
 525 /* Stop the Command Processor.  This will not flush any pending
 526  * commands, so you must flush the command stream and wait for the CP
 527  * to go idle before calling this routine.
 528  */
 529 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 530 {
 531         DRM_DEBUG("\n");
 532
 533         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 534
 535         dev_priv->cp_running = 0;
 536 }
 537
 538 /* Reset the engine.  This will stop the CP if it is running.
 539  */
 540 static int radeon_do_engine_reset(struct drm_device * dev)
 541 {
 542         drm_radeon_private_t *dev_priv = dev->dev_private;
 543         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 544         DRM_DEBUG("\n");
 545
 546         radeon_do_pixcache_flush(dev_priv);
 547
 548         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 549                 /* may need something similar for newer chips */
 550                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 551                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 552
 553                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 554                                                     RADEON_FORCEON_MCLKA |
 555                                                     RADEON_FORCEON_MCLKB |
 556                                                     RADEON_FORCEON_YCLKA |
 557                                                     RADEON_FORCEON_YCLKB |
 558                                                     RADEON_FORCEON_MC |
 559                                                     RADEON_FORCEON_AIC));
 560         }
 561
 562         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 563
 564         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 565                                               RADEON_SOFT_RESET_CP |
 566                                               RADEON_SOFT_RESET_HI |
 567                                               RADEON_SOFT_RESET_SE |
 568                                               RADEON_SOFT_RESET_RE |
 569                                               RADEON_SOFT_RESET_PP |
 570                                               RADEON_SOFT_RESET_E2 |
 571                                               RADEON_SOFT_RESET_RB));
 572         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 573         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 574                                               ~(RADEON_SOFT_RESET_CP |
 575                                                 RADEON_SOFT_RESET_HI |
 576                                                 RADEON_SOFT_RESET_SE |
 577                                                 RADEON_SOFT_RESET_RE |
 578                                                 RADEON_SOFT_RESET_PP |
 579                                                 RADEON_SOFT_RESET_E2 |
 580                                                 RADEON_SOFT_RESET_RB)));
 581         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 582
 583         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 584                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 585                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 586                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 587         }
 588
 589         /* setup the raster pipes */
 590         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 591             radeon_init_pipes(dev_priv);
 592
 593         /* Reset the CP ring */
 594         radeon_do_cp_reset(dev_priv);
 595
 596         /* The CP is no longer running after an engine reset */
 597         dev_priv->cp_running = 0;
 598
 599         /* Reset any pending vertex, indirect buffers */
 600         radeon_freelist_reset(dev);
 601
 602         return 0;
 603 }
 604
 605 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 606                                        drm_radeon_private_t *dev_priv,
 607                                        struct drm_file *file_priv)
 608 {
 609         struct drm_radeon_master_private *master_priv;
 610         u32 ring_start, cur_read_ptr;
 611         u32 tmp;
 612
 613         /* Initialize the memory controller. With new memory map, the fb location
 614          * is not changed, it should have been properly initialized already. Part
 615          * of the problem is that the code below is bogus, assuming the GART is
 616          * always appended to the fb which is not necessarily the case
 617          */
 618         if (!dev_priv->new_memmap)
 619                 radeon_write_fb_location(dev_priv,
 620                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 621                              | (dev_priv->fb_location >> 16));
 622
 623 #if __OS_HAS_AGP
 624         if (dev_priv->flags & RADEON_IS_AGP) {
 625                 radeon_write_agp_base(dev_priv, dev->agp->base);
 626
 627                 radeon_write_agp_location(dev_priv,
 628                              (((dev_priv->gart_vm_start - 1 +
 629                                 dev_priv->gart_size) & 0xffff0000) |
 630                               (dev_priv->gart_vm_start >> 16)));
 631
 632                 ring_start = (dev_priv->cp_ring->offset
 633                               - dev->agp->base
 634                               + dev_priv->gart_vm_start);
 635         } else
 636 #endif
 637                 ring_start = (dev_priv->cp_ring->offset
 638                               - (unsigned long)dev->sg->virtual
 639                               + dev_priv->gart_vm_start);
 640
 641         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 642
 643         /* Set the write pointer delay */
 644         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 645
 646         /* Initialize the ring buffer's read and write pointers */
 647         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 648         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 649         SET_RING_HEAD(dev_priv, cur_read_ptr);
 650         dev_priv->ring.tail = cur_read_ptr;
 651
 652 #if __OS_HAS_AGP
 653         if (dev_priv->flags & RADEON_IS_AGP) {
 654                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 655                              dev_priv->ring_rptr->offset
 656                              - dev->agp->base + dev_priv->gart_vm_start);
 657         } else
 658 #endif
 659         {
 660                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 661                              dev_priv->ring_rptr->offset
 662                              - ((unsigned long) dev->sg->virtual)
 663                              + dev_priv->gart_vm_start);
 664         }
 665
 666         /* Set ring buffer size */
 667 #ifdef __BIG_ENDIAN
 668         RADEON_WRITE(RADEON_CP_RB_CNTL,
 669                      RADEON_BUF_SWAP_32BIT |
 670                      (dev_priv->ring.fetch_size_l2ow << 18) |
 671                      (dev_priv->ring.rptr_update_l2qw << 8) |
 672                      dev_priv->ring.size_l2qw);
 673 #else
 674         RADEON_WRITE(RADEON_CP_RB_CNTL,
 675                      (dev_priv->ring.fetch_size_l2ow << 18) |
 676                      (dev_priv->ring.rptr_update_l2qw << 8) |
 677                      dev_priv->ring.size_l2qw);
 678 #endif
 679
 680
 681         /* Initialize the scratch register pointer.  This will cause
 682          * the scratch register values to be written out to memory
 683          * whenever they are updated.
 684          *
 685          * We simply put this behind the ring read pointer, this works
 686          * with PCI GART as well as (whatever kind of) AGP GART
 687          */
 688         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 689                      + RADEON_SCRATCH_REG_OFFSET);
 690
 691         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 692
 693         /* Turn on bus mastering */
 694         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 695             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 696                 /* rs600/rs690/rs740 */
 697                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 698                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 699         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
 700                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 701                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 702                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 703                 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 704                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 705                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 706         } /* PCIE cards appears to not need this */
 707
 708         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
 709         RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
 710
 711         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 712         RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
 713
 714         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
 715         RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
 716
 717         /* reset sarea copies of these */
 718         master_priv = file_priv->master->driver_priv;
 719         if (master_priv->sarea_priv) {
 720                 master_priv->sarea_priv->last_frame = 0;
 721                 master_priv->sarea_priv->last_dispatch = 0;
 722                 master_priv->sarea_priv->last_clear = 0;
 723         }
 724
 725         radeon_do_wait_for_idle(dev_priv);
 726
 727         /* Sync everything up */
 728         RADEON_WRITE(RADEON_ISYNC_CNTL,
 729                      (RADEON_ISYNC_ANY2D_IDLE3D |
 730                       RADEON_ISYNC_ANY3D_IDLE2D |
 731                       RADEON_ISYNC_WAIT_IDLEGUI |
 732                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 733
 734 }
 735
 736 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 737 {
 738         u32 tmp;
 739
 740         /* Start with assuming that writeback doesn't work */
 741         dev_priv->writeback_works = 0;
 742
 743         /* Writeback doesn't seem to work everywhere, test it here and possibly
 744          * enable it if it appears to work
 745          */
 746         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 747
 748         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 749
 750         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 751                 u32 val;
 752
 753                 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
 754                 if (val == 0xdeadbeef)
 755                         break;
 756                 DRM_UDELAY(1);
 757         }
 758
 759         if (tmp < dev_priv->usec_timeout) {
 760                 dev_priv->writeback_works = 1;
 761                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 762         } else {
 763                 dev_priv->writeback_works = 0;
 764                 DRM_INFO("writeback test failed\n");
 765         }
 766         if (radeon_no_wb == 1) {
 767                 dev_priv->writeback_works = 0;
 768                 DRM_INFO("writeback forced off\n");
 769         }
 770
 771         if (!dev_priv->writeback_works) {
 772                 /* Disable writeback to avoid unnecessary bus master transfer */
 773                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
 774                              RADEON_RB_NO_UPDATE);
 775                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 776         }
 777 }
 778
 779 /* Enable or disable IGP GART on the chip */
 780 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 781 {
 782         u32 temp;
 783
 784         if (on) {
 785                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 786                           dev_priv->gart_vm_start,
 787                           (long)dev_priv->gart_info.bus_addr,
 788                           dev_priv->gart_size);
 789
 790                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 791                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 792                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 793                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 794                                                              RS690_BLOCK_GFX_D3_EN));
 795                 else
 796                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 797
 798                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 799                                                                RS480_VA_SIZE_32MB));
 800
 801                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 802                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 803                                                         RS480_TLB_ENABLE |
 804                                                         RS480_GTW_LAC_EN |
 805                                                         RS480_1LEVEL_GART));
 806
 807                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 808                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 809                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 810
 811                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 812                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 813                                                       RS480_REQ_TYPE_SNOOP_DIS));
 814
 815                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 816
 817                 dev_priv->gart_size = 32*1024*1024;
 818                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 819                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 820
 821                 radeon_write_agp_location(dev_priv, temp);
 822
 823                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 824                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 825                                                                RS480_VA_SIZE_32MB));
 826
 827                 do {
 828                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 829                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 830                                 break;
 831                         DRM_UDELAY(1);
 832                 } while (1);
 833
 834                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 835                                 RS480_GART_CACHE_INVALIDATE);
 836
 837                 do {
 838                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 839                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 840                                 break;
 841                         DRM_UDELAY(1);
 842                 } while (1);
 843
 844                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 845         } else {
 846                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 847         }
 848 }
 849
 850 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 851 {
 852         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 853         if (on) {
 854
 855                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
 856                           dev_priv->gart_vm_start,
 857                           (long)dev_priv->gart_info.bus_addr,
 858                           dev_priv->gart_size);
 859                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
 860                                   dev_priv->gart_vm_start);
 861                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
 862                                   dev_priv->gart_info.bus_addr);
 863                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
 864                                   dev_priv->gart_vm_start);
 865                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
 866                                   dev_priv->gart_vm_start +
 867                                   dev_priv->gart_size - 1);
 868
 869                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
 870
 871                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 872                                   RADEON_PCIE_TX_GART_EN);
 873         } else {
 874                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 875                                   tmp & ~RADEON_PCIE_TX_GART_EN);
 876         }
 877 }
 878
 879 /* Enable or disable PCI GART on the chip */
 880 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 881 {
 882         u32 tmp;
 883
 884         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 885             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
 886             (dev_priv->flags & RADEON_IS_IGPGART)) {
 887                 radeon_set_igpgart(dev_priv, on);
 888                 return;
 889         }
 890
 891         if (dev_priv->flags & RADEON_IS_PCIE) {
 892                 radeon_set_pciegart(dev_priv, on);
 893                 return;
 894         }
 895
 896         tmp = RADEON_READ(RADEON_AIC_CNTL);
 897
 898         if (on) {
 899                 RADEON_WRITE(RADEON_AIC_CNTL,
 900                              tmp | RADEON_PCIGART_TRANSLATE_EN);
 901
 902                 /* set PCI GART page-table base address
 903                  */
 904                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
 905
 906                 /* set address range for PCI address translate
 907                  */
 908                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
 909                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
 910                              + dev_priv->gart_size - 1);
 911
 912                 /* Turn off AGP aperture -- is this required for PCI GART?
 913                  */
 914                 radeon_write_agp_location(dev_priv, 0xffffffc0);
 915                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
 916         } else {
 917                 RADEON_WRITE(RADEON_AIC_CNTL,
 918                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 919         }
 920 }
 921
 922 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
 923 {
 924         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
 925         struct radeon_virt_surface *vp;
 926         int i;
 927
 928         for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
 929                 if (!dev_priv->virt_surfaces[i].file_priv ||
 930                     dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
 931                         break;
 932         }
 933         if (i >= 2 * RADEON_MAX_SURFACES)
 934                 return -ENOMEM;
 935         vp = &dev_priv->virt_surfaces[i];
 936
 937         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
 938                 struct radeon_surface *sp = &dev_priv->surfaces[i];
 939                 if (sp->refcount)
 940                         continue;
 941
 942                 vp->surface_index = i;
 943                 vp->lower = gart_info->bus_addr;
 944                 vp->upper = vp->lower + gart_info->table_size;
 945                 vp->flags = 0;
 946                 vp->file_priv = PCIGART_FILE_PRIV;
 947
 948                 sp->refcount = 1;
 949                 sp->lower = vp->lower;
 950                 sp->upper = vp->upper;
 951                 sp->flags = 0;
 952
 953                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
 954                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
 955                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
 956                 return 0;
 957         }
 958
 959         return -ENOMEM;
 960 }
 961
 962 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
 963                              struct drm_file *file_priv)
 964 {
 965         drm_radeon_private_t *dev_priv = dev->dev_private;
 966         struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
 967
 968         DRM_DEBUG("\n");
 969
 970         /* if we require new memory map but we don't have it fail */
 971         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
 972                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
 973                 radeon_do_cleanup_cp(dev);
 974                 return -EINVAL;
 975         }
 976
 977         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
 978                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
 979                 dev_priv->flags &= ~RADEON_IS_AGP;
 980         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
 981                    && !init->is_pci) {
 982                 DRM_DEBUG("Restoring AGP flag\n");
 983                 dev_priv->flags |= RADEON_IS_AGP;
 984         }
 985
 986         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
 987                 DRM_ERROR("PCI GART memory not allocated!\n");
 988                 radeon_do_cleanup_cp(dev);
 989                 return -EINVAL;
 990         }
 991
 992         dev_priv->usec_timeout = init->usec_timeout;
 993         if (dev_priv->usec_timeout < 1 ||
 994             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
 995                 DRM_DEBUG("TIMEOUT problem!\n");
 996                 radeon_do_cleanup_cp(dev);
 997                 return -EINVAL;
 998         }
 999
1000         /* Enable vblank on CRTC1 for older X servers
1001          */
1002         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1003
1004         switch(init->func) {
1005         case RADEON_INIT_R200_CP:
1006                 dev_priv->microcode_version = UCODE_R200;
1007                 break;
1008         case RADEON_INIT_R300_CP:
1009                 dev_priv->microcode_version = UCODE_R300;
1010                 break;
1011         default:
1012                 dev_priv->microcode_version = UCODE_R100;
1013         }
1014
1015         dev_priv->do_boxes = 0;
1016         dev_priv->cp_mode = init->cp_mode;
1017
1018         /* We don't support anything other than bus-mastering ring mode,
1019          * but the ring can be in either AGP or PCI space for the ring
1020          * read pointer.
1021          */
1022         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1023             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1024                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1025                 radeon_do_cleanup_cp(dev);
1026                 return -EINVAL;
1027         }
1028
1029         switch (init->fb_bpp) {
1030         case 16:
1031                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1032                 break;
1033         case 32:
1034         default:
1035                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1036                 break;
1037         }
1038         dev_priv->front_offset = init->front_offset;
1039         dev_priv->front_pitch = init->front_pitch;
1040         dev_priv->back_offset = init->back_offset;
1041         dev_priv->back_pitch = init->back_pitch;
1042
1043         switch (init->depth_bpp) {
1044         case 16:
1045                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1046                 break;
1047         case 32:
1048         default:
1049                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1050                 break;
1051         }
1052         dev_priv->depth_offset = init->depth_offset;
1053         dev_priv->depth_pitch = init->depth_pitch;
1054
1055         /* Hardware state for depth clears.  Remove this if/when we no
1056          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1057          * all values to prevent unwanted 3D state from slipping through
1058          * and screwing with the clear operation.
1059          */
1060         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1061                                            (dev_priv->color_fmt << 10) |
1062                                            (dev_priv->microcode_version ==
1063                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1064
1065         dev_priv->depth_clear.rb3d_zstencilcntl =
1066             (dev_priv->depth_fmt |
1067              RADEON_Z_TEST_ALWAYS |
1068              RADEON_STENCIL_TEST_ALWAYS |
1069              RADEON_STENCIL_S_FAIL_REPLACE |
1070              RADEON_STENCIL_ZPASS_REPLACE |
1071              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1072
1073         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1074                                          RADEON_BFACE_SOLID |
1075                                          RADEON_FFACE_SOLID |
1076                                          RADEON_FLAT_SHADE_VTX_LAST |
1077                                          RADEON_DIFFUSE_SHADE_FLAT |
1078                                          RADEON_ALPHA_SHADE_FLAT |
1079                                          RADEON_SPECULAR_SHADE_FLAT |
1080                                          RADEON_FOG_SHADE_FLAT |
1081                                          RADEON_VTX_PIX_CENTER_OGL |
1082                                          RADEON_ROUND_MODE_TRUNC |
1083                                          RADEON_ROUND_PREC_8TH_PIX);
1084
1085
1086         dev_priv->ring_offset = init->ring_offset;
1087         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1088         dev_priv->buffers_offset = init->buffers_offset;
1089         dev_priv->gart_textures_offset = init->gart_textures_offset;
1090
1091         master_priv->sarea = drm_getsarea(dev);
1092         if (!master_priv->sarea) {
1093                 DRM_ERROR("could not find sarea!\n");
1094                 radeon_do_cleanup_cp(dev);
1095                 return -EINVAL;
1096         }
1097
1098         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1099         if (!dev_priv->cp_ring) {
1100                 DRM_ERROR("could not find cp ring region!\n");
1101                 radeon_do_cleanup_cp(dev);
1102                 return -EINVAL;
1103         }
1104         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1105         if (!dev_priv->ring_rptr) {
1106                 DRM_ERROR("could not find ring read pointer!\n");
1107                 radeon_do_cleanup_cp(dev);
1108                 return -EINVAL;
1109         }
1110         dev->agp_buffer_token = init->buffers_offset;
1111         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1112         if (!dev->agp_buffer_map) {
1113                 DRM_ERROR("could not find dma buffer region!\n");
1114                 radeon_do_cleanup_cp(dev);
1115                 return -EINVAL;
1116         }
1117
1118         if (init->gart_textures_offset) {
1119                 dev_priv->gart_textures =
1120                     drm_core_findmap(dev, init->gart_textures_offset);
1121                 if (!dev_priv->gart_textures) {
1122                         DRM_ERROR("could not find GART texture region!\n");
1123                         radeon_do_cleanup_cp(dev);
1124                         return -EINVAL;
1125                 }
1126         }
1127
1128 #if __OS_HAS_AGP
1129         if (dev_priv->flags & RADEON_IS_AGP) {
1130                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1131                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1132                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1133                 if (!dev_priv->cp_ring->handle ||
1134                     !dev_priv->ring_rptr->handle ||
1135                     !dev->agp_buffer_map->handle) {
1136                         DRM_ERROR("could not find ioremap agp regions!\n");
1137                         radeon_do_cleanup_cp(dev);
1138                         return -EINVAL;
1139                 }
1140         } else
1141 #endif
1142         {
1143                 dev_priv->cp_ring->handle =
1144                         (void *)(unsigned long)dev_priv->cp_ring->offset;
1145                 dev_priv->ring_rptr->handle =
1146                         (void *)(unsigned long)dev_priv->ring_rptr->offset;
1147                 dev->agp_buffer_map->handle =
1148                         (void *)(unsigned long)dev->agp_buffer_map->offset;
1149
1150                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1151                           dev_priv->cp_ring->handle);
1152                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1153                           dev_priv->ring_rptr->handle);
1154                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1155                           dev->agp_buffer_map->handle);
1156         }
1157
1158         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1159         dev_priv->fb_size =
1160                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1161                 - dev_priv->fb_location;
1162
1163         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1164                                         ((dev_priv->front_offset
1165                                           + dev_priv->fb_location) >> 10));
1166
1167         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1168                                        ((dev_priv->back_offset
1169                                          + dev_priv->fb_location) >> 10));
1170
1171         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1172                                         ((dev_priv->depth_offset
1173                                           + dev_priv->fb_location) >> 10));
1174
1175         dev_priv->gart_size = init->gart_size;
1176
1177         /* New let's set the memory map ... */
1178         if (dev_priv->new_memmap) {
1179                 u32 base = 0;
1180
1181                 DRM_INFO("Setting GART location based on new memory map\n");
1182
1183                 /* If using AGP, try to locate the AGP aperture at the same
1184                  * location in the card and on the bus, though we have to
1185                  * align it down.
1186                  */
1187 #if __OS_HAS_AGP
1188                 if (dev_priv->flags & RADEON_IS_AGP) {
1189                         base = dev->agp->base;
1190                         /* Check if valid */
1191                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1192                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1193                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1194                                          dev->agp->base);
1195                                 base = 0;
1196                         }
1197                 }
1198 #endif
1199                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1200                 if (base == 0) {
1201                         base = dev_priv->fb_location + dev_priv->fb_size;
1202                         if (base < dev_priv->fb_location ||
1203                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1204                                 base = dev_priv->fb_location
1205                                         - dev_priv->gart_size;
1206                 }
1207                 dev_priv->gart_vm_start = base & 0xffc00000u;
1208                 if (dev_priv->gart_vm_start != base)
1209                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1210                                  base, dev_priv->gart_vm_start);
1211         } else {
1212                 DRM_INFO("Setting GART location based on old memory map\n");
1213                 dev_priv->gart_vm_start = dev_priv->fb_location +
1214                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1215         }
1216
1217 #if __OS_HAS_AGP
1218         if (dev_priv->flags & RADEON_IS_AGP)
1219                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1220                                                  - dev->agp->base
1221                                                  + dev_priv->gart_vm_start);
1222         else
1223 #endif
1224                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1225                                         - (unsigned long)dev->sg->virtual
1226                                         + dev_priv->gart_vm_start);
1227
1228         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1229         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1230         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1231                   dev_priv->gart_buffers_offset);
1232
1233         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1234         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1235                               + init->ring_size / sizeof(u32));
1236         dev_priv->ring.size = init->ring_size;
1237         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1238
1239         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1240         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1241
1242         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1243         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1244         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1245
1246         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1247
1248 #if __OS_HAS_AGP
1249         if (dev_priv->flags & RADEON_IS_AGP) {
1250                 /* Turn off PCI GART */
1251                 radeon_set_pcigart(dev_priv, 0);
1252         } else
1253 #endif
1254         {
1255                 u32 sctrl;
1256                 int ret;
1257
1258                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1259                 /* if we have an offset set from userspace */
1260                 if (dev_priv->pcigart_offset_set) {
1261                         dev_priv->gart_info.bus_addr =
1262                                 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1263                         dev_priv->gart_info.mapping.offset =
1264                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1265                         dev_priv->gart_info.mapping.size =
1266                             dev_priv->gart_info.table_size;
1267
1268                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1269                         dev_priv->gart_info.addr =
1270                             dev_priv->gart_info.mapping.handle;
1271
1272                         if (dev_priv->flags & RADEON_IS_PCIE)
1273                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1274                         else
1275                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1276                         dev_priv->gart_info.gart_table_location =
1277                             DRM_ATI_GART_FB;
1278
1279                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1280                                   dev_priv->gart_info.addr,
1281                                   dev_priv->pcigart_offset);
1282                 } else {
1283                         if (dev_priv->flags & RADEON_IS_IGPGART)
1284                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1285                         else
1286                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1287                         dev_priv->gart_info.gart_table_location =
1288                             DRM_ATI_GART_MAIN;
1289                         dev_priv->gart_info.addr = NULL;
1290                         dev_priv->gart_info.bus_addr = 0;
1291                         if (dev_priv->flags & RADEON_IS_PCIE) {
1292                                 DRM_ERROR
1293                                     ("Cannot use PCI Express without GART in FB memory\n");
1294                                 radeon_do_cleanup_cp(dev);
1295                                 return -EINVAL;
1296                         }
1297                 }
1298
1299                 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1300                 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1301                 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1302                 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1303
1304                 if (!ret) {
1305                         DRM_ERROR("failed to init PCI GART!\n");
1306                         radeon_do_cleanup_cp(dev);
1307                         return -ENOMEM;
1308                 }
1309
1310                 ret = radeon_setup_pcigart_surface(dev_priv);
1311                 if (ret) {
1312                         DRM_ERROR("failed to setup GART surface!\n");
1313                         drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1314                         radeon_do_cleanup_cp(dev);
1315                         return ret;
1316                 }
1317
1318                 /* Turn on PCI GART */
1319                 radeon_set_pcigart(dev_priv, 1);
1320         }
1321
1322         radeon_cp_load_microcode(dev_priv);
1323         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1324
1325         dev_priv->last_buf = 0;
1326
1327         radeon_do_engine_reset(dev);
1328         radeon_test_writeback(dev_priv);
1329
1330         return 0;
1331 }
1332
1333 static int radeon_do_cleanup_cp(struct drm_device * dev)
1334 {
1335         drm_radeon_private_t *dev_priv = dev->dev_private;
1336         DRM_DEBUG("\n");
1337
1338         /* Make sure interrupts are disabled here because the uninstall ioctl
1339          * may not have been called from userspace and after dev_private
1340          * is freed, it's too late.
1341          */
1342         if (dev->irq_enabled)
1343                 drm_irq_uninstall(dev);
1344
1345 #if __OS_HAS_AGP
1346         if (dev_priv->flags & RADEON_IS_AGP) {
1347                 if (dev_priv->cp_ring != NULL) {
1348                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1349                         dev_priv->cp_ring = NULL;
1350                 }
1351                 if (dev_priv->ring_rptr != NULL) {
1352                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1353                         dev_priv->ring_rptr = NULL;
1354                 }
1355                 if (dev->agp_buffer_map != NULL) {
1356                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1357                         dev->agp_buffer_map = NULL;
1358                 }
1359         } else
1360 #endif
1361         {
1362
1363                 if (dev_priv->gart_info.bus_addr) {
1364                         /* Turn off PCI GART */
1365                         radeon_set_pcigart(dev_priv, 0);
1366                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1367                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1368                 }
1369
1370                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1371                 {
1372                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1373                         dev_priv->gart_info.addr = 0;
1374                 }
1375         }
1376         /* only clear to the start of flags */
1377         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1378
1379         return 0;
1380 }
1381
1382 /* This code will reinit the Radeon CP hardware after a resume from disc.
1383  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1384  * here we make sure that all Radeon hardware initialisation is re-done without
1385  * affecting running applications.
1386  *
1387  * Charl P. Botha <http://cpbotha.net>
1388  */
1389 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1390 {
1391         drm_radeon_private_t *dev_priv = dev->dev_private;
1392
1393         if (!dev_priv) {
1394                 DRM_ERROR("Called with no initialization\n");
1395                 return -EINVAL;
1396         }
1397
1398         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1399
1400 #if __OS_HAS_AGP
1401         if (dev_priv->flags & RADEON_IS_AGP) {
1402                 /* Turn off PCI GART */
1403                 radeon_set_pcigart(dev_priv, 0);
1404         } else
1405 #endif
1406         {
1407                 /* Turn on PCI GART */
1408                 radeon_set_pcigart(dev_priv, 1);
1409         }
1410
1411         radeon_cp_load_microcode(dev_priv);
1412         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1413
1414         radeon_do_engine_reset(dev);
1415         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1416
1417         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1418
1419         return 0;
1420 }
1421
1422 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1423 {
1424         drm_radeon_init_t *init = data;
1425
1426         LOCK_TEST_WITH_RETURN(dev, file_priv);
1427
1428         if (init->func == RADEON_INIT_R300_CP)
1429                 r300_init_reg_flags(dev);
1430
1431         switch (init->func) {
1432         case RADEON_INIT_CP:
1433         case RADEON_INIT_R200_CP:
1434         case RADEON_INIT_R300_CP:
1435                 return radeon_do_init_cp(dev, init, file_priv);
1436         case RADEON_CLEANUP_CP:
1437                 return radeon_do_cleanup_cp(dev);
1438         }
1439
1440         return -EINVAL;
1441 }
1442
1443 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1444 {
1445         drm_radeon_private_t *dev_priv = dev->dev_private;
1446         DRM_DEBUG("\n");
1447
1448         LOCK_TEST_WITH_RETURN(dev, file_priv);
1449
1450         if (dev_priv->cp_running) {
1451                 DRM_DEBUG("while CP running\n");
1452                 return 0;
1453         }
1454         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1455                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1456                           dev_priv->cp_mode);
1457                 return 0;
1458         }
1459
1460         radeon_do_cp_start(dev_priv);
1461
1462         return 0;
1463 }
1464
1465 /* Stop the CP.  The engine must have been idled before calling this
1466  * routine.
1467  */
1468 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1469 {
1470         drm_radeon_private_t *dev_priv = dev->dev_private;
1471         drm_radeon_cp_stop_t *stop = data;
1472         int ret;
1473         DRM_DEBUG("\n");
1474
1475         LOCK_TEST_WITH_RETURN(dev, file_priv);
1476
1477         if (!dev_priv->cp_running)
1478                 return 0;
1479
1480         /* Flush any pending CP commands.  This ensures any outstanding
1481          * commands are exectuted by the engine before we turn it off.
1482          */
1483         if (stop->flush) {
1484                 radeon_do_cp_flush(dev_priv);
1485         }
1486
1487         /* If we fail to make the engine go idle, we return an error
1488          * code so that the DRM ioctl wrapper can try again.
1489          */
1490         if (stop->idle) {
1491                 ret = radeon_do_cp_idle(dev_priv);
1492                 if (ret)
1493                         return ret;
1494         }
1495
1496         /* Finally, we can turn off the CP.  If the engine isn't idle,
1497          * we will get some dropped triangles as they won't be fully
1498          * rendered before the CP is shut down.
1499          */
1500         radeon_do_cp_stop(dev_priv);
1501
1502         /* Reset the engine */
1503         radeon_do_engine_reset(dev);
1504
1505         return 0;
1506 }
1507
1508 void radeon_do_release(struct drm_device * dev)
1509 {
1510         drm_radeon_private_t *dev_priv = dev->dev_private;
1511         int i, ret;
1512
1513         if (dev_priv) {
1514                 if (dev_priv->cp_running) {
1515                         /* Stop the cp */
1516                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1517                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1518 #ifdef __linux__
1519                                 schedule();
1520 #else
1521                                 tsleep(&ret, PZERO, "rdnrel", 1);
1522 #endif
1523                         }
1524                         radeon_do_cp_stop(dev_priv);
1525                         radeon_do_engine_reset(dev);
1526                 }
1527
1528                 /* Disable *all* interrupts */
1529                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1530                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1531
1532                 if (dev_priv->mmio) {   /* remove all surfaces */
1533                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1534                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1535                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1536                                              16 * i, 0);
1537                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1538                                              16 * i, 0);
1539                         }
1540                 }
1541
1542                 /* Free memory heap structures */
1543                 radeon_mem_takedown(&(dev_priv->gart_heap));
1544                 radeon_mem_takedown(&(dev_priv->fb_heap));
1545
1546                 /* deallocate kernel resources */
1547                 radeon_do_cleanup_cp(dev);
1548         }
1549 }
1550
1551 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1552  */
1553 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1554 {
1555         drm_radeon_private_t *dev_priv = dev->dev_private;
1556         DRM_DEBUG("\n");
1557
1558         LOCK_TEST_WITH_RETURN(dev, file_priv);
1559
1560         if (!dev_priv) {
1561                 DRM_DEBUG("called before init done\n");
1562                 return -EINVAL;
1563         }
1564
1565         radeon_do_cp_reset(dev_priv);
1566
1567         /* The CP is no longer running after an engine reset */
1568         dev_priv->cp_running = 0;
1569
1570         return 0;
1571 }
1572
1573 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1574 {
1575         drm_radeon_private_t *dev_priv = dev->dev_private;
1576         DRM_DEBUG("\n");
1577
1578         LOCK_TEST_WITH_RETURN(dev, file_priv);
1579
1580         return radeon_do_cp_idle(dev_priv);
1581 }
1582
1583 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1584  */
1585 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1586 {
1587         return radeon_do_resume_cp(dev, file_priv);
1588 }
1589
1590 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1591 {
1592         DRM_DEBUG("\n");
1593
1594         LOCK_TEST_WITH_RETURN(dev, file_priv);
1595
1596         return radeon_do_engine_reset(dev);
1597 }
1598
1599 /* ================================================================
1600  * Fullscreen mode
1601  */
1602
1603 /* KW: Deprecated to say the least:
1604  */
1605 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1606 {
1607         return 0;
1608 }
1609
1610 /* ================================================================
1611  * Freelist management
1612  */
1613
1614 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1615  *   bufs until freelist code is used.  Note this hides a problem with
1616  *   the scratch register * (used to keep track of last buffer
1617  *   completed) being written to before * the last buffer has actually
1618  *   completed rendering.
1619  *
1620  * KW:  It's also a good way to find free buffers quickly.
1621  *
1622  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1623  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1624  * we essentially have to do this, else old clients will break.
1625  *
1626  * However, it does leave open a potential deadlock where all the
1627  * buffers are held by other clients, which can't release them because
1628  * they can't get the lock.
1629  */
1630
1631 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1632 {
1633         struct drm_device_dma *dma = dev->dma;
1634         drm_radeon_private_t *dev_priv = dev->dev_private;
1635         drm_radeon_buf_priv_t *buf_priv;
1636         struct drm_buf *buf;
1637         int i, t;
1638         int start;
1639
1640         if (++dev_priv->last_buf >= dma->buf_count)
1641                 dev_priv->last_buf = 0;
1642
1643         start = dev_priv->last_buf;
1644
1645         for (t = 0; t < dev_priv->usec_timeout; t++) {
1646                 u32 done_age = GET_SCRATCH(dev_priv, 1);
1647                 DRM_DEBUG("done_age = %d\n", done_age);
1648                 for (i = start; i < dma->buf_count; i++) {
1649                         buf = dma->buflist[i];
1650                         buf_priv = buf->dev_private;
1651                         if (buf->file_priv == NULL || (buf->pending &&
1652                                                        buf_priv->age <=
1653                                                        done_age)) {
1654                                 dev_priv->stats.requested_bufs++;
1655                                 buf->pending = 0;
1656                                 return buf;
1657                         }
1658                         start = 0;
1659                 }
1660
1661                 if (t) {
1662                         DRM_UDELAY(1);
1663                         dev_priv->stats.freelist_loops++;
1664                 }
1665         }
1666
1667         DRM_DEBUG("returning NULL!\n");
1668         return NULL;
1669 }
1670
1671 #if 0
1672 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1673 {
1674         struct drm_device_dma *dma = dev->dma;
1675         drm_radeon_private_t *dev_priv = dev->dev_private;
1676         drm_radeon_buf_priv_t *buf_priv;
1677         struct drm_buf *buf;
1678         int i, t;
1679         int start;
1680         u32 done_age;
1681
1682         done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
1683         if (++dev_priv->last_buf >= dma->buf_count)
1684                 dev_priv->last_buf = 0;
1685
1686         start = dev_priv->last_buf;
1687         dev_priv->stats.freelist_loops++;
1688
1689         for (t = 0; t < 2; t++) {
1690                 for (i = start; i < dma->buf_count; i++) {
1691                         buf = dma->buflist[i];
1692                         buf_priv = buf->dev_private;
1693                         if (buf->file_priv == 0 || (buf->pending &&
1694                                                     buf_priv->age <=
1695                                                     done_age)) {
1696                                 dev_priv->stats.requested_bufs++;
1697                                 buf->pending = 0;
1698                                 return buf;
1699                         }
1700                 }
1701                 start = 0;
1702         }
1703
1704         return NULL;
1705 }
1706 #endif
1707
1708 void radeon_freelist_reset(struct drm_device * dev)
1709 {
1710         struct drm_device_dma *dma = dev->dma;
1711         drm_radeon_private_t *dev_priv = dev->dev_private;
1712         int i;
1713
1714         dev_priv->last_buf = 0;
1715         for (i = 0; i < dma->buf_count; i++) {
1716                 struct drm_buf *buf = dma->buflist[i];
1717                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1718                 buf_priv->age = 0;
1719         }
1720 }
1721
1722 /* ================================================================
1723  * CP command submission
1724  */
1725
1726 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1727 {
1728         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1729         int i;
1730         u32 last_head = GET_RING_HEAD(dev_priv);
1731
1732         for (i = 0; i < dev_priv->usec_timeout; i++) {
1733                 u32 head = GET_RING_HEAD(dev_priv);
1734
1735                 ring->space = (head - ring->tail) * sizeof(u32);
1736                 if (ring->space <= 0)
1737                         ring->space += ring->size;
1738                 if (ring->space > n)
1739                         return 0;
1740
1741                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1742
1743                 if (head != last_head)
1744                         i = 0;
1745                 last_head = head;
1746
1747                 DRM_UDELAY(1);
1748         }
1749
1750         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1751 #if RADEON_FIFO_DEBUG
1752         radeon_status(dev_priv);
1753         DRM_ERROR("failed!\n");
1754 #endif
1755         return -EBUSY;
1756 }
1757
1758 static int radeon_cp_get_buffers(struct drm_device *dev,
1759                                  struct drm_file *file_priv,
1760                                  struct drm_dma * d)
1761 {
1762         int i;
1763         struct drm_buf *buf;
1764
1765         for (i = d->granted_count; i < d->request_count; i++) {
1766                 buf = radeon_freelist_get(dev);
1767                 if (!buf)
1768                         return -EBUSY;  /* NOTE: broken client */
1769
1770                 buf->file_priv = file_priv;
1771
1772                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1773                                      sizeof(buf->idx)))
1774                         return -EFAULT;
1775                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1776                                      sizeof(buf->total)))
1777                         return -EFAULT;
1778
1779                 d->granted_count++;
1780         }
1781         return 0;
1782 }
1783
1784 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1785 {
1786         struct drm_device_dma *dma = dev->dma;
1787         int ret = 0;
1788         struct drm_dma *d = data;
1789
1790         LOCK_TEST_WITH_RETURN(dev, file_priv);
1791
1792         /* Please don't send us buffers.
1793          */
1794         if (d->send_count != 0) {
1795                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1796                           DRM_CURRENTPID, d->send_count);
1797                 return -EINVAL;
1798         }
1799
1800         /* We'll send you buffers.
1801          */
1802         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1803                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1804                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1805                 return -EINVAL;
1806         }
1807
1808         d->granted_count = 0;
1809
1810         if (d->request_count) {
1811                 ret = radeon_cp_get_buffers(dev, file_priv, d);
1812         }
1813
1814         return ret;
1815 }
1816
1817 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1818 {
1819         drm_radeon_private_t *dev_priv;
1820         int ret = 0;
1821
1822         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1823         if (dev_priv == NULL)
1824                 return -ENOMEM;
1825
1826         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1827         dev->dev_private = (void *)dev_priv;
1828         dev_priv->flags = flags;
1829
1830         switch (flags & RADEON_FAMILY_MASK) {
1831         case CHIP_R100:
1832         case CHIP_RV200:
1833         case CHIP_R200:
1834         case CHIP_R300:
1835         case CHIP_R350:
1836         case CHIP_R420:
1837         case CHIP_R423:
1838         case CHIP_RV410:
1839         case CHIP_RV515:
1840         case CHIP_R520:
1841         case CHIP_RV570:
1842         case CHIP_R580:
1843                 dev_priv->flags |= RADEON_HAS_HIERZ;
1844                 break;
1845         default:
1846                 /* all other chips have no hierarchical z buffer */
1847                 break;
1848         }
1849
1850         if (drm_device_is_agp(dev))
1851                 dev_priv->flags |= RADEON_IS_AGP;
1852         else if (drm_device_is_pcie(dev))
1853                 dev_priv->flags |= RADEON_IS_PCIE;
1854         else
1855                 dev_priv->flags |= RADEON_IS_PCI;
1856
1857         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1858                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1859                          _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
1860         if (ret != 0)
1861                 return ret;
1862
1863         ret = drm_vblank_init(dev, 2);
1864         if (ret) {
1865                 radeon_driver_unload(dev);
1866                 return ret;
1867         }
1868
1869         DRM_DEBUG("%s card detected\n",
1870                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1871         return ret;
1872 }
1873
1874 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
1875 {
1876         struct drm_radeon_master_private *master_priv;
1877         unsigned long sareapage;
1878         int ret;
1879
1880         master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
1881         if (!master_priv)
1882                 return -ENOMEM;
1883
1884         /* prebuild the SAREA */
1885         sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
1886         ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
1887                          &master_priv->sarea);
1888         if (ret) {
1889                 DRM_ERROR("SAREA setup failed\n");
1890                 return ret;
1891         }
1892         master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
1893         master_priv->sarea_priv->pfCurrentPage = 0;
1894
1895         master->driver_priv = master_priv;
1896         return 0;
1897 }
1898
1899 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
1900 {
1901         struct drm_radeon_master_private *master_priv = master->driver_priv;
1902
1903         if (!master_priv)
1904                 return;
1905
1906         if (master_priv->sarea_priv &&
1907             master_priv->sarea_priv->pfCurrentPage != 0)
1908                 radeon_cp_dispatch_flip(dev, master);
1909
1910         master_priv->sarea_priv = NULL;
1911         if (master_priv->sarea)
1912                 drm_rmmap_locked(dev, master_priv->sarea);
1913
1914         drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
1915
1916         master->driver_priv = NULL;
1917 }
1918
1919 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1920  * have to find them.
1921  */
1922 int radeon_driver_firstopen(struct drm_device *dev)
1923 {
1924         int ret;
1925         drm_local_map_t *map;
1926         drm_radeon_private_t *dev_priv = dev->dev_private;
1927
1928         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1929
1930         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1931         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1932                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1933                          _DRM_WRITE_COMBINING, &map);
1934         if (ret != 0)
1935                 return ret;
1936
1937         return 0;
1938 }
1939
1940 int radeon_driver_unload(struct drm_device *dev)
1941 {
1942         drm_radeon_private_t *dev_priv = dev->dev_private;
1943
1944         DRM_DEBUG("\n");
1945
1946         drm_rmmap(dev, dev_priv->mmio);
1947
1948         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1949
1950         dev->dev_private = NULL;
1951         return 0;
1952 }
1953
1954 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
1955 {
1956         int i;
1957         u32 *ring;
1958         int tail_aligned;
1959
1960         /* check if the ring is padded out to 16-dword alignment */
1961
1962         tail_aligned = dev_priv->ring.tail & 0xf;
1963         if (tail_aligned) {
1964                 int num_p2 = 16 - tail_aligned;
1965
1966                 ring = dev_priv->ring.start;
1967                 /* pad with some CP_PACKET2 */
1968                 for (i = 0; i < num_p2; i++)
1969                         ring[dev_priv->ring.tail + i] = CP_PACKET2();
1970
1971                 dev_priv->ring.tail += i;
1972
1973                 dev_priv->ring.space -= num_p2 * sizeof(u32);
1974         }
1975
1976         dev_priv->ring.tail &= dev_priv->ring.tail_mask;
1977
1978         DRM_MEMORYBARRIER();
1979         GET_RING_HEAD( dev_priv );
1980
1981         RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail );
1982         /* read from PCI bus to ensure correct posting */
1983         RADEON_READ( RADEON_CP_RB_RPTR );
1984 }