drivers/gpu/drm/radeon/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2007 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  */
  31
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "drm_sarea.h"
  35 #include "radeon_drm.h"
  36 #include "radeon_drv.h"
  37 #include "r300_reg.h"
  38
  39 #define RADEON_FIFO_DEBUG       0
  40
  41 /* Firmware Names */
  42 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  43 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  44 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  45 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  46 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  47 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  48 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  49
  50 MODULE_FIRMWARE(FIRMWARE_R100);
  51 MODULE_FIRMWARE(FIRMWARE_R200);
  52 MODULE_FIRMWARE(FIRMWARE_R300);
  53 MODULE_FIRMWARE(FIRMWARE_R420);
  54 MODULE_FIRMWARE(FIRMWARE_RS690);
  55 MODULE_FIRMWARE(FIRMWARE_RS600);
  56 MODULE_FIRMWARE(FIRMWARE_R520);
  57
  58 static int radeon_do_cleanup_cp(struct drm_device * dev);
  59 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
  60
  61 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
  62 {
  63         u32 val;
  64
  65         if (dev_priv->flags & RADEON_IS_AGP) {
  66                 val = DRM_READ32(dev_priv->ring_rptr, off);
  67         } else {
  68                 val = *(((volatile u32 *)
  69                          dev_priv->ring_rptr->handle) +
  70                         (off / sizeof(u32)));
  71                 val = le32_to_cpu(val);
  72         }
  73         return val;
  74 }
  75
  76 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
  77 {
  78         if (dev_priv->writeback_works)
  79                 return radeon_read_ring_rptr(dev_priv, 0);
  80         else {
  81                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  82                         return RADEON_READ(R600_CP_RB_RPTR);
  83                 else
  84                         return RADEON_READ(RADEON_CP_RB_RPTR);
  85         }
  86 }
  87
  88 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
  89 {
  90         if (dev_priv->flags & RADEON_IS_AGP)
  91                 DRM_WRITE32(dev_priv->ring_rptr, off, val);
  92         else
  93                 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
  94                   (off / sizeof(u32))) = cpu_to_le32(val);
  95 }
  96
  97 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
  98 {
  99         radeon_write_ring_rptr(dev_priv, 0, val);
 100 }
 101
 102 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
 103 {
 104         if (dev_priv->writeback_works) {
 105                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 106                         return radeon_read_ring_rptr(dev_priv,
 107                                                      R600_SCRATCHOFF(index));
 108                 else
 109                         return radeon_read_ring_rptr(dev_priv,
 110                                                      RADEON_SCRATCHOFF(index));
 111         } else {
 112                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 113                         return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
 114                 else
 115                         return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
 116         }
 117 }
 118
 119 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
 120 {
 121         u32 ret;
 122
 123         if (addr < 0x10000)
 124                 ret = DRM_READ32(dev_priv->mmio, addr);
 125         else {
 126                 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
 127                 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
 128         }
 129
 130         return ret;
 131 }
 132
 133 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 134 {
 135         u32 ret;
 136         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
 137         ret = RADEON_READ(R520_MC_IND_DATA);
 138         RADEON_WRITE(R520_MC_IND_INDEX, 0);
 139         return ret;
 140 }
 141
 142 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 143 {
 144         u32 ret;
 145         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
 146         ret = RADEON_READ(RS480_NB_MC_DATA);
 147         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
 148         return ret;
 149 }
 150
 151 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 152 {
 153         u32 ret;
 154         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
 155         ret = RADEON_READ(RS690_MC_DATA);
 156         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
 157         return ret;
 158 }
 159
 160 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 161 {
 162         u32 ret;
 163         RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
 164                                       RS600_MC_IND_CITF_ARB0));
 165         ret = RADEON_READ(RS600_MC_DATA);
 166         return ret;
 167 }
 168
 169 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 170 {
 171         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 172             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 173                 return RS690_READ_MCIND(dev_priv, addr);
 174         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 175                 return RS600_READ_MCIND(dev_priv, addr);
 176         else
 177                 return RS480_READ_MCIND(dev_priv, addr);
 178 }
 179
 180 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 181 {
 182
 183         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 184                 return RADEON_READ(R700_MC_VM_FB_LOCATION);
 185         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 186                 return RADEON_READ(R600_MC_VM_FB_LOCATION);
 187         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 188                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
 189         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 190                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 191                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
 192         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 193                 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
 194         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 195                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
 196         else
 197                 return RADEON_READ(RADEON_MC_FB_LOCATION);
 198 }
 199
 200 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 201 {
 202         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 203                 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
 204         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 205                 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
 206         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 207                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
 208         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 209                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 210                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 211         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 212                 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
 213         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 214                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 215         else
 216                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 217 }
 218
 219 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 220 {
 221         /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
 222         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
 223                 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 224                 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 225         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
 226                 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 227                 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 228         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 229                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 230         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 231                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 232                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 233         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 234                 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
 235         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 236                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 237         else
 238                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 239 }
 240
 241 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 242 {
 243         u32 agp_base_hi = upper_32_bits(agp_base);
 244         u32 agp_base_lo = agp_base & 0xffffffff;
 245         u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
 246
 247         /* R6xx/R7xx must be aligned to a 4MB boundry */
 248         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 249                 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
 250         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 251                 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
 252         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 253                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 254                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 255         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 256                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 257                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 258                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 259         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
 260                 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
 261                 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
 262         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 263                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 264                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 265         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 266                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 267                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 268                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
 269         } else {
 270                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 271                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 272                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 273         }
 274 }
 275
 276 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
 277 {
 278         u32 tmp;
 279         /* Turn on bus mastering */
 280         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 281             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 282                 /* rs600/rs690/rs740 */
 283                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 284                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 285         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
 286                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 287                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 288                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 289                 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 290                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 291                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 292         } /* PCIE cards appears to not need this */
 293 }
 294
 295 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 296 {
 297         drm_radeon_private_t *dev_priv = dev->dev_private;
 298
 299         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 300         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 301 }
 302
 303 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 304 {
 305         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 306         return RADEON_READ(RADEON_PCIE_DATA);
 307 }
 308
 309 #if RADEON_FIFO_DEBUG
 310 static void radeon_status(drm_radeon_private_t * dev_priv)
 311 {
 312         printk("%s:\n", __func__);
 313         printk("RBBM_STATUS = 0x%08x\n",
 314                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 315         printk("CP_RB_RTPR = 0x%08x\n",
 316                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 317         printk("CP_RB_WTPR = 0x%08x\n",
 318                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 319         printk("AIC_CNTL = 0x%08x\n",
 320                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 321         printk("AIC_STAT = 0x%08x\n",
 322                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 323         printk("AIC_PT_BASE = 0x%08x\n",
 324                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 325         printk("TLB_ADDR = 0x%08x\n",
 326                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 327         printk("TLB_DATA = 0x%08x\n",
 328                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 329 }
 330 #endif
 331
 332 /* ================================================================
 333  * Engine, FIFO control
 334  */
 335
 336 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 337 {
 338         u32 tmp;
 339         int i;
 340
 341         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 342
 343         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 344                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 345                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 346                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 347
 348                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 349                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 350                               & RADEON_RB3D_DC_BUSY)) {
 351                                 return 0;
 352                         }
 353                         DRM_UDELAY(1);
 354                 }
 355         } else {
 356                 /* don't flush or purge cache here or lockup */
 357                 return 0;
 358         }
 359
 360 #if RADEON_FIFO_DEBUG
 361         DRM_ERROR("failed!\n");
 362         radeon_status(dev_priv);
 363 #endif
 364         return -EBUSY;
 365 }
 366
 367 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 368 {
 369         int i;
 370
 371         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 372
 373         for (i = 0; i < dev_priv->usec_timeout; i++) {
 374                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 375                              & RADEON_RBBM_FIFOCNT_MASK);
 376                 if (slots >= entries)
 377                         return 0;
 378                 DRM_UDELAY(1);
 379         }
 380         DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
 381                  RADEON_READ(RADEON_RBBM_STATUS),
 382                  RADEON_READ(R300_VAP_CNTL_STATUS));
 383
 384 #if RADEON_FIFO_DEBUG
 385         DRM_ERROR("failed!\n");
 386         radeon_status(dev_priv);
 387 #endif
 388         return -EBUSY;
 389 }
 390
 391 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 392 {
 393         int i, ret;
 394
 395         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 396
 397         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 398         if (ret)
 399                 return ret;
 400
 401         for (i = 0; i < dev_priv->usec_timeout; i++) {
 402                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 403                       & RADEON_RBBM_ACTIVE)) {
 404                         radeon_do_pixcache_flush(dev_priv);
 405                         return 0;
 406                 }
 407                 DRM_UDELAY(1);
 408         }
 409         DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
 410                  RADEON_READ(RADEON_RBBM_STATUS),
 411                  RADEON_READ(R300_VAP_CNTL_STATUS));
 412
 413 #if RADEON_FIFO_DEBUG
 414         DRM_ERROR("failed!\n");
 415         radeon_status(dev_priv);
 416 #endif
 417         return -EBUSY;
 418 }
 419
 420 static void radeon_init_pipes(struct drm_device *dev)
 421 {
 422         drm_radeon_private_t *dev_priv = dev->dev_private;
 423         uint32_t gb_tile_config, gb_pipe_sel = 0;
 424
 425         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
 426                 uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
 427                 if ((z_pipe_sel & 3) == 3)
 428                         dev_priv->num_z_pipes = 2;
 429                 else
 430                         dev_priv->num_z_pipes = 1;
 431         } else
 432                 dev_priv->num_z_pipes = 1;
 433
 434         /* RS4xx/RS6xx/R4xx/R5xx */
 435         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 436                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 437                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 438         } else {
 439                 /* R3xx */
 440                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
 441                      dev->pdev->device != 0x4144) ||
 442                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
 443                         dev_priv->num_gb_pipes = 2;
 444                 } else {
 445                         /* RV3xx/R300 AD */
 446                         dev_priv->num_gb_pipes = 1;
 447                 }
 448         }
 449         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 450
 451         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 452
 453         switch (dev_priv->num_gb_pipes) {
 454         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 455         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 456         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 457         default:
 458         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 459         }
 460
 461         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 462                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 463                 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 464         }
 465         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 466         radeon_do_wait_for_idle(dev_priv);
 467         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 468         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 469                                                R300_DC_AUTOFLUSH_ENABLE |
 470                                                R300_DC_DC_DISABLE_IGNORE_PE));
 471
 472
 473 }
 474
 475 /* ================================================================
 476  * CP control, initialization
 477  */
 478
 479 /* Load the microcode for the CP */
 480 static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
 481 {
 482         struct platform_device *pdev;
 483         const char *fw_name = NULL;
 484         int err;
 485
 486         DRM_DEBUG("\n");
 487
 488         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 489         err = IS_ERR(pdev);
 490         if (err) {
 491                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 492                 return -EINVAL;
 493         }
 494
 495         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 496             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 497             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 498             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 499             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 500                 DRM_INFO("Loading R100 Microcode\n");
 501                 fw_name = FIRMWARE_R100;
 502         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 503                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 504                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 505                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 506                 DRM_INFO("Loading R200 Microcode\n");
 507                 fw_name = FIRMWARE_R200;
 508         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 509                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 510                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 511                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 512                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 513                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 514                 DRM_INFO("Loading R300 Microcode\n");
 515                 fw_name = FIRMWARE_R300;
 516         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 517                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
 518                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 519                 DRM_INFO("Loading R400 Microcode\n");
 520                 fw_name = FIRMWARE_R420;
 521         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 522                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 523                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 524                 fw_name = FIRMWARE_RS690;
 525         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
 526                 DRM_INFO("Loading RS600 Microcode\n");
 527                 fw_name = FIRMWARE_RS600;
 528         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 529                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 530                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 531                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 532                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 533                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 534                 DRM_INFO("Loading R500 Microcode\n");
 535                 fw_name = FIRMWARE_R520;
 536         }
 537
 538         err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
 539         platform_device_unregister(pdev);
 540         if (err) {
 541                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 542                        fw_name);
 543         } else if (dev_priv->me_fw->size % 8) {
 544                 printk(KERN_ERR
 545                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 546                        dev_priv->me_fw->size, fw_name);
 547                 err = -EINVAL;
 548                 release_firmware(dev_priv->me_fw);
 549                 dev_priv->me_fw = NULL;
 550         }
 551         return err;
 552 }
 553
 554 static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
 555 {
 556         const __be32 *fw_data;
 557         int i, size;
 558
 559         radeon_do_wait_for_idle(dev_priv);
 560
 561         if (dev_priv->me_fw) {
 562                 size = dev_priv->me_fw->size / 4;
 563                 fw_data = (const __be32 *)&dev_priv->me_fw->data[0];
 564                 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 565                 for (i = 0; i < size; i += 2) {
 566                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 567                                      be32_to_cpup(&fw_data[i]));
 568                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 569                                      be32_to_cpup(&fw_data[i + 1]));
 570                 }
 571         }
 572 }
 573
 574 /* Flush any pending commands to the CP.  This should only be used just
 575  * prior to a wait for idle, as it informs the engine that the command
 576  * stream is ending.
 577  */
 578 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 579 {
 580         DRM_DEBUG("\n");
 581 #if 0
 582         u32 tmp;
 583
 584         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 585         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 586 #endif
 587 }
 588
 589 /* Wait for the CP to go idle.
 590  */
 591 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 592 {
 593         RING_LOCALS;
 594         DRM_DEBUG("\n");
 595
 596         BEGIN_RING(6);
 597
 598         RADEON_PURGE_CACHE();
 599         RADEON_PURGE_ZCACHE();
 600         RADEON_WAIT_UNTIL_IDLE();
 601
 602         ADVANCE_RING();
 603         COMMIT_RING();
 604
 605         return radeon_do_wait_for_idle(dev_priv);
 606 }
 607
 608 /* Start the Command Processor.
 609  */
 610 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 611 {
 612         RING_LOCALS;
 613         DRM_DEBUG("\n");
 614
 615         radeon_do_wait_for_idle(dev_priv);
 616
 617         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 618
 619         dev_priv->cp_running = 1;
 620
 621         /* on r420, any DMA from CP to system memory while 2D is active
 622          * can cause a hang.  workaround is to queue a CP RESYNC token
 623          */
 624         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
 625                 BEGIN_RING(3);
 626                 OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
 627                 OUT_RING(5); /* scratch reg 5 */
 628                 OUT_RING(0xdeadbeef);
 629                 ADVANCE_RING();
 630                 COMMIT_RING();
 631         }
 632
 633         BEGIN_RING(8);
 634         /* isync can only be written through cp on r5xx write it here */
 635         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
 636         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
 637                  RADEON_ISYNC_ANY3D_IDLE2D |
 638                  RADEON_ISYNC_WAIT_IDLEGUI |
 639                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 640         RADEON_PURGE_CACHE();
 641         RADEON_PURGE_ZCACHE();
 642         RADEON_WAIT_UNTIL_IDLE();
 643         ADVANCE_RING();
 644         COMMIT_RING();
 645
 646         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 647 }
 648
 649 /* Reset the Command Processor.  This will not flush any pending
 650  * commands, so you must wait for the CP command stream to complete
 651  * before calling this routine.
 652  */
 653 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 654 {
 655         u32 cur_read_ptr;
 656         DRM_DEBUG("\n");
 657
 658         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 659         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 660         SET_RING_HEAD(dev_priv, cur_read_ptr);
 661         dev_priv->ring.tail = cur_read_ptr;
 662 }
 663
 664 /* Stop the Command Processor.  This will not flush any pending
 665  * commands, so you must flush the command stream and wait for the CP
 666  * to go idle before calling this routine.
 667  */
 668 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 669 {
 670         RING_LOCALS;
 671         DRM_DEBUG("\n");
 672
 673         /* finish the pending CP_RESYNC token */
 674         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
 675                 BEGIN_RING(2);
 676                 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 677                 OUT_RING(R300_RB3D_DC_FINISH);
 678                 ADVANCE_RING();
 679                 COMMIT_RING();
 680                 radeon_do_wait_for_idle(dev_priv);
 681         }
 682
 683         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 684
 685         dev_priv->cp_running = 0;
 686 }
 687
 688 /* Reset the engine.  This will stop the CP if it is running.
 689  */
 690 static int radeon_do_engine_reset(struct drm_device * dev)
 691 {
 692         drm_radeon_private_t *dev_priv = dev->dev_private;
 693         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 694         DRM_DEBUG("\n");
 695
 696         radeon_do_pixcache_flush(dev_priv);
 697
 698         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 699                 /* may need something similar for newer chips */
 700                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 701                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 702
 703                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 704                                                     RADEON_FORCEON_MCLKA |
 705                                                     RADEON_FORCEON_MCLKB |
 706                                                     RADEON_FORCEON_YCLKA |
 707                                                     RADEON_FORCEON_YCLKB |
 708                                                     RADEON_FORCEON_MC |
 709                                                     RADEON_FORCEON_AIC));
 710         }
 711
 712         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 713
 714         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 715                                               RADEON_SOFT_RESET_CP |
 716                                               RADEON_SOFT_RESET_HI |
 717                                               RADEON_SOFT_RESET_SE |
 718                                               RADEON_SOFT_RESET_RE |
 719                                               RADEON_SOFT_RESET_PP |
 720                                               RADEON_SOFT_RESET_E2 |
 721                                               RADEON_SOFT_RESET_RB));
 722         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 723         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 724                                               ~(RADEON_SOFT_RESET_CP |
 725                                                 RADEON_SOFT_RESET_HI |
 726                                                 RADEON_SOFT_RESET_SE |
 727                                                 RADEON_SOFT_RESET_RE |
 728                                                 RADEON_SOFT_RESET_PP |
 729                                                 RADEON_SOFT_RESET_E2 |
 730                                                 RADEON_SOFT_RESET_RB)));
 731         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 732
 733         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 734                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 735                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 736                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 737         }
 738
 739         /* setup the raster pipes */
 740         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 741             radeon_init_pipes(dev);
 742
 743         /* Reset the CP ring */
 744         radeon_do_cp_reset(dev_priv);
 745
 746         /* The CP is no longer running after an engine reset */
 747         dev_priv->cp_running = 0;
 748
 749         /* Reset any pending vertex, indirect buffers */
 750         radeon_freelist_reset(dev);
 751
 752         return 0;
 753 }
 754
 755 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 756                                        drm_radeon_private_t *dev_priv,
 757                                        struct drm_file *file_priv)
 758 {
 759         struct drm_radeon_master_private *master_priv;
 760         u32 ring_start, cur_read_ptr;
 761
 762         /* Initialize the memory controller. With new memory map, the fb location
 763          * is not changed, it should have been properly initialized already. Part
 764          * of the problem is that the code below is bogus, assuming the GART is
 765          * always appended to the fb which is not necessarily the case
 766          */
 767         if (!dev_priv->new_memmap)
 768                 radeon_write_fb_location(dev_priv,
 769                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 770                              | (dev_priv->fb_location >> 16));
 771
 772 #if __OS_HAS_AGP
 773         if (dev_priv->flags & RADEON_IS_AGP) {
 774                 radeon_write_agp_base(dev_priv, dev->agp->base);
 775
 776                 radeon_write_agp_location(dev_priv,
 777                              (((dev_priv->gart_vm_start - 1 +
 778                                 dev_priv->gart_size) & 0xffff0000) |
 779                               (dev_priv->gart_vm_start >> 16)));
 780
 781                 ring_start = (dev_priv->cp_ring->offset
 782                               - dev->agp->base
 783                               + dev_priv->gart_vm_start);
 784         } else
 785 #endif
 786                 ring_start = (dev_priv->cp_ring->offset
 787                               - (unsigned long)dev->sg->virtual
 788                               + dev_priv->gart_vm_start);
 789
 790         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 791
 792         /* Set the write pointer delay */
 793         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 794
 795         /* Initialize the ring buffer's read and write pointers */
 796         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 797         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 798         SET_RING_HEAD(dev_priv, cur_read_ptr);
 799         dev_priv->ring.tail = cur_read_ptr;
 800
 801 #if __OS_HAS_AGP
 802         if (dev_priv->flags & RADEON_IS_AGP) {
 803                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 804                              dev_priv->ring_rptr->offset
 805                              - dev->agp->base + dev_priv->gart_vm_start);
 806         } else
 807 #endif
 808         {
 809                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 810                              dev_priv->ring_rptr->offset
 811                              - ((unsigned long) dev->sg->virtual)
 812                              + dev_priv->gart_vm_start);
 813         }
 814
 815         /* Set ring buffer size */
 816 #ifdef __BIG_ENDIAN
 817         RADEON_WRITE(RADEON_CP_RB_CNTL,
 818                      RADEON_BUF_SWAP_32BIT |
 819                      (dev_priv->ring.fetch_size_l2ow << 18) |
 820                      (dev_priv->ring.rptr_update_l2qw << 8) |
 821                      dev_priv->ring.size_l2qw);
 822 #else
 823         RADEON_WRITE(RADEON_CP_RB_CNTL,
 824                      (dev_priv->ring.fetch_size_l2ow << 18) |
 825                      (dev_priv->ring.rptr_update_l2qw << 8) |
 826                      dev_priv->ring.size_l2qw);
 827 #endif
 828
 829
 830         /* Initialize the scratch register pointer.  This will cause
 831          * the scratch register values to be written out to memory
 832          * whenever they are updated.
 833          *
 834          * We simply put this behind the ring read pointer, this works
 835          * with PCI GART as well as (whatever kind of) AGP GART
 836          */
 837         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 838                      + RADEON_SCRATCH_REG_OFFSET);
 839
 840         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 841
 842         radeon_enable_bm(dev_priv);
 843
 844         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
 845         RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
 846
 847         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 848         RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
 849
 850         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
 851         RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
 852
 853         /* reset sarea copies of these */
 854         master_priv = file_priv->master->driver_priv;
 855         if (master_priv->sarea_priv) {
 856                 master_priv->sarea_priv->last_frame = 0;
 857                 master_priv->sarea_priv->last_dispatch = 0;
 858                 master_priv->sarea_priv->last_clear = 0;
 859         }
 860
 861         radeon_do_wait_for_idle(dev_priv);
 862
 863         /* Sync everything up */
 864         RADEON_WRITE(RADEON_ISYNC_CNTL,
 865                      (RADEON_ISYNC_ANY2D_IDLE3D |
 866                       RADEON_ISYNC_ANY3D_IDLE2D |
 867                       RADEON_ISYNC_WAIT_IDLEGUI |
 868                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 869
 870 }
 871
 872 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 873 {
 874         u32 tmp;
 875
 876         /* Start with assuming that writeback doesn't work */
 877         dev_priv->writeback_works = 0;
 878
 879         /* Writeback doesn't seem to work everywhere, test it here and possibly
 880          * enable it if it appears to work
 881          */
 882         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 883
 884         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 885
 886         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 887                 u32 val;
 888
 889                 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
 890                 if (val == 0xdeadbeef)
 891                         break;
 892                 DRM_UDELAY(1);
 893         }
 894
 895         if (tmp < dev_priv->usec_timeout) {
 896                 dev_priv->writeback_works = 1;
 897                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 898         } else {
 899                 dev_priv->writeback_works = 0;
 900                 DRM_INFO("writeback test failed\n");
 901         }
 902         if (radeon_no_wb == 1) {
 903                 dev_priv->writeback_works = 0;
 904                 DRM_INFO("writeback forced off\n");
 905         }
 906
 907         if (!dev_priv->writeback_works) {
 908                 /* Disable writeback to avoid unnecessary bus master transfer */
 909                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
 910                              RADEON_RB_NO_UPDATE);
 911                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 912         }
 913 }
 914
 915 /* Enable or disable IGP GART on the chip */
 916 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 917 {
 918         u32 temp;
 919
 920         if (on) {
 921                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 922                           dev_priv->gart_vm_start,
 923                           (long)dev_priv->gart_info.bus_addr,
 924                           dev_priv->gart_size);
 925
 926                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 927                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 928                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 929                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 930                                                              RS690_BLOCK_GFX_D3_EN));
 931                 else
 932                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 933
 934                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 935                                                                RS480_VA_SIZE_32MB));
 936
 937                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 938                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 939                                                         RS480_TLB_ENABLE |
 940                                                         RS480_GTW_LAC_EN |
 941                                                         RS480_1LEVEL_GART));
 942
 943                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 944                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 945                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 946
 947                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 948                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 949                                                       RS480_REQ_TYPE_SNOOP_DIS));
 950
 951                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 952
 953                 dev_priv->gart_size = 32*1024*1024;
 954                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 955                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 956
 957                 radeon_write_agp_location(dev_priv, temp);
 958
 959                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 960                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 961                                                                RS480_VA_SIZE_32MB));
 962
 963                 do {
 964                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 965                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 966                                 break;
 967                         DRM_UDELAY(1);
 968                 } while (1);
 969
 970                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 971                                 RS480_GART_CACHE_INVALIDATE);
 972
 973                 do {
 974                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 975                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 976                                 break;
 977                         DRM_UDELAY(1);
 978                 } while (1);
 979
 980                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 981         } else {
 982                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 983         }
 984 }
 985
 986 /* Enable or disable IGP GART on the chip */
 987 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
 988 {
 989         u32 temp;
 990         int i;
 991
 992         if (on) {
 993                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 994                          dev_priv->gart_vm_start,
 995                          (long)dev_priv->gart_info.bus_addr,
 996                          dev_priv->gart_size);
 997
 998                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
 999                                                     RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
1000
1001                 for (i = 0; i < 19; i++)
1002                         IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
1003                                         (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
1004                                          RS600_SYSTEM_ACCESS_MODE_IN_SYS |
1005                                          RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
1006                                          RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
1007                                          RS600_ENABLE_FRAGMENT_PROCESSING |
1008                                          RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
1009
1010                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
1011                                                              RS600_PAGE_TABLE_TYPE_FLAT));
1012
1013                 /* disable all other contexts */
1014                 for (i = 1; i < 8; i++)
1015                         IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
1016
1017                 /* setup the page table aperture */
1018                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
1019                                 dev_priv->gart_info.bus_addr);
1020                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
1021                                 dev_priv->gart_vm_start);
1022                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
1023                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1024                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
1025
1026                 /* setup the system aperture */
1027                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
1028                                 dev_priv->gart_vm_start);
1029                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
1030                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1031
1032                 /* enable page tables */
1033                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1034                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
1035
1036                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1037                 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
1038
1039                 /* invalidate the cache */
1040                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1041
1042                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1043                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1044                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1045
1046                 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
1047                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1048                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1049
1050                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1051                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1052                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1053
1054         } else {
1055                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
1056                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1057                 temp &= ~RS600_ENABLE_PAGE_TABLES;
1058                 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
1059         }
1060 }
1061
1062 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1063 {
1064         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1065         if (on) {
1066
1067                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1068                           dev_priv->gart_vm_start,
1069                           (long)dev_priv->gart_info.bus_addr,
1070                           dev_priv->gart_size);
1071                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1072                                   dev_priv->gart_vm_start);
1073                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1074                                   dev_priv->gart_info.bus_addr);
1075                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1076                                   dev_priv->gart_vm_start);
1077                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1078                                   dev_priv->gart_vm_start +
1079                                   dev_priv->gart_size - 1);
1080
1081                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1082
1083                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1084                                   RADEON_PCIE_TX_GART_EN);
1085         } else {
1086                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1087                                   tmp & ~RADEON_PCIE_TX_GART_EN);
1088         }
1089 }
1090
1091 /* Enable or disable PCI GART on the chip */
1092 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1093 {
1094         u32 tmp;
1095
1096         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1097             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1098             (dev_priv->flags & RADEON_IS_IGPGART)) {
1099                 radeon_set_igpgart(dev_priv, on);
1100                 return;
1101         }
1102
1103         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1104                 rs600_set_igpgart(dev_priv, on);
1105                 return;
1106         }
1107
1108         if (dev_priv->flags & RADEON_IS_PCIE) {
1109                 radeon_set_pciegart(dev_priv, on);
1110                 return;
1111         }
1112
1113         tmp = RADEON_READ(RADEON_AIC_CNTL);
1114
1115         if (on) {
1116                 RADEON_WRITE(RADEON_AIC_CNTL,
1117                              tmp | RADEON_PCIGART_TRANSLATE_EN);
1118
1119                 /* set PCI GART page-table base address
1120                  */
1121                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1122
1123                 /* set address range for PCI address translate
1124                  */
1125                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1126                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1127                              + dev_priv->gart_size - 1);
1128
1129                 /* Turn off AGP aperture -- is this required for PCI GART?
1130                  */
1131                 radeon_write_agp_location(dev_priv, 0xffffffc0);
1132                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
1133         } else {
1134                 RADEON_WRITE(RADEON_AIC_CNTL,
1135                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1136         }
1137 }
1138
1139 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1140 {
1141         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1142         struct radeon_virt_surface *vp;
1143         int i;
1144
1145         for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1146                 if (!dev_priv->virt_surfaces[i].file_priv ||
1147                     dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1148                         break;
1149         }
1150         if (i >= 2 * RADEON_MAX_SURFACES)
1151                 return -ENOMEM;
1152         vp = &dev_priv->virt_surfaces[i];
1153
1154         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1155                 struct radeon_surface *sp = &dev_priv->surfaces[i];
1156                 if (sp->refcount)
1157                         continue;
1158
1159                 vp->surface_index = i;
1160                 vp->lower = gart_info->bus_addr;
1161                 vp->upper = vp->lower + gart_info->table_size;
1162                 vp->flags = 0;
1163                 vp->file_priv = PCIGART_FILE_PRIV;
1164
1165                 sp->refcount = 1;
1166                 sp->lower = vp->lower;
1167                 sp->upper = vp->upper;
1168                 sp->flags = 0;
1169
1170                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1171                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1172                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1173                 return 0;
1174         }
1175
1176         return -ENOMEM;
1177 }
1178
1179 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1180                              struct drm_file *file_priv)
1181 {
1182         drm_radeon_private_t *dev_priv = dev->dev_private;
1183         struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1184
1185         DRM_DEBUG("\n");
1186
1187         /* if we require new memory map but we don't have it fail */
1188         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1189                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1190                 radeon_do_cleanup_cp(dev);
1191                 return -EINVAL;
1192         }
1193
1194         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1195                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1196                 dev_priv->flags &= ~RADEON_IS_AGP;
1197         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1198                    && !init->is_pci) {
1199                 DRM_DEBUG("Restoring AGP flag\n");
1200                 dev_priv->flags |= RADEON_IS_AGP;
1201         }
1202
1203         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1204                 DRM_ERROR("PCI GART memory not allocated!\n");
1205                 radeon_do_cleanup_cp(dev);
1206                 return -EINVAL;
1207         }
1208
1209         dev_priv->usec_timeout = init->usec_timeout;
1210         if (dev_priv->usec_timeout < 1 ||
1211             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1212                 DRM_DEBUG("TIMEOUT problem!\n");
1213                 radeon_do_cleanup_cp(dev);
1214                 return -EINVAL;
1215         }
1216
1217         /* Enable vblank on CRTC1 for older X servers
1218          */
1219         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1220
1221         switch(init->func) {
1222         case RADEON_INIT_R200_CP:
1223                 dev_priv->microcode_version = UCODE_R200;
1224                 break;
1225         case RADEON_INIT_R300_CP:
1226                 dev_priv->microcode_version = UCODE_R300;
1227                 break;
1228         default:
1229                 dev_priv->microcode_version = UCODE_R100;
1230         }
1231
1232         dev_priv->do_boxes = 0;
1233         dev_priv->cp_mode = init->cp_mode;
1234
1235         /* We don't support anything other than bus-mastering ring mode,
1236          * but the ring can be in either AGP or PCI space for the ring
1237          * read pointer.
1238          */
1239         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1240             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1241                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1242                 radeon_do_cleanup_cp(dev);
1243                 return -EINVAL;
1244         }
1245
1246         switch (init->fb_bpp) {
1247         case 16:
1248                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1249                 break;
1250         case 32:
1251         default:
1252                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1253                 break;
1254         }
1255         dev_priv->front_offset = init->front_offset;
1256         dev_priv->front_pitch = init->front_pitch;
1257         dev_priv->back_offset = init->back_offset;
1258         dev_priv->back_pitch = init->back_pitch;
1259
1260         switch (init->depth_bpp) {
1261         case 16:
1262                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1263                 break;
1264         case 32:
1265         default:
1266                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1267                 break;
1268         }
1269         dev_priv->depth_offset = init->depth_offset;
1270         dev_priv->depth_pitch = init->depth_pitch;
1271
1272         /* Hardware state for depth clears.  Remove this if/when we no
1273          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1274          * all values to prevent unwanted 3D state from slipping through
1275          * and screwing with the clear operation.
1276          */
1277         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1278                                            (dev_priv->color_fmt << 10) |
1279                                            (dev_priv->microcode_version ==
1280                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1281
1282         dev_priv->depth_clear.rb3d_zstencilcntl =
1283             (dev_priv->depth_fmt |
1284              RADEON_Z_TEST_ALWAYS |
1285              RADEON_STENCIL_TEST_ALWAYS |
1286              RADEON_STENCIL_S_FAIL_REPLACE |
1287              RADEON_STENCIL_ZPASS_REPLACE |
1288              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1289
1290         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1291                                          RADEON_BFACE_SOLID |
1292                                          RADEON_FFACE_SOLID |
1293                                          RADEON_FLAT_SHADE_VTX_LAST |
1294                                          RADEON_DIFFUSE_SHADE_FLAT |
1295                                          RADEON_ALPHA_SHADE_FLAT |
1296                                          RADEON_SPECULAR_SHADE_FLAT |
1297                                          RADEON_FOG_SHADE_FLAT |
1298                                          RADEON_VTX_PIX_CENTER_OGL |
1299                                          RADEON_ROUND_MODE_TRUNC |
1300                                          RADEON_ROUND_PREC_8TH_PIX);
1301
1302
1303         dev_priv->ring_offset = init->ring_offset;
1304         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1305         dev_priv->buffers_offset = init->buffers_offset;
1306         dev_priv->gart_textures_offset = init->gart_textures_offset;
1307
1308         master_priv->sarea = drm_getsarea(dev);
1309         if (!master_priv->sarea) {
1310                 DRM_ERROR("could not find sarea!\n");
1311                 radeon_do_cleanup_cp(dev);
1312                 return -EINVAL;
1313         }
1314
1315         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1316         if (!dev_priv->cp_ring) {
1317                 DRM_ERROR("could not find cp ring region!\n");
1318                 radeon_do_cleanup_cp(dev);
1319                 return -EINVAL;
1320         }
1321         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1322         if (!dev_priv->ring_rptr) {
1323                 DRM_ERROR("could not find ring read pointer!\n");
1324                 radeon_do_cleanup_cp(dev);
1325                 return -EINVAL;
1326         }
1327         dev->agp_buffer_token = init->buffers_offset;
1328         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1329         if (!dev->agp_buffer_map) {
1330                 DRM_ERROR("could not find dma buffer region!\n");
1331                 radeon_do_cleanup_cp(dev);
1332                 return -EINVAL;
1333         }
1334
1335         if (init->gart_textures_offset) {
1336                 dev_priv->gart_textures =
1337                     drm_core_findmap(dev, init->gart_textures_offset);
1338                 if (!dev_priv->gart_textures) {
1339                         DRM_ERROR("could not find GART texture region!\n");
1340                         radeon_do_cleanup_cp(dev);
1341                         return -EINVAL;
1342                 }
1343         }
1344
1345 #if __OS_HAS_AGP
1346         if (dev_priv->flags & RADEON_IS_AGP) {
1347                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1348                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1349                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1350                 if (!dev_priv->cp_ring->handle ||
1351                     !dev_priv->ring_rptr->handle ||
1352                     !dev->agp_buffer_map->handle) {
1353                         DRM_ERROR("could not find ioremap agp regions!\n");
1354                         radeon_do_cleanup_cp(dev);
1355                         return -EINVAL;
1356                 }
1357         } else
1358 #endif
1359         {
1360                 dev_priv->cp_ring->handle =
1361                         (void *)(unsigned long)dev_priv->cp_ring->offset;
1362                 dev_priv->ring_rptr->handle =
1363                         (void *)(unsigned long)dev_priv->ring_rptr->offset;
1364                 dev->agp_buffer_map->handle =
1365                         (void *)(unsigned long)dev->agp_buffer_map->offset;
1366
1367                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1368                           dev_priv->cp_ring->handle);
1369                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1370                           dev_priv->ring_rptr->handle);
1371                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1372                           dev->agp_buffer_map->handle);
1373         }
1374
1375         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1376         dev_priv->fb_size =
1377                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1378                 - dev_priv->fb_location;
1379
1380         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1381                                         ((dev_priv->front_offset
1382                                           + dev_priv->fb_location) >> 10));
1383
1384         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1385                                        ((dev_priv->back_offset
1386                                          + dev_priv->fb_location) >> 10));
1387
1388         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1389                                         ((dev_priv->depth_offset
1390                                           + dev_priv->fb_location) >> 10));
1391
1392         dev_priv->gart_size = init->gart_size;
1393
1394         /* New let's set the memory map ... */
1395         if (dev_priv->new_memmap) {
1396                 u32 base = 0;
1397
1398                 DRM_INFO("Setting GART location based on new memory map\n");
1399
1400                 /* If using AGP, try to locate the AGP aperture at the same
1401                  * location in the card and on the bus, though we have to
1402                  * align it down.
1403                  */
1404 #if __OS_HAS_AGP
1405                 if (dev_priv->flags & RADEON_IS_AGP) {
1406                         base = dev->agp->base;
1407                         /* Check if valid */
1408                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1409                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1410                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1411                                          dev->agp->base);
1412                                 base = 0;
1413                         }
1414                 }
1415 #endif
1416                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1417                 if (base == 0) {
1418                         base = dev_priv->fb_location + dev_priv->fb_size;
1419                         if (base < dev_priv->fb_location ||
1420                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1421                                 base = dev_priv->fb_location
1422                                         - dev_priv->gart_size;
1423                 }
1424                 dev_priv->gart_vm_start = base & 0xffc00000u;
1425                 if (dev_priv->gart_vm_start != base)
1426                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1427                                  base, dev_priv->gart_vm_start);
1428         } else {
1429                 DRM_INFO("Setting GART location based on old memory map\n");
1430                 dev_priv->gart_vm_start = dev_priv->fb_location +
1431                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1432         }
1433
1434 #if __OS_HAS_AGP
1435         if (dev_priv->flags & RADEON_IS_AGP)
1436                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1437                                                  - dev->agp->base
1438                                                  + dev_priv->gart_vm_start);
1439         else
1440 #endif
1441                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1442                                         - (unsigned long)dev->sg->virtual
1443                                         + dev_priv->gart_vm_start);
1444
1445         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1446         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1447         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1448                   dev_priv->gart_buffers_offset);
1449
1450         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1451         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1452                               + init->ring_size / sizeof(u32));
1453         dev_priv->ring.size = init->ring_size;
1454         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1455
1456         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1457         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1458
1459         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1460         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1461         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1462
1463         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1464
1465 #if __OS_HAS_AGP
1466         if (dev_priv->flags & RADEON_IS_AGP) {
1467                 /* Turn off PCI GART */
1468                 radeon_set_pcigart(dev_priv, 0);
1469         } else
1470 #endif
1471         {
1472                 u32 sctrl;
1473                 int ret;
1474
1475                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1476                 /* if we have an offset set from userspace */
1477                 if (dev_priv->pcigart_offset_set) {
1478                         dev_priv->gart_info.bus_addr =
1479                                 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1480                         dev_priv->gart_info.mapping.offset =
1481                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1482                         dev_priv->gart_info.mapping.size =
1483                             dev_priv->gart_info.table_size;
1484
1485                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1486                         dev_priv->gart_info.addr =
1487                             dev_priv->gart_info.mapping.handle;
1488
1489                         if (dev_priv->flags & RADEON_IS_PCIE)
1490                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1491                         else
1492                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1493                         dev_priv->gart_info.gart_table_location =
1494                             DRM_ATI_GART_FB;
1495
1496                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1497                                   dev_priv->gart_info.addr,
1498                                   dev_priv->pcigart_offset);
1499                 } else {
1500                         if (dev_priv->flags & RADEON_IS_IGPGART)
1501                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1502                         else
1503                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1504                         dev_priv->gart_info.gart_table_location =
1505                             DRM_ATI_GART_MAIN;
1506                         dev_priv->gart_info.addr = NULL;
1507                         dev_priv->gart_info.bus_addr = 0;
1508                         if (dev_priv->flags & RADEON_IS_PCIE) {
1509                                 DRM_ERROR
1510                                     ("Cannot use PCI Express without GART in FB memory\n");
1511                                 radeon_do_cleanup_cp(dev);
1512                                 return -EINVAL;
1513                         }
1514                 }
1515
1516                 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1517                 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1518                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1519                         ret = r600_page_table_init(dev);
1520                 else
1521                         ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1522                 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1523
1524                 if (!ret) {
1525                         DRM_ERROR("failed to init PCI GART!\n");
1526                         radeon_do_cleanup_cp(dev);
1527                         return -ENOMEM;
1528                 }
1529
1530                 ret = radeon_setup_pcigart_surface(dev_priv);
1531                 if (ret) {
1532                         DRM_ERROR("failed to setup GART surface!\n");
1533                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1534                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1535                         else
1536                                 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1537                         radeon_do_cleanup_cp(dev);
1538                         return ret;
1539                 }
1540
1541                 /* Turn on PCI GART */
1542                 radeon_set_pcigart(dev_priv, 1);
1543         }
1544
1545         if (!dev_priv->me_fw) {
1546                 int err = radeon_cp_init_microcode(dev_priv);
1547                 if (err) {
1548                         DRM_ERROR("Failed to load firmware!\n");
1549                         radeon_do_cleanup_cp(dev);
1550                         return err;
1551                 }
1552         }
1553         radeon_cp_load_microcode(dev_priv);
1554         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1555
1556         dev_priv->last_buf = 0;
1557
1558         radeon_do_engine_reset(dev);
1559         radeon_test_writeback(dev_priv);
1560
1561         return 0;
1562 }
1563
1564 static int radeon_do_cleanup_cp(struct drm_device * dev)
1565 {
1566         drm_radeon_private_t *dev_priv = dev->dev_private;
1567         DRM_DEBUG("\n");
1568
1569         /* Make sure interrupts are disabled here because the uninstall ioctl
1570          * may not have been called from userspace and after dev_private
1571          * is freed, it's too late.
1572          */
1573         if (dev->irq_enabled)
1574                 drm_irq_uninstall(dev);
1575
1576 #if __OS_HAS_AGP
1577         if (dev_priv->flags & RADEON_IS_AGP) {
1578                 if (dev_priv->cp_ring != NULL) {
1579                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1580                         dev_priv->cp_ring = NULL;
1581                 }
1582                 if (dev_priv->ring_rptr != NULL) {
1583                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1584                         dev_priv->ring_rptr = NULL;
1585                 }
1586                 if (dev->agp_buffer_map != NULL) {
1587                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1588                         dev->agp_buffer_map = NULL;
1589                 }
1590         } else
1591 #endif
1592         {
1593
1594                 if (dev_priv->gart_info.bus_addr) {
1595                         /* Turn off PCI GART */
1596                         radeon_set_pcigart(dev_priv, 0);
1597                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1598                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1599                         else {
1600                                 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1601                                         DRM_ERROR("failed to cleanup PCI GART!\n");
1602                         }
1603                 }
1604
1605                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1606                 {
1607                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1608                         dev_priv->gart_info.addr = NULL;
1609                 }
1610         }
1611         /* only clear to the start of flags */
1612         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1613
1614         return 0;
1615 }
1616
1617 /* This code will reinit the Radeon CP hardware after a resume from disc.
1618  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1619  * here we make sure that all Radeon hardware initialisation is re-done without
1620  * affecting running applications.
1621  *
1622  * Charl P. Botha <http://cpbotha.net>
1623  */
1624 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1625 {
1626         drm_radeon_private_t *dev_priv = dev->dev_private;
1627
1628         if (!dev_priv) {
1629                 DRM_ERROR("Called with no initialization\n");
1630                 return -EINVAL;
1631         }
1632
1633         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1634
1635 #if __OS_HAS_AGP
1636         if (dev_priv->flags & RADEON_IS_AGP) {
1637                 /* Turn off PCI GART */
1638                 radeon_set_pcigart(dev_priv, 0);
1639         } else
1640 #endif
1641         {
1642                 /* Turn on PCI GART */
1643                 radeon_set_pcigart(dev_priv, 1);
1644         }
1645
1646         radeon_cp_load_microcode(dev_priv);
1647         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1648
1649         dev_priv->have_z_offset = 0;
1650         radeon_do_engine_reset(dev);
1651         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1652
1653         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1654
1655         return 0;
1656 }
1657
1658 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1659 {
1660         drm_radeon_private_t *dev_priv = dev->dev_private;
1661         drm_radeon_init_t *init = data;
1662
1663         LOCK_TEST_WITH_RETURN(dev, file_priv);
1664
1665         if (init->func == RADEON_INIT_R300_CP)
1666                 r300_init_reg_flags(dev);
1667
1668         switch (init->func) {
1669         case RADEON_INIT_CP:
1670         case RADEON_INIT_R200_CP:
1671         case RADEON_INIT_R300_CP:
1672                 return radeon_do_init_cp(dev, init, file_priv);
1673         case RADEON_INIT_R600_CP:
1674                 return r600_do_init_cp(dev, init, file_priv);
1675         case RADEON_CLEANUP_CP:
1676                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1677                         return r600_do_cleanup_cp(dev);
1678                 else
1679                         return radeon_do_cleanup_cp(dev);
1680         }
1681
1682         return -EINVAL;
1683 }
1684
1685 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1686 {
1687         drm_radeon_private_t *dev_priv = dev->dev_private;
1688         DRM_DEBUG("\n");
1689
1690         LOCK_TEST_WITH_RETURN(dev, file_priv);
1691
1692         if (dev_priv->cp_running) {
1693                 DRM_DEBUG("while CP running\n");
1694                 return 0;
1695         }
1696         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1697                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1698                           dev_priv->cp_mode);
1699                 return 0;
1700         }
1701
1702         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1703                 r600_do_cp_start(dev_priv);
1704         else
1705                 radeon_do_cp_start(dev_priv);
1706
1707         return 0;
1708 }
1709
1710 /* Stop the CP.  The engine must have been idled before calling this
1711  * routine.
1712  */
1713 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1714 {
1715         drm_radeon_private_t *dev_priv = dev->dev_private;
1716         drm_radeon_cp_stop_t *stop = data;
1717         int ret;
1718         DRM_DEBUG("\n");
1719
1720         LOCK_TEST_WITH_RETURN(dev, file_priv);
1721
1722         if (!dev_priv->cp_running)
1723                 return 0;
1724
1725         /* Flush any pending CP commands.  This ensures any outstanding
1726          * commands are exectuted by the engine before we turn it off.
1727          */
1728         if (stop->flush) {
1729                 radeon_do_cp_flush(dev_priv);
1730         }
1731
1732         /* If we fail to make the engine go idle, we return an error
1733          * code so that the DRM ioctl wrapper can try again.
1734          */
1735         if (stop->idle) {
1736                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1737                         ret = r600_do_cp_idle(dev_priv);
1738                 else
1739                         ret = radeon_do_cp_idle(dev_priv);
1740                 if (ret)
1741                         return ret;
1742         }
1743
1744         /* Finally, we can turn off the CP.  If the engine isn't idle,
1745          * we will get some dropped triangles as they won't be fully
1746          * rendered before the CP is shut down.
1747          */
1748         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1749                 r600_do_cp_stop(dev_priv);
1750         else
1751                 radeon_do_cp_stop(dev_priv);
1752
1753         /* Reset the engine */
1754         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1755                 r600_do_engine_reset(dev);
1756         else
1757                 radeon_do_engine_reset(dev);
1758
1759         return 0;
1760 }
1761
1762 void radeon_do_release(struct drm_device * dev)
1763 {
1764         drm_radeon_private_t *dev_priv = dev->dev_private;
1765         int i, ret;
1766
1767         if (dev_priv) {
1768                 if (dev_priv->cp_running) {
1769                         /* Stop the cp */
1770                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1771                                 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1772                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1773 #ifdef __linux__
1774                                         schedule();
1775 #else
1776                                         tsleep(&ret, PZERO, "rdnrel", 1);
1777 #endif
1778                                 }
1779                         } else {
1780                                 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1781                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1782 #ifdef __linux__
1783                                         schedule();
1784 #else
1785                                         tsleep(&ret, PZERO, "rdnrel", 1);
1786 #endif
1787                                 }
1788                         }
1789                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1790                                 r600_do_cp_stop(dev_priv);
1791                                 r600_do_engine_reset(dev);
1792                         } else {
1793                                 radeon_do_cp_stop(dev_priv);
1794                                 radeon_do_engine_reset(dev);
1795                         }
1796                 }
1797
1798                 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1799                         /* Disable *all* interrupts */
1800                         if (dev_priv->mmio)     /* remove this after permanent addmaps */
1801                                 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1802
1803                         if (dev_priv->mmio) {   /* remove all surfaces */
1804                                 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1805                                         RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1806                                         RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1807                                                      16 * i, 0);
1808                                         RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1809                                                      16 * i, 0);
1810                                 }
1811                         }
1812                 }
1813
1814                 /* Free memory heap structures */
1815                 radeon_mem_takedown(&(dev_priv->gart_heap));
1816                 radeon_mem_takedown(&(dev_priv->fb_heap));
1817
1818                 /* deallocate kernel resources */
1819                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1820                         r600_do_cleanup_cp(dev);
1821                 else
1822                         radeon_do_cleanup_cp(dev);
1823                 if (dev_priv->me_fw) {
1824                         release_firmware(dev_priv->me_fw);
1825                         dev_priv->me_fw = NULL;
1826                 }
1827                 if (dev_priv->pfp_fw) {
1828                         release_firmware(dev_priv->pfp_fw);
1829                         dev_priv->pfp_fw = NULL;
1830                 }
1831         }
1832 }
1833
1834 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1835  */
1836 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1837 {
1838         drm_radeon_private_t *dev_priv = dev->dev_private;
1839         DRM_DEBUG("\n");
1840
1841         LOCK_TEST_WITH_RETURN(dev, file_priv);
1842
1843         if (!dev_priv) {
1844                 DRM_DEBUG("called before init done\n");
1845                 return -EINVAL;
1846         }
1847
1848         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1849                 r600_do_cp_reset(dev_priv);
1850         else
1851                 radeon_do_cp_reset(dev_priv);
1852
1853         /* The CP is no longer running after an engine reset */
1854         dev_priv->cp_running = 0;
1855
1856         return 0;
1857 }
1858
1859 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1860 {
1861         drm_radeon_private_t *dev_priv = dev->dev_private;
1862         DRM_DEBUG("\n");
1863
1864         LOCK_TEST_WITH_RETURN(dev, file_priv);
1865
1866         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1867                 return r600_do_cp_idle(dev_priv);
1868         else
1869                 return radeon_do_cp_idle(dev_priv);
1870 }
1871
1872 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1873  */
1874 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1875 {
1876         drm_radeon_private_t *dev_priv = dev->dev_private;
1877         DRM_DEBUG("\n");
1878
1879         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1880                 return r600_do_resume_cp(dev, file_priv);
1881         else
1882                 return radeon_do_resume_cp(dev, file_priv);
1883 }
1884
1885 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1886 {
1887         drm_radeon_private_t *dev_priv = dev->dev_private;
1888         DRM_DEBUG("\n");
1889
1890         LOCK_TEST_WITH_RETURN(dev, file_priv);
1891
1892         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1893                 return r600_do_engine_reset(dev);
1894         else
1895                 return radeon_do_engine_reset(dev);
1896 }
1897
1898 /* ================================================================
1899  * Fullscreen mode
1900  */
1901
1902 /* KW: Deprecated to say the least:
1903  */
1904 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1905 {
1906         return 0;
1907 }
1908
1909 /* ================================================================
1910  * Freelist management
1911  */
1912
1913 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1914  *   bufs until freelist code is used.  Note this hides a problem with
1915  *   the scratch register * (used to keep track of last buffer
1916  *   completed) being written to before * the last buffer has actually
1917  *   completed rendering.
1918  *
1919  * KW:  It's also a good way to find free buffers quickly.
1920  *
1921  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1922  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1923  * we essentially have to do this, else old clients will break.
1924  *
1925  * However, it does leave open a potential deadlock where all the
1926  * buffers are held by other clients, which can't release them because
1927  * they can't get the lock.
1928  */
1929
1930 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1931 {
1932         struct drm_device_dma *dma = dev->dma;
1933         drm_radeon_private_t *dev_priv = dev->dev_private;
1934         drm_radeon_buf_priv_t *buf_priv;
1935         struct drm_buf *buf;
1936         int i, t;
1937         int start;
1938
1939         if (++dev_priv->last_buf >= dma->buf_count)
1940                 dev_priv->last_buf = 0;
1941
1942         start = dev_priv->last_buf;
1943
1944         for (t = 0; t < dev_priv->usec_timeout; t++) {
1945                 u32 done_age = GET_SCRATCH(dev_priv, 1);
1946                 DRM_DEBUG("done_age = %d\n", done_age);
1947                 for (i = 0; i < dma->buf_count; i++) {
1948                         buf = dma->buflist[start];
1949                         buf_priv = buf->dev_private;
1950                         if (buf->file_priv == NULL || (buf->pending &&
1951                                                        buf_priv->age <=
1952                                                        done_age)) {
1953                                 dev_priv->stats.requested_bufs++;
1954                                 buf->pending = 0;
1955                                 return buf;
1956                         }
1957                         if (++start >= dma->buf_count)
1958                                 start = 0;
1959                 }
1960
1961                 if (t) {
1962                         DRM_UDELAY(1);
1963                         dev_priv->stats.freelist_loops++;
1964                 }
1965         }
1966
1967         return NULL;
1968 }
1969
1970 void radeon_freelist_reset(struct drm_device * dev)
1971 {
1972         struct drm_device_dma *dma = dev->dma;
1973         drm_radeon_private_t *dev_priv = dev->dev_private;
1974         int i;
1975
1976         dev_priv->last_buf = 0;
1977         for (i = 0; i < dma->buf_count; i++) {
1978                 struct drm_buf *buf = dma->buflist[i];
1979                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1980                 buf_priv->age = 0;
1981         }
1982 }
1983
1984 /* ================================================================
1985  * CP command submission
1986  */
1987
1988 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1989 {
1990         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1991         int i;
1992         u32 last_head = GET_RING_HEAD(dev_priv);
1993
1994         for (i = 0; i < dev_priv->usec_timeout; i++) {
1995                 u32 head = GET_RING_HEAD(dev_priv);
1996
1997                 ring->space = (head - ring->tail) * sizeof(u32);
1998                 if (ring->space <= 0)
1999                         ring->space += ring->size;
2000                 if (ring->space > n)
2001                         return 0;
2002
2003                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2004
2005                 if (head != last_head)
2006                         i = 0;
2007                 last_head = head;
2008
2009                 DRM_UDELAY(1);
2010         }
2011
2012         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2013 #if RADEON_FIFO_DEBUG
2014         radeon_status(dev_priv);
2015         DRM_ERROR("failed!\n");
2016 #endif
2017         return -EBUSY;
2018 }
2019
2020 static int radeon_cp_get_buffers(struct drm_device *dev,
2021                                  struct drm_file *file_priv,
2022                                  struct drm_dma * d)
2023 {
2024         int i;
2025         struct drm_buf *buf;
2026
2027         for (i = d->granted_count; i < d->request_count; i++) {
2028                 buf = radeon_freelist_get(dev);
2029                 if (!buf)
2030                         return -EBUSY;  /* NOTE: broken client */
2031
2032                 buf->file_priv = file_priv;
2033
2034                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2035                                      sizeof(buf->idx)))
2036                         return -EFAULT;
2037                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2038                                      sizeof(buf->total)))
2039                         return -EFAULT;
2040
2041                 d->granted_count++;
2042         }
2043         return 0;
2044 }
2045
2046 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
2047 {
2048         struct drm_device_dma *dma = dev->dma;
2049         int ret = 0;
2050         struct drm_dma *d = data;
2051
2052         LOCK_TEST_WITH_RETURN(dev, file_priv);
2053
2054         /* Please don't send us buffers.
2055          */
2056         if (d->send_count != 0) {
2057                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2058                           DRM_CURRENTPID, d->send_count);
2059                 return -EINVAL;
2060         }
2061
2062         /* We'll send you buffers.
2063          */
2064         if (d->request_count < 0 || d->request_count > dma->buf_count) {
2065                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2066                           DRM_CURRENTPID, d->request_count, dma->buf_count);
2067                 return -EINVAL;
2068         }
2069
2070         d->granted_count = 0;
2071
2072         if (d->request_count) {
2073                 ret = radeon_cp_get_buffers(dev, file_priv, d);
2074         }
2075
2076         return ret;
2077 }
2078
2079 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2080 {
2081         drm_radeon_private_t *dev_priv;
2082         int ret = 0;
2083
2084         dev_priv = kzalloc(sizeof(drm_radeon_private_t), GFP_KERNEL);
2085         if (dev_priv == NULL)
2086                 return -ENOMEM;
2087
2088         dev->dev_private = (void *)dev_priv;
2089         dev_priv->flags = flags;
2090
2091         switch (flags & RADEON_FAMILY_MASK) {
2092         case CHIP_R100:
2093         case CHIP_RV200:
2094         case CHIP_R200:
2095         case CHIP_R300:
2096         case CHIP_R350:
2097         case CHIP_R420:
2098         case CHIP_R423:
2099         case CHIP_RV410:
2100         case CHIP_RV515:
2101         case CHIP_R520:
2102         case CHIP_RV570:
2103         case CHIP_R580:
2104                 dev_priv->flags |= RADEON_HAS_HIERZ;
2105                 break;
2106         default:
2107                 /* all other chips have no hierarchical z buffer */
2108                 break;
2109         }
2110
2111         if (drm_device_is_agp(dev))
2112                 dev_priv->flags |= RADEON_IS_AGP;
2113         else if (drm_device_is_pcie(dev))
2114                 dev_priv->flags |= RADEON_IS_PCIE;
2115         else
2116                 dev_priv->flags |= RADEON_IS_PCI;
2117
2118         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2119                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2120                          _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2121         if (ret != 0)
2122                 return ret;
2123
2124         ret = drm_vblank_init(dev, 2);
2125         if (ret) {
2126                 radeon_driver_unload(dev);
2127                 return ret;
2128         }
2129
2130         DRM_DEBUG("%s card detected\n",
2131                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2132         return ret;
2133 }
2134
2135 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2136 {
2137         struct drm_radeon_master_private *master_priv;
2138         unsigned long sareapage;
2139         int ret;
2140
2141         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
2142         if (!master_priv)
2143                 return -ENOMEM;
2144
2145         /* prebuild the SAREA */
2146         sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
2147         ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK,
2148                          &master_priv->sarea);
2149         if (ret) {
2150                 DRM_ERROR("SAREA setup failed\n");
2151                 kfree(master_priv);
2152                 return ret;
2153         }
2154         master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
2155         master_priv->sarea_priv->pfCurrentPage = 0;
2156
2157         master->driver_priv = master_priv;
2158         return 0;
2159 }
2160
2161 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2162 {
2163         struct drm_radeon_master_private *master_priv = master->driver_priv;
2164
2165         if (!master_priv)
2166                 return;
2167
2168         if (master_priv->sarea_priv &&
2169             master_priv->sarea_priv->pfCurrentPage != 0)
2170                 radeon_cp_dispatch_flip(dev, master);
2171
2172         master_priv->sarea_priv = NULL;
2173         if (master_priv->sarea)
2174                 drm_rmmap_locked(dev, master_priv->sarea);
2175
2176         kfree(master_priv);
2177
2178         master->driver_priv = NULL;
2179 }
2180
2181 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2182  * have to find them.
2183  */
2184 int radeon_driver_firstopen(struct drm_device *dev)
2185 {
2186         int ret;
2187         drm_local_map_t *map;
2188         drm_radeon_private_t *dev_priv = dev->dev_private;
2189
2190         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2191
2192         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2193         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2194                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2195                          _DRM_WRITE_COMBINING, &map);
2196         if (ret != 0)
2197                 return ret;
2198
2199         return 0;
2200 }
2201
2202 int radeon_driver_unload(struct drm_device *dev)
2203 {
2204         drm_radeon_private_t *dev_priv = dev->dev_private;
2205
2206         DRM_DEBUG("\n");
2207
2208         drm_rmmap(dev, dev_priv->mmio);
2209
2210         kfree(dev_priv);
2211
2212         dev->dev_private = NULL;
2213         return 0;
2214 }
2215
2216 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2217 {
2218         int i;
2219         u32 *ring;
2220         int tail_aligned;
2221
2222         /* check if the ring is padded out to 16-dword alignment */
2223
2224         tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1);
2225         if (tail_aligned) {
2226                 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
2227
2228                 ring = dev_priv->ring.start;
2229                 /* pad with some CP_PACKET2 */
2230                 for (i = 0; i < num_p2; i++)
2231                         ring[dev_priv->ring.tail + i] = CP_PACKET2();
2232
2233                 dev_priv->ring.tail += i;
2234
2235                 dev_priv->ring.space -= num_p2 * sizeof(u32);
2236         }
2237
2238         dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2239
2240         DRM_MEMORYBARRIER();
2241         GET_RING_HEAD( dev_priv );
2242
2243         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2244                 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2245                 /* read from PCI bus to ensure correct posting */
2246                 RADEON_READ(R600_CP_RB_RPTR);
2247         } else {
2248                 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2249                 /* read from PCI bus to ensure correct posting */
2250                 RADEON_READ(RADEON_CP_RB_RPTR);
2251         }
2252 }