drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif /* CONFIG_PPC_PMAC */
  39
  40 /* from radeon_encoder.c */
  41 extern uint32_t
  42 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  43                       uint8_t dac);
  44 extern void radeon_link_encoder_connector(struct drm_device *dev);
  45
  46 /* from radeon_connector.c */
  47 extern void
  48 radeon_add_legacy_connector(struct drm_device *dev,
  49                             uint32_t connector_id,
  50                             uint32_t supported_device,
  51                             int connector_type,
  52                             struct radeon_i2c_bus_rec *i2c_bus,
  53                             uint16_t connector_object_id,
  54                             struct radeon_hpd *hpd);
  55
  56 /* from radeon_legacy_encoder.c */
  57 extern void
  58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  59                           uint32_t supported_device);
  60
  61 /* old legacy ATI BIOS routines */
  62
  63 /* COMBIOS table offsets */
  64 enum radeon_combios_table_offset {
  65         /* absolute offset tables */
  66         COMBIOS_ASIC_INIT_1_TABLE,
  67         COMBIOS_BIOS_SUPPORT_TABLE,
  68         COMBIOS_DAC_PROGRAMMING_TABLE,
  69         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  70         COMBIOS_CRTC_INFO_TABLE,
  71         COMBIOS_PLL_INFO_TABLE,
  72         COMBIOS_TV_INFO_TABLE,
  73         COMBIOS_DFP_INFO_TABLE,
  74         COMBIOS_HW_CONFIG_INFO_TABLE,
  75         COMBIOS_MULTIMEDIA_INFO_TABLE,
  76         COMBIOS_TV_STD_PATCH_TABLE,
  77         COMBIOS_LCD_INFO_TABLE,
  78         COMBIOS_MOBILE_INFO_TABLE,
  79         COMBIOS_PLL_INIT_TABLE,
  80         COMBIOS_MEM_CONFIG_TABLE,
  81         COMBIOS_SAVE_MASK_TABLE,
  82         COMBIOS_HARDCODED_EDID_TABLE,
  83         COMBIOS_ASIC_INIT_2_TABLE,
  84         COMBIOS_CONNECTOR_INFO_TABLE,
  85         COMBIOS_DYN_CLK_1_TABLE,
  86         COMBIOS_RESERVED_MEM_TABLE,
  87         COMBIOS_EXT_TMDS_INFO_TABLE,
  88         COMBIOS_MEM_CLK_INFO_TABLE,
  89         COMBIOS_EXT_DAC_INFO_TABLE,
  90         COMBIOS_MISC_INFO_TABLE,
  91         COMBIOS_CRT_INFO_TABLE,
  92         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  93         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  94         COMBIOS_FAN_SPEED_INFO_TABLE,
  95         COMBIOS_OVERDRIVE_INFO_TABLE,
  96         COMBIOS_OEM_INFO_TABLE,
  97         COMBIOS_DYN_CLK_2_TABLE,
  98         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  99         COMBIOS_I2C_INFO_TABLE,
 100         /* relative offset tables */
 101         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
 102         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
 103         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
 104         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
 105         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
 106         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
 107         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
 108         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
 109         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
 110         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
 111         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
 112 };
 113
 114 enum radeon_combios_ddc {
 115         DDC_NONE_DETECTED,
 116         DDC_MONID,
 117         DDC_DVI,
 118         DDC_VGA,
 119         DDC_CRT2,
 120         DDC_LCD,
 121         DDC_GPIO,
 122 };
 123
 124 enum radeon_combios_connector {
 125         CONNECTOR_NONE_LEGACY,
 126         CONNECTOR_PROPRIETARY_LEGACY,
 127         CONNECTOR_CRT_LEGACY,
 128         CONNECTOR_DVI_I_LEGACY,
 129         CONNECTOR_DVI_D_LEGACY,
 130         CONNECTOR_CTV_LEGACY,
 131         CONNECTOR_STV_LEGACY,
 132         CONNECTOR_UNSUPPORTED_LEGACY
 133 };
 134
 135 const int legacy_connector_convert[] = {
 136         DRM_MODE_CONNECTOR_Unknown,
 137         DRM_MODE_CONNECTOR_DVID,
 138         DRM_MODE_CONNECTOR_VGA,
 139         DRM_MODE_CONNECTOR_DVII,
 140         DRM_MODE_CONNECTOR_DVID,
 141         DRM_MODE_CONNECTOR_Composite,
 142         DRM_MODE_CONNECTOR_SVIDEO,
 143         DRM_MODE_CONNECTOR_Unknown,
 144 };
 145
 146 static uint16_t combios_get_table_offset(struct drm_device *dev,
 147                                          enum radeon_combios_table_offset table)
 148 {
 149         struct radeon_device *rdev = dev->dev_private;
 150         int rev;
 151         uint16_t offset = 0, check_offset;
 152
 153         switch (table) {
 154                 /* absolute offset tables */
 155         case COMBIOS_ASIC_INIT_1_TABLE:
 156                 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
 157                 if (check_offset)
 158                         offset = check_offset;
 159                 break;
 160         case COMBIOS_BIOS_SUPPORT_TABLE:
 161                 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
 162                 if (check_offset)
 163                         offset = check_offset;
 164                 break;
 165         case COMBIOS_DAC_PROGRAMMING_TABLE:
 166                 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
 167                 if (check_offset)
 168                         offset = check_offset;
 169                 break;
 170         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 171                 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
 172                 if (check_offset)
 173                         offset = check_offset;
 174                 break;
 175         case COMBIOS_CRTC_INFO_TABLE:
 176                 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
 177                 if (check_offset)
 178                         offset = check_offset;
 179                 break;
 180         case COMBIOS_PLL_INFO_TABLE:
 181                 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
 182                 if (check_offset)
 183                         offset = check_offset;
 184                 break;
 185         case COMBIOS_TV_INFO_TABLE:
 186                 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
 187                 if (check_offset)
 188                         offset = check_offset;
 189                 break;
 190         case COMBIOS_DFP_INFO_TABLE:
 191                 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
 192                 if (check_offset)
 193                         offset = check_offset;
 194                 break;
 195         case COMBIOS_HW_CONFIG_INFO_TABLE:
 196                 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
 197                 if (check_offset)
 198                         offset = check_offset;
 199                 break;
 200         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 201                 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
 202                 if (check_offset)
 203                         offset = check_offset;
 204                 break;
 205         case COMBIOS_TV_STD_PATCH_TABLE:
 206                 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
 207                 if (check_offset)
 208                         offset = check_offset;
 209                 break;
 210         case COMBIOS_LCD_INFO_TABLE:
 211                 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
 212                 if (check_offset)
 213                         offset = check_offset;
 214                 break;
 215         case COMBIOS_MOBILE_INFO_TABLE:
 216                 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
 217                 if (check_offset)
 218                         offset = check_offset;
 219                 break;
 220         case COMBIOS_PLL_INIT_TABLE:
 221                 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
 222                 if (check_offset)
 223                         offset = check_offset;
 224                 break;
 225         case COMBIOS_MEM_CONFIG_TABLE:
 226                 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
 227                 if (check_offset)
 228                         offset = check_offset;
 229                 break;
 230         case COMBIOS_SAVE_MASK_TABLE:
 231                 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
 232                 if (check_offset)
 233                         offset = check_offset;
 234                 break;
 235         case COMBIOS_HARDCODED_EDID_TABLE:
 236                 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
 237                 if (check_offset)
 238                         offset = check_offset;
 239                 break;
 240         case COMBIOS_ASIC_INIT_2_TABLE:
 241                 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
 242                 if (check_offset)
 243                         offset = check_offset;
 244                 break;
 245         case COMBIOS_CONNECTOR_INFO_TABLE:
 246                 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
 247                 if (check_offset)
 248                         offset = check_offset;
 249                 break;
 250         case COMBIOS_DYN_CLK_1_TABLE:
 251                 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
 252                 if (check_offset)
 253                         offset = check_offset;
 254                 break;
 255         case COMBIOS_RESERVED_MEM_TABLE:
 256                 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
 257                 if (check_offset)
 258                         offset = check_offset;
 259                 break;
 260         case COMBIOS_EXT_TMDS_INFO_TABLE:
 261                 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
 262                 if (check_offset)
 263                         offset = check_offset;
 264                 break;
 265         case COMBIOS_MEM_CLK_INFO_TABLE:
 266                 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
 267                 if (check_offset)
 268                         offset = check_offset;
 269                 break;
 270         case COMBIOS_EXT_DAC_INFO_TABLE:
 271                 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
 272                 if (check_offset)
 273                         offset = check_offset;
 274                 break;
 275         case COMBIOS_MISC_INFO_TABLE:
 276                 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
 277                 if (check_offset)
 278                         offset = check_offset;
 279                 break;
 280         case COMBIOS_CRT_INFO_TABLE:
 281                 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
 282                 if (check_offset)
 283                         offset = check_offset;
 284                 break;
 285         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 286                 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
 287                 if (check_offset)
 288                         offset = check_offset;
 289                 break;
 290         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 291                 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
 292                 if (check_offset)
 293                         offset = check_offset;
 294                 break;
 295         case COMBIOS_FAN_SPEED_INFO_TABLE:
 296                 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
 297                 if (check_offset)
 298                         offset = check_offset;
 299                 break;
 300         case COMBIOS_OVERDRIVE_INFO_TABLE:
 301                 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
 302                 if (check_offset)
 303                         offset = check_offset;
 304                 break;
 305         case COMBIOS_OEM_INFO_TABLE:
 306                 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
 307                 if (check_offset)
 308                         offset = check_offset;
 309                 break;
 310         case COMBIOS_DYN_CLK_2_TABLE:
 311                 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
 312                 if (check_offset)
 313                         offset = check_offset;
 314                 break;
 315         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 316                 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
 317                 if (check_offset)
 318                         offset = check_offset;
 319                 break;
 320         case COMBIOS_I2C_INFO_TABLE:
 321                 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
 322                 if (check_offset)
 323                         offset = check_offset;
 324                 break;
 325                 /* relative offset tables */
 326         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 327                 check_offset =
 328                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 329                 if (check_offset) {
 330                         rev = RBIOS8(check_offset);
 331                         if (rev > 0) {
 332                                 check_offset = RBIOS16(check_offset + 0x3);
 333                                 if (check_offset)
 334                                         offset = check_offset;
 335                         }
 336                 }
 337                 break;
 338         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 339                 check_offset =
 340                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 341                 if (check_offset) {
 342                         rev = RBIOS8(check_offset);
 343                         if (rev > 0) {
 344                                 check_offset = RBIOS16(check_offset + 0x5);
 345                                 if (check_offset)
 346                                         offset = check_offset;
 347                         }
 348                 }
 349                 break;
 350         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 351                 check_offset =
 352                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 353                 if (check_offset) {
 354                         rev = RBIOS8(check_offset);
 355                         if (rev > 0) {
 356                                 check_offset = RBIOS16(check_offset + 0x7);
 357                                 if (check_offset)
 358                                         offset = check_offset;
 359                         }
 360                 }
 361                 break;
 362         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 363                 check_offset =
 364                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 365                 if (check_offset) {
 366                         rev = RBIOS8(check_offset);
 367                         if (rev == 2) {
 368                                 check_offset = RBIOS16(check_offset + 0x9);
 369                                 if (check_offset)
 370                                         offset = check_offset;
 371                         }
 372                 }
 373                 break;
 374         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 375                 check_offset =
 376                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 377                 if (check_offset) {
 378                         while (RBIOS8(check_offset++));
 379                         check_offset += 2;
 380                         if (check_offset)
 381                                 offset = check_offset;
 382                 }
 383                 break;
 384         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 385                 check_offset =
 386                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 387                 if (check_offset) {
 388                         check_offset = RBIOS16(check_offset + 0x11);
 389                         if (check_offset)
 390                                 offset = check_offset;
 391                 }
 392                 break;
 393         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 394                 check_offset =
 395                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 396                 if (check_offset) {
 397                         check_offset = RBIOS16(check_offset + 0x13);
 398                         if (check_offset)
 399                                 offset = check_offset;
 400                 }
 401                 break;
 402         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 403                 check_offset =
 404                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 405                 if (check_offset) {
 406                         check_offset = RBIOS16(check_offset + 0x15);
 407                         if (check_offset)
 408                                 offset = check_offset;
 409                 }
 410                 break;
 411         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 412                 check_offset =
 413                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 414                 if (check_offset) {
 415                         check_offset = RBIOS16(check_offset + 0x17);
 416                         if (check_offset)
 417                                 offset = check_offset;
 418                 }
 419                 break;
 420         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 421                 check_offset =
 422                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 423                 if (check_offset) {
 424                         check_offset = RBIOS16(check_offset + 0x2);
 425                         if (check_offset)
 426                                 offset = check_offset;
 427                 }
 428                 break;
 429         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 430                 check_offset =
 431                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 432                 if (check_offset) {
 433                         check_offset = RBIOS16(check_offset + 0x4);
 434                         if (check_offset)
 435                                 offset = check_offset;
 436                 }
 437                 break;
 438         default:
 439                 break;
 440         }
 441
 442         return offset;
 443
 444 }
 445
 446 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
 447                                                        int ddc_line)
 448 {
 449         struct radeon_i2c_bus_rec i2c;
 450
 451         if (ddc_line == RADEON_GPIOPAD_MASK) {
 452                 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 453                 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 454                 i2c.a_clk_reg = RADEON_GPIOPAD_A;
 455                 i2c.a_data_reg = RADEON_GPIOPAD_A;
 456                 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
 457                 i2c.en_data_reg = RADEON_GPIOPAD_EN;
 458                 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
 459                 i2c.y_data_reg = RADEON_GPIOPAD_Y;
 460         } else if (ddc_line == RADEON_MDGPIO_MASK) {
 461                 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
 462                 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
 463                 i2c.a_clk_reg = RADEON_MDGPIO_A;
 464                 i2c.a_data_reg = RADEON_MDGPIO_A;
 465                 i2c.en_clk_reg = RADEON_MDGPIO_EN;
 466                 i2c.en_data_reg = RADEON_MDGPIO_EN;
 467                 i2c.y_clk_reg = RADEON_MDGPIO_Y;
 468                 i2c.y_data_reg = RADEON_MDGPIO_Y;
 469         } else {
 470                 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
 471                 i2c.mask_data_mask = RADEON_GPIO_EN_0;
 472                 i2c.a_clk_mask = RADEON_GPIO_A_1;
 473                 i2c.a_data_mask = RADEON_GPIO_A_0;
 474                 i2c.en_clk_mask = RADEON_GPIO_EN_1;
 475                 i2c.en_data_mask = RADEON_GPIO_EN_0;
 476                 i2c.y_clk_mask = RADEON_GPIO_Y_1;
 477                 i2c.y_data_mask = RADEON_GPIO_Y_0;
 478
 479                 i2c.mask_clk_reg = ddc_line;
 480                 i2c.mask_data_reg = ddc_line;
 481                 i2c.a_clk_reg = ddc_line;
 482                 i2c.a_data_reg = ddc_line;
 483                 i2c.en_clk_reg = ddc_line;
 484                 i2c.en_data_reg = ddc_line;
 485                 i2c.y_clk_reg = ddc_line;
 486                 i2c.y_data_reg = ddc_line;
 487         }
 488
 489         if (rdev->family < CHIP_R200)
 490                 i2c.hw_capable = false;
 491         else {
 492                 switch (ddc_line) {
 493                 case RADEON_GPIO_VGA_DDC:
 494                 case RADEON_GPIO_DVI_DDC:
 495                         i2c.hw_capable = true;
 496                         break;
 497                 case RADEON_GPIO_MONID:
 498                         /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
 499                          * reliably on some pre-r4xx hardware; not sure why.
 500                          */
 501                         i2c.hw_capable = false;
 502                         break;
 503                 default:
 504                         i2c.hw_capable = false;
 505                         break;
 506                 }
 507         }
 508         i2c.mm_i2c = false;
 509         i2c.i2c_id = 0;
 510
 511         if (ddc_line)
 512                 i2c.valid = true;
 513         else
 514                 i2c.valid = false;
 515
 516         return i2c;
 517 }
 518
 519 bool radeon_combios_get_clock_info(struct drm_device *dev)
 520 {
 521         struct radeon_device *rdev = dev->dev_private;
 522         uint16_t pll_info;
 523         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 524         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 525         struct radeon_pll *spll = &rdev->clock.spll;
 526         struct radeon_pll *mpll = &rdev->clock.mpll;
 527         int8_t rev;
 528         uint16_t sclk, mclk;
 529
 530         if (rdev->bios == NULL)
 531                 return false;
 532
 533         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 534         if (pll_info) {
 535                 rev = RBIOS8(pll_info);
 536
 537                 /* pixel clocks */
 538                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 539                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 540                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 541                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 542
 543                 if (rev > 9) {
 544                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 545                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 546                 } else {
 547                         p1pll->pll_in_min = 40;
 548                         p1pll->pll_in_max = 500;
 549                 }
 550                 *p2pll = *p1pll;
 551
 552                 /* system clock */
 553                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 554                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 555                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 556                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 557
 558                 if (rev > 10) {
 559                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 560                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 561                 } else {
 562                         /* ??? */
 563                         spll->pll_in_min = 40;
 564                         spll->pll_in_max = 500;
 565                 }
 566
 567                 /* memory clock */
 568                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 569                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 570                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 571                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 572
 573                 if (rev > 10) {
 574                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 575                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 576                 } else {
 577                         /* ??? */
 578                         mpll->pll_in_min = 40;
 579                         mpll->pll_in_max = 500;
 580                 }
 581
 582                 /* default sclk/mclk */
 583                 sclk = RBIOS16(pll_info + 0xa);
 584                 mclk = RBIOS16(pll_info + 0x8);
 585                 if (sclk == 0)
 586                         sclk = 200 * 100;
 587                 if (mclk == 0)
 588                         mclk = 200 * 100;
 589
 590                 rdev->clock.default_sclk = sclk;
 591                 rdev->clock.default_mclk = mclk;
 592
 593                 return true;
 594         }
 595         return false;
 596 }
 597
 598 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 599                                                                        radeon_encoder
 600                                                                        *encoder)
 601 {
 602         struct drm_device *dev = encoder->base.dev;
 603         struct radeon_device *rdev = dev->dev_private;
 604         uint16_t dac_info;
 605         uint8_t rev, bg, dac;
 606         struct radeon_encoder_primary_dac *p_dac = NULL;
 607
 608         if (rdev->bios == NULL)
 609                 return NULL;
 610
 611         /* check CRT table */
 612         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 613         if (dac_info) {
 614                 p_dac =
 615                     kzalloc(sizeof(struct radeon_encoder_primary_dac),
 616                             GFP_KERNEL);
 617
 618                 if (!p_dac)
 619                         return NULL;
 620
 621                 rev = RBIOS8(dac_info) & 0x3;
 622                 if (rev < 2) {
 623                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 624                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 625                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 626                 } else {
 627                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 628                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 629                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 630                 }
 631
 632         }
 633
 634         return p_dac;
 635 }
 636
 637 enum radeon_tv_std
 638 radeon_combios_get_tv_info(struct radeon_device *rdev)
 639 {
 640         struct drm_device *dev = rdev->ddev;
 641         uint16_t tv_info;
 642         enum radeon_tv_std tv_std = TV_STD_NTSC;
 643
 644         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 645         if (tv_info) {
 646                 if (RBIOS8(tv_info + 6) == 'T') {
 647                         switch (RBIOS8(tv_info + 7) & 0xf) {
 648                         case 1:
 649                                 tv_std = TV_STD_NTSC;
 650                                 DRM_INFO("Default TV standard: NTSC\n");
 651                                 break;
 652                         case 2:
 653                                 tv_std = TV_STD_PAL;
 654                                 DRM_INFO("Default TV standard: PAL\n");
 655                                 break;
 656                         case 3:
 657                                 tv_std = TV_STD_PAL_M;
 658                                 DRM_INFO("Default TV standard: PAL-M\n");
 659                                 break;
 660                         case 4:
 661                                 tv_std = TV_STD_PAL_60;
 662                                 DRM_INFO("Default TV standard: PAL-60\n");
 663                                 break;
 664                         case 5:
 665                                 tv_std = TV_STD_NTSC_J;
 666                                 DRM_INFO("Default TV standard: NTSC-J\n");
 667                                 break;
 668                         case 6:
 669                                 tv_std = TV_STD_SCART_PAL;
 670                                 DRM_INFO("Default TV standard: SCART-PAL\n");
 671                                 break;
 672                         default:
 673                                 tv_std = TV_STD_NTSC;
 674                                 DRM_INFO
 675                                     ("Unknown TV standard; defaulting to NTSC\n");
 676                                 break;
 677                         }
 678
 679                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
 680                         case 0:
 681                                 DRM_INFO("29.498928713 MHz TV ref clk\n");
 682                                 break;
 683                         case 1:
 684                                 DRM_INFO("28.636360000 MHz TV ref clk\n");
 685                                 break;
 686                         case 2:
 687                                 DRM_INFO("14.318180000 MHz TV ref clk\n");
 688                                 break;
 689                         case 3:
 690                                 DRM_INFO("27.000000000 MHz TV ref clk\n");
 691                                 break;
 692                         default:
 693                                 break;
 694                         }
 695                 }
 696         }
 697         return tv_std;
 698 }
 699
 700 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
 701         0x00000000,             /* r100  */
 702         0x00280000,             /* rv100 */
 703         0x00000000,             /* rs100 */
 704         0x00880000,             /* rv200 */
 705         0x00000000,             /* rs200 */
 706         0x00000000,             /* r200  */
 707         0x00770000,             /* rv250 */
 708         0x00290000,             /* rs300 */
 709         0x00560000,             /* rv280 */
 710         0x00780000,             /* r300  */
 711         0x00770000,             /* r350  */
 712         0x00780000,             /* rv350 */
 713         0x00780000,             /* rv380 */
 714         0x01080000,             /* r420  */
 715         0x01080000,             /* r423  */
 716         0x01080000,             /* rv410 */
 717         0x00780000,             /* rs400 */
 718         0x00780000,             /* rs480 */
 719 };
 720
 721 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
 722                                                      struct radeon_encoder_tv_dac *tv_dac)
 723 {
 724         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
 725         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
 726                 tv_dac->ps2_tvdac_adj = 0x00880000;
 727         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 728         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 729         return;
 730 }
 731
 732 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
 733                                                              radeon_encoder
 734                                                              *encoder)
 735 {
 736         struct drm_device *dev = encoder->base.dev;
 737         struct radeon_device *rdev = dev->dev_private;
 738         uint16_t dac_info;
 739         uint8_t rev, bg, dac;
 740         struct radeon_encoder_tv_dac *tv_dac = NULL;
 741         int found = 0;
 742
 743         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
 744         if (!tv_dac)
 745                 return NULL;
 746
 747         if (rdev->bios == NULL)
 748                 goto out;
 749
 750         /* first check TV table */
 751         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 752         if (dac_info) {
 753                 rev = RBIOS8(dac_info + 0x3);
 754                 if (rev > 4) {
 755                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 756                         dac = RBIOS8(dac_info + 0xd) & 0xf;
 757                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 758
 759                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 760                         dac = RBIOS8(dac_info + 0xf) & 0xf;
 761                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 762
 763                         bg = RBIOS8(dac_info + 0x10) & 0xf;
 764                         dac = RBIOS8(dac_info + 0x11) & 0xf;
 765                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 766                         found = 1;
 767                 } else if (rev > 1) {
 768                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 769                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
 770                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 771
 772                         bg = RBIOS8(dac_info + 0xd) & 0xf;
 773                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
 774                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 775
 776                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 777                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
 778                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 779                         found = 1;
 780                 }
 781                 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
 782         }
 783         if (!found) {
 784                 /* then check CRT table */
 785                 dac_info =
 786                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 787                 if (dac_info) {
 788                         rev = RBIOS8(dac_info) & 0x3;
 789                         if (rev < 2) {
 790                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
 791                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
 792                                 tv_dac->ps2_tvdac_adj =
 793                                     (bg << 16) | (dac << 20);
 794                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 795                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 796                                 found = 1;
 797                         } else {
 798                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
 799                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
 800                                 tv_dac->ps2_tvdac_adj =
 801                                     (bg << 16) | (dac << 20);
 802                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 803                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 804                                 found = 1;
 805                         }
 806                 } else {
 807                         DRM_INFO("No TV DAC info found in BIOS\n");
 808                 }
 809         }
 810
 811 out:
 812         if (!found) /* fallback to defaults */
 813                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
 814
 815         return tv_dac;
 816 }
 817
 818 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
 819                                                                          radeon_device
 820                                                                          *rdev)
 821 {
 822         struct radeon_encoder_lvds *lvds = NULL;
 823         uint32_t fp_vert_stretch, fp_horz_stretch;
 824         uint32_t ppll_div_sel, ppll_val;
 825         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
 826
 827         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
 828
 829         if (!lvds)
 830                 return NULL;
 831
 832         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
 833         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
 834
 835         /* These should be fail-safe defaults, fingers crossed */
 836         lvds->panel_pwr_delay = 200;
 837         lvds->panel_vcc_delay = 2000;
 838
 839         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 840         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
 841         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
 842
 843         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
 844                 lvds->native_mode.vdisplay =
 845                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
 846                      RADEON_VERT_PANEL_SHIFT) + 1;
 847         else
 848                 lvds->native_mode.vdisplay =
 849                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
 850
 851         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
 852                 lvds->native_mode.hdisplay =
 853                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
 854                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
 855         else
 856                 lvds->native_mode.hdisplay =
 857                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
 858
 859         if ((lvds->native_mode.hdisplay < 640) ||
 860             (lvds->native_mode.vdisplay < 480)) {
 861                 lvds->native_mode.hdisplay = 640;
 862                 lvds->native_mode.vdisplay = 480;
 863         }
 864
 865         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
 866         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
 867         if ((ppll_val & 0x000707ff) == 0x1bb)
 868                 lvds->use_bios_dividers = false;
 869         else {
 870                 lvds->panel_ref_divider =
 871                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
 872                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
 873                 lvds->panel_fb_divider = ppll_val & 0x7ff;
 874
 875                 if ((lvds->panel_ref_divider != 0) &&
 876                     (lvds->panel_fb_divider > 3))
 877                         lvds->use_bios_dividers = true;
 878         }
 879         lvds->panel_vcc_delay = 200;
 880
 881         DRM_INFO("Panel info derived from registers\n");
 882         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
 883                  lvds->native_mode.vdisplay);
 884
 885         return lvds;
 886 }
 887
 888 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
 889                                                          *encoder)
 890 {
 891         struct drm_device *dev = encoder->base.dev;
 892         struct radeon_device *rdev = dev->dev_private;
 893         uint16_t lcd_info;
 894         uint32_t panel_setup;
 895         char stmp[30];
 896         int tmp, i;
 897         struct radeon_encoder_lvds *lvds = NULL;
 898
 899         if (rdev->bios == NULL) {
 900                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
 901                 goto out;
 902         }
 903
 904         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
 905
 906         if (lcd_info) {
 907                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
 908
 909                 if (!lvds)
 910                         return NULL;
 911
 912                 for (i = 0; i < 24; i++)
 913                         stmp[i] = RBIOS8(lcd_info + i + 1);
 914                 stmp[24] = 0;
 915
 916                 DRM_INFO("Panel ID String: %s\n", stmp);
 917
 918                 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
 919                 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
 920
 921                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
 922                          lvds->native_mode.vdisplay);
 923
 924                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
 925                 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0)
 926                         lvds->panel_vcc_delay = 2000;
 927
 928                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
 929                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
 930                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
 931
 932                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
 933                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
 934                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
 935                 if ((lvds->panel_ref_divider != 0) &&
 936                     (lvds->panel_fb_divider > 3))
 937                         lvds->use_bios_dividers = true;
 938
 939                 panel_setup = RBIOS32(lcd_info + 0x39);
 940                 lvds->lvds_gen_cntl = 0xff00;
 941                 if (panel_setup & 0x1)
 942                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
 943
 944                 if ((panel_setup >> 4) & 0x1)
 945                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
 946
 947                 switch ((panel_setup >> 8) & 0x7) {
 948                 case 0:
 949                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
 950                         break;
 951                 case 1:
 952                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
 953                         break;
 954                 case 2:
 955                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
 956                         break;
 957                 default:
 958                         break;
 959                 }
 960
 961                 if ((panel_setup >> 16) & 0x1)
 962                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
 963
 964                 if ((panel_setup >> 17) & 0x1)
 965                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
 966
 967                 if ((panel_setup >> 18) & 0x1)
 968                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
 969
 970                 if ((panel_setup >> 23) & 0x1)
 971                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
 972
 973                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
 974
 975                 for (i = 0; i < 32; i++) {
 976                         tmp = RBIOS16(lcd_info + 64 + i * 2);
 977                         if (tmp == 0)
 978                                 break;
 979
 980                         if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
 981                             (RBIOS16(tmp + 2) ==
 982                              lvds->native_mode.vdisplay)) {
 983                                 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
 984                                 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
 985                                 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
 986                                                                RBIOS16(tmp + 21)) * 8;
 987
 988                                 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
 989                                 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
 990                                 lvds->native_mode.vsync_end =
 991                                         ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
 992                                         (RBIOS16(tmp + 28) & 0x7ff);
 993
 994                                 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
 995                                 lvds->native_mode.flags = 0;
 996                                 /* set crtc values */
 997                                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
 998
 999                         }
1000                 }
1001         } else {
1002                 DRM_INFO("No panel info found in BIOS\n");
1003                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1004         }
1005 out:
1006         if (lvds)
1007                 encoder->native_mode = lvds->native_mode;
1008         return lvds;
1009 }
1010
1011 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1012         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
1013         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
1014         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
1015         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
1016         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
1017         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
1018         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
1019         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
1020         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
1021         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
1022         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
1023         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
1024         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
1025         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
1026         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
1027         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
1028         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS400 */
1029         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS480 */
1030 };
1031
1032 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1033                                             struct radeon_encoder_int_tmds *tmds)
1034 {
1035         struct drm_device *dev = encoder->base.dev;
1036         struct radeon_device *rdev = dev->dev_private;
1037         int i;
1038
1039         for (i = 0; i < 4; i++) {
1040                 tmds->tmds_pll[i].value =
1041                         default_tmds_pll[rdev->family][i].value;
1042                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1043         }
1044
1045         return true;
1046 }
1047
1048 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1049                                               struct radeon_encoder_int_tmds *tmds)
1050 {
1051         struct drm_device *dev = encoder->base.dev;
1052         struct radeon_device *rdev = dev->dev_private;
1053         uint16_t tmds_info;
1054         int i, n;
1055         uint8_t ver;
1056
1057         if (rdev->bios == NULL)
1058                 return false;
1059
1060         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1061
1062         if (tmds_info) {
1063                 ver = RBIOS8(tmds_info);
1064                 DRM_INFO("DFP table revision: %d\n", ver);
1065                 if (ver == 3) {
1066                         n = RBIOS8(tmds_info + 5) + 1;
1067                         if (n > 4)
1068                                 n = 4;
1069                         for (i = 0; i < n; i++) {
1070                                 tmds->tmds_pll[i].value =
1071                                     RBIOS32(tmds_info + i * 10 + 0x08);
1072                                 tmds->tmds_pll[i].freq =
1073                                     RBIOS16(tmds_info + i * 10 + 0x10);
1074                                 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1075                                           tmds->tmds_pll[i].freq,
1076                                           tmds->tmds_pll[i].value);
1077                         }
1078                 } else if (ver == 4) {
1079                         int stride = 0;
1080                         n = RBIOS8(tmds_info + 5) + 1;
1081                         if (n > 4)
1082                                 n = 4;
1083                         for (i = 0; i < n; i++) {
1084                                 tmds->tmds_pll[i].value =
1085                                     RBIOS32(tmds_info + stride + 0x08);
1086                                 tmds->tmds_pll[i].freq =
1087                                     RBIOS16(tmds_info + stride + 0x10);
1088                                 if (i == 0)
1089                                         stride += 10;
1090                                 else
1091                                         stride += 6;
1092                                 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1093                                           tmds->tmds_pll[i].freq,
1094                                           tmds->tmds_pll[i].value);
1095                         }
1096                 }
1097         } else {
1098                 DRM_INFO("No TMDS info found in BIOS\n");
1099                 return false;
1100         }
1101         return true;
1102 }
1103
1104 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1105                                                 struct radeon_encoder_ext_tmds *tmds)
1106 {
1107         struct drm_device *dev = encoder->base.dev;
1108         struct radeon_device *rdev = dev->dev_private;
1109         struct radeon_i2c_bus_rec i2c_bus;
1110
1111         /* default for macs */
1112         i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1113         tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1114
1115         /* XXX some macs have duallink chips */
1116         switch (rdev->mode_info.connector_table) {
1117         case CT_POWERBOOK_EXTERNAL:
1118         case CT_MINI_EXTERNAL:
1119         default:
1120                 tmds->dvo_chip = DVO_SIL164;
1121                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1122                 break;
1123         }
1124
1125         return true;
1126 }
1127
1128 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1129                                                   struct radeon_encoder_ext_tmds *tmds)
1130 {
1131         struct drm_device *dev = encoder->base.dev;
1132         struct radeon_device *rdev = dev->dev_private;
1133         uint16_t offset;
1134         uint8_t ver, id, blocks, clk, data;
1135         int i;
1136         enum radeon_combios_ddc gpio;
1137         struct radeon_i2c_bus_rec i2c_bus;
1138
1139         if (rdev->bios == NULL)
1140                 return false;
1141
1142         tmds->i2c_bus = NULL;
1143         if (rdev->flags & RADEON_IS_IGP) {
1144                 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1145                 if (offset) {
1146                         ver = RBIOS8(offset);
1147                         DRM_INFO("GPIO Table revision: %d\n", ver);
1148                         blocks = RBIOS8(offset + 2);
1149                         for (i = 0; i < blocks; i++) {
1150                                 id = RBIOS8(offset + 3 + (i * 5) + 0);
1151                                 if (id == 136) {
1152                                         clk = RBIOS8(offset + 3 + (i * 5) + 3);
1153                                         data = RBIOS8(offset + 3 + (i * 5) + 4);
1154                                         i2c_bus.valid = true;
1155                                         i2c_bus.mask_clk_mask = (1 << clk);
1156                                         i2c_bus.mask_data_mask = (1 << data);
1157                                         i2c_bus.a_clk_mask = (1 << clk);
1158                                         i2c_bus.a_data_mask = (1 << data);
1159                                         i2c_bus.en_clk_mask = (1 << clk);
1160                                         i2c_bus.en_data_mask = (1 << data);
1161                                         i2c_bus.y_clk_mask = (1 << clk);
1162                                         i2c_bus.y_data_mask = (1 << data);
1163                                         i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1164                                         i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1165                                         i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1166                                         i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1167                                         i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1168                                         i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1169                                         i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1170                                         i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1171                                         tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1172                                         tmds->dvo_chip = DVO_SIL164;
1173                                         tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1174                                         break;
1175                                 }
1176                         }
1177                 }
1178         } else {
1179                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1180                 if (offset) {
1181                         ver = RBIOS8(offset);
1182                         DRM_INFO("External TMDS Table revision: %d\n", ver);
1183                         tmds->slave_addr = RBIOS8(offset + 4 + 2);
1184                         tmds->slave_addr >>= 1; /* 7 bit addressing */
1185                         gpio = RBIOS8(offset + 4 + 3);
1186                         switch (gpio) {
1187                         case DDC_MONID:
1188                                 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1189                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1190                                 break;
1191                         case DDC_DVI:
1192                                 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1193                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1194                                 break;
1195                         case DDC_VGA:
1196                                 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1197                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1198                                 break;
1199                         case DDC_CRT2:
1200                                 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1201                                 if (rdev->family >= CHIP_R300)
1202                                         i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1203                                 else
1204                                         i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1205                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1206                                 break;
1207                         case DDC_LCD: /* MM i2c */
1208                                 DRM_ERROR("MM i2c requires hw i2c engine\n");
1209                                 break;
1210                         default:
1211                                 DRM_ERROR("Unsupported gpio %d\n", gpio);
1212                                 break;
1213                         }
1214                 }
1215         }
1216
1217         if (!tmds->i2c_bus) {
1218                 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1219                 return false;
1220         }
1221
1222         return true;
1223 }
1224
1225 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1226 {
1227         struct radeon_device *rdev = dev->dev_private;
1228         struct radeon_i2c_bus_rec ddc_i2c;
1229         struct radeon_hpd hpd;
1230
1231         rdev->mode_info.connector_table = radeon_connector_table;
1232         if (rdev->mode_info.connector_table == CT_NONE) {
1233 #ifdef CONFIG_PPC_PMAC
1234                 if (machine_is_compatible("PowerBook3,3")) {
1235                         /* powerbook with VGA */
1236                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1237                 } else if (machine_is_compatible("PowerBook3,4") ||
1238                            machine_is_compatible("PowerBook3,5")) {
1239                         /* powerbook with internal tmds */
1240                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1241                 } else if (machine_is_compatible("PowerBook5,1") ||
1242                            machine_is_compatible("PowerBook5,2") ||
1243                            machine_is_compatible("PowerBook5,3") ||
1244                            machine_is_compatible("PowerBook5,4") ||
1245                            machine_is_compatible("PowerBook5,5")) {
1246                         /* powerbook with external single link tmds (sil164) */
1247                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1248                 } else if (machine_is_compatible("PowerBook5,6")) {
1249                         /* powerbook with external dual or single link tmds */
1250                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1251                 } else if (machine_is_compatible("PowerBook5,7") ||
1252                            machine_is_compatible("PowerBook5,8") ||
1253                            machine_is_compatible("PowerBook5,9")) {
1254                         /* PowerBook6,2 ? */
1255                         /* powerbook with external dual link tmds (sil1178?) */
1256                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1257                 } else if (machine_is_compatible("PowerBook4,1") ||
1258                            machine_is_compatible("PowerBook4,2") ||
1259                            machine_is_compatible("PowerBook4,3") ||
1260                            machine_is_compatible("PowerBook6,3") ||
1261                            machine_is_compatible("PowerBook6,5") ||
1262                            machine_is_compatible("PowerBook6,7")) {
1263                         /* ibook */
1264                         rdev->mode_info.connector_table = CT_IBOOK;
1265                 } else if (machine_is_compatible("PowerMac4,4")) {
1266                         /* emac */
1267                         rdev->mode_info.connector_table = CT_EMAC;
1268                 } else if (machine_is_compatible("PowerMac10,1")) {
1269                         /* mini with internal tmds */
1270                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1271                 } else if (machine_is_compatible("PowerMac10,2")) {
1272                         /* mini with external tmds */
1273                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1274                 } else if (machine_is_compatible("PowerMac12,1")) {
1275                         /* PowerMac8,1 ? */
1276                         /* imac g5 isight */
1277                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1278                 } else
1279 #endif /* CONFIG_PPC_PMAC */
1280                         rdev->mode_info.connector_table = CT_GENERIC;
1281         }
1282
1283         switch (rdev->mode_info.connector_table) {
1284         case CT_GENERIC:
1285                 DRM_INFO("Connector Table: %d (generic)\n",
1286                          rdev->mode_info.connector_table);
1287                 /* these are the most common settings */
1288                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1289                         /* VGA - primary dac */
1290                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1291                         hpd.hpd = RADEON_HPD_NONE;
1292                         radeon_add_legacy_encoder(dev,
1293                                                   radeon_get_encoder_id(dev,
1294                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1295                                                                         1),
1296                                                   ATOM_DEVICE_CRT1_SUPPORT);
1297                         radeon_add_legacy_connector(dev, 0,
1298                                                     ATOM_DEVICE_CRT1_SUPPORT,
1299                                                     DRM_MODE_CONNECTOR_VGA,
1300                                                     &ddc_i2c,
1301                                                     CONNECTOR_OBJECT_ID_VGA,
1302                                                     &hpd);
1303                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1304                         /* LVDS */
1305                         ddc_i2c = combios_setup_i2c_bus(rdev, 0);
1306                         hpd.hpd = RADEON_HPD_NONE;
1307                         radeon_add_legacy_encoder(dev,
1308                                                   radeon_get_encoder_id(dev,
1309                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1310                                                                         0),
1311                                                   ATOM_DEVICE_LCD1_SUPPORT);
1312                         radeon_add_legacy_connector(dev, 0,
1313                                                     ATOM_DEVICE_LCD1_SUPPORT,
1314                                                     DRM_MODE_CONNECTOR_LVDS,
1315                                                     &ddc_i2c,
1316                                                     CONNECTOR_OBJECT_ID_LVDS,
1317                                                     &hpd);
1318
1319                         /* VGA - primary dac */
1320                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1321                         hpd.hpd = RADEON_HPD_NONE;
1322                         radeon_add_legacy_encoder(dev,
1323                                                   radeon_get_encoder_id(dev,
1324                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1325                                                                         1),
1326                                                   ATOM_DEVICE_CRT1_SUPPORT);
1327                         radeon_add_legacy_connector(dev, 1,
1328                                                     ATOM_DEVICE_CRT1_SUPPORT,
1329                                                     DRM_MODE_CONNECTOR_VGA,
1330                                                     &ddc_i2c,
1331                                                     CONNECTOR_OBJECT_ID_VGA,
1332                                                     &hpd);
1333                 } else {
1334                         /* DVI-I - tv dac, int tmds */
1335                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1336                         hpd.hpd = RADEON_HPD_1;
1337                         radeon_add_legacy_encoder(dev,
1338                                                   radeon_get_encoder_id(dev,
1339                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1340                                                                         0),
1341                                                   ATOM_DEVICE_DFP1_SUPPORT);
1342                         radeon_add_legacy_encoder(dev,
1343                                                   radeon_get_encoder_id(dev,
1344                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1345                                                                         2),
1346                                                   ATOM_DEVICE_CRT2_SUPPORT);
1347                         radeon_add_legacy_connector(dev, 0,
1348                                                     ATOM_DEVICE_DFP1_SUPPORT |
1349                                                     ATOM_DEVICE_CRT2_SUPPORT,
1350                                                     DRM_MODE_CONNECTOR_DVII,
1351                                                     &ddc_i2c,
1352                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1353                                                     &hpd);
1354
1355                         /* VGA - primary dac */
1356                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1357                         hpd.hpd = RADEON_HPD_NONE;
1358                         radeon_add_legacy_encoder(dev,
1359                                                   radeon_get_encoder_id(dev,
1360                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1361                                                                         1),
1362                                                   ATOM_DEVICE_CRT1_SUPPORT);
1363                         radeon_add_legacy_connector(dev, 1,
1364                                                     ATOM_DEVICE_CRT1_SUPPORT,
1365                                                     DRM_MODE_CONNECTOR_VGA,
1366                                                     &ddc_i2c,
1367                                                     CONNECTOR_OBJECT_ID_VGA,
1368                                                     &hpd);
1369                 }
1370
1371                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1372                         /* TV - tv dac */
1373                         ddc_i2c.valid = false;
1374                         hpd.hpd = RADEON_HPD_NONE;
1375                         radeon_add_legacy_encoder(dev,
1376                                                   radeon_get_encoder_id(dev,
1377                                                                         ATOM_DEVICE_TV1_SUPPORT,
1378                                                                         2),
1379                                                   ATOM_DEVICE_TV1_SUPPORT);
1380                         radeon_add_legacy_connector(dev, 2,
1381                                                     ATOM_DEVICE_TV1_SUPPORT,
1382                                                     DRM_MODE_CONNECTOR_SVIDEO,
1383                                                     &ddc_i2c,
1384                                                     CONNECTOR_OBJECT_ID_SVIDEO,
1385                                                     &hpd);
1386                 }
1387                 break;
1388         case CT_IBOOK:
1389                 DRM_INFO("Connector Table: %d (ibook)\n",
1390                          rdev->mode_info.connector_table);
1391                 /* LVDS */
1392                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1393                 hpd.hpd = RADEON_HPD_NONE;
1394                 radeon_add_legacy_encoder(dev,
1395                                           radeon_get_encoder_id(dev,
1396                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1397                                                                 0),
1398                                           ATOM_DEVICE_LCD1_SUPPORT);
1399                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1400                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1401                                             CONNECTOR_OBJECT_ID_LVDS,
1402                                             &hpd);
1403                 /* VGA - TV DAC */
1404                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1405                 hpd.hpd = RADEON_HPD_NONE;
1406                 radeon_add_legacy_encoder(dev,
1407                                           radeon_get_encoder_id(dev,
1408                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1409                                                                 2),
1410                                           ATOM_DEVICE_CRT2_SUPPORT);
1411                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1412                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1413                                             CONNECTOR_OBJECT_ID_VGA,
1414                                             &hpd);
1415                 /* TV - TV DAC */
1416                 ddc_i2c.valid = false;
1417                 hpd.hpd = RADEON_HPD_NONE;
1418                 radeon_add_legacy_encoder(dev,
1419                                           radeon_get_encoder_id(dev,
1420                                                                 ATOM_DEVICE_TV1_SUPPORT,
1421                                                                 2),
1422                                           ATOM_DEVICE_TV1_SUPPORT);
1423                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1424                                             DRM_MODE_CONNECTOR_SVIDEO,
1425                                             &ddc_i2c,
1426                                             CONNECTOR_OBJECT_ID_SVIDEO,
1427                                             &hpd);
1428                 break;
1429         case CT_POWERBOOK_EXTERNAL:
1430                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1431                          rdev->mode_info.connector_table);
1432                 /* LVDS */
1433                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1434                 hpd.hpd = RADEON_HPD_NONE;
1435                 radeon_add_legacy_encoder(dev,
1436                                           radeon_get_encoder_id(dev,
1437                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1438                                                                 0),
1439                                           ATOM_DEVICE_LCD1_SUPPORT);
1440                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1441                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1442                                             CONNECTOR_OBJECT_ID_LVDS,
1443                                             &hpd);
1444                 /* DVI-I - primary dac, ext tmds */
1445                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1446                 hpd.hpd = RADEON_HPD_2; /* ??? */
1447                 radeon_add_legacy_encoder(dev,
1448                                           radeon_get_encoder_id(dev,
1449                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1450                                                                 0),
1451                                           ATOM_DEVICE_DFP2_SUPPORT);
1452                 radeon_add_legacy_encoder(dev,
1453                                           radeon_get_encoder_id(dev,
1454                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1455                                                                 1),
1456                                           ATOM_DEVICE_CRT1_SUPPORT);
1457                 /* XXX some are SL */
1458                 radeon_add_legacy_connector(dev, 1,
1459                                             ATOM_DEVICE_DFP2_SUPPORT |
1460                                             ATOM_DEVICE_CRT1_SUPPORT,
1461                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1462                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1463                                             &hpd);
1464                 /* TV - TV DAC */
1465                 ddc_i2c.valid = false;
1466                 hpd.hpd = RADEON_HPD_NONE;
1467                 radeon_add_legacy_encoder(dev,
1468                                           radeon_get_encoder_id(dev,
1469                                                                 ATOM_DEVICE_TV1_SUPPORT,
1470                                                                 2),
1471                                           ATOM_DEVICE_TV1_SUPPORT);
1472                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1473                                             DRM_MODE_CONNECTOR_SVIDEO,
1474                                             &ddc_i2c,
1475                                             CONNECTOR_OBJECT_ID_SVIDEO,
1476                                             &hpd);
1477                 break;
1478         case CT_POWERBOOK_INTERNAL:
1479                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1480                          rdev->mode_info.connector_table);
1481                 /* LVDS */
1482                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1483                 hpd.hpd = RADEON_HPD_NONE;
1484                 radeon_add_legacy_encoder(dev,
1485                                           radeon_get_encoder_id(dev,
1486                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1487                                                                 0),
1488                                           ATOM_DEVICE_LCD1_SUPPORT);
1489                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1490                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1491                                             CONNECTOR_OBJECT_ID_LVDS,
1492                                             &hpd);
1493                 /* DVI-I - primary dac, int tmds */
1494                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1495                 hpd.hpd = RADEON_HPD_1; /* ??? */
1496                 radeon_add_legacy_encoder(dev,
1497                                           radeon_get_encoder_id(dev,
1498                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1499                                                                 0),
1500                                           ATOM_DEVICE_DFP1_SUPPORT);
1501                 radeon_add_legacy_encoder(dev,
1502                                           radeon_get_encoder_id(dev,
1503                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1504                                                                 1),
1505                                           ATOM_DEVICE_CRT1_SUPPORT);
1506                 radeon_add_legacy_connector(dev, 1,
1507                                             ATOM_DEVICE_DFP1_SUPPORT |
1508                                             ATOM_DEVICE_CRT1_SUPPORT,
1509                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1510                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1511                                             &hpd);
1512                 /* TV - TV DAC */
1513                 ddc_i2c.valid = false;
1514                 hpd.hpd = RADEON_HPD_NONE;
1515                 radeon_add_legacy_encoder(dev,
1516                                           radeon_get_encoder_id(dev,
1517                                                                 ATOM_DEVICE_TV1_SUPPORT,
1518                                                                 2),
1519                                           ATOM_DEVICE_TV1_SUPPORT);
1520                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1521                                             DRM_MODE_CONNECTOR_SVIDEO,
1522                                             &ddc_i2c,
1523                                             CONNECTOR_OBJECT_ID_SVIDEO,
1524                                             &hpd);
1525                 break;
1526         case CT_POWERBOOK_VGA:
1527                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1528                          rdev->mode_info.connector_table);
1529                 /* LVDS */
1530                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1531                 hpd.hpd = RADEON_HPD_NONE;
1532                 radeon_add_legacy_encoder(dev,
1533                                           radeon_get_encoder_id(dev,
1534                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1535                                                                 0),
1536                                           ATOM_DEVICE_LCD1_SUPPORT);
1537                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1538                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1539                                             CONNECTOR_OBJECT_ID_LVDS,
1540                                             &hpd);
1541                 /* VGA - primary dac */
1542                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1543                 hpd.hpd = RADEON_HPD_NONE;
1544                 radeon_add_legacy_encoder(dev,
1545                                           radeon_get_encoder_id(dev,
1546                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1547                                                                 1),
1548                                           ATOM_DEVICE_CRT1_SUPPORT);
1549                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1550                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1551                                             CONNECTOR_OBJECT_ID_VGA,
1552                                             &hpd);
1553                 /* TV - TV DAC */
1554                 ddc_i2c.valid = false;
1555                 hpd.hpd = RADEON_HPD_NONE;
1556                 radeon_add_legacy_encoder(dev,
1557                                           radeon_get_encoder_id(dev,
1558                                                                 ATOM_DEVICE_TV1_SUPPORT,
1559                                                                 2),
1560                                           ATOM_DEVICE_TV1_SUPPORT);
1561                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1562                                             DRM_MODE_CONNECTOR_SVIDEO,
1563                                             &ddc_i2c,
1564                                             CONNECTOR_OBJECT_ID_SVIDEO,
1565                                             &hpd);
1566                 break;
1567         case CT_MINI_EXTERNAL:
1568                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1569                          rdev->mode_info.connector_table);
1570                 /* DVI-I - tv dac, ext tmds */
1571                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1572                 hpd.hpd = RADEON_HPD_2; /* ??? */
1573                 radeon_add_legacy_encoder(dev,
1574                                           radeon_get_encoder_id(dev,
1575                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1576                                                                 0),
1577                                           ATOM_DEVICE_DFP2_SUPPORT);
1578                 radeon_add_legacy_encoder(dev,
1579                                           radeon_get_encoder_id(dev,
1580                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1581                                                                 2),
1582                                           ATOM_DEVICE_CRT2_SUPPORT);
1583                 /* XXX are any DL? */
1584                 radeon_add_legacy_connector(dev, 0,
1585                                             ATOM_DEVICE_DFP2_SUPPORT |
1586                                             ATOM_DEVICE_CRT2_SUPPORT,
1587                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1588                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1589                                             &hpd);
1590                 /* TV - TV DAC */
1591                 ddc_i2c.valid = false;
1592                 hpd.hpd = RADEON_HPD_NONE;
1593                 radeon_add_legacy_encoder(dev,
1594                                           radeon_get_encoder_id(dev,
1595                                                                 ATOM_DEVICE_TV1_SUPPORT,
1596                                                                 2),
1597                                           ATOM_DEVICE_TV1_SUPPORT);
1598                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1599                                             DRM_MODE_CONNECTOR_SVIDEO,
1600                                             &ddc_i2c,
1601                                             CONNECTOR_OBJECT_ID_SVIDEO,
1602                                             &hpd);
1603                 break;
1604         case CT_MINI_INTERNAL:
1605                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1606                          rdev->mode_info.connector_table);
1607                 /* DVI-I - tv dac, int tmds */
1608                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1609                 hpd.hpd = RADEON_HPD_1; /* ??? */
1610                 radeon_add_legacy_encoder(dev,
1611                                           radeon_get_encoder_id(dev,
1612                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1613                                                                 0),
1614                                           ATOM_DEVICE_DFP1_SUPPORT);
1615                 radeon_add_legacy_encoder(dev,
1616                                           radeon_get_encoder_id(dev,
1617                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1618                                                                 2),
1619                                           ATOM_DEVICE_CRT2_SUPPORT);
1620                 radeon_add_legacy_connector(dev, 0,
1621                                             ATOM_DEVICE_DFP1_SUPPORT |
1622                                             ATOM_DEVICE_CRT2_SUPPORT,
1623                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1624                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1625                                             &hpd);
1626                 /* TV - TV DAC */
1627                 ddc_i2c.valid = false;
1628                 hpd.hpd = RADEON_HPD_NONE;
1629                 radeon_add_legacy_encoder(dev,
1630                                           radeon_get_encoder_id(dev,
1631                                                                 ATOM_DEVICE_TV1_SUPPORT,
1632                                                                 2),
1633                                           ATOM_DEVICE_TV1_SUPPORT);
1634                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1635                                             DRM_MODE_CONNECTOR_SVIDEO,
1636                                             &ddc_i2c,
1637                                             CONNECTOR_OBJECT_ID_SVIDEO,
1638                                             &hpd);
1639                 break;
1640         case CT_IMAC_G5_ISIGHT:
1641                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1642                          rdev->mode_info.connector_table);
1643                 /* DVI-D - int tmds */
1644                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1645                 hpd.hpd = RADEON_HPD_1; /* ??? */
1646                 radeon_add_legacy_encoder(dev,
1647                                           radeon_get_encoder_id(dev,
1648                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1649                                                                 0),
1650                                           ATOM_DEVICE_DFP1_SUPPORT);
1651                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1652                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1653                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1654                                             &hpd);
1655                 /* VGA - tv dac */
1656                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1657                 hpd.hpd = RADEON_HPD_NONE;
1658                 radeon_add_legacy_encoder(dev,
1659                                           radeon_get_encoder_id(dev,
1660                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1661                                                                 2),
1662                                           ATOM_DEVICE_CRT2_SUPPORT);
1663                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1664                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1665                                             CONNECTOR_OBJECT_ID_VGA,
1666                                             &hpd);
1667                 /* TV - TV DAC */
1668                 ddc_i2c.valid = false;
1669                 hpd.hpd = RADEON_HPD_NONE;
1670                 radeon_add_legacy_encoder(dev,
1671                                           radeon_get_encoder_id(dev,
1672                                                                 ATOM_DEVICE_TV1_SUPPORT,
1673                                                                 2),
1674                                           ATOM_DEVICE_TV1_SUPPORT);
1675                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1676                                             DRM_MODE_CONNECTOR_SVIDEO,
1677                                             &ddc_i2c,
1678                                             CONNECTOR_OBJECT_ID_SVIDEO,
1679                                             &hpd);
1680                 break;
1681         case CT_EMAC:
1682                 DRM_INFO("Connector Table: %d (emac)\n",
1683                          rdev->mode_info.connector_table);
1684                 /* VGA - primary dac */
1685                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1686                 hpd.hpd = RADEON_HPD_NONE;
1687                 radeon_add_legacy_encoder(dev,
1688                                           radeon_get_encoder_id(dev,
1689                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1690                                                                 1),
1691                                           ATOM_DEVICE_CRT1_SUPPORT);
1692                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1693                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1694                                             CONNECTOR_OBJECT_ID_VGA,
1695                                             &hpd);
1696                 /* VGA - tv dac */
1697                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1698                 hpd.hpd = RADEON_HPD_NONE;
1699                 radeon_add_legacy_encoder(dev,
1700                                           radeon_get_encoder_id(dev,
1701                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1702                                                                 2),
1703                                           ATOM_DEVICE_CRT2_SUPPORT);
1704                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1705                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1706                                             CONNECTOR_OBJECT_ID_VGA,
1707                                             &hpd);
1708                 /* TV - TV DAC */
1709                 ddc_i2c.valid = false;
1710                 hpd.hpd = RADEON_HPD_NONE;
1711                 radeon_add_legacy_encoder(dev,
1712                                           radeon_get_encoder_id(dev,
1713                                                                 ATOM_DEVICE_TV1_SUPPORT,
1714                                                                 2),
1715                                           ATOM_DEVICE_TV1_SUPPORT);
1716                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1717                                             DRM_MODE_CONNECTOR_SVIDEO,
1718                                             &ddc_i2c,
1719                                             CONNECTOR_OBJECT_ID_SVIDEO,
1720                                             &hpd);
1721                 break;
1722         default:
1723                 DRM_INFO("Connector table: %d (invalid)\n",
1724                          rdev->mode_info.connector_table);
1725                 return false;
1726         }
1727
1728         radeon_link_encoder_connector(dev);
1729
1730         return true;
1731 }
1732
1733 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1734                                        int bios_index,
1735                                        enum radeon_combios_connector
1736                                        *legacy_connector,
1737                                        struct radeon_i2c_bus_rec *ddc_i2c,
1738                                        struct radeon_hpd *hpd)
1739 {
1740         struct radeon_device *rdev = dev->dev_private;
1741
1742         /* XPRESS DDC quirks */
1743         if ((rdev->family == CHIP_RS400 ||
1744              rdev->family == CHIP_RS480) &&
1745             ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1746                 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1747         else if ((rdev->family == CHIP_RS400 ||
1748                   rdev->family == CHIP_RS480) &&
1749                  ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1750                 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
1751                 ddc_i2c->mask_clk_mask = (0x20 << 8);
1752                 ddc_i2c->mask_data_mask = 0x80;
1753                 ddc_i2c->a_clk_mask = (0x20 << 8);
1754                 ddc_i2c->a_data_mask = 0x80;
1755                 ddc_i2c->en_clk_mask = (0x20 << 8);
1756                 ddc_i2c->en_data_mask = 0x80;
1757                 ddc_i2c->y_clk_mask = (0x20 << 8);
1758                 ddc_i2c->y_data_mask = 0x80;
1759         }
1760
1761         /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1762         if ((rdev->family >= CHIP_R300) &&
1763             ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1764                 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1765
1766         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1767            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1768         if (dev->pdev->device == 0x515e &&
1769             dev->pdev->subsystem_vendor == 0x1014) {
1770                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1771                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1772                         return false;
1773         }
1774
1775         /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1776         if (dev->pdev->device == 0x5159 &&
1777             dev->pdev->subsystem_vendor == 0x1002 &&
1778             dev->pdev->subsystem_device == 0x013a) {
1779                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1780                         *legacy_connector = CONNECTOR_CRT_LEGACY;
1781
1782         }
1783
1784         /* X300 card with extra non-existent DVI port */
1785         if (dev->pdev->device == 0x5B60 &&
1786             dev->pdev->subsystem_vendor == 0x17af &&
1787             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1788                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1789                         return false;
1790         }
1791
1792         return true;
1793 }
1794
1795 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1796 {
1797         /* Acer 5102 has non-existent TV port */
1798         if (dev->pdev->device == 0x5975 &&
1799             dev->pdev->subsystem_vendor == 0x1025 &&
1800             dev->pdev->subsystem_device == 0x009f)
1801                 return false;
1802
1803         /* HP dc5750 has non-existent TV port */
1804         if (dev->pdev->device == 0x5974 &&
1805             dev->pdev->subsystem_vendor == 0x103c &&
1806             dev->pdev->subsystem_device == 0x280a)
1807                 return false;
1808
1809         /* MSI S270 has non-existent TV port */
1810         if (dev->pdev->device == 0x5955 &&
1811             dev->pdev->subsystem_vendor == 0x1462 &&
1812             dev->pdev->subsystem_device == 0x0131)
1813                 return false;
1814
1815         return true;
1816 }
1817
1818 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1819 {
1820         struct radeon_device *rdev = dev->dev_private;
1821         uint32_t ext_tmds_info;
1822
1823         if (rdev->flags & RADEON_IS_IGP) {
1824                 if (is_dvi_d)
1825                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1826                 else
1827                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1828         }
1829         ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1830         if (ext_tmds_info) {
1831                 uint8_t rev = RBIOS8(ext_tmds_info);
1832                 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1833                 if (rev >= 3) {
1834                         if (is_dvi_d)
1835                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1836                         else
1837                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1838                 } else {
1839                         if (flags & 1) {
1840                                 if (is_dvi_d)
1841                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1842                                 else
1843                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1844                         }
1845                 }
1846         }
1847         if (is_dvi_d)
1848                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1849         else
1850                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1851 }
1852
1853 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1854 {
1855         struct radeon_device *rdev = dev->dev_private;
1856         uint32_t conn_info, entry, devices;
1857         uint16_t tmp, connector_object_id;
1858         enum radeon_combios_ddc ddc_type;
1859         enum radeon_combios_connector connector;
1860         int i = 0;
1861         struct radeon_i2c_bus_rec ddc_i2c;
1862         struct radeon_hpd hpd;
1863
1864         if (rdev->bios == NULL)
1865                 return false;
1866
1867         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1868         if (conn_info) {
1869                 for (i = 0; i < 4; i++) {
1870                         entry = conn_info + 2 + i * 2;
1871
1872                         if (!RBIOS16(entry))
1873                                 break;
1874
1875                         tmp = RBIOS16(entry);
1876
1877                         connector = (tmp >> 12) & 0xf;
1878
1879                         ddc_type = (tmp >> 8) & 0xf;
1880                         switch (ddc_type) {
1881                         case DDC_MONID:
1882                                 ddc_i2c =
1883                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1884                                 break;
1885                         case DDC_DVI:
1886                                 ddc_i2c =
1887                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1888                                 break;
1889                         case DDC_VGA:
1890                                 ddc_i2c =
1891                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1892                                 break;
1893                         case DDC_CRT2:
1894                                 ddc_i2c =
1895                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1896                                 break;
1897                         default:
1898                                 break;
1899                         }
1900
1901                         switch (connector) {
1902                         case CONNECTOR_PROPRIETARY_LEGACY:
1903                         case CONNECTOR_DVI_I_LEGACY:
1904                         case CONNECTOR_DVI_D_LEGACY:
1905                                 if ((tmp >> 4) & 0x1)
1906                                         hpd.hpd = RADEON_HPD_2;
1907                                 else
1908                                         hpd.hpd = RADEON_HPD_1;
1909                                 break;
1910                         default:
1911                                 hpd.hpd = RADEON_HPD_NONE;
1912                                 break;
1913                         }
1914
1915                         if (!radeon_apply_legacy_quirks(dev, i, &connector,
1916                                                         &ddc_i2c, &hpd))
1917                                 continue;
1918
1919                         switch (connector) {
1920                         case CONNECTOR_PROPRIETARY_LEGACY:
1921                                 if ((tmp >> 4) & 0x1)
1922                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
1923                                 else
1924                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
1925                                 radeon_add_legacy_encoder(dev,
1926                                                           radeon_get_encoder_id
1927                                                           (dev, devices, 0),
1928                                                           devices);
1929                                 radeon_add_legacy_connector(dev, i, devices,
1930                                                             legacy_connector_convert
1931                                                             [connector],
1932                                                             &ddc_i2c,
1933                                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1934                                                             &hpd);
1935                                 break;
1936                         case CONNECTOR_CRT_LEGACY:
1937                                 if (tmp & 0x1) {
1938                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
1939                                         radeon_add_legacy_encoder(dev,
1940                                                                   radeon_get_encoder_id
1941                                                                   (dev,
1942                                                                    ATOM_DEVICE_CRT2_SUPPORT,
1943                                                                    2),
1944                                                                   ATOM_DEVICE_CRT2_SUPPORT);
1945                                 } else {
1946                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
1947                                         radeon_add_legacy_encoder(dev,
1948                                                                   radeon_get_encoder_id
1949                                                                   (dev,
1950                                                                    ATOM_DEVICE_CRT1_SUPPORT,
1951                                                                    1),
1952                                                                   ATOM_DEVICE_CRT1_SUPPORT);
1953                                 }
1954                                 radeon_add_legacy_connector(dev,
1955                                                             i,
1956                                                             devices,
1957                                                             legacy_connector_convert
1958                                                             [connector],
1959                                                             &ddc_i2c,
1960                                                             CONNECTOR_OBJECT_ID_VGA,
1961                                                             &hpd);
1962                                 break;
1963                         case CONNECTOR_DVI_I_LEGACY:
1964                                 devices = 0;
1965                                 if (tmp & 0x1) {
1966                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
1967                                         radeon_add_legacy_encoder(dev,
1968                                                                   radeon_get_encoder_id
1969                                                                   (dev,
1970                                                                    ATOM_DEVICE_CRT2_SUPPORT,
1971                                                                    2),
1972                                                                   ATOM_DEVICE_CRT2_SUPPORT);
1973                                 } else {
1974                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
1975                                         radeon_add_legacy_encoder(dev,
1976                                                                   radeon_get_encoder_id
1977                                                                   (dev,
1978                                                                    ATOM_DEVICE_CRT1_SUPPORT,
1979                                                                    1),
1980                                                                   ATOM_DEVICE_CRT1_SUPPORT);
1981                                 }
1982                                 if ((tmp >> 4) & 0x1) {
1983                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
1984                                         radeon_add_legacy_encoder(dev,
1985                                                                   radeon_get_encoder_id
1986                                                                   (dev,
1987                                                                    ATOM_DEVICE_DFP2_SUPPORT,
1988                                                                    0),
1989                                                                   ATOM_DEVICE_DFP2_SUPPORT);
1990                                         connector_object_id = combios_check_dl_dvi(dev, 0);
1991                                 } else {
1992                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
1993                                         radeon_add_legacy_encoder(dev,
1994                                                                   radeon_get_encoder_id
1995                                                                   (dev,
1996                                                                    ATOM_DEVICE_DFP1_SUPPORT,
1997                                                                    0),
1998                                                                   ATOM_DEVICE_DFP1_SUPPORT);
1999                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2000                                 }
2001                                 radeon_add_legacy_connector(dev,
2002                                                             i,
2003                                                             devices,
2004                                                             legacy_connector_convert
2005                                                             [connector],
2006                                                             &ddc_i2c,
2007                                                             connector_object_id,
2008                                                             &hpd);
2009                                 break;
2010                         case CONNECTOR_DVI_D_LEGACY:
2011                                 if ((tmp >> 4) & 0x1) {
2012                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2013                                         connector_object_id = combios_check_dl_dvi(dev, 1);
2014                                 } else {
2015                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2016                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2017                                 }
2018                                 radeon_add_legacy_encoder(dev,
2019                                                           radeon_get_encoder_id
2020                                                           (dev, devices, 0),
2021                                                           devices);
2022                                 radeon_add_legacy_connector(dev, i, devices,
2023                                                             legacy_connector_convert
2024                                                             [connector],
2025                                                             &ddc_i2c,
2026                                                             connector_object_id,
2027                                                             &hpd);
2028                                 break;
2029                         case CONNECTOR_CTV_LEGACY:
2030                         case CONNECTOR_STV_LEGACY:
2031                                 radeon_add_legacy_encoder(dev,
2032                                                           radeon_get_encoder_id
2033                                                           (dev,
2034                                                            ATOM_DEVICE_TV1_SUPPORT,
2035                                                            2),
2036                                                           ATOM_DEVICE_TV1_SUPPORT);
2037                                 radeon_add_legacy_connector(dev, i,
2038                                                             ATOM_DEVICE_TV1_SUPPORT,
2039                                                             legacy_connector_convert
2040                                                             [connector],
2041                                                             &ddc_i2c,
2042                                                             CONNECTOR_OBJECT_ID_SVIDEO,
2043                                                             &hpd);
2044                                 break;
2045                         default:
2046                                 DRM_ERROR("Unknown connector type: %d\n",
2047                                           connector);
2048                                 continue;
2049                         }
2050
2051                 }
2052         } else {
2053                 uint16_t tmds_info =
2054                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2055                 if (tmds_info) {
2056                         DRM_DEBUG("Found DFP table, assuming DVI connector\n");
2057
2058                         radeon_add_legacy_encoder(dev,
2059                                                   radeon_get_encoder_id(dev,
2060                                                                         ATOM_DEVICE_CRT1_SUPPORT,
2061                                                                         1),
2062                                                   ATOM_DEVICE_CRT1_SUPPORT);
2063                         radeon_add_legacy_encoder(dev,
2064                                                   radeon_get_encoder_id(dev,
2065                                                                         ATOM_DEVICE_DFP1_SUPPORT,
2066                                                                         0),
2067                                                   ATOM_DEVICE_DFP1_SUPPORT);
2068
2069                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2070                         hpd.hpd = RADEON_HPD_NONE;
2071                         radeon_add_legacy_connector(dev,
2072                                                     0,
2073                                                     ATOM_DEVICE_CRT1_SUPPORT |
2074                                                     ATOM_DEVICE_DFP1_SUPPORT,
2075                                                     DRM_MODE_CONNECTOR_DVII,
2076                                                     &ddc_i2c,
2077                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2078                                                     &hpd);
2079                 } else {
2080                         uint16_t crt_info =
2081                                 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2082                         DRM_DEBUG("Found CRT table, assuming VGA connector\n");
2083                         if (crt_info) {
2084                                 radeon_add_legacy_encoder(dev,
2085                                                           radeon_get_encoder_id(dev,
2086                                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2087                                                                                 1),
2088                                                           ATOM_DEVICE_CRT1_SUPPORT);
2089                                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2090                                 hpd.hpd = RADEON_HPD_NONE;
2091                                 radeon_add_legacy_connector(dev,
2092                                                             0,
2093                                                             ATOM_DEVICE_CRT1_SUPPORT,
2094                                                             DRM_MODE_CONNECTOR_VGA,
2095                                                             &ddc_i2c,
2096                                                             CONNECTOR_OBJECT_ID_VGA,
2097                                                             &hpd);
2098                         } else {
2099                                 DRM_DEBUG("No connector info found\n");
2100                                 return false;
2101                         }
2102                 }
2103         }
2104
2105         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2106                 uint16_t lcd_info =
2107                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2108                 if (lcd_info) {
2109                         uint16_t lcd_ddc_info =
2110                             combios_get_table_offset(dev,
2111                                                      COMBIOS_LCD_DDC_INFO_TABLE);
2112
2113                         radeon_add_legacy_encoder(dev,
2114                                                   radeon_get_encoder_id(dev,
2115                                                                         ATOM_DEVICE_LCD1_SUPPORT,
2116                                                                         0),
2117                                                   ATOM_DEVICE_LCD1_SUPPORT);
2118
2119                         if (lcd_ddc_info) {
2120                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
2121                                 switch (ddc_type) {
2122                                 case DDC_MONID:
2123                                         ddc_i2c =
2124                                             combios_setup_i2c_bus
2125                                                 (rdev, RADEON_GPIO_MONID);
2126                                         break;
2127                                 case DDC_DVI:
2128                                         ddc_i2c =
2129                                             combios_setup_i2c_bus
2130                                                 (rdev, RADEON_GPIO_DVI_DDC);
2131                                         break;
2132                                 case DDC_VGA:
2133                                         ddc_i2c =
2134                                             combios_setup_i2c_bus
2135                                                 (rdev, RADEON_GPIO_VGA_DDC);
2136                                         break;
2137                                 case DDC_CRT2:
2138                                         ddc_i2c =
2139                                             combios_setup_i2c_bus
2140                                                 (rdev, RADEON_GPIO_CRT2_DDC);
2141                                         break;
2142                                 case DDC_LCD:
2143                                         ddc_i2c =
2144                                             combios_setup_i2c_bus
2145                                                 (rdev, RADEON_GPIOPAD_MASK);
2146                                         ddc_i2c.mask_clk_mask =
2147                                             RBIOS32(lcd_ddc_info + 3);
2148                                         ddc_i2c.mask_data_mask =
2149                                             RBIOS32(lcd_ddc_info + 7);
2150                                         ddc_i2c.a_clk_mask =
2151                                             RBIOS32(lcd_ddc_info + 3);
2152                                         ddc_i2c.a_data_mask =
2153                                             RBIOS32(lcd_ddc_info + 7);
2154                                         ddc_i2c.en_clk_mask =
2155                                             RBIOS32(lcd_ddc_info + 3);
2156                                         ddc_i2c.en_data_mask =
2157                                             RBIOS32(lcd_ddc_info + 7);
2158                                         ddc_i2c.y_clk_mask =
2159                                             RBIOS32(lcd_ddc_info + 3);
2160                                         ddc_i2c.y_data_mask =
2161                                             RBIOS32(lcd_ddc_info + 7);
2162                                         break;
2163                                 case DDC_GPIO:
2164                                         ddc_i2c =
2165                                             combios_setup_i2c_bus
2166                                                 (rdev, RADEON_MDGPIO_MASK);
2167                                         ddc_i2c.mask_clk_mask =
2168                                             RBIOS32(lcd_ddc_info + 3);
2169                                         ddc_i2c.mask_data_mask =
2170                                             RBIOS32(lcd_ddc_info + 7);
2171                                         ddc_i2c.a_clk_mask =
2172                                             RBIOS32(lcd_ddc_info + 3);
2173                                         ddc_i2c.a_data_mask =
2174                                             RBIOS32(lcd_ddc_info + 7);
2175                                         ddc_i2c.en_clk_mask =
2176                                             RBIOS32(lcd_ddc_info + 3);
2177                                         ddc_i2c.en_data_mask =
2178                                             RBIOS32(lcd_ddc_info + 7);
2179                                         ddc_i2c.y_clk_mask =
2180                                             RBIOS32(lcd_ddc_info + 3);
2181                                         ddc_i2c.y_data_mask =
2182                                             RBIOS32(lcd_ddc_info + 7);
2183                                         break;
2184                                 default:
2185                                         ddc_i2c.valid = false;
2186                                         break;
2187                                 }
2188                                 DRM_DEBUG("LCD DDC Info Table found!\n");
2189                         } else
2190                                 ddc_i2c.valid = false;
2191
2192                         hpd.hpd = RADEON_HPD_NONE;
2193                         radeon_add_legacy_connector(dev,
2194                                                     5,
2195                                                     ATOM_DEVICE_LCD1_SUPPORT,
2196                                                     DRM_MODE_CONNECTOR_LVDS,
2197                                                     &ddc_i2c,
2198                                                     CONNECTOR_OBJECT_ID_LVDS,
2199                                                     &hpd);
2200                 }
2201         }
2202
2203         /* check TV table */
2204         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2205                 uint32_t tv_info =
2206                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2207                 if (tv_info) {
2208                         if (RBIOS8(tv_info + 6) == 'T') {
2209                                 if (radeon_apply_legacy_tv_quirks(dev)) {
2210                                         hpd.hpd = RADEON_HPD_NONE;
2211                                         radeon_add_legacy_encoder(dev,
2212                                                                   radeon_get_encoder_id
2213                                                                   (dev,
2214                                                                    ATOM_DEVICE_TV1_SUPPORT,
2215                                                                    2),
2216                                                                   ATOM_DEVICE_TV1_SUPPORT);
2217                                         radeon_add_legacy_connector(dev, 6,
2218                                                                     ATOM_DEVICE_TV1_SUPPORT,
2219                                                                     DRM_MODE_CONNECTOR_SVIDEO,
2220                                                                     &ddc_i2c,
2221                                                                     CONNECTOR_OBJECT_ID_SVIDEO,
2222                                                                     &hpd);
2223                                 }
2224                         }
2225                 }
2226         }
2227
2228         radeon_link_encoder_connector(dev);
2229
2230         return true;
2231 }
2232
2233 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2234 {
2235         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2236         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2237
2238         if (!tmds)
2239                 return;
2240
2241         switch (tmds->dvo_chip) {
2242         case DVO_SIL164:
2243                 /* sil 164 */
2244                 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2245                 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2246                                        tmds->slave_addr,
2247                                        0x08, 0x30);
2248                 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2249                                        tmds->slave_addr,
2250                                        0x09, 0x00);
2251                 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2252                                        tmds->slave_addr,
2253                                        0x0a, 0x90);
2254                 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2255                                        tmds->slave_addr,
2256                                        0x0c, 0x89);
2257                 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2258                                        tmds->slave_addr,
2259                                        0x08, 0x3b);
2260                 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2261                 break;
2262         case DVO_SIL1178:
2263                 /* sil 1178 - untested */
2264                 /*
2265                  * 0x0f, 0x44
2266                  * 0x0f, 0x4c
2267                  * 0x0e, 0x01
2268                  * 0x0a, 0x80
2269                  * 0x09, 0x30
2270                  * 0x0c, 0xc9
2271                  * 0x0d, 0x70
2272                  * 0x08, 0x32
2273                  * 0x08, 0x33
2274                  */
2275                 break;
2276         default:
2277                 break;
2278         }
2279
2280 }
2281
2282 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2283 {
2284         struct drm_device *dev = encoder->dev;
2285         struct radeon_device *rdev = dev->dev_private;
2286         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2287         uint16_t offset;
2288         uint8_t blocks, slave_addr, rev;
2289         uint32_t index, id;
2290         uint32_t reg, val, and_mask, or_mask;
2291         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2292
2293         if (rdev->bios == NULL)
2294                 return false;
2295
2296         if (!tmds)
2297                 return false;
2298
2299         if (rdev->flags & RADEON_IS_IGP) {
2300                 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2301                 rev = RBIOS8(offset);
2302                 if (offset) {
2303                         rev = RBIOS8(offset);
2304                         if (rev > 1) {
2305                                 blocks = RBIOS8(offset + 3);
2306                                 index = offset + 4;
2307                                 while (blocks > 0) {
2308                                         id = RBIOS16(index);
2309                                         index += 2;
2310                                         switch (id >> 13) {
2311                                         case 0:
2312                                                 reg = (id & 0x1fff) * 4;
2313                                                 val = RBIOS32(index);
2314                                                 index += 4;
2315                                                 WREG32(reg, val);
2316                                                 break;
2317                                         case 2:
2318                                                 reg = (id & 0x1fff) * 4;
2319                                                 and_mask = RBIOS32(index);
2320                                                 index += 4;
2321                                                 or_mask = RBIOS32(index);
2322                                                 index += 4;
2323                                                 val = RREG32(reg);
2324                                                 val = (val & and_mask) | or_mask;
2325                                                 WREG32(reg, val);
2326                                                 break;
2327                                         case 3:
2328                                                 val = RBIOS16(index);
2329                                                 index += 2;
2330                                                 udelay(val);
2331                                                 break;
2332                                         case 4:
2333                                                 val = RBIOS16(index);
2334                                                 index += 2;
2335                                                 udelay(val * 1000);
2336                                                 break;
2337                                         case 6:
2338                                                 slave_addr = id & 0xff;
2339                                                 slave_addr >>= 1; /* 7 bit addressing */
2340                                                 index++;
2341                                                 reg = RBIOS8(index);
2342                                                 index++;
2343                                                 val = RBIOS8(index);
2344                                                 index++;
2345                                                 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2346                                                 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2347                                                                        slave_addr,
2348                                                                        reg, val);
2349                                                 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2350                                                 break;
2351                                         default:
2352                                                 DRM_ERROR("Unknown id %d\n", id >> 13);
2353                                                 break;
2354                                         }
2355                                         blocks--;
2356                                 }
2357                                 return true;
2358                         }
2359                 }
2360         } else {
2361                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2362                 if (offset) {
2363                         index = offset + 10;
2364                         id = RBIOS16(index);
2365                         while (id != 0xffff) {
2366                                 index += 2;
2367                                 switch (id >> 13) {
2368                                 case 0:
2369                                         reg = (id & 0x1fff) * 4;
2370                                         val = RBIOS32(index);
2371                                         WREG32(reg, val);
2372                                         break;
2373                                 case 2:
2374                                         reg = (id & 0x1fff) * 4;
2375                                         and_mask = RBIOS32(index);
2376                                         index += 4;
2377                                         or_mask = RBIOS32(index);
2378                                         index += 4;
2379                                         val = RREG32(reg);
2380                                         val = (val & and_mask) | or_mask;
2381                                         WREG32(reg, val);
2382                                         break;
2383                                 case 4:
2384                                         val = RBIOS16(index);
2385                                         index += 2;
2386                                         udelay(val);
2387                                         break;
2388                                 case 5:
2389                                         reg = id & 0x1fff;
2390                                         and_mask = RBIOS32(index);
2391                                         index += 4;
2392                                         or_mask = RBIOS32(index);
2393                                         index += 4;
2394                                         val = RREG32_PLL(reg);
2395                                         val = (val & and_mask) | or_mask;
2396                                         WREG32_PLL(reg, val);
2397                                         break;
2398                                 case 6:
2399                                         reg = id & 0x1fff;
2400                                         val = RBIOS8(index);
2401                                         index += 1;
2402                                         radeon_i2c_do_lock(tmds->i2c_bus, 1);
2403                                         radeon_i2c_sw_put_byte(tmds->i2c_bus,
2404                                                                tmds->slave_addr,
2405                                                                reg, val);
2406                                         radeon_i2c_do_lock(tmds->i2c_bus, 0);
2407                                         break;
2408                                 default:
2409                                         DRM_ERROR("Unknown id %d\n", id >> 13);
2410                                         break;
2411                                 }
2412                                 id = RBIOS16(index);
2413                         }
2414                         return true;
2415                 }
2416         }
2417         return false;
2418 }
2419
2420 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2421 {
2422         struct radeon_device *rdev = dev->dev_private;
2423
2424         if (offset) {
2425                 while (RBIOS16(offset)) {
2426                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2427                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
2428                         uint32_t val, and_mask, or_mask;
2429                         uint32_t tmp;
2430
2431                         offset += 2;
2432                         switch (cmd) {
2433                         case 0:
2434                                 val = RBIOS32(offset);
2435                                 offset += 4;
2436                                 WREG32(addr, val);
2437                                 break;
2438                         case 1:
2439                                 val = RBIOS32(offset);
2440                                 offset += 4;
2441                                 WREG32(addr, val);
2442                                 break;
2443                         case 2:
2444                                 and_mask = RBIOS32(offset);
2445                                 offset += 4;
2446                                 or_mask = RBIOS32(offset);
2447                                 offset += 4;
2448                                 tmp = RREG32(addr);
2449                                 tmp &= and_mask;
2450                                 tmp |= or_mask;
2451                                 WREG32(addr, tmp);
2452                                 break;
2453                         case 3:
2454                                 and_mask = RBIOS32(offset);
2455                                 offset += 4;
2456                                 or_mask = RBIOS32(offset);
2457                                 offset += 4;
2458                                 tmp = RREG32(addr);
2459                                 tmp &= and_mask;
2460                                 tmp |= or_mask;
2461                                 WREG32(addr, tmp);
2462                                 break;
2463                         case 4:
2464                                 val = RBIOS16(offset);
2465                                 offset += 2;
2466                                 udelay(val);
2467                                 break;
2468                         case 5:
2469                                 val = RBIOS16(offset);
2470                                 offset += 2;
2471                                 switch (addr) {
2472                                 case 8:
2473                                         while (val--) {
2474                                                 if (!
2475                                                     (RREG32_PLL
2476                                                      (RADEON_CLK_PWRMGT_CNTL) &
2477                                                      RADEON_MC_BUSY))
2478                                                         break;
2479                                         }
2480                                         break;
2481                                 case 9:
2482                                         while (val--) {
2483                                                 if ((RREG32(RADEON_MC_STATUS) &
2484                                                      RADEON_MC_IDLE))
2485                                                         break;
2486                                         }
2487                                         break;
2488                                 default:
2489                                         break;
2490                                 }
2491                                 break;
2492                         default:
2493                                 break;
2494                         }
2495                 }
2496         }
2497 }
2498
2499 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2500 {
2501         struct radeon_device *rdev = dev->dev_private;
2502
2503         if (offset) {
2504                 while (RBIOS8(offset)) {
2505                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2506                         uint8_t addr = (RBIOS8(offset) & 0x3f);
2507                         uint32_t val, shift, tmp;
2508                         uint32_t and_mask, or_mask;
2509
2510                         offset++;
2511                         switch (cmd) {
2512                         case 0:
2513                                 val = RBIOS32(offset);
2514                                 offset += 4;
2515                                 WREG32_PLL(addr, val);
2516                                 break;
2517                         case 1:
2518                                 shift = RBIOS8(offset) * 8;
2519                                 offset++;
2520                                 and_mask = RBIOS8(offset) << shift;
2521                                 and_mask |= ~(0xff << shift);
2522                                 offset++;
2523                                 or_mask = RBIOS8(offset) << shift;
2524                                 offset++;
2525                                 tmp = RREG32_PLL(addr);
2526                                 tmp &= and_mask;
2527                                 tmp |= or_mask;
2528                                 WREG32_PLL(addr, tmp);
2529                                 break;
2530                         case 2:
2531                         case 3:
2532                                 tmp = 1000;
2533                                 switch (addr) {
2534                                 case 1:
2535                                         udelay(150);
2536                                         break;
2537                                 case 2:
2538                                         udelay(1000);
2539                                         break;
2540                                 case 3:
2541                                         while (tmp--) {
2542                                                 if (!
2543                                                     (RREG32_PLL
2544                                                      (RADEON_CLK_PWRMGT_CNTL) &
2545                                                      RADEON_MC_BUSY))
2546                                                         break;
2547                                         }
2548                                         break;
2549                                 case 4:
2550                                         while (tmp--) {
2551                                                 if (RREG32_PLL
2552                                                     (RADEON_CLK_PWRMGT_CNTL) &
2553                                                     RADEON_DLL_READY)
2554                                                         break;
2555                                         }
2556                                         break;
2557                                 case 5:
2558                                         tmp =
2559                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2560                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
2561 #if 0
2562                                                 uint32_t mclk_cntl =
2563                                                     RREG32_PLL
2564                                                     (RADEON_MCLK_CNTL);
2565                                                 mclk_cntl &= 0xffff0000;
2566                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
2567                                                 WREG32_PLL(RADEON_MCLK_CNTL,
2568                                                            mclk_cntl);
2569                                                 udelay(10000);
2570 #endif
2571                                                 WREG32_PLL
2572                                                     (RADEON_CLK_PWRMGT_CNTL,
2573                                                      tmp &
2574                                                      ~RADEON_CG_NO1_DEBUG_0);
2575                                                 udelay(10000);
2576                                         }
2577                                         break;
2578                                 default:
2579                                         break;
2580                                 }
2581                                 break;
2582                         default:
2583                                 break;
2584                         }
2585                 }
2586         }
2587 }
2588
2589 static void combios_parse_ram_reset_table(struct drm_device *dev,
2590                                           uint16_t offset)
2591 {
2592         struct radeon_device *rdev = dev->dev_private;
2593         uint32_t tmp;
2594
2595         if (offset) {
2596                 uint8_t val = RBIOS8(offset);
2597                 while (val != 0xff) {
2598                         offset++;
2599
2600                         if (val == 0x0f) {
2601                                 uint32_t channel_complete_mask;
2602
2603                                 if (ASIC_IS_R300(rdev))
2604                                         channel_complete_mask =
2605                                             R300_MEM_PWRUP_COMPLETE;
2606                                 else
2607                                         channel_complete_mask =
2608                                             RADEON_MEM_PWRUP_COMPLETE;
2609                                 tmp = 20000;
2610                                 while (tmp--) {
2611                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
2612                                              channel_complete_mask) ==
2613                                             channel_complete_mask)
2614                                                 break;
2615                                 }
2616                         } else {
2617                                 uint32_t or_mask = RBIOS16(offset);
2618                                 offset += 2;
2619
2620                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2621                                 tmp &= RADEON_SDRAM_MODE_MASK;
2622                                 tmp |= or_mask;
2623                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2624
2625                                 or_mask = val << 24;
2626                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2627                                 tmp &= RADEON_B3MEM_RESET_MASK;
2628                                 tmp |= or_mask;
2629                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2630                         }
2631                         val = RBIOS8(offset);
2632                 }
2633         }
2634 }
2635
2636 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2637                                    int mem_addr_mapping)
2638 {
2639         struct radeon_device *rdev = dev->dev_private;
2640         uint32_t mem_cntl;
2641         uint32_t mem_size;
2642         uint32_t addr = 0;
2643
2644         mem_cntl = RREG32(RADEON_MEM_CNTL);
2645         if (mem_cntl & RV100_HALF_MODE)
2646                 ram /= 2;
2647         mem_size = ram;
2648         mem_cntl &= ~(0xff << 8);
2649         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2650         WREG32(RADEON_MEM_CNTL, mem_cntl);
2651         RREG32(RADEON_MEM_CNTL);
2652
2653         /* sdram reset ? */
2654
2655         /* something like this????  */
2656         while (ram--) {
2657                 addr = ram * 1024 * 1024;
2658                 /* write to each page */
2659                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2660                 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2661                 /* read back and verify */
2662                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2663                 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2664                         return 0;
2665         }
2666
2667         return mem_size;
2668 }
2669
2670 static void combios_write_ram_size(struct drm_device *dev)
2671 {
2672         struct radeon_device *rdev = dev->dev_private;
2673         uint8_t rev;
2674         uint16_t offset;
2675         uint32_t mem_size = 0;
2676         uint32_t mem_cntl = 0;
2677
2678         /* should do something smarter here I guess... */
2679         if (rdev->flags & RADEON_IS_IGP)
2680                 return;
2681
2682         /* first check detected mem table */
2683         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2684         if (offset) {
2685                 rev = RBIOS8(offset);
2686                 if (rev < 3) {
2687                         mem_cntl = RBIOS32(offset + 1);
2688                         mem_size = RBIOS16(offset + 5);
2689                         if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2690                             ((dev->pdev->device != 0x515e)
2691                              && (dev->pdev->device != 0x5969)))
2692                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
2693                 }
2694         }
2695
2696         if (!mem_size) {
2697                 offset =
2698                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2699                 if (offset) {
2700                         rev = RBIOS8(offset - 1);
2701                         if (rev < 1) {
2702                                 if (((rdev->flags & RADEON_FAMILY_MASK) <
2703                                      CHIP_R200)
2704                                     && ((dev->pdev->device != 0x515e)
2705                                         && (dev->pdev->device != 0x5969))) {
2706                                         int ram = 0;
2707                                         int mem_addr_mapping = 0;
2708
2709                                         while (RBIOS8(offset)) {
2710                                                 ram = RBIOS8(offset);
2711                                                 mem_addr_mapping =
2712                                                     RBIOS8(offset + 1);
2713                                                 if (mem_addr_mapping != 0x25)
2714                                                         ram *= 2;
2715                                                 mem_size =
2716                                                     combios_detect_ram(dev, ram,
2717                                                                        mem_addr_mapping);
2718                                                 if (mem_size)
2719                                                         break;
2720                                                 offset += 2;
2721                                         }
2722                                 } else
2723                                         mem_size = RBIOS8(offset);
2724                         } else {
2725                                 mem_size = RBIOS8(offset);
2726                                 mem_size *= 2;  /* convert to MB */
2727                         }
2728                 }
2729         }
2730
2731         mem_size *= (1024 * 1024);      /* convert to bytes */
2732         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2733 }
2734
2735 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2736 {
2737         uint16_t dyn_clk_info =
2738             combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2739
2740         if (dyn_clk_info)
2741                 combios_parse_pll_table(dev, dyn_clk_info);
2742 }
2743
2744 void radeon_combios_asic_init(struct drm_device *dev)
2745 {
2746         struct radeon_device *rdev = dev->dev_private;
2747         uint16_t table;
2748
2749         /* port hardcoded mac stuff from radeonfb */
2750         if (rdev->bios == NULL)
2751                 return;
2752
2753         /* ASIC INIT 1 */
2754         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2755         if (table)
2756                 combios_parse_mmio_table(dev, table);
2757
2758         /* PLL INIT */
2759         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2760         if (table)
2761                 combios_parse_pll_table(dev, table);
2762
2763         /* ASIC INIT 2 */
2764         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2765         if (table)
2766                 combios_parse_mmio_table(dev, table);
2767
2768         if (!(rdev->flags & RADEON_IS_IGP)) {
2769                 /* ASIC INIT 4 */
2770                 table =
2771                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
2772                 if (table)
2773                         combios_parse_mmio_table(dev, table);
2774
2775                 /* RAM RESET */
2776                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
2777                 if (table)
2778                         combios_parse_ram_reset_table(dev, table);
2779
2780                 /* ASIC INIT 3 */
2781                 table =
2782                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
2783                 if (table)
2784                         combios_parse_mmio_table(dev, table);
2785
2786                 /* write CONFIG_MEMSIZE */
2787                 combios_write_ram_size(dev);
2788         }
2789
2790         /* DYN CLK 1 */
2791         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2792         if (table)
2793                 combios_parse_pll_table(dev, table);
2794
2795 }
2796
2797 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
2798 {
2799         struct radeon_device *rdev = dev->dev_private;
2800         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
2801
2802         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2803         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2804         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
2805
2806         /* let the bios control the backlight */
2807         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
2808
2809         /* tell the bios not to handle mode switching */
2810         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
2811                            RADEON_ACC_MODE_CHANGE);
2812
2813         /* tell the bios a driver is loaded */
2814         bios_7_scratch |= RADEON_DRV_LOADED;
2815
2816         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2817         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2818         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
2819 }
2820
2821 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
2822 {
2823         struct drm_device *dev = encoder->dev;
2824         struct radeon_device *rdev = dev->dev_private;
2825         uint32_t bios_6_scratch;
2826
2827         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2828
2829         if (lock)
2830                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
2831         else
2832                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
2833
2834         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2835 }
2836
2837 void
2838 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
2839                                       struct drm_encoder *encoder,
2840                                       bool connected)
2841 {
2842         struct drm_device *dev = connector->dev;
2843         struct radeon_device *rdev = dev->dev_private;
2844         struct radeon_connector *radeon_connector =
2845             to_radeon_connector(connector);
2846         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2847         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
2848         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2849
2850         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2851             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2852                 if (connected) {
2853                         DRM_DEBUG("TV1 connected\n");
2854                         /* fix me */
2855                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
2856                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
2857                         bios_5_scratch |= RADEON_TV1_ON;
2858                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
2859                 } else {
2860                         DRM_DEBUG("TV1 disconnected\n");
2861                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
2862                         bios_5_scratch &= ~RADEON_TV1_ON;
2863                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
2864                 }
2865         }
2866         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2867             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2868                 if (connected) {
2869                         DRM_DEBUG("LCD1 connected\n");
2870                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
2871                         bios_5_scratch |= RADEON_LCD1_ON;
2872                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
2873                 } else {
2874                         DRM_DEBUG("LCD1 disconnected\n");
2875                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
2876                         bios_5_scratch &= ~RADEON_LCD1_ON;
2877                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
2878                 }
2879         }
2880         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2881             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2882                 if (connected) {
2883                         DRM_DEBUG("CRT1 connected\n");
2884                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
2885                         bios_5_scratch |= RADEON_CRT1_ON;
2886                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
2887                 } else {
2888                         DRM_DEBUG("CRT1 disconnected\n");
2889                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
2890                         bios_5_scratch &= ~RADEON_CRT1_ON;
2891                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
2892                 }
2893         }
2894         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2895             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2896                 if (connected) {
2897                         DRM_DEBUG("CRT2 connected\n");
2898                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
2899                         bios_5_scratch |= RADEON_CRT2_ON;
2900                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
2901                 } else {
2902                         DRM_DEBUG("CRT2 disconnected\n");
2903                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
2904                         bios_5_scratch &= ~RADEON_CRT2_ON;
2905                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
2906                 }
2907         }
2908         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2909             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2910                 if (connected) {
2911                         DRM_DEBUG("DFP1 connected\n");
2912                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
2913                         bios_5_scratch |= RADEON_DFP1_ON;
2914                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
2915                 } else {
2916                         DRM_DEBUG("DFP1 disconnected\n");
2917                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
2918                         bios_5_scratch &= ~RADEON_DFP1_ON;
2919                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
2920                 }
2921         }
2922         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2923             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2924                 if (connected) {
2925                         DRM_DEBUG("DFP2 connected\n");
2926                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
2927                         bios_5_scratch |= RADEON_DFP2_ON;
2928                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
2929                 } else {
2930                         DRM_DEBUG("DFP2 disconnected\n");
2931                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
2932                         bios_5_scratch &= ~RADEON_DFP2_ON;
2933                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
2934                 }
2935         }
2936         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
2937         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2938 }
2939
2940 void
2941 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2942 {
2943         struct drm_device *dev = encoder->dev;
2944         struct radeon_device *rdev = dev->dev_private;
2945         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2946         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2947
2948         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2949                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
2950                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
2951         }
2952         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2953                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
2954                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
2955         }
2956         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2957                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
2958                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
2959         }
2960         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2961                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
2962                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
2963         }
2964         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2965                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
2966                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
2967         }
2968         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2969                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
2970                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
2971         }
2972         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2973 }
2974
2975 void
2976 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2977 {
2978         struct drm_device *dev = encoder->dev;
2979         struct radeon_device *rdev = dev->dev_private;
2980         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2981         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2982
2983         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
2984                 if (on)
2985                         bios_6_scratch |= RADEON_TV_DPMS_ON;
2986                 else
2987                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
2988         }
2989         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2990                 if (on)
2991                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
2992                 else
2993                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
2994         }
2995         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2996                 if (on)
2997                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
2998                 else
2999                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3000         }
3001         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3002                 if (on)
3003                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
3004                 else
3005                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3006         }
3007         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3008 }