drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif /* CONFIG_PPC_PMAC */
  39
  40 /* from radeon_encoder.c */
  41 extern uint32_t
  42 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  43                         uint8_t dac);
  44 extern void radeon_link_encoder_connector(struct drm_device *dev);
  45
  46 /* from radeon_connector.c */
  47 extern void
  48 radeon_add_legacy_connector(struct drm_device *dev,
  49                             uint32_t connector_id,
  50                             uint32_t supported_device,
  51                             int connector_type,
  52                             struct radeon_i2c_bus_rec *i2c_bus,
  53                             uint16_t connector_object_id,
  54                             struct radeon_hpd *hpd);
  55
  56 /* from radeon_legacy_encoder.c */
  57 extern void
  58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  59                           uint32_t supported_device);
  60
  61 /* old legacy ATI BIOS routines */
  62
  63 /* COMBIOS table offsets */
  64 enum radeon_combios_table_offset {
  65         /* absolute offset tables */
  66         COMBIOS_ASIC_INIT_1_TABLE,
  67         COMBIOS_BIOS_SUPPORT_TABLE,
  68         COMBIOS_DAC_PROGRAMMING_TABLE,
  69         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  70         COMBIOS_CRTC_INFO_TABLE,
  71         COMBIOS_PLL_INFO_TABLE,
  72         COMBIOS_TV_INFO_TABLE,
  73         COMBIOS_DFP_INFO_TABLE,
  74         COMBIOS_HW_CONFIG_INFO_TABLE,
  75         COMBIOS_MULTIMEDIA_INFO_TABLE,
  76         COMBIOS_TV_STD_PATCH_TABLE,
  77         COMBIOS_LCD_INFO_TABLE,
  78         COMBIOS_MOBILE_INFO_TABLE,
  79         COMBIOS_PLL_INIT_TABLE,
  80         COMBIOS_MEM_CONFIG_TABLE,
  81         COMBIOS_SAVE_MASK_TABLE,
  82         COMBIOS_HARDCODED_EDID_TABLE,
  83         COMBIOS_ASIC_INIT_2_TABLE,
  84         COMBIOS_CONNECTOR_INFO_TABLE,
  85         COMBIOS_DYN_CLK_1_TABLE,
  86         COMBIOS_RESERVED_MEM_TABLE,
  87         COMBIOS_EXT_TMDS_INFO_TABLE,
  88         COMBIOS_MEM_CLK_INFO_TABLE,
  89         COMBIOS_EXT_DAC_INFO_TABLE,
  90         COMBIOS_MISC_INFO_TABLE,
  91         COMBIOS_CRT_INFO_TABLE,
  92         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  93         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  94         COMBIOS_FAN_SPEED_INFO_TABLE,
  95         COMBIOS_OVERDRIVE_INFO_TABLE,
  96         COMBIOS_OEM_INFO_TABLE,
  97         COMBIOS_DYN_CLK_2_TABLE,
  98         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  99         COMBIOS_I2C_INFO_TABLE,
 100         /* relative offset tables */
 101         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
 102         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
 103         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
 104         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
 105         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
 106         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
 107         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
 108         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
 109         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
 110         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
 111         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
 112 };
 113
 114 enum radeon_combios_ddc {
 115         DDC_NONE_DETECTED,
 116         DDC_MONID,
 117         DDC_DVI,
 118         DDC_VGA,
 119         DDC_CRT2,
 120         DDC_LCD,
 121         DDC_GPIO,
 122 };
 123
 124 enum radeon_combios_connector {
 125         CONNECTOR_NONE_LEGACY,
 126         CONNECTOR_PROPRIETARY_LEGACY,
 127         CONNECTOR_CRT_LEGACY,
 128         CONNECTOR_DVI_I_LEGACY,
 129         CONNECTOR_DVI_D_LEGACY,
 130         CONNECTOR_CTV_LEGACY,
 131         CONNECTOR_STV_LEGACY,
 132         CONNECTOR_UNSUPPORTED_LEGACY
 133 };
 134
 135 const int legacy_connector_convert[] = {
 136         DRM_MODE_CONNECTOR_Unknown,
 137         DRM_MODE_CONNECTOR_DVID,
 138         DRM_MODE_CONNECTOR_VGA,
 139         DRM_MODE_CONNECTOR_DVII,
 140         DRM_MODE_CONNECTOR_DVID,
 141         DRM_MODE_CONNECTOR_Composite,
 142         DRM_MODE_CONNECTOR_SVIDEO,
 143         DRM_MODE_CONNECTOR_Unknown,
 144 };
 145
 146 static uint16_t combios_get_table_offset(struct drm_device *dev,
 147                                          enum radeon_combios_table_offset table)
 148 {
 149         struct radeon_device *rdev = dev->dev_private;
 150         int rev;
 151         uint16_t offset = 0, check_offset;
 152
 153         if (!rdev->bios)
 154                 return 0;
 155
 156         switch (table) {
 157                 /* absolute offset tables */
 158         case COMBIOS_ASIC_INIT_1_TABLE:
 159                 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
 160                 if (check_offset)
 161                         offset = check_offset;
 162                 break;
 163         case COMBIOS_BIOS_SUPPORT_TABLE:
 164                 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
 165                 if (check_offset)
 166                         offset = check_offset;
 167                 break;
 168         case COMBIOS_DAC_PROGRAMMING_TABLE:
 169                 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
 170                 if (check_offset)
 171                         offset = check_offset;
 172                 break;
 173         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 174                 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
 175                 if (check_offset)
 176                         offset = check_offset;
 177                 break;
 178         case COMBIOS_CRTC_INFO_TABLE:
 179                 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
 180                 if (check_offset)
 181                         offset = check_offset;
 182                 break;
 183         case COMBIOS_PLL_INFO_TABLE:
 184                 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
 185                 if (check_offset)
 186                         offset = check_offset;
 187                 break;
 188         case COMBIOS_TV_INFO_TABLE:
 189                 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
 190                 if (check_offset)
 191                         offset = check_offset;
 192                 break;
 193         case COMBIOS_DFP_INFO_TABLE:
 194                 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
 195                 if (check_offset)
 196                         offset = check_offset;
 197                 break;
 198         case COMBIOS_HW_CONFIG_INFO_TABLE:
 199                 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
 200                 if (check_offset)
 201                         offset = check_offset;
 202                 break;
 203         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 204                 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
 205                 if (check_offset)
 206                         offset = check_offset;
 207                 break;
 208         case COMBIOS_TV_STD_PATCH_TABLE:
 209                 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
 210                 if (check_offset)
 211                         offset = check_offset;
 212                 break;
 213         case COMBIOS_LCD_INFO_TABLE:
 214                 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
 215                 if (check_offset)
 216                         offset = check_offset;
 217                 break;
 218         case COMBIOS_MOBILE_INFO_TABLE:
 219                 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
 220                 if (check_offset)
 221                         offset = check_offset;
 222                 break;
 223         case COMBIOS_PLL_INIT_TABLE:
 224                 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
 225                 if (check_offset)
 226                         offset = check_offset;
 227                 break;
 228         case COMBIOS_MEM_CONFIG_TABLE:
 229                 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
 230                 if (check_offset)
 231                         offset = check_offset;
 232                 break;
 233         case COMBIOS_SAVE_MASK_TABLE:
 234                 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
 235                 if (check_offset)
 236                         offset = check_offset;
 237                 break;
 238         case COMBIOS_HARDCODED_EDID_TABLE:
 239                 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
 240                 if (check_offset)
 241                         offset = check_offset;
 242                 break;
 243         case COMBIOS_ASIC_INIT_2_TABLE:
 244                 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
 245                 if (check_offset)
 246                         offset = check_offset;
 247                 break;
 248         case COMBIOS_CONNECTOR_INFO_TABLE:
 249                 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
 250                 if (check_offset)
 251                         offset = check_offset;
 252                 break;
 253         case COMBIOS_DYN_CLK_1_TABLE:
 254                 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
 255                 if (check_offset)
 256                         offset = check_offset;
 257                 break;
 258         case COMBIOS_RESERVED_MEM_TABLE:
 259                 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
 260                 if (check_offset)
 261                         offset = check_offset;
 262                 break;
 263         case COMBIOS_EXT_TMDS_INFO_TABLE:
 264                 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
 265                 if (check_offset)
 266                         offset = check_offset;
 267                 break;
 268         case COMBIOS_MEM_CLK_INFO_TABLE:
 269                 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
 270                 if (check_offset)
 271                         offset = check_offset;
 272                 break;
 273         case COMBIOS_EXT_DAC_INFO_TABLE:
 274                 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
 275                 if (check_offset)
 276                         offset = check_offset;
 277                 break;
 278         case COMBIOS_MISC_INFO_TABLE:
 279                 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
 280                 if (check_offset)
 281                         offset = check_offset;
 282                 break;
 283         case COMBIOS_CRT_INFO_TABLE:
 284                 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
 285                 if (check_offset)
 286                         offset = check_offset;
 287                 break;
 288         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 289                 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
 290                 if (check_offset)
 291                         offset = check_offset;
 292                 break;
 293         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 294                 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
 295                 if (check_offset)
 296                         offset = check_offset;
 297                 break;
 298         case COMBIOS_FAN_SPEED_INFO_TABLE:
 299                 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
 300                 if (check_offset)
 301                         offset = check_offset;
 302                 break;
 303         case COMBIOS_OVERDRIVE_INFO_TABLE:
 304                 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
 305                 if (check_offset)
 306                         offset = check_offset;
 307                 break;
 308         case COMBIOS_OEM_INFO_TABLE:
 309                 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
 310                 if (check_offset)
 311                         offset = check_offset;
 312                 break;
 313         case COMBIOS_DYN_CLK_2_TABLE:
 314                 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
 315                 if (check_offset)
 316                         offset = check_offset;
 317                 break;
 318         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 319                 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
 320                 if (check_offset)
 321                         offset = check_offset;
 322                 break;
 323         case COMBIOS_I2C_INFO_TABLE:
 324                 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
 325                 if (check_offset)
 326                         offset = check_offset;
 327                 break;
 328                 /* relative offset tables */
 329         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 330                 check_offset =
 331                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 332                 if (check_offset) {
 333                         rev = RBIOS8(check_offset);
 334                         if (rev > 0) {
 335                                 check_offset = RBIOS16(check_offset + 0x3);
 336                                 if (check_offset)
 337                                         offset = check_offset;
 338                         }
 339                 }
 340                 break;
 341         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 342                 check_offset =
 343                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 344                 if (check_offset) {
 345                         rev = RBIOS8(check_offset);
 346                         if (rev > 0) {
 347                                 check_offset = RBIOS16(check_offset + 0x5);
 348                                 if (check_offset)
 349                                         offset = check_offset;
 350                         }
 351                 }
 352                 break;
 353         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 354                 check_offset =
 355                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 356                 if (check_offset) {
 357                         rev = RBIOS8(check_offset);
 358                         if (rev > 0) {
 359                                 check_offset = RBIOS16(check_offset + 0x7);
 360                                 if (check_offset)
 361                                         offset = check_offset;
 362                         }
 363                 }
 364                 break;
 365         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 366                 check_offset =
 367                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 368                 if (check_offset) {
 369                         rev = RBIOS8(check_offset);
 370                         if (rev == 2) {
 371                                 check_offset = RBIOS16(check_offset + 0x9);
 372                                 if (check_offset)
 373                                         offset = check_offset;
 374                         }
 375                 }
 376                 break;
 377         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 378                 check_offset =
 379                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 380                 if (check_offset) {
 381                         while (RBIOS8(check_offset++));
 382                         check_offset += 2;
 383                         if (check_offset)
 384                                 offset = check_offset;
 385                 }
 386                 break;
 387         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 388                 check_offset =
 389                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 390                 if (check_offset) {
 391                         check_offset = RBIOS16(check_offset + 0x11);
 392                         if (check_offset)
 393                                 offset = check_offset;
 394                 }
 395                 break;
 396         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 397                 check_offset =
 398                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 399                 if (check_offset) {
 400                         check_offset = RBIOS16(check_offset + 0x13);
 401                         if (check_offset)
 402                                 offset = check_offset;
 403                 }
 404                 break;
 405         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 406                 check_offset =
 407                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 408                 if (check_offset) {
 409                         check_offset = RBIOS16(check_offset + 0x15);
 410                         if (check_offset)
 411                                 offset = check_offset;
 412                 }
 413                 break;
 414         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 415                 check_offset =
 416                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 417                 if (check_offset) {
 418                         check_offset = RBIOS16(check_offset + 0x17);
 419                         if (check_offset)
 420                                 offset = check_offset;
 421                 }
 422                 break;
 423         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 424                 check_offset =
 425                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 426                 if (check_offset) {
 427                         check_offset = RBIOS16(check_offset + 0x2);
 428                         if (check_offset)
 429                                 offset = check_offset;
 430                 }
 431                 break;
 432         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 433                 check_offset =
 434                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 435                 if (check_offset) {
 436                         check_offset = RBIOS16(check_offset + 0x4);
 437                         if (check_offset)
 438                                 offset = check_offset;
 439                 }
 440                 break;
 441         default:
 442                 break;
 443         }
 444
 445         return offset;
 446
 447 }
 448
 449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
 450 {
 451         int edid_info;
 452         struct edid *edid;
 453         unsigned char *raw;
 454         edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
 455         if (!edid_info)
 456                 return false;
 457
 458         raw = rdev->bios + edid_info;
 459         edid = kmalloc(EDID_LENGTH * (raw[0x7e] + 1), GFP_KERNEL);
 460         if (edid == NULL)
 461                 return false;
 462
 463         memcpy((unsigned char *)edid, raw, EDID_LENGTH * (raw[0x7e] + 1));
 464
 465         if (!drm_edid_is_valid(edid)) {
 466                 kfree(edid);
 467                 return false;
 468         }
 469
 470         rdev->mode_info.bios_hardcoded_edid = edid;
 471         return true;
 472 }
 473
 474 /* this is used for atom LCDs as well */
 475 struct edid *
 476 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
 477 {
 478         if (rdev->mode_info.bios_hardcoded_edid)
 479                 return rdev->mode_info.bios_hardcoded_edid;
 480         return NULL;
 481 }
 482
 483 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
 484                                                        enum radeon_combios_ddc ddc,
 485                                                        u32 clk_mask,
 486                                                        u32 data_mask)
 487 {
 488         struct radeon_i2c_bus_rec i2c;
 489         int ddc_line = 0;
 490
 491         /* ddc id            = mask reg
 492          * DDC_NONE_DETECTED = none
 493          * DDC_DVI           = RADEON_GPIO_DVI_DDC
 494          * DDC_VGA           = RADEON_GPIO_VGA_DDC
 495          * DDC_LCD           = RADEON_GPIOPAD_MASK
 496          * DDC_GPIO          = RADEON_MDGPIO_MASK
 497          * r1xx/r2xx
 498          * DDC_MONID         = RADEON_GPIO_MONID
 499          * DDC_CRT2          = RADEON_GPIO_CRT2_DDC
 500          * r3xx
 501          * DDC_MONID         = RADEON_GPIO_MONID
 502          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 503          * rs3xx/rs4xx
 504          * DDC_MONID         = RADEON_GPIOPAD_MASK
 505          * DDC_CRT2          = RADEON_GPIO_MONID
 506          */
 507         switch (ddc) {
 508         case DDC_NONE_DETECTED:
 509         default:
 510                 ddc_line = 0;
 511                 break;
 512         case DDC_DVI:
 513                 ddc_line = RADEON_GPIO_DVI_DDC;
 514                 break;
 515         case DDC_VGA:
 516                 ddc_line = RADEON_GPIO_VGA_DDC;
 517                 break;
 518         case DDC_LCD:
 519                 ddc_line = RADEON_GPIOPAD_MASK;
 520                 break;
 521         case DDC_GPIO:
 522                 ddc_line = RADEON_MDGPIO_MASK;
 523                 break;
 524         case DDC_MONID:
 525                 if (rdev->family == CHIP_RS300 ||
 526                     rdev->family == CHIP_RS400 ||
 527                     rdev->family == CHIP_RS480)
 528                         ddc_line = RADEON_GPIOPAD_MASK;
 529                 else
 530                         ddc_line = RADEON_GPIO_MONID;
 531                 break;
 532         case DDC_CRT2:
 533                 if (rdev->family == CHIP_RS300 ||
 534                     rdev->family == CHIP_RS400 ||
 535                     rdev->family == CHIP_RS480)
 536                         ddc_line = RADEON_GPIO_MONID;
 537                 else if (rdev->family >= CHIP_R300) {
 538                         ddc_line = RADEON_GPIO_DVI_DDC;
 539                         ddc = DDC_DVI;
 540                 } else
 541                         ddc_line = RADEON_GPIO_CRT2_DDC;
 542                 break;
 543         }
 544
 545         if (ddc_line == RADEON_GPIOPAD_MASK) {
 546                 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 547                 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 548                 i2c.a_clk_reg = RADEON_GPIOPAD_A;
 549                 i2c.a_data_reg = RADEON_GPIOPAD_A;
 550                 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
 551                 i2c.en_data_reg = RADEON_GPIOPAD_EN;
 552                 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
 553                 i2c.y_data_reg = RADEON_GPIOPAD_Y;
 554         } else if (ddc_line == RADEON_MDGPIO_MASK) {
 555                 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
 556                 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
 557                 i2c.a_clk_reg = RADEON_MDGPIO_A;
 558                 i2c.a_data_reg = RADEON_MDGPIO_A;
 559                 i2c.en_clk_reg = RADEON_MDGPIO_EN;
 560                 i2c.en_data_reg = RADEON_MDGPIO_EN;
 561                 i2c.y_clk_reg = RADEON_MDGPIO_Y;
 562                 i2c.y_data_reg = RADEON_MDGPIO_Y;
 563         } else {
 564                 i2c.mask_clk_reg = ddc_line;
 565                 i2c.mask_data_reg = ddc_line;
 566                 i2c.a_clk_reg = ddc_line;
 567                 i2c.a_data_reg = ddc_line;
 568                 i2c.en_clk_reg = ddc_line;
 569                 i2c.en_data_reg = ddc_line;
 570                 i2c.y_clk_reg = ddc_line;
 571                 i2c.y_data_reg = ddc_line;
 572         }
 573
 574         if (clk_mask && data_mask) {
 575                 /* system specific masks */
 576                 i2c.mask_clk_mask = clk_mask;
 577                 i2c.mask_data_mask = data_mask;
 578                 i2c.a_clk_mask = clk_mask;
 579                 i2c.a_data_mask = data_mask;
 580                 i2c.en_clk_mask = clk_mask;
 581                 i2c.en_data_mask = data_mask;
 582                 i2c.y_clk_mask = clk_mask;
 583                 i2c.y_data_mask = data_mask;
 584         } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
 585                    (ddc_line == RADEON_MDGPIO_MASK)) {
 586                 /* default gpiopad masks */
 587                 i2c.mask_clk_mask = (0x20 << 8);
 588                 i2c.mask_data_mask = 0x80;
 589                 i2c.a_clk_mask = (0x20 << 8);
 590                 i2c.a_data_mask = 0x80;
 591                 i2c.en_clk_mask = (0x20 << 8);
 592                 i2c.en_data_mask = 0x80;
 593                 i2c.y_clk_mask = (0x20 << 8);
 594                 i2c.y_data_mask = 0x80;
 595         } else {
 596                 /* default masks for ddc pads */
 597                 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
 598                 i2c.mask_data_mask = RADEON_GPIO_EN_0;
 599                 i2c.a_clk_mask = RADEON_GPIO_A_1;
 600                 i2c.a_data_mask = RADEON_GPIO_A_0;
 601                 i2c.en_clk_mask = RADEON_GPIO_EN_1;
 602                 i2c.en_data_mask = RADEON_GPIO_EN_0;
 603                 i2c.y_clk_mask = RADEON_GPIO_Y_1;
 604                 i2c.y_data_mask = RADEON_GPIO_Y_0;
 605         }
 606
 607         switch (rdev->family) {
 608         case CHIP_R100:
 609         case CHIP_RV100:
 610         case CHIP_RS100:
 611         case CHIP_RV200:
 612         case CHIP_RS200:
 613         case CHIP_RS300:
 614                 switch (ddc_line) {
 615                 case RADEON_GPIO_DVI_DDC:
 616                         i2c.hw_capable = true;
 617                         break;
 618                 default:
 619                         i2c.hw_capable = false;
 620                         break;
 621                 }
 622                 break;
 623         case CHIP_R200:
 624                 switch (ddc_line) {
 625                 case RADEON_GPIO_DVI_DDC:
 626                 case RADEON_GPIO_MONID:
 627                         i2c.hw_capable = true;
 628                         break;
 629                 default:
 630                         i2c.hw_capable = false;
 631                         break;
 632                 }
 633                 break;
 634         case CHIP_RV250:
 635         case CHIP_RV280:
 636                 switch (ddc_line) {
 637                 case RADEON_GPIO_VGA_DDC:
 638                 case RADEON_GPIO_DVI_DDC:
 639                 case RADEON_GPIO_CRT2_DDC:
 640                         i2c.hw_capable = true;
 641                         break;
 642                 default:
 643                         i2c.hw_capable = false;
 644                         break;
 645                 }
 646                 break;
 647         case CHIP_R300:
 648         case CHIP_R350:
 649                 switch (ddc_line) {
 650                 case RADEON_GPIO_VGA_DDC:
 651                 case RADEON_GPIO_DVI_DDC:
 652                         i2c.hw_capable = true;
 653                         break;
 654                 default:
 655                         i2c.hw_capable = false;
 656                         break;
 657                 }
 658                 break;
 659         case CHIP_RV350:
 660         case CHIP_RV380:
 661         case CHIP_RS400:
 662         case CHIP_RS480:
 663                 switch (ddc_line) {
 664                 case RADEON_GPIO_VGA_DDC:
 665                 case RADEON_GPIO_DVI_DDC:
 666                         i2c.hw_capable = true;
 667                         break;
 668                 case RADEON_GPIO_MONID:
 669                         /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
 670                          * reliably on some pre-r4xx hardware; not sure why.
 671                          */
 672                         i2c.hw_capable = false;
 673                         break;
 674                 default:
 675                         i2c.hw_capable = false;
 676                         break;
 677                 }
 678                 break;
 679         default:
 680                 i2c.hw_capable = false;
 681                 break;
 682         }
 683         i2c.mm_i2c = false;
 684
 685         i2c.i2c_id = ddc;
 686         i2c.hpd = RADEON_HPD_NONE;
 687
 688         if (ddc_line)
 689                 i2c.valid = true;
 690         else
 691                 i2c.valid = false;
 692
 693         return i2c;
 694 }
 695
 696 void radeon_combios_i2c_init(struct radeon_device *rdev)
 697 {
 698         struct drm_device *dev = rdev->ddev;
 699         struct radeon_i2c_bus_rec i2c;
 700
 701
 702         i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
 703         rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
 704
 705         i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
 706         rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
 707
 708         i2c.valid = true;
 709         i2c.hw_capable = true;
 710         i2c.mm_i2c = true;
 711         i2c.i2c_id = 0xa0;
 712         rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
 713
 714         if (rdev->family == CHIP_RS300 ||
 715             rdev->family == CHIP_RS400 ||
 716             rdev->family == CHIP_RS480) {
 717                 u16 offset;
 718                 u8 id, blocks, clk, data;
 719                 int i;
 720
 721                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 722                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 723
 724                 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
 725                 if (offset) {
 726                         blocks = RBIOS8(offset + 2);
 727                         for (i = 0; i < blocks; i++) {
 728                                 id = RBIOS8(offset + 3 + (i * 5) + 0);
 729                                 if (id == 136) {
 730                                         clk = RBIOS8(offset + 3 + (i * 5) + 3);
 731                                         data = RBIOS8(offset + 3 + (i * 5) + 4);
 732                                         i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
 733                                                                     (1 << clk), (1 << data));
 734                                         rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
 735                                         break;
 736                                 }
 737                         }
 738                 }
 739
 740         } else if (rdev->family >= CHIP_R300) {
 741                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 742                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 743         } else {
 744                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 745                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 746
 747                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 748                 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
 749         }
 750 }
 751
 752 bool radeon_combios_get_clock_info(struct drm_device *dev)
 753 {
 754         struct radeon_device *rdev = dev->dev_private;
 755         uint16_t pll_info;
 756         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 757         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 758         struct radeon_pll *spll = &rdev->clock.spll;
 759         struct radeon_pll *mpll = &rdev->clock.mpll;
 760         int8_t rev;
 761         uint16_t sclk, mclk;
 762
 763         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 764         if (pll_info) {
 765                 rev = RBIOS8(pll_info);
 766
 767                 /* pixel clocks */
 768                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 769                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 770                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 771                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 772                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 773                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 774
 775                 if (rev > 9) {
 776                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 777                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 778                 } else {
 779                         p1pll->pll_in_min = 40;
 780                         p1pll->pll_in_max = 500;
 781                 }
 782                 *p2pll = *p1pll;
 783
 784                 /* system clock */
 785                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 786                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 787                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 788                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 789
 790                 if (rev > 10) {
 791                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 792                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 793                 } else {
 794                         /* ??? */
 795                         spll->pll_in_min = 40;
 796                         spll->pll_in_max = 500;
 797                 }
 798
 799                 /* memory clock */
 800                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 801                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 802                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 803                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 804
 805                 if (rev > 10) {
 806                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 807                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 808                 } else {
 809                         /* ??? */
 810                         mpll->pll_in_min = 40;
 811                         mpll->pll_in_max = 500;
 812                 }
 813
 814                 /* default sclk/mclk */
 815                 sclk = RBIOS16(pll_info + 0xa);
 816                 mclk = RBIOS16(pll_info + 0x8);
 817                 if (sclk == 0)
 818                         sclk = 200 * 100;
 819                 if (mclk == 0)
 820                         mclk = 200 * 100;
 821
 822                 rdev->clock.default_sclk = sclk;
 823                 rdev->clock.default_mclk = mclk;
 824
 825                 return true;
 826         }
 827         return false;
 828 }
 829
 830 bool radeon_combios_sideport_present(struct radeon_device *rdev)
 831 {
 832         struct drm_device *dev = rdev->ddev;
 833         u16 igp_info;
 834
 835         /* sideport is AMD only */
 836         if (rdev->family == CHIP_RS400)
 837                 return false;
 838
 839         igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
 840
 841         if (igp_info) {
 842                 if (RBIOS16(igp_info + 0x4))
 843                         return true;
 844         }
 845         return false;
 846 }
 847
 848 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
 849         0x00000808,             /* r100  */
 850         0x00000808,             /* rv100 */
 851         0x00000808,             /* rs100 */
 852         0x00000808,             /* rv200 */
 853         0x00000808,             /* rs200 */
 854         0x00000808,             /* r200  */
 855         0x00000808,             /* rv250 */
 856         0x00000000,             /* rs300 */
 857         0x00000808,             /* rv280 */
 858         0x00000808,             /* r300  */
 859         0x00000808,             /* r350  */
 860         0x00000808,             /* rv350 */
 861         0x00000808,             /* rv380 */
 862         0x00000808,             /* r420  */
 863         0x00000808,             /* r423  */
 864         0x00000808,             /* rv410 */
 865         0x00000000,             /* rs400 */
 866         0x00000000,             /* rs480 */
 867 };
 868
 869 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
 870                                                           struct radeon_encoder_primary_dac *p_dac)
 871 {
 872         p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
 873         return;
 874 }
 875
 876 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 877                                                                        radeon_encoder
 878                                                                        *encoder)
 879 {
 880         struct drm_device *dev = encoder->base.dev;
 881         struct radeon_device *rdev = dev->dev_private;
 882         uint16_t dac_info;
 883         uint8_t rev, bg, dac;
 884         struct radeon_encoder_primary_dac *p_dac = NULL;
 885         int found = 0;
 886
 887         p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
 888                         GFP_KERNEL);
 889
 890         if (!p_dac)
 891                 return NULL;
 892
 893         /* check CRT table */
 894         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 895         if (dac_info) {
 896                 rev = RBIOS8(dac_info) & 0x3;
 897                 if (rev < 2) {
 898                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 899                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 900                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 901                 } else {
 902                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 903                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 904                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 905                 }
 906                 /* if the values are all zeros, use the table */
 907                 if (p_dac->ps2_pdac_adj)
 908                         found = 1;
 909         }
 910
 911         if (!found) /* fallback to defaults */
 912                 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
 913
 914         return p_dac;
 915 }
 916
 917 enum radeon_tv_std
 918 radeon_combios_get_tv_info(struct radeon_device *rdev)
 919 {
 920         struct drm_device *dev = rdev->ddev;
 921         uint16_t tv_info;
 922         enum radeon_tv_std tv_std = TV_STD_NTSC;
 923
 924         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 925         if (tv_info) {
 926                 if (RBIOS8(tv_info + 6) == 'T') {
 927                         switch (RBIOS8(tv_info + 7) & 0xf) {
 928                         case 1:
 929                                 tv_std = TV_STD_NTSC;
 930                                 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
 931                                 break;
 932                         case 2:
 933                                 tv_std = TV_STD_PAL;
 934                                 DRM_DEBUG_KMS("Default TV standard: PAL\n");
 935                                 break;
 936                         case 3:
 937                                 tv_std = TV_STD_PAL_M;
 938                                 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
 939                                 break;
 940                         case 4:
 941                                 tv_std = TV_STD_PAL_60;
 942                                 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
 943                                 break;
 944                         case 5:
 945                                 tv_std = TV_STD_NTSC_J;
 946                                 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
 947                                 break;
 948                         case 6:
 949                                 tv_std = TV_STD_SCART_PAL;
 950                                 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
 951                                 break;
 952                         default:
 953                                 tv_std = TV_STD_NTSC;
 954                                 DRM_DEBUG_KMS
 955                                     ("Unknown TV standard; defaulting to NTSC\n");
 956                                 break;
 957                         }
 958
 959                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
 960                         case 0:
 961                                 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
 962                                 break;
 963                         case 1:
 964                                 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
 965                                 break;
 966                         case 2:
 967                                 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
 968                                 break;
 969                         case 3:
 970                                 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
 971                                 break;
 972                         default:
 973                                 break;
 974                         }
 975                 }
 976         }
 977         return tv_std;
 978 }
 979
 980 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
 981         0x00000000,             /* r100  */
 982         0x00280000,             /* rv100 */
 983         0x00000000,             /* rs100 */
 984         0x00880000,             /* rv200 */
 985         0x00000000,             /* rs200 */
 986         0x00000000,             /* r200  */
 987         0x00770000,             /* rv250 */
 988         0x00290000,             /* rs300 */
 989         0x00560000,             /* rv280 */
 990         0x00780000,             /* r300  */
 991         0x00770000,             /* r350  */
 992         0x00780000,             /* rv350 */
 993         0x00780000,             /* rv380 */
 994         0x01080000,             /* r420  */
 995         0x01080000,             /* r423  */
 996         0x01080000,             /* rv410 */
 997         0x00780000,             /* rs400 */
 998         0x00780000,             /* rs480 */
 999 };
1000
1001 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1002                                                      struct radeon_encoder_tv_dac *tv_dac)
1003 {
1004         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1005         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1006                 tv_dac->ps2_tvdac_adj = 0x00880000;
1007         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1008         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1009         return;
1010 }
1011
1012 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1013                                                              radeon_encoder
1014                                                              *encoder)
1015 {
1016         struct drm_device *dev = encoder->base.dev;
1017         struct radeon_device *rdev = dev->dev_private;
1018         uint16_t dac_info;
1019         uint8_t rev, bg, dac;
1020         struct radeon_encoder_tv_dac *tv_dac = NULL;
1021         int found = 0;
1022
1023         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1024         if (!tv_dac)
1025                 return NULL;
1026
1027         /* first check TV table */
1028         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1029         if (dac_info) {
1030                 rev = RBIOS8(dac_info + 0x3);
1031                 if (rev > 4) {
1032                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1033                         dac = RBIOS8(dac_info + 0xd) & 0xf;
1034                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1035
1036                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1037                         dac = RBIOS8(dac_info + 0xf) & 0xf;
1038                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1039
1040                         bg = RBIOS8(dac_info + 0x10) & 0xf;
1041                         dac = RBIOS8(dac_info + 0x11) & 0xf;
1042                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1043                         /* if the values are all zeros, use the table */
1044                         if (tv_dac->ps2_tvdac_adj)
1045                                 found = 1;
1046                 } else if (rev > 1) {
1047                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1048                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1049                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1050
1051                         bg = RBIOS8(dac_info + 0xd) & 0xf;
1052                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1053                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1054
1055                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1056                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1057                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1058                         /* if the values are all zeros, use the table */
1059                         if (tv_dac->ps2_tvdac_adj)
1060                                 found = 1;
1061                 }
1062                 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1063         }
1064         if (!found) {
1065                 /* then check CRT table */
1066                 dac_info =
1067                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1068                 if (dac_info) {
1069                         rev = RBIOS8(dac_info) & 0x3;
1070                         if (rev < 2) {
1071                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
1072                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1073                                 tv_dac->ps2_tvdac_adj =
1074                                     (bg << 16) | (dac << 20);
1075                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1076                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1077                                 /* if the values are all zeros, use the table */
1078                                 if (tv_dac->ps2_tvdac_adj)
1079                                         found = 1;
1080                         } else {
1081                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
1082                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
1083                                 tv_dac->ps2_tvdac_adj =
1084                                     (bg << 16) | (dac << 20);
1085                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1086                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1087                                 /* if the values are all zeros, use the table */
1088                                 if (tv_dac->ps2_tvdac_adj)
1089                                         found = 1;
1090                         }
1091                 } else {
1092                         DRM_INFO("No TV DAC info found in BIOS\n");
1093                 }
1094         }
1095
1096         if (!found) /* fallback to defaults */
1097                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1098
1099         return tv_dac;
1100 }
1101
1102 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1103                                                                          radeon_device
1104                                                                          *rdev)
1105 {
1106         struct radeon_encoder_lvds *lvds = NULL;
1107         uint32_t fp_vert_stretch, fp_horz_stretch;
1108         uint32_t ppll_div_sel, ppll_val;
1109         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1110
1111         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1112
1113         if (!lvds)
1114                 return NULL;
1115
1116         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1117         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1118
1119         /* These should be fail-safe defaults, fingers crossed */
1120         lvds->panel_pwr_delay = 200;
1121         lvds->panel_vcc_delay = 2000;
1122
1123         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1124         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1125         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1126
1127         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1128                 lvds->native_mode.vdisplay =
1129                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1130                      RADEON_VERT_PANEL_SHIFT) + 1;
1131         else
1132                 lvds->native_mode.vdisplay =
1133                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1134
1135         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1136                 lvds->native_mode.hdisplay =
1137                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1138                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1139         else
1140                 lvds->native_mode.hdisplay =
1141                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1142
1143         if ((lvds->native_mode.hdisplay < 640) ||
1144             (lvds->native_mode.vdisplay < 480)) {
1145                 lvds->native_mode.hdisplay = 640;
1146                 lvds->native_mode.vdisplay = 480;
1147         }
1148
1149         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1150         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1151         if ((ppll_val & 0x000707ff) == 0x1bb)
1152                 lvds->use_bios_dividers = false;
1153         else {
1154                 lvds->panel_ref_divider =
1155                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1156                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1157                 lvds->panel_fb_divider = ppll_val & 0x7ff;
1158
1159                 if ((lvds->panel_ref_divider != 0) &&
1160                     (lvds->panel_fb_divider > 3))
1161                         lvds->use_bios_dividers = true;
1162         }
1163         lvds->panel_vcc_delay = 200;
1164
1165         DRM_INFO("Panel info derived from registers\n");
1166         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1167                  lvds->native_mode.vdisplay);
1168
1169         return lvds;
1170 }
1171
1172 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1173                                                          *encoder)
1174 {
1175         struct drm_device *dev = encoder->base.dev;
1176         struct radeon_device *rdev = dev->dev_private;
1177         uint16_t lcd_info;
1178         uint32_t panel_setup;
1179         char stmp[30];
1180         int tmp, i;
1181         struct radeon_encoder_lvds *lvds = NULL;
1182
1183         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1184
1185         if (lcd_info) {
1186                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1187
1188                 if (!lvds)
1189                         return NULL;
1190
1191                 for (i = 0; i < 24; i++)
1192                         stmp[i] = RBIOS8(lcd_info + i + 1);
1193                 stmp[24] = 0;
1194
1195                 DRM_INFO("Panel ID String: %s\n", stmp);
1196
1197                 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1198                 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1199
1200                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1201                          lvds->native_mode.vdisplay);
1202
1203                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1204                 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1205
1206                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1207                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1208                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1209
1210                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1211                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1212                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1213                 if ((lvds->panel_ref_divider != 0) &&
1214                     (lvds->panel_fb_divider > 3))
1215                         lvds->use_bios_dividers = true;
1216
1217                 panel_setup = RBIOS32(lcd_info + 0x39);
1218                 lvds->lvds_gen_cntl = 0xff00;
1219                 if (panel_setup & 0x1)
1220                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1221
1222                 if ((panel_setup >> 4) & 0x1)
1223                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1224
1225                 switch ((panel_setup >> 8) & 0x7) {
1226                 case 0:
1227                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1228                         break;
1229                 case 1:
1230                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1231                         break;
1232                 case 2:
1233                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1234                         break;
1235                 default:
1236                         break;
1237                 }
1238
1239                 if ((panel_setup >> 16) & 0x1)
1240                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1241
1242                 if ((panel_setup >> 17) & 0x1)
1243                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1244
1245                 if ((panel_setup >> 18) & 0x1)
1246                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1247
1248                 if ((panel_setup >> 23) & 0x1)
1249                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1250
1251                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1252
1253                 for (i = 0; i < 32; i++) {
1254                         tmp = RBIOS16(lcd_info + 64 + i * 2);
1255                         if (tmp == 0)
1256                                 break;
1257
1258                         if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1259                             (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1260                                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1261                                         (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1262                                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1263                                         (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1264                                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1265                                         (RBIOS8(tmp + 23) * 8);
1266
1267                                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1268                                         (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1269                                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1270                                         ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1271                                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1272                                         ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1273
1274                                 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1275                                 lvds->native_mode.flags = 0;
1276                                 /* set crtc values */
1277                                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1278
1279                         }
1280                 }
1281         } else {
1282                 DRM_INFO("No panel info found in BIOS\n");
1283                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1284         }
1285
1286         if (lvds)
1287                 encoder->native_mode = lvds->native_mode;
1288         return lvds;
1289 }
1290
1291 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1292         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
1293         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
1294         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
1295         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
1296         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
1297         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
1298         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
1299         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
1300         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
1301         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
1302         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
1303         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
1304         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
1305         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
1306         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
1307         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
1308         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS400 */
1309         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS480 */
1310 };
1311
1312 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1313                                             struct radeon_encoder_int_tmds *tmds)
1314 {
1315         struct drm_device *dev = encoder->base.dev;
1316         struct radeon_device *rdev = dev->dev_private;
1317         int i;
1318
1319         for (i = 0; i < 4; i++) {
1320                 tmds->tmds_pll[i].value =
1321                         default_tmds_pll[rdev->family][i].value;
1322                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1323         }
1324
1325         return true;
1326 }
1327
1328 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1329                                               struct radeon_encoder_int_tmds *tmds)
1330 {
1331         struct drm_device *dev = encoder->base.dev;
1332         struct radeon_device *rdev = dev->dev_private;
1333         uint16_t tmds_info;
1334         int i, n;
1335         uint8_t ver;
1336
1337         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1338
1339         if (tmds_info) {
1340                 ver = RBIOS8(tmds_info);
1341                 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1342                 if (ver == 3) {
1343                         n = RBIOS8(tmds_info + 5) + 1;
1344                         if (n > 4)
1345                                 n = 4;
1346                         for (i = 0; i < n; i++) {
1347                                 tmds->tmds_pll[i].value =
1348                                     RBIOS32(tmds_info + i * 10 + 0x08);
1349                                 tmds->tmds_pll[i].freq =
1350                                     RBIOS16(tmds_info + i * 10 + 0x10);
1351                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1352                                           tmds->tmds_pll[i].freq,
1353                                           tmds->tmds_pll[i].value);
1354                         }
1355                 } else if (ver == 4) {
1356                         int stride = 0;
1357                         n = RBIOS8(tmds_info + 5) + 1;
1358                         if (n > 4)
1359                                 n = 4;
1360                         for (i = 0; i < n; i++) {
1361                                 tmds->tmds_pll[i].value =
1362                                     RBIOS32(tmds_info + stride + 0x08);
1363                                 tmds->tmds_pll[i].freq =
1364                                     RBIOS16(tmds_info + stride + 0x10);
1365                                 if (i == 0)
1366                                         stride += 10;
1367                                 else
1368                                         stride += 6;
1369                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1370                                           tmds->tmds_pll[i].freq,
1371                                           tmds->tmds_pll[i].value);
1372                         }
1373                 }
1374         } else {
1375                 DRM_INFO("No TMDS info found in BIOS\n");
1376                 return false;
1377         }
1378         return true;
1379 }
1380
1381 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1382                                                 struct radeon_encoder_ext_tmds *tmds)
1383 {
1384         struct drm_device *dev = encoder->base.dev;
1385         struct radeon_device *rdev = dev->dev_private;
1386         struct radeon_i2c_bus_rec i2c_bus;
1387
1388         /* default for macs */
1389         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1390         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1391
1392         /* XXX some macs have duallink chips */
1393         switch (rdev->mode_info.connector_table) {
1394         case CT_POWERBOOK_EXTERNAL:
1395         case CT_MINI_EXTERNAL:
1396         default:
1397                 tmds->dvo_chip = DVO_SIL164;
1398                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1399                 break;
1400         }
1401
1402         return true;
1403 }
1404
1405 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1406                                                   struct radeon_encoder_ext_tmds *tmds)
1407 {
1408         struct drm_device *dev = encoder->base.dev;
1409         struct radeon_device *rdev = dev->dev_private;
1410         uint16_t offset;
1411         uint8_t ver;
1412         enum radeon_combios_ddc gpio;
1413         struct radeon_i2c_bus_rec i2c_bus;
1414
1415         tmds->i2c_bus = NULL;
1416         if (rdev->flags & RADEON_IS_IGP) {
1417                 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1418                 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1419                 tmds->dvo_chip = DVO_SIL164;
1420                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1421         } else {
1422                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1423                 if (offset) {
1424                         ver = RBIOS8(offset);
1425                         DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1426                         tmds->slave_addr = RBIOS8(offset + 4 + 2);
1427                         tmds->slave_addr >>= 1; /* 7 bit addressing */
1428                         gpio = RBIOS8(offset + 4 + 3);
1429                         if (gpio == DDC_LCD) {
1430                                 /* MM i2c */
1431                                 i2c_bus.valid = true;
1432                                 i2c_bus.hw_capable = true;
1433                                 i2c_bus.mm_i2c = true;
1434                                 i2c_bus.i2c_id = 0xa0;
1435                         } else
1436                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1437                         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1438                 }
1439         }
1440
1441         if (!tmds->i2c_bus) {
1442                 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1443                 return false;
1444         }
1445
1446         return true;
1447 }
1448
1449 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1450 {
1451         struct radeon_device *rdev = dev->dev_private;
1452         struct radeon_i2c_bus_rec ddc_i2c;
1453         struct radeon_hpd hpd;
1454
1455         rdev->mode_info.connector_table = radeon_connector_table;
1456         if (rdev->mode_info.connector_table == CT_NONE) {
1457 #ifdef CONFIG_PPC_PMAC
1458                 if (of_machine_is_compatible("PowerBook3,3")) {
1459                         /* powerbook with VGA */
1460                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1461                 } else if (of_machine_is_compatible("PowerBook3,4") ||
1462                            of_machine_is_compatible("PowerBook3,5")) {
1463                         /* powerbook with internal tmds */
1464                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1465                 } else if (of_machine_is_compatible("PowerBook5,1") ||
1466                            of_machine_is_compatible("PowerBook5,2") ||
1467                            of_machine_is_compatible("PowerBook5,3") ||
1468                            of_machine_is_compatible("PowerBook5,4") ||
1469                            of_machine_is_compatible("PowerBook5,5")) {
1470                         /* powerbook with external single link tmds (sil164) */
1471                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1472                 } else if (of_machine_is_compatible("PowerBook5,6")) {
1473                         /* powerbook with external dual or single link tmds */
1474                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1475                 } else if (of_machine_is_compatible("PowerBook5,7") ||
1476                            of_machine_is_compatible("PowerBook5,8") ||
1477                            of_machine_is_compatible("PowerBook5,9")) {
1478                         /* PowerBook6,2 ? */
1479                         /* powerbook with external dual link tmds (sil1178?) */
1480                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1481                 } else if (of_machine_is_compatible("PowerBook4,1") ||
1482                            of_machine_is_compatible("PowerBook4,2") ||
1483                            of_machine_is_compatible("PowerBook4,3") ||
1484                            of_machine_is_compatible("PowerBook6,3") ||
1485                            of_machine_is_compatible("PowerBook6,5") ||
1486                            of_machine_is_compatible("PowerBook6,7")) {
1487                         /* ibook */
1488                         rdev->mode_info.connector_table = CT_IBOOK;
1489                 } else if (of_machine_is_compatible("PowerMac4,4")) {
1490                         /* emac */
1491                         rdev->mode_info.connector_table = CT_EMAC;
1492                 } else if (of_machine_is_compatible("PowerMac10,1")) {
1493                         /* mini with internal tmds */
1494                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1495                 } else if (of_machine_is_compatible("PowerMac10,2")) {
1496                         /* mini with external tmds */
1497                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1498                 } else if (of_machine_is_compatible("PowerMac12,1")) {
1499                         /* PowerMac8,1 ? */
1500                         /* imac g5 isight */
1501                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1502                 } else if ((rdev->pdev->device == 0x4a48) &&
1503                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1504                            (rdev->pdev->subsystem_device == 0x4a48)) {
1505                         /* Mac X800 */
1506                         rdev->mode_info.connector_table = CT_MAC_X800;
1507                 } else if ((rdev->pdev->device == 0x4150) &&
1508                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1509                            (rdev->pdev->subsystem_device == 0x4150)) {
1510                         /* Mac G5 9600 */
1511                         rdev->mode_info.connector_table = CT_MAC_G5_9600;
1512                 } else
1513 #endif /* CONFIG_PPC_PMAC */
1514 #ifdef CONFIG_PPC64
1515                 if (ASIC_IS_RN50(rdev))
1516                         rdev->mode_info.connector_table = CT_RN50_POWER;
1517                 else
1518 #endif
1519                         rdev->mode_info.connector_table = CT_GENERIC;
1520         }
1521
1522         switch (rdev->mode_info.connector_table) {
1523         case CT_GENERIC:
1524                 DRM_INFO("Connector Table: %d (generic)\n",
1525                          rdev->mode_info.connector_table);
1526                 /* these are the most common settings */
1527                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1528                         /* VGA - primary dac */
1529                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1530                         hpd.hpd = RADEON_HPD_NONE;
1531                         radeon_add_legacy_encoder(dev,
1532                                                   radeon_get_encoder_enum(dev,
1533                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1534                                                                         1),
1535                                                   ATOM_DEVICE_CRT1_SUPPORT);
1536                         radeon_add_legacy_connector(dev, 0,
1537                                                     ATOM_DEVICE_CRT1_SUPPORT,
1538                                                     DRM_MODE_CONNECTOR_VGA,
1539                                                     &ddc_i2c,
1540                                                     CONNECTOR_OBJECT_ID_VGA,
1541                                                     &hpd);
1542                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1543                         /* LVDS */
1544                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1545                         hpd.hpd = RADEON_HPD_NONE;
1546                         radeon_add_legacy_encoder(dev,
1547                                                   radeon_get_encoder_enum(dev,
1548                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1549                                                                         0),
1550                                                   ATOM_DEVICE_LCD1_SUPPORT);
1551                         radeon_add_legacy_connector(dev, 0,
1552                                                     ATOM_DEVICE_LCD1_SUPPORT,
1553                                                     DRM_MODE_CONNECTOR_LVDS,
1554                                                     &ddc_i2c,
1555                                                     CONNECTOR_OBJECT_ID_LVDS,
1556                                                     &hpd);
1557
1558                         /* VGA - primary dac */
1559                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1560                         hpd.hpd = RADEON_HPD_NONE;
1561                         radeon_add_legacy_encoder(dev,
1562                                                   radeon_get_encoder_enum(dev,
1563                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1564                                                                         1),
1565                                                   ATOM_DEVICE_CRT1_SUPPORT);
1566                         radeon_add_legacy_connector(dev, 1,
1567                                                     ATOM_DEVICE_CRT1_SUPPORT,
1568                                                     DRM_MODE_CONNECTOR_VGA,
1569                                                     &ddc_i2c,
1570                                                     CONNECTOR_OBJECT_ID_VGA,
1571                                                     &hpd);
1572                 } else {
1573                         /* DVI-I - tv dac, int tmds */
1574                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1575                         hpd.hpd = RADEON_HPD_1;
1576                         radeon_add_legacy_encoder(dev,
1577                                                   radeon_get_encoder_enum(dev,
1578                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1579                                                                         0),
1580                                                   ATOM_DEVICE_DFP1_SUPPORT);
1581                         radeon_add_legacy_encoder(dev,
1582                                                   radeon_get_encoder_enum(dev,
1583                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1584                                                                         2),
1585                                                   ATOM_DEVICE_CRT2_SUPPORT);
1586                         radeon_add_legacy_connector(dev, 0,
1587                                                     ATOM_DEVICE_DFP1_SUPPORT |
1588                                                     ATOM_DEVICE_CRT2_SUPPORT,
1589                                                     DRM_MODE_CONNECTOR_DVII,
1590                                                     &ddc_i2c,
1591                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1592                                                     &hpd);
1593
1594                         /* VGA - primary dac */
1595                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1596                         hpd.hpd = RADEON_HPD_NONE;
1597                         radeon_add_legacy_encoder(dev,
1598                                                   radeon_get_encoder_enum(dev,
1599                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1600                                                                         1),
1601                                                   ATOM_DEVICE_CRT1_SUPPORT);
1602                         radeon_add_legacy_connector(dev, 1,
1603                                                     ATOM_DEVICE_CRT1_SUPPORT,
1604                                                     DRM_MODE_CONNECTOR_VGA,
1605                                                     &ddc_i2c,
1606                                                     CONNECTOR_OBJECT_ID_VGA,
1607                                                     &hpd);
1608                 }
1609
1610                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1611                         /* TV - tv dac */
1612                         ddc_i2c.valid = false;
1613                         hpd.hpd = RADEON_HPD_NONE;
1614                         radeon_add_legacy_encoder(dev,
1615                                                   radeon_get_encoder_enum(dev,
1616                                                                         ATOM_DEVICE_TV1_SUPPORT,
1617                                                                         2),
1618                                                   ATOM_DEVICE_TV1_SUPPORT);
1619                         radeon_add_legacy_connector(dev, 2,
1620                                                     ATOM_DEVICE_TV1_SUPPORT,
1621                                                     DRM_MODE_CONNECTOR_SVIDEO,
1622                                                     &ddc_i2c,
1623                                                     CONNECTOR_OBJECT_ID_SVIDEO,
1624                                                     &hpd);
1625                 }
1626                 break;
1627         case CT_IBOOK:
1628                 DRM_INFO("Connector Table: %d (ibook)\n",
1629                          rdev->mode_info.connector_table);
1630                 /* LVDS */
1631                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1632                 hpd.hpd = RADEON_HPD_NONE;
1633                 radeon_add_legacy_encoder(dev,
1634                                           radeon_get_encoder_enum(dev,
1635                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1636                                                                 0),
1637                                           ATOM_DEVICE_LCD1_SUPPORT);
1638                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1639                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1640                                             CONNECTOR_OBJECT_ID_LVDS,
1641                                             &hpd);
1642                 /* VGA - TV DAC */
1643                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1644                 hpd.hpd = RADEON_HPD_NONE;
1645                 radeon_add_legacy_encoder(dev,
1646                                           radeon_get_encoder_enum(dev,
1647                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1648                                                                 2),
1649                                           ATOM_DEVICE_CRT2_SUPPORT);
1650                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1651                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1652                                             CONNECTOR_OBJECT_ID_VGA,
1653                                             &hpd);
1654                 /* TV - TV DAC */
1655                 ddc_i2c.valid = false;
1656                 hpd.hpd = RADEON_HPD_NONE;
1657                 radeon_add_legacy_encoder(dev,
1658                                           radeon_get_encoder_enum(dev,
1659                                                                 ATOM_DEVICE_TV1_SUPPORT,
1660                                                                 2),
1661                                           ATOM_DEVICE_TV1_SUPPORT);
1662                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1663                                             DRM_MODE_CONNECTOR_SVIDEO,
1664                                             &ddc_i2c,
1665                                             CONNECTOR_OBJECT_ID_SVIDEO,
1666                                             &hpd);
1667                 break;
1668         case CT_POWERBOOK_EXTERNAL:
1669                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1670                          rdev->mode_info.connector_table);
1671                 /* LVDS */
1672                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1673                 hpd.hpd = RADEON_HPD_NONE;
1674                 radeon_add_legacy_encoder(dev,
1675                                           radeon_get_encoder_enum(dev,
1676                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1677                                                                 0),
1678                                           ATOM_DEVICE_LCD1_SUPPORT);
1679                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1680                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1681                                             CONNECTOR_OBJECT_ID_LVDS,
1682                                             &hpd);
1683                 /* DVI-I - primary dac, ext tmds */
1684                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1685                 hpd.hpd = RADEON_HPD_2; /* ??? */
1686                 radeon_add_legacy_encoder(dev,
1687                                           radeon_get_encoder_enum(dev,
1688                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1689                                                                 0),
1690                                           ATOM_DEVICE_DFP2_SUPPORT);
1691                 radeon_add_legacy_encoder(dev,
1692                                           radeon_get_encoder_enum(dev,
1693                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1694                                                                 1),
1695                                           ATOM_DEVICE_CRT1_SUPPORT);
1696                 /* XXX some are SL */
1697                 radeon_add_legacy_connector(dev, 1,
1698                                             ATOM_DEVICE_DFP2_SUPPORT |
1699                                             ATOM_DEVICE_CRT1_SUPPORT,
1700                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1701                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1702                                             &hpd);
1703                 /* TV - TV DAC */
1704                 ddc_i2c.valid = false;
1705                 hpd.hpd = RADEON_HPD_NONE;
1706                 radeon_add_legacy_encoder(dev,
1707                                           radeon_get_encoder_enum(dev,
1708                                                                 ATOM_DEVICE_TV1_SUPPORT,
1709                                                                 2),
1710                                           ATOM_DEVICE_TV1_SUPPORT);
1711                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1712                                             DRM_MODE_CONNECTOR_SVIDEO,
1713                                             &ddc_i2c,
1714                                             CONNECTOR_OBJECT_ID_SVIDEO,
1715                                             &hpd);
1716                 break;
1717         case CT_POWERBOOK_INTERNAL:
1718                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1719                          rdev->mode_info.connector_table);
1720                 /* LVDS */
1721                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1722                 hpd.hpd = RADEON_HPD_NONE;
1723                 radeon_add_legacy_encoder(dev,
1724                                           radeon_get_encoder_enum(dev,
1725                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1726                                                                 0),
1727                                           ATOM_DEVICE_LCD1_SUPPORT);
1728                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1729                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1730                                             CONNECTOR_OBJECT_ID_LVDS,
1731                                             &hpd);
1732                 /* DVI-I - primary dac, int tmds */
1733                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1734                 hpd.hpd = RADEON_HPD_1; /* ??? */
1735                 radeon_add_legacy_encoder(dev,
1736                                           radeon_get_encoder_enum(dev,
1737                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1738                                                                 0),
1739                                           ATOM_DEVICE_DFP1_SUPPORT);
1740                 radeon_add_legacy_encoder(dev,
1741                                           radeon_get_encoder_enum(dev,
1742                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1743                                                                 1),
1744                                           ATOM_DEVICE_CRT1_SUPPORT);
1745                 radeon_add_legacy_connector(dev, 1,
1746                                             ATOM_DEVICE_DFP1_SUPPORT |
1747                                             ATOM_DEVICE_CRT1_SUPPORT,
1748                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1749                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1750                                             &hpd);
1751                 /* TV - TV DAC */
1752                 ddc_i2c.valid = false;
1753                 hpd.hpd = RADEON_HPD_NONE;
1754                 radeon_add_legacy_encoder(dev,
1755                                           radeon_get_encoder_enum(dev,
1756                                                                 ATOM_DEVICE_TV1_SUPPORT,
1757                                                                 2),
1758                                           ATOM_DEVICE_TV1_SUPPORT);
1759                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1760                                             DRM_MODE_CONNECTOR_SVIDEO,
1761                                             &ddc_i2c,
1762                                             CONNECTOR_OBJECT_ID_SVIDEO,
1763                                             &hpd);
1764                 break;
1765         case CT_POWERBOOK_VGA:
1766                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1767                          rdev->mode_info.connector_table);
1768                 /* LVDS */
1769                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1770                 hpd.hpd = RADEON_HPD_NONE;
1771                 radeon_add_legacy_encoder(dev,
1772                                           radeon_get_encoder_enum(dev,
1773                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1774                                                                 0),
1775                                           ATOM_DEVICE_LCD1_SUPPORT);
1776                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1777                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1778                                             CONNECTOR_OBJECT_ID_LVDS,
1779                                             &hpd);
1780                 /* VGA - primary dac */
1781                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1782                 hpd.hpd = RADEON_HPD_NONE;
1783                 radeon_add_legacy_encoder(dev,
1784                                           radeon_get_encoder_enum(dev,
1785                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1786                                                                 1),
1787                                           ATOM_DEVICE_CRT1_SUPPORT);
1788                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1789                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1790                                             CONNECTOR_OBJECT_ID_VGA,
1791                                             &hpd);
1792                 /* TV - TV DAC */
1793                 ddc_i2c.valid = false;
1794                 hpd.hpd = RADEON_HPD_NONE;
1795                 radeon_add_legacy_encoder(dev,
1796                                           radeon_get_encoder_enum(dev,
1797                                                                 ATOM_DEVICE_TV1_SUPPORT,
1798                                                                 2),
1799                                           ATOM_DEVICE_TV1_SUPPORT);
1800                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1801                                             DRM_MODE_CONNECTOR_SVIDEO,
1802                                             &ddc_i2c,
1803                                             CONNECTOR_OBJECT_ID_SVIDEO,
1804                                             &hpd);
1805                 break;
1806         case CT_MINI_EXTERNAL:
1807                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1808                          rdev->mode_info.connector_table);
1809                 /* DVI-I - tv dac, ext tmds */
1810                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1811                 hpd.hpd = RADEON_HPD_2; /* ??? */
1812                 radeon_add_legacy_encoder(dev,
1813                                           radeon_get_encoder_enum(dev,
1814                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1815                                                                 0),
1816                                           ATOM_DEVICE_DFP2_SUPPORT);
1817                 radeon_add_legacy_encoder(dev,
1818                                           radeon_get_encoder_enum(dev,
1819                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1820                                                                 2),
1821                                           ATOM_DEVICE_CRT2_SUPPORT);
1822                 /* XXX are any DL? */
1823                 radeon_add_legacy_connector(dev, 0,
1824                                             ATOM_DEVICE_DFP2_SUPPORT |
1825                                             ATOM_DEVICE_CRT2_SUPPORT,
1826                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1827                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1828                                             &hpd);
1829                 /* TV - TV DAC */
1830                 ddc_i2c.valid = false;
1831                 hpd.hpd = RADEON_HPD_NONE;
1832                 radeon_add_legacy_encoder(dev,
1833                                           radeon_get_encoder_enum(dev,
1834                                                                 ATOM_DEVICE_TV1_SUPPORT,
1835                                                                 2),
1836                                           ATOM_DEVICE_TV1_SUPPORT);
1837                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1838                                             DRM_MODE_CONNECTOR_SVIDEO,
1839                                             &ddc_i2c,
1840                                             CONNECTOR_OBJECT_ID_SVIDEO,
1841                                             &hpd);
1842                 break;
1843         case CT_MINI_INTERNAL:
1844                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1845                          rdev->mode_info.connector_table);
1846                 /* DVI-I - tv dac, int tmds */
1847                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1848                 hpd.hpd = RADEON_HPD_1; /* ??? */
1849                 radeon_add_legacy_encoder(dev,
1850                                           radeon_get_encoder_enum(dev,
1851                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1852                                                                 0),
1853                                           ATOM_DEVICE_DFP1_SUPPORT);
1854                 radeon_add_legacy_encoder(dev,
1855                                           radeon_get_encoder_enum(dev,
1856                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1857                                                                 2),
1858                                           ATOM_DEVICE_CRT2_SUPPORT);
1859                 radeon_add_legacy_connector(dev, 0,
1860                                             ATOM_DEVICE_DFP1_SUPPORT |
1861                                             ATOM_DEVICE_CRT2_SUPPORT,
1862                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1863                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1864                                             &hpd);
1865                 /* TV - TV DAC */
1866                 ddc_i2c.valid = false;
1867                 hpd.hpd = RADEON_HPD_NONE;
1868                 radeon_add_legacy_encoder(dev,
1869                                           radeon_get_encoder_enum(dev,
1870                                                                 ATOM_DEVICE_TV1_SUPPORT,
1871                                                                 2),
1872                                           ATOM_DEVICE_TV1_SUPPORT);
1873                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1874                                             DRM_MODE_CONNECTOR_SVIDEO,
1875                                             &ddc_i2c,
1876                                             CONNECTOR_OBJECT_ID_SVIDEO,
1877                                             &hpd);
1878                 break;
1879         case CT_IMAC_G5_ISIGHT:
1880                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1881                          rdev->mode_info.connector_table);
1882                 /* DVI-D - int tmds */
1883                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1884                 hpd.hpd = RADEON_HPD_1; /* ??? */
1885                 radeon_add_legacy_encoder(dev,
1886                                           radeon_get_encoder_enum(dev,
1887                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1888                                                                 0),
1889                                           ATOM_DEVICE_DFP1_SUPPORT);
1890                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1891                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1892                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1893                                             &hpd);
1894                 /* VGA - tv dac */
1895                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1896                 hpd.hpd = RADEON_HPD_NONE;
1897                 radeon_add_legacy_encoder(dev,
1898                                           radeon_get_encoder_enum(dev,
1899                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1900                                                                 2),
1901                                           ATOM_DEVICE_CRT2_SUPPORT);
1902                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1903                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1904                                             CONNECTOR_OBJECT_ID_VGA,
1905                                             &hpd);
1906                 /* TV - TV DAC */
1907                 ddc_i2c.valid = false;
1908                 hpd.hpd = RADEON_HPD_NONE;
1909                 radeon_add_legacy_encoder(dev,
1910                                           radeon_get_encoder_enum(dev,
1911                                                                 ATOM_DEVICE_TV1_SUPPORT,
1912                                                                 2),
1913                                           ATOM_DEVICE_TV1_SUPPORT);
1914                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1915                                             DRM_MODE_CONNECTOR_SVIDEO,
1916                                             &ddc_i2c,
1917                                             CONNECTOR_OBJECT_ID_SVIDEO,
1918                                             &hpd);
1919                 break;
1920         case CT_EMAC:
1921                 DRM_INFO("Connector Table: %d (emac)\n",
1922                          rdev->mode_info.connector_table);
1923                 /* VGA - primary dac */
1924                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1925                 hpd.hpd = RADEON_HPD_NONE;
1926                 radeon_add_legacy_encoder(dev,
1927                                           radeon_get_encoder_enum(dev,
1928                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1929                                                                 1),
1930                                           ATOM_DEVICE_CRT1_SUPPORT);
1931                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1932                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1933                                             CONNECTOR_OBJECT_ID_VGA,
1934                                             &hpd);
1935                 /* VGA - tv dac */
1936                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1937                 hpd.hpd = RADEON_HPD_NONE;
1938                 radeon_add_legacy_encoder(dev,
1939                                           radeon_get_encoder_enum(dev,
1940                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1941                                                                 2),
1942                                           ATOM_DEVICE_CRT2_SUPPORT);
1943                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1944                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1945                                             CONNECTOR_OBJECT_ID_VGA,
1946                                             &hpd);
1947                 /* TV - TV DAC */
1948                 ddc_i2c.valid = false;
1949                 hpd.hpd = RADEON_HPD_NONE;
1950                 radeon_add_legacy_encoder(dev,
1951                                           radeon_get_encoder_enum(dev,
1952                                                                 ATOM_DEVICE_TV1_SUPPORT,
1953                                                                 2),
1954                                           ATOM_DEVICE_TV1_SUPPORT);
1955                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1956                                             DRM_MODE_CONNECTOR_SVIDEO,
1957                                             &ddc_i2c,
1958                                             CONNECTOR_OBJECT_ID_SVIDEO,
1959                                             &hpd);
1960                 break;
1961         case CT_RN50_POWER:
1962                 DRM_INFO("Connector Table: %d (rn50-power)\n",
1963                          rdev->mode_info.connector_table);
1964                 /* VGA - primary dac */
1965                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1966                 hpd.hpd = RADEON_HPD_NONE;
1967                 radeon_add_legacy_encoder(dev,
1968                                           radeon_get_encoder_enum(dev,
1969                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1970                                                                 1),
1971                                           ATOM_DEVICE_CRT1_SUPPORT);
1972                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1973                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1974                                             CONNECTOR_OBJECT_ID_VGA,
1975                                             &hpd);
1976                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1977                 hpd.hpd = RADEON_HPD_NONE;
1978                 radeon_add_legacy_encoder(dev,
1979                                           radeon_get_encoder_enum(dev,
1980                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1981                                                                 2),
1982                                           ATOM_DEVICE_CRT2_SUPPORT);
1983                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1984                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1985                                             CONNECTOR_OBJECT_ID_VGA,
1986                                             &hpd);
1987                 break;
1988         case CT_MAC_X800:
1989                 DRM_INFO("Connector Table: %d (mac x800)\n",
1990                          rdev->mode_info.connector_table);
1991                 /* DVI - primary dac, internal tmds */
1992                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1993                 hpd.hpd = RADEON_HPD_1; /* ??? */
1994                 radeon_add_legacy_encoder(dev,
1995                                           radeon_get_encoder_enum(dev,
1996                                                                   ATOM_DEVICE_DFP1_SUPPORT,
1997                                                                   0),
1998                                           ATOM_DEVICE_DFP1_SUPPORT);
1999                 radeon_add_legacy_encoder(dev,
2000                                           radeon_get_encoder_enum(dev,
2001                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2002                                                                   1),
2003                                           ATOM_DEVICE_CRT1_SUPPORT);
2004                 radeon_add_legacy_connector(dev, 0,
2005                                             ATOM_DEVICE_DFP1_SUPPORT |
2006                                             ATOM_DEVICE_CRT1_SUPPORT,
2007                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2008                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2009                                             &hpd);
2010                 /* DVI - tv dac, dvo */
2011                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2012                 hpd.hpd = RADEON_HPD_2; /* ??? */
2013                 radeon_add_legacy_encoder(dev,
2014                                           radeon_get_encoder_enum(dev,
2015                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2016                                                                   0),
2017                                           ATOM_DEVICE_DFP2_SUPPORT);
2018                 radeon_add_legacy_encoder(dev,
2019                                           radeon_get_encoder_enum(dev,
2020                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2021                                                                   2),
2022                                           ATOM_DEVICE_CRT2_SUPPORT);
2023                 radeon_add_legacy_connector(dev, 1,
2024                                             ATOM_DEVICE_DFP2_SUPPORT |
2025                                             ATOM_DEVICE_CRT2_SUPPORT,
2026                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2027                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2028                                             &hpd);
2029                 break;
2030         case CT_MAC_G5_9600:
2031                 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2032                          rdev->mode_info.connector_table);
2033                 /* DVI - tv dac, dvo */
2034                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2035                 hpd.hpd = RADEON_HPD_1; /* ??? */
2036                 radeon_add_legacy_encoder(dev,
2037                                           radeon_get_encoder_enum(dev,
2038                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2039                                                                   0),
2040                                           ATOM_DEVICE_DFP2_SUPPORT);
2041                 radeon_add_legacy_encoder(dev,
2042                                           radeon_get_encoder_enum(dev,
2043                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2044                                                                   2),
2045                                           ATOM_DEVICE_CRT2_SUPPORT);
2046                 radeon_add_legacy_connector(dev, 0,
2047                                             ATOM_DEVICE_DFP2_SUPPORT |
2048                                             ATOM_DEVICE_CRT2_SUPPORT,
2049                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2050                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2051                                             &hpd);
2052                 /* ADC - primary dac, internal tmds */
2053                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2054                 hpd.hpd = RADEON_HPD_2; /* ??? */
2055                 radeon_add_legacy_encoder(dev,
2056                                           radeon_get_encoder_enum(dev,
2057                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2058                                                                   0),
2059                                           ATOM_DEVICE_DFP1_SUPPORT);
2060                 radeon_add_legacy_encoder(dev,
2061                                           radeon_get_encoder_enum(dev,
2062                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2063                                                                   1),
2064                                           ATOM_DEVICE_CRT1_SUPPORT);
2065                 radeon_add_legacy_connector(dev, 1,
2066                                             ATOM_DEVICE_DFP1_SUPPORT |
2067                                             ATOM_DEVICE_CRT1_SUPPORT,
2068                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2069                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2070                                             &hpd);
2071                 break;
2072         default:
2073                 DRM_INFO("Connector table: %d (invalid)\n",
2074                          rdev->mode_info.connector_table);
2075                 return false;
2076         }
2077
2078         radeon_link_encoder_connector(dev);
2079
2080         return true;
2081 }
2082
2083 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2084                                        int bios_index,
2085                                        enum radeon_combios_connector
2086                                        *legacy_connector,
2087                                        struct radeon_i2c_bus_rec *ddc_i2c,
2088                                        struct radeon_hpd *hpd)
2089 {
2090
2091         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2092            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2093         if (dev->pdev->device == 0x515e &&
2094             dev->pdev->subsystem_vendor == 0x1014) {
2095                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2096                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2097                         return false;
2098         }
2099
2100         /* X300 card with extra non-existent DVI port */
2101         if (dev->pdev->device == 0x5B60 &&
2102             dev->pdev->subsystem_vendor == 0x17af &&
2103             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2104                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2105                         return false;
2106         }
2107
2108         return true;
2109 }
2110
2111 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2112 {
2113         /* Acer 5102 has non-existent TV port */
2114         if (dev->pdev->device == 0x5975 &&
2115             dev->pdev->subsystem_vendor == 0x1025 &&
2116             dev->pdev->subsystem_device == 0x009f)
2117                 return false;
2118
2119         /* HP dc5750 has non-existent TV port */
2120         if (dev->pdev->device == 0x5974 &&
2121             dev->pdev->subsystem_vendor == 0x103c &&
2122             dev->pdev->subsystem_device == 0x280a)
2123                 return false;
2124
2125         /* MSI S270 has non-existent TV port */
2126         if (dev->pdev->device == 0x5955 &&
2127             dev->pdev->subsystem_vendor == 0x1462 &&
2128             dev->pdev->subsystem_device == 0x0131)
2129                 return false;
2130
2131         return true;
2132 }
2133
2134 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2135 {
2136         struct radeon_device *rdev = dev->dev_private;
2137         uint32_t ext_tmds_info;
2138
2139         if (rdev->flags & RADEON_IS_IGP) {
2140                 if (is_dvi_d)
2141                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2142                 else
2143                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2144         }
2145         ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2146         if (ext_tmds_info) {
2147                 uint8_t rev = RBIOS8(ext_tmds_info);
2148                 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2149                 if (rev >= 3) {
2150                         if (is_dvi_d)
2151                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2152                         else
2153                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2154                 } else {
2155                         if (flags & 1) {
2156                                 if (is_dvi_d)
2157                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2158                                 else
2159                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2160                         }
2161                 }
2162         }
2163         if (is_dvi_d)
2164                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2165         else
2166                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2167 }
2168
2169 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2170 {
2171         struct radeon_device *rdev = dev->dev_private;
2172         uint32_t conn_info, entry, devices;
2173         uint16_t tmp, connector_object_id;
2174         enum radeon_combios_ddc ddc_type;
2175         enum radeon_combios_connector connector;
2176         int i = 0;
2177         struct radeon_i2c_bus_rec ddc_i2c;
2178         struct radeon_hpd hpd;
2179
2180         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2181         if (conn_info) {
2182                 for (i = 0; i < 4; i++) {
2183                         entry = conn_info + 2 + i * 2;
2184
2185                         if (!RBIOS16(entry))
2186                                 break;
2187
2188                         tmp = RBIOS16(entry);
2189
2190                         connector = (tmp >> 12) & 0xf;
2191
2192                         ddc_type = (tmp >> 8) & 0xf;
2193                         ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2194
2195                         switch (connector) {
2196                         case CONNECTOR_PROPRIETARY_LEGACY:
2197                         case CONNECTOR_DVI_I_LEGACY:
2198                         case CONNECTOR_DVI_D_LEGACY:
2199                                 if ((tmp >> 4) & 0x1)
2200                                         hpd.hpd = RADEON_HPD_2;
2201                                 else
2202                                         hpd.hpd = RADEON_HPD_1;
2203                                 break;
2204                         default:
2205                                 hpd.hpd = RADEON_HPD_NONE;
2206                                 break;
2207                         }
2208
2209                         if (!radeon_apply_legacy_quirks(dev, i, &connector,
2210                                                         &ddc_i2c, &hpd))
2211                                 continue;
2212
2213                         switch (connector) {
2214                         case CONNECTOR_PROPRIETARY_LEGACY:
2215                                 if ((tmp >> 4) & 0x1)
2216                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2217                                 else
2218                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2219                                 radeon_add_legacy_encoder(dev,
2220                                                           radeon_get_encoder_enum
2221                                                           (dev, devices, 0),
2222                                                           devices);
2223                                 radeon_add_legacy_connector(dev, i, devices,
2224                                                             legacy_connector_convert
2225                                                             [connector],
2226                                                             &ddc_i2c,
2227                                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2228                                                             &hpd);
2229                                 break;
2230                         case CONNECTOR_CRT_LEGACY:
2231                                 if (tmp & 0x1) {
2232                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
2233                                         radeon_add_legacy_encoder(dev,
2234                                                                   radeon_get_encoder_enum
2235                                                                   (dev,
2236                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2237                                                                    2),
2238                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2239                                 } else {
2240                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
2241                                         radeon_add_legacy_encoder(dev,
2242                                                                   radeon_get_encoder_enum
2243                                                                   (dev,
2244                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2245                                                                    1),
2246                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2247                                 }
2248                                 radeon_add_legacy_connector(dev,
2249                                                             i,
2250                                                             devices,
2251                                                             legacy_connector_convert
2252                                                             [connector],
2253                                                             &ddc_i2c,
2254                                                             CONNECTOR_OBJECT_ID_VGA,
2255                                                             &hpd);
2256                                 break;
2257                         case CONNECTOR_DVI_I_LEGACY:
2258                                 devices = 0;
2259                                 if (tmp & 0x1) {
2260                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
2261                                         radeon_add_legacy_encoder(dev,
2262                                                                   radeon_get_encoder_enum
2263                                                                   (dev,
2264                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2265                                                                    2),
2266                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2267                                 } else {
2268                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
2269                                         radeon_add_legacy_encoder(dev,
2270                                                                   radeon_get_encoder_enum
2271                                                                   (dev,
2272                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2273                                                                    1),
2274                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2275                                 }
2276                                 if ((tmp >> 4) & 0x1) {
2277                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
2278                                         radeon_add_legacy_encoder(dev,
2279                                                                   radeon_get_encoder_enum
2280                                                                   (dev,
2281                                                                    ATOM_DEVICE_DFP2_SUPPORT,
2282                                                                    0),
2283                                                                   ATOM_DEVICE_DFP2_SUPPORT);
2284                                         connector_object_id = combios_check_dl_dvi(dev, 0);
2285                                 } else {
2286                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
2287                                         radeon_add_legacy_encoder(dev,
2288                                                                   radeon_get_encoder_enum
2289                                                                   (dev,
2290                                                                    ATOM_DEVICE_DFP1_SUPPORT,
2291                                                                    0),
2292                                                                   ATOM_DEVICE_DFP1_SUPPORT);
2293                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2294                                 }
2295                                 radeon_add_legacy_connector(dev,
2296                                                             i,
2297                                                             devices,
2298                                                             legacy_connector_convert
2299                                                             [connector],
2300                                                             &ddc_i2c,
2301                                                             connector_object_id,
2302                                                             &hpd);
2303                                 break;
2304                         case CONNECTOR_DVI_D_LEGACY:
2305                                 if ((tmp >> 4) & 0x1) {
2306                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2307                                         connector_object_id = combios_check_dl_dvi(dev, 1);
2308                                 } else {
2309                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2310                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2311                                 }
2312                                 radeon_add_legacy_encoder(dev,
2313                                                           radeon_get_encoder_enum
2314                                                           (dev, devices, 0),
2315                                                           devices);
2316                                 radeon_add_legacy_connector(dev, i, devices,
2317                                                             legacy_connector_convert
2318                                                             [connector],
2319                                                             &ddc_i2c,
2320                                                             connector_object_id,
2321                                                             &hpd);
2322                                 break;
2323                         case CONNECTOR_CTV_LEGACY:
2324                         case CONNECTOR_STV_LEGACY:
2325                                 radeon_add_legacy_encoder(dev,
2326                                                           radeon_get_encoder_enum
2327                                                           (dev,
2328                                                            ATOM_DEVICE_TV1_SUPPORT,
2329                                                            2),
2330                                                           ATOM_DEVICE_TV1_SUPPORT);
2331                                 radeon_add_legacy_connector(dev, i,
2332                                                             ATOM_DEVICE_TV1_SUPPORT,
2333                                                             legacy_connector_convert
2334                                                             [connector],
2335                                                             &ddc_i2c,
2336                                                             CONNECTOR_OBJECT_ID_SVIDEO,
2337                                                             &hpd);
2338                                 break;
2339                         default:
2340                                 DRM_ERROR("Unknown connector type: %d\n",
2341                                           connector);
2342                                 continue;
2343                         }
2344
2345                 }
2346         } else {
2347                 uint16_t tmds_info =
2348                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2349                 if (tmds_info) {
2350                         DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2351
2352                         radeon_add_legacy_encoder(dev,
2353                                                   radeon_get_encoder_enum(dev,
2354                                                                         ATOM_DEVICE_CRT1_SUPPORT,
2355                                                                         1),
2356                                                   ATOM_DEVICE_CRT1_SUPPORT);
2357                         radeon_add_legacy_encoder(dev,
2358                                                   radeon_get_encoder_enum(dev,
2359                                                                         ATOM_DEVICE_DFP1_SUPPORT,
2360                                                                         0),
2361                                                   ATOM_DEVICE_DFP1_SUPPORT);
2362
2363                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2364                         hpd.hpd = RADEON_HPD_1;
2365                         radeon_add_legacy_connector(dev,
2366                                                     0,
2367                                                     ATOM_DEVICE_CRT1_SUPPORT |
2368                                                     ATOM_DEVICE_DFP1_SUPPORT,
2369                                                     DRM_MODE_CONNECTOR_DVII,
2370                                                     &ddc_i2c,
2371                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2372                                                     &hpd);
2373                 } else {
2374                         uint16_t crt_info =
2375                                 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2376                         DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2377                         if (crt_info) {
2378                                 radeon_add_legacy_encoder(dev,
2379                                                           radeon_get_encoder_enum(dev,
2380                                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2381                                                                                 1),
2382                                                           ATOM_DEVICE_CRT1_SUPPORT);
2383                                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2384                                 hpd.hpd = RADEON_HPD_NONE;
2385                                 radeon_add_legacy_connector(dev,
2386                                                             0,
2387                                                             ATOM_DEVICE_CRT1_SUPPORT,
2388                                                             DRM_MODE_CONNECTOR_VGA,
2389                                                             &ddc_i2c,
2390                                                             CONNECTOR_OBJECT_ID_VGA,
2391                                                             &hpd);
2392                         } else {
2393                                 DRM_DEBUG_KMS("No connector info found\n");
2394                                 return false;
2395                         }
2396                 }
2397         }
2398
2399         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2400                 uint16_t lcd_info =
2401                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2402                 if (lcd_info) {
2403                         uint16_t lcd_ddc_info =
2404                             combios_get_table_offset(dev,
2405                                                      COMBIOS_LCD_DDC_INFO_TABLE);
2406
2407                         radeon_add_legacy_encoder(dev,
2408                                                   radeon_get_encoder_enum(dev,
2409                                                                         ATOM_DEVICE_LCD1_SUPPORT,
2410                                                                         0),
2411                                                   ATOM_DEVICE_LCD1_SUPPORT);
2412
2413                         if (lcd_ddc_info) {
2414                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
2415                                 switch (ddc_type) {
2416                                 case DDC_LCD:
2417                                         ddc_i2c =
2418                                                 combios_setup_i2c_bus(rdev,
2419                                                                       DDC_LCD,
2420                                                                       RBIOS32(lcd_ddc_info + 3),
2421                                                                       RBIOS32(lcd_ddc_info + 7));
2422                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2423                                         break;
2424                                 case DDC_GPIO:
2425                                         ddc_i2c =
2426                                                 combios_setup_i2c_bus(rdev,
2427                                                                       DDC_GPIO,
2428                                                                       RBIOS32(lcd_ddc_info + 3),
2429                                                                       RBIOS32(lcd_ddc_info + 7));
2430                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2431                                         break;
2432                                 default:
2433                                         ddc_i2c =
2434                                                 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2435                                         break;
2436                                 }
2437                                 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2438                         } else
2439                                 ddc_i2c.valid = false;
2440
2441                         hpd.hpd = RADEON_HPD_NONE;
2442                         radeon_add_legacy_connector(dev,
2443                                                     5,
2444                                                     ATOM_DEVICE_LCD1_SUPPORT,
2445                                                     DRM_MODE_CONNECTOR_LVDS,
2446                                                     &ddc_i2c,
2447                                                     CONNECTOR_OBJECT_ID_LVDS,
2448                                                     &hpd);
2449                 }
2450         }
2451
2452         /* check TV table */
2453         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2454                 uint32_t tv_info =
2455                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2456                 if (tv_info) {
2457                         if (RBIOS8(tv_info + 6) == 'T') {
2458                                 if (radeon_apply_legacy_tv_quirks(dev)) {
2459                                         hpd.hpd = RADEON_HPD_NONE;
2460                                         ddc_i2c.valid = false;
2461                                         radeon_add_legacy_encoder(dev,
2462                                                                   radeon_get_encoder_enum
2463                                                                   (dev,
2464                                                                    ATOM_DEVICE_TV1_SUPPORT,
2465                                                                    2),
2466                                                                   ATOM_DEVICE_TV1_SUPPORT);
2467                                         radeon_add_legacy_connector(dev, 6,
2468                                                                     ATOM_DEVICE_TV1_SUPPORT,
2469                                                                     DRM_MODE_CONNECTOR_SVIDEO,
2470                                                                     &ddc_i2c,
2471                                                                     CONNECTOR_OBJECT_ID_SVIDEO,
2472                                                                     &hpd);
2473                                 }
2474                         }
2475                 }
2476         }
2477
2478         radeon_link_encoder_connector(dev);
2479
2480         return true;
2481 }
2482
2483 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2484 {
2485         struct drm_device *dev = rdev->ddev;
2486         u16 offset, misc, misc2 = 0;
2487         u8 rev, blocks, tmp;
2488         int state_index = 0;
2489
2490         rdev->pm.default_power_state_index = -1;
2491
2492         /* allocate 2 power states */
2493         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2494         if (!rdev->pm.power_state) {
2495                 rdev->pm.default_power_state_index = state_index;
2496                 rdev->pm.num_power_states = 0;
2497
2498                 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2499                 rdev->pm.current_clock_mode_index = 0;
2500                 return;
2501         }
2502
2503         if (rdev->flags & RADEON_IS_MOBILITY) {
2504                 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2505                 if (offset) {
2506                         rev = RBIOS8(offset);
2507                         blocks = RBIOS8(offset + 0x2);
2508                         /* power mode 0 tends to be the only valid one */
2509                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2510                         rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2511                         rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2512                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2513                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2514                                 goto default_mode;
2515                         rdev->pm.power_state[state_index].type =
2516                                 POWER_STATE_TYPE_BATTERY;
2517                         misc = RBIOS16(offset + 0x5 + 0x0);
2518                         if (rev > 4)
2519                                 misc2 = RBIOS16(offset + 0x5 + 0xe);
2520                         rdev->pm.power_state[state_index].misc = misc;
2521                         rdev->pm.power_state[state_index].misc2 = misc2;
2522                         if (misc & 0x4) {
2523                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2524                                 if (misc & 0x8)
2525                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2526                                                 true;
2527                                 else
2528                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2529                                                 false;
2530                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2531                                 if (rev < 6) {
2532                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2533                                                 RBIOS16(offset + 0x5 + 0xb) * 4;
2534                                         tmp = RBIOS8(offset + 0x5 + 0xd);
2535                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2536                                 } else {
2537                                         u8 entries = RBIOS8(offset + 0x5 + 0xb);
2538                                         u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2539                                         if (entries && voltage_table_offset) {
2540                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2541                                                         RBIOS16(voltage_table_offset) * 4;
2542                                                 tmp = RBIOS8(voltage_table_offset + 0x2);
2543                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2544                                         } else
2545                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2546                                 }
2547                                 switch ((misc2 & 0x700) >> 8) {
2548                                 case 0:
2549                                 default:
2550                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2551                                         break;
2552                                 case 1:
2553                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2554                                         break;
2555                                 case 2:
2556                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2557                                         break;
2558                                 case 3:
2559                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2560                                         break;
2561                                 case 4:
2562                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2563                                         break;
2564                                 }
2565                         } else
2566                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2567                         if (rev > 6)
2568                                 rdev->pm.power_state[state_index].pcie_lanes =
2569                                         RBIOS8(offset + 0x5 + 0x10);
2570                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2571                         state_index++;
2572                 } else {
2573                         /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2574                 }
2575         } else {
2576                 /* XXX figure out some good default low power mode for desktop cards */
2577         }
2578
2579 default_mode:
2580         /* add the default mode */
2581         rdev->pm.power_state[state_index].type =
2582                 POWER_STATE_TYPE_DEFAULT;
2583         rdev->pm.power_state[state_index].num_clock_modes = 1;
2584         rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2585         rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2586         rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2587         if ((state_index > 0) &&
2588             (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2589                 rdev->pm.power_state[state_index].clock_info[0].voltage =
2590                         rdev->pm.power_state[0].clock_info[0].voltage;
2591         else
2592                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2593         rdev->pm.power_state[state_index].pcie_lanes = 16;
2594         rdev->pm.power_state[state_index].flags = 0;
2595         rdev->pm.default_power_state_index = state_index;
2596         rdev->pm.num_power_states = state_index + 1;
2597
2598         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2599         rdev->pm.current_clock_mode_index = 0;
2600 }
2601
2602 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2603 {
2604         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2605         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2606
2607         if (!tmds)
2608                 return;
2609
2610         switch (tmds->dvo_chip) {
2611         case DVO_SIL164:
2612                 /* sil 164 */
2613                 radeon_i2c_put_byte(tmds->i2c_bus,
2614                                     tmds->slave_addr,
2615                                     0x08, 0x30);
2616                 radeon_i2c_put_byte(tmds->i2c_bus,
2617                                        tmds->slave_addr,
2618                                        0x09, 0x00);
2619                 radeon_i2c_put_byte(tmds->i2c_bus,
2620                                     tmds->slave_addr,
2621                                     0x0a, 0x90);
2622                 radeon_i2c_put_byte(tmds->i2c_bus,
2623                                     tmds->slave_addr,
2624                                     0x0c, 0x89);
2625                 radeon_i2c_put_byte(tmds->i2c_bus,
2626                                        tmds->slave_addr,
2627                                        0x08, 0x3b);
2628                 break;
2629         case DVO_SIL1178:
2630                 /* sil 1178 - untested */
2631                 /*
2632                  * 0x0f, 0x44
2633                  * 0x0f, 0x4c
2634                  * 0x0e, 0x01
2635                  * 0x0a, 0x80
2636                  * 0x09, 0x30
2637                  * 0x0c, 0xc9
2638                  * 0x0d, 0x70
2639                  * 0x08, 0x32
2640                  * 0x08, 0x33
2641                  */
2642                 break;
2643         default:
2644                 break;
2645         }
2646
2647 }
2648
2649 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2650 {
2651         struct drm_device *dev = encoder->dev;
2652         struct radeon_device *rdev = dev->dev_private;
2653         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2654         uint16_t offset;
2655         uint8_t blocks, slave_addr, rev;
2656         uint32_t index, id;
2657         uint32_t reg, val, and_mask, or_mask;
2658         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2659
2660         if (!tmds)
2661                 return false;
2662
2663         if (rdev->flags & RADEON_IS_IGP) {
2664                 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2665                 rev = RBIOS8(offset);
2666                 if (offset) {
2667                         rev = RBIOS8(offset);
2668                         if (rev > 1) {
2669                                 blocks = RBIOS8(offset + 3);
2670                                 index = offset + 4;
2671                                 while (blocks > 0) {
2672                                         id = RBIOS16(index);
2673                                         index += 2;
2674                                         switch (id >> 13) {
2675                                         case 0:
2676                                                 reg = (id & 0x1fff) * 4;
2677                                                 val = RBIOS32(index);
2678                                                 index += 4;
2679                                                 WREG32(reg, val);
2680                                                 break;
2681                                         case 2:
2682                                                 reg = (id & 0x1fff) * 4;
2683                                                 and_mask = RBIOS32(index);
2684                                                 index += 4;
2685                                                 or_mask = RBIOS32(index);
2686                                                 index += 4;
2687                                                 val = RREG32(reg);
2688                                                 val = (val & and_mask) | or_mask;
2689                                                 WREG32(reg, val);
2690                                                 break;
2691                                         case 3:
2692                                                 val = RBIOS16(index);
2693                                                 index += 2;
2694                                                 udelay(val);
2695                                                 break;
2696                                         case 4:
2697                                                 val = RBIOS16(index);
2698                                                 index += 2;
2699                                                 udelay(val * 1000);
2700                                                 break;
2701                                         case 6:
2702                                                 slave_addr = id & 0xff;
2703                                                 slave_addr >>= 1; /* 7 bit addressing */
2704                                                 index++;
2705                                                 reg = RBIOS8(index);
2706                                                 index++;
2707                                                 val = RBIOS8(index);
2708                                                 index++;
2709                                                 radeon_i2c_put_byte(tmds->i2c_bus,
2710                                                                     slave_addr,
2711                                                                     reg, val);
2712                                                 break;
2713                                         default:
2714                                                 DRM_ERROR("Unknown id %d\n", id >> 13);
2715                                                 break;
2716                                         }
2717                                         blocks--;
2718                                 }
2719                                 return true;
2720                         }
2721                 }
2722         } else {
2723                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2724                 if (offset) {
2725                         index = offset + 10;
2726                         id = RBIOS16(index);
2727                         while (id != 0xffff) {
2728                                 index += 2;
2729                                 switch (id >> 13) {
2730                                 case 0:
2731                                         reg = (id & 0x1fff) * 4;
2732                                         val = RBIOS32(index);
2733                                         WREG32(reg, val);
2734                                         break;
2735                                 case 2:
2736                                         reg = (id & 0x1fff) * 4;
2737                                         and_mask = RBIOS32(index);
2738                                         index += 4;
2739                                         or_mask = RBIOS32(index);
2740                                         index += 4;
2741                                         val = RREG32(reg);
2742                                         val = (val & and_mask) | or_mask;
2743                                         WREG32(reg, val);
2744                                         break;
2745                                 case 4:
2746                                         val = RBIOS16(index);
2747                                         index += 2;
2748                                         udelay(val);
2749                                         break;
2750                                 case 5:
2751                                         reg = id & 0x1fff;
2752                                         and_mask = RBIOS32(index);
2753                                         index += 4;
2754                                         or_mask = RBIOS32(index);
2755                                         index += 4;
2756                                         val = RREG32_PLL(reg);
2757                                         val = (val & and_mask) | or_mask;
2758                                         WREG32_PLL(reg, val);
2759                                         break;
2760                                 case 6:
2761                                         reg = id & 0x1fff;
2762                                         val = RBIOS8(index);
2763                                         index += 1;
2764                                         radeon_i2c_put_byte(tmds->i2c_bus,
2765                                                             tmds->slave_addr,
2766                                                             reg, val);
2767                                         break;
2768                                 default:
2769                                         DRM_ERROR("Unknown id %d\n", id >> 13);
2770                                         break;
2771                                 }
2772                                 id = RBIOS16(index);
2773                         }
2774                         return true;
2775                 }
2776         }
2777         return false;
2778 }
2779
2780 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2781 {
2782         struct radeon_device *rdev = dev->dev_private;
2783
2784         if (offset) {
2785                 while (RBIOS16(offset)) {
2786                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2787                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
2788                         uint32_t val, and_mask, or_mask;
2789                         uint32_t tmp;
2790
2791                         offset += 2;
2792                         switch (cmd) {
2793                         case 0:
2794                                 val = RBIOS32(offset);
2795                                 offset += 4;
2796                                 WREG32(addr, val);
2797                                 break;
2798                         case 1:
2799                                 val = RBIOS32(offset);
2800                                 offset += 4;
2801                                 WREG32(addr, val);
2802                                 break;
2803                         case 2:
2804                                 and_mask = RBIOS32(offset);
2805                                 offset += 4;
2806                                 or_mask = RBIOS32(offset);
2807                                 offset += 4;
2808                                 tmp = RREG32(addr);
2809                                 tmp &= and_mask;
2810                                 tmp |= or_mask;
2811                                 WREG32(addr, tmp);
2812                                 break;
2813                         case 3:
2814                                 and_mask = RBIOS32(offset);
2815                                 offset += 4;
2816                                 or_mask = RBIOS32(offset);
2817                                 offset += 4;
2818                                 tmp = RREG32(addr);
2819                                 tmp &= and_mask;
2820                                 tmp |= or_mask;
2821                                 WREG32(addr, tmp);
2822                                 break;
2823                         case 4:
2824                                 val = RBIOS16(offset);
2825                                 offset += 2;
2826                                 udelay(val);
2827                                 break;
2828                         case 5:
2829                                 val = RBIOS16(offset);
2830                                 offset += 2;
2831                                 switch (addr) {
2832                                 case 8:
2833                                         while (val--) {
2834                                                 if (!
2835                                                     (RREG32_PLL
2836                                                      (RADEON_CLK_PWRMGT_CNTL) &
2837                                                      RADEON_MC_BUSY))
2838                                                         break;
2839                                         }
2840                                         break;
2841                                 case 9:
2842                                         while (val--) {
2843                                                 if ((RREG32(RADEON_MC_STATUS) &
2844                                                      RADEON_MC_IDLE))
2845                                                         break;
2846                                         }
2847                                         break;
2848                                 default:
2849                                         break;
2850                                 }
2851                                 break;
2852                         default:
2853                                 break;
2854                         }
2855                 }
2856         }
2857 }
2858
2859 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2860 {
2861         struct radeon_device *rdev = dev->dev_private;
2862
2863         if (offset) {
2864                 while (RBIOS8(offset)) {
2865                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2866                         uint8_t addr = (RBIOS8(offset) & 0x3f);
2867                         uint32_t val, shift, tmp;
2868                         uint32_t and_mask, or_mask;
2869
2870                         offset++;
2871                         switch (cmd) {
2872                         case 0:
2873                                 val = RBIOS32(offset);
2874                                 offset += 4;
2875                                 WREG32_PLL(addr, val);
2876                                 break;
2877                         case 1:
2878                                 shift = RBIOS8(offset) * 8;
2879                                 offset++;
2880                                 and_mask = RBIOS8(offset) << shift;
2881                                 and_mask |= ~(0xff << shift);
2882                                 offset++;
2883                                 or_mask = RBIOS8(offset) << shift;
2884                                 offset++;
2885                                 tmp = RREG32_PLL(addr);
2886                                 tmp &= and_mask;
2887                                 tmp |= or_mask;
2888                                 WREG32_PLL(addr, tmp);
2889                                 break;
2890                         case 2:
2891                         case 3:
2892                                 tmp = 1000;
2893                                 switch (addr) {
2894                                 case 1:
2895                                         udelay(150);
2896                                         break;
2897                                 case 2:
2898                                         udelay(1000);
2899                                         break;
2900                                 case 3:
2901                                         while (tmp--) {
2902                                                 if (!
2903                                                     (RREG32_PLL
2904                                                      (RADEON_CLK_PWRMGT_CNTL) &
2905                                                      RADEON_MC_BUSY))
2906                                                         break;
2907                                         }
2908                                         break;
2909                                 case 4:
2910                                         while (tmp--) {
2911                                                 if (RREG32_PLL
2912                                                     (RADEON_CLK_PWRMGT_CNTL) &
2913                                                     RADEON_DLL_READY)
2914                                                         break;
2915                                         }
2916                                         break;
2917                                 case 5:
2918                                         tmp =
2919                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2920                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
2921 #if 0
2922                                                 uint32_t mclk_cntl =
2923                                                     RREG32_PLL
2924                                                     (RADEON_MCLK_CNTL);
2925                                                 mclk_cntl &= 0xffff0000;
2926                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
2927                                                 WREG32_PLL(RADEON_MCLK_CNTL,
2928                                                            mclk_cntl);
2929                                                 udelay(10000);
2930 #endif
2931                                                 WREG32_PLL
2932                                                     (RADEON_CLK_PWRMGT_CNTL,
2933                                                      tmp &
2934                                                      ~RADEON_CG_NO1_DEBUG_0);
2935                                                 udelay(10000);
2936                                         }
2937                                         break;
2938                                 default:
2939                                         break;
2940                                 }
2941                                 break;
2942                         default:
2943                                 break;
2944                         }
2945                 }
2946         }
2947 }
2948
2949 static void combios_parse_ram_reset_table(struct drm_device *dev,
2950                                           uint16_t offset)
2951 {
2952         struct radeon_device *rdev = dev->dev_private;
2953         uint32_t tmp;
2954
2955         if (offset) {
2956                 uint8_t val = RBIOS8(offset);
2957                 while (val != 0xff) {
2958                         offset++;
2959
2960                         if (val == 0x0f) {
2961                                 uint32_t channel_complete_mask;
2962
2963                                 if (ASIC_IS_R300(rdev))
2964                                         channel_complete_mask =
2965                                             R300_MEM_PWRUP_COMPLETE;
2966                                 else
2967                                         channel_complete_mask =
2968                                             RADEON_MEM_PWRUP_COMPLETE;
2969                                 tmp = 20000;
2970                                 while (tmp--) {
2971                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
2972                                              channel_complete_mask) ==
2973                                             channel_complete_mask)
2974                                                 break;
2975                                 }
2976                         } else {
2977                                 uint32_t or_mask = RBIOS16(offset);
2978                                 offset += 2;
2979
2980                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2981                                 tmp &= RADEON_SDRAM_MODE_MASK;
2982                                 tmp |= or_mask;
2983                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2984
2985                                 or_mask = val << 24;
2986                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2987                                 tmp &= RADEON_B3MEM_RESET_MASK;
2988                                 tmp |= or_mask;
2989                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2990                         }
2991                         val = RBIOS8(offset);
2992                 }
2993         }
2994 }
2995
2996 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2997                                    int mem_addr_mapping)
2998 {
2999         struct radeon_device *rdev = dev->dev_private;
3000         uint32_t mem_cntl;
3001         uint32_t mem_size;
3002         uint32_t addr = 0;
3003
3004         mem_cntl = RREG32(RADEON_MEM_CNTL);
3005         if (mem_cntl & RV100_HALF_MODE)
3006                 ram /= 2;
3007         mem_size = ram;
3008         mem_cntl &= ~(0xff << 8);
3009         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3010         WREG32(RADEON_MEM_CNTL, mem_cntl);
3011         RREG32(RADEON_MEM_CNTL);
3012
3013         /* sdram reset ? */
3014
3015         /* something like this????  */
3016         while (ram--) {
3017                 addr = ram * 1024 * 1024;
3018                 /* write to each page */
3019                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3020                 WREG32(RADEON_MM_DATA, 0xdeadbeef);
3021                 /* read back and verify */
3022                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3023                 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
3024                         return 0;
3025         }
3026
3027         return mem_size;
3028 }
3029
3030 static void combios_write_ram_size(struct drm_device *dev)
3031 {
3032         struct radeon_device *rdev = dev->dev_private;
3033         uint8_t rev;
3034         uint16_t offset;
3035         uint32_t mem_size = 0;
3036         uint32_t mem_cntl = 0;
3037
3038         /* should do something smarter here I guess... */
3039         if (rdev->flags & RADEON_IS_IGP)
3040                 return;
3041
3042         /* first check detected mem table */
3043         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3044         if (offset) {
3045                 rev = RBIOS8(offset);
3046                 if (rev < 3) {
3047                         mem_cntl = RBIOS32(offset + 1);
3048                         mem_size = RBIOS16(offset + 5);
3049                         if ((rdev->family < CHIP_R200) &&
3050                             !ASIC_IS_RN50(rdev))
3051                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
3052                 }
3053         }
3054
3055         if (!mem_size) {
3056                 offset =
3057                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3058                 if (offset) {
3059                         rev = RBIOS8(offset - 1);
3060                         if (rev < 1) {
3061                                 if ((rdev->family < CHIP_R200)
3062                                     && !ASIC_IS_RN50(rdev)) {
3063                                         int ram = 0;
3064                                         int mem_addr_mapping = 0;
3065
3066                                         while (RBIOS8(offset)) {
3067                                                 ram = RBIOS8(offset);
3068                                                 mem_addr_mapping =
3069                                                     RBIOS8(offset + 1);
3070                                                 if (mem_addr_mapping != 0x25)
3071                                                         ram *= 2;
3072                                                 mem_size =
3073                                                     combios_detect_ram(dev, ram,
3074                                                                        mem_addr_mapping);
3075                                                 if (mem_size)
3076                                                         break;
3077                                                 offset += 2;
3078                                         }
3079                                 } else
3080                                         mem_size = RBIOS8(offset);
3081                         } else {
3082                                 mem_size = RBIOS8(offset);
3083                                 mem_size *= 2;  /* convert to MB */
3084                         }
3085                 }
3086         }
3087
3088         mem_size *= (1024 * 1024);      /* convert to bytes */
3089         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3090 }
3091
3092 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
3093 {
3094         uint16_t dyn_clk_info =
3095             combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3096
3097         if (dyn_clk_info)
3098                 combios_parse_pll_table(dev, dyn_clk_info);
3099 }
3100
3101 void radeon_combios_asic_init(struct drm_device *dev)
3102 {
3103         struct radeon_device *rdev = dev->dev_private;
3104         uint16_t table;
3105
3106         /* port hardcoded mac stuff from radeonfb */
3107         if (rdev->bios == NULL)
3108                 return;
3109
3110         /* ASIC INIT 1 */
3111         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3112         if (table)
3113                 combios_parse_mmio_table(dev, table);
3114
3115         /* PLL INIT */
3116         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3117         if (table)
3118                 combios_parse_pll_table(dev, table);
3119
3120         /* ASIC INIT 2 */
3121         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3122         if (table)
3123                 combios_parse_mmio_table(dev, table);
3124
3125         if (!(rdev->flags & RADEON_IS_IGP)) {
3126                 /* ASIC INIT 4 */
3127                 table =
3128                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3129                 if (table)
3130                         combios_parse_mmio_table(dev, table);
3131
3132                 /* RAM RESET */
3133                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3134                 if (table)
3135                         combios_parse_ram_reset_table(dev, table);
3136
3137                 /* ASIC INIT 3 */
3138                 table =
3139                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3140                 if (table)
3141                         combios_parse_mmio_table(dev, table);
3142
3143                 /* write CONFIG_MEMSIZE */
3144                 combios_write_ram_size(dev);
3145         }
3146
3147         /* quirk for rs4xx HP nx6125 laptop to make it resume
3148          * - it hangs on resume inside the dynclk 1 table.
3149          */
3150         if (rdev->family == CHIP_RS480 &&
3151             rdev->pdev->subsystem_vendor == 0x103c &&
3152             rdev->pdev->subsystem_device == 0x308b)
3153                 return;
3154
3155         /* quirk for rs4xx HP dv5000 laptop to make it resume
3156          * - it hangs on resume inside the dynclk 1 table.
3157          */
3158         if (rdev->family == CHIP_RS480 &&
3159             rdev->pdev->subsystem_vendor == 0x103c &&
3160             rdev->pdev->subsystem_device == 0x30a4)
3161                 return;
3162
3163         /* DYN CLK 1 */
3164         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3165         if (table)
3166                 combios_parse_pll_table(dev, table);
3167
3168 }
3169
3170 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3171 {
3172         struct radeon_device *rdev = dev->dev_private;
3173         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3174
3175         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3176         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3177         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3178
3179         /* let the bios control the backlight */
3180         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3181
3182         /* tell the bios not to handle mode switching */
3183         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3184                            RADEON_ACC_MODE_CHANGE);
3185
3186         /* tell the bios a driver is loaded */
3187         bios_7_scratch |= RADEON_DRV_LOADED;
3188
3189         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3190         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3191         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3192 }
3193
3194 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3195 {
3196         struct drm_device *dev = encoder->dev;
3197         struct radeon_device *rdev = dev->dev_private;
3198         uint32_t bios_6_scratch;
3199
3200         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3201
3202         if (lock)
3203                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3204         else
3205                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3206
3207         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3208 }
3209
3210 void
3211 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3212                                       struct drm_encoder *encoder,
3213                                       bool connected)
3214 {
3215         struct drm_device *dev = connector->dev;
3216         struct radeon_device *rdev = dev->dev_private;
3217         struct radeon_connector *radeon_connector =
3218             to_radeon_connector(connector);
3219         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3220         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3221         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3222
3223         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3224             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3225                 if (connected) {
3226                         DRM_DEBUG_KMS("TV1 connected\n");
3227                         /* fix me */
3228                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3229                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3230                         bios_5_scratch |= RADEON_TV1_ON;
3231                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
3232                 } else {
3233                         DRM_DEBUG_KMS("TV1 disconnected\n");
3234                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3235                         bios_5_scratch &= ~RADEON_TV1_ON;
3236                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3237                 }
3238         }
3239         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3240             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3241                 if (connected) {
3242                         DRM_DEBUG_KMS("LCD1 connected\n");
3243                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
3244                         bios_5_scratch |= RADEON_LCD1_ON;
3245                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3246                 } else {
3247                         DRM_DEBUG_KMS("LCD1 disconnected\n");
3248                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3249                         bios_5_scratch &= ~RADEON_LCD1_ON;
3250                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3251                 }
3252         }
3253         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3254             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3255                 if (connected) {
3256                         DRM_DEBUG_KMS("CRT1 connected\n");
3257                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3258                         bios_5_scratch |= RADEON_CRT1_ON;
3259                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3260                 } else {
3261                         DRM_DEBUG_KMS("CRT1 disconnected\n");
3262                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3263                         bios_5_scratch &= ~RADEON_CRT1_ON;
3264                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3265                 }
3266         }
3267         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3268             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3269                 if (connected) {
3270                         DRM_DEBUG_KMS("CRT2 connected\n");
3271                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3272                         bios_5_scratch |= RADEON_CRT2_ON;
3273                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3274                 } else {
3275                         DRM_DEBUG_KMS("CRT2 disconnected\n");
3276                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3277                         bios_5_scratch &= ~RADEON_CRT2_ON;
3278                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3279                 }
3280         }
3281         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3282             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3283                 if (connected) {
3284                         DRM_DEBUG_KMS("DFP1 connected\n");
3285                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
3286                         bios_5_scratch |= RADEON_DFP1_ON;
3287                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3288                 } else {
3289                         DRM_DEBUG_KMS("DFP1 disconnected\n");
3290                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3291                         bios_5_scratch &= ~RADEON_DFP1_ON;
3292                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3293                 }
3294         }
3295         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3296             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3297                 if (connected) {
3298                         DRM_DEBUG_KMS("DFP2 connected\n");
3299                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
3300                         bios_5_scratch |= RADEON_DFP2_ON;
3301                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3302                 } else {
3303                         DRM_DEBUG_KMS("DFP2 disconnected\n");
3304                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3305                         bios_5_scratch &= ~RADEON_DFP2_ON;
3306                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3307                 }
3308         }
3309         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3310         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3311 }
3312
3313 void
3314 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3315 {
3316         struct drm_device *dev = encoder->dev;
3317         struct radeon_device *rdev = dev->dev_private;
3318         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3319         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3320
3321         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3322                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3323                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3324         }
3325         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3326                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3327                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3328         }
3329         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3330                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3331                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3332         }
3333         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3334                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3335                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3336         }
3337         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3338                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3339                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3340         }
3341         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3342                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3343                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3344         }
3345         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3346 }
3347
3348 void
3349 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3350 {
3351         struct drm_device *dev = encoder->dev;
3352         struct radeon_device *rdev = dev->dev_private;
3353         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3354         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3355
3356         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3357                 if (on)
3358                         bios_6_scratch |= RADEON_TV_DPMS_ON;
3359                 else
3360                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3361         }
3362         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3363                 if (on)
3364                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
3365                 else
3366                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3367         }
3368         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3369                 if (on)
3370                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
3371                 else
3372                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3373         }
3374         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3375                 if (on)
3376                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
3377                 else
3378                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3379         }
3380         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3381 }