drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif /* CONFIG_PPC_PMAC */
  39
  40 /* from radeon_encoder.c */
  41 extern uint32_t
  42 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  43                         uint8_t dac);
  44 extern void radeon_link_encoder_connector(struct drm_device *dev);
  45
  46 /* from radeon_connector.c */
  47 extern void
  48 radeon_add_legacy_connector(struct drm_device *dev,
  49                             uint32_t connector_id,
  50                             uint32_t supported_device,
  51                             int connector_type,
  52                             struct radeon_i2c_bus_rec *i2c_bus,
  53                             uint16_t connector_object_id,
  54                             struct radeon_hpd *hpd);
  55
  56 /* from radeon_legacy_encoder.c */
  57 extern void
  58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  59                           uint32_t supported_device);
  60
  61 /* old legacy ATI BIOS routines */
  62
  63 /* COMBIOS table offsets */
  64 enum radeon_combios_table_offset {
  65         /* absolute offset tables */
  66         COMBIOS_ASIC_INIT_1_TABLE,
  67         COMBIOS_BIOS_SUPPORT_TABLE,
  68         COMBIOS_DAC_PROGRAMMING_TABLE,
  69         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  70         COMBIOS_CRTC_INFO_TABLE,
  71         COMBIOS_PLL_INFO_TABLE,
  72         COMBIOS_TV_INFO_TABLE,
  73         COMBIOS_DFP_INFO_TABLE,
  74         COMBIOS_HW_CONFIG_INFO_TABLE,
  75         COMBIOS_MULTIMEDIA_INFO_TABLE,
  76         COMBIOS_TV_STD_PATCH_TABLE,
  77         COMBIOS_LCD_INFO_TABLE,
  78         COMBIOS_MOBILE_INFO_TABLE,
  79         COMBIOS_PLL_INIT_TABLE,
  80         COMBIOS_MEM_CONFIG_TABLE,
  81         COMBIOS_SAVE_MASK_TABLE,
  82         COMBIOS_HARDCODED_EDID_TABLE,
  83         COMBIOS_ASIC_INIT_2_TABLE,
  84         COMBIOS_CONNECTOR_INFO_TABLE,
  85         COMBIOS_DYN_CLK_1_TABLE,
  86         COMBIOS_RESERVED_MEM_TABLE,
  87         COMBIOS_EXT_TMDS_INFO_TABLE,
  88         COMBIOS_MEM_CLK_INFO_TABLE,
  89         COMBIOS_EXT_DAC_INFO_TABLE,
  90         COMBIOS_MISC_INFO_TABLE,
  91         COMBIOS_CRT_INFO_TABLE,
  92         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  93         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  94         COMBIOS_FAN_SPEED_INFO_TABLE,
  95         COMBIOS_OVERDRIVE_INFO_TABLE,
  96         COMBIOS_OEM_INFO_TABLE,
  97         COMBIOS_DYN_CLK_2_TABLE,
  98         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  99         COMBIOS_I2C_INFO_TABLE,
 100         /* relative offset tables */
 101         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
 102         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
 103         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
 104         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
 105         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
 106         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
 107         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
 108         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
 109         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
 110         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
 111         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
 112 };
 113
 114 enum radeon_combios_ddc {
 115         DDC_NONE_DETECTED,
 116         DDC_MONID,
 117         DDC_DVI,
 118         DDC_VGA,
 119         DDC_CRT2,
 120         DDC_LCD,
 121         DDC_GPIO,
 122 };
 123
 124 enum radeon_combios_connector {
 125         CONNECTOR_NONE_LEGACY,
 126         CONNECTOR_PROPRIETARY_LEGACY,
 127         CONNECTOR_CRT_LEGACY,
 128         CONNECTOR_DVI_I_LEGACY,
 129         CONNECTOR_DVI_D_LEGACY,
 130         CONNECTOR_CTV_LEGACY,
 131         CONNECTOR_STV_LEGACY,
 132         CONNECTOR_UNSUPPORTED_LEGACY
 133 };
 134
 135 const int legacy_connector_convert[] = {
 136         DRM_MODE_CONNECTOR_Unknown,
 137         DRM_MODE_CONNECTOR_DVID,
 138         DRM_MODE_CONNECTOR_VGA,
 139         DRM_MODE_CONNECTOR_DVII,
 140         DRM_MODE_CONNECTOR_DVID,
 141         DRM_MODE_CONNECTOR_Composite,
 142         DRM_MODE_CONNECTOR_SVIDEO,
 143         DRM_MODE_CONNECTOR_Unknown,
 144 };
 145
 146 static uint16_t combios_get_table_offset(struct drm_device *dev,
 147                                          enum radeon_combios_table_offset table)
 148 {
 149         struct radeon_device *rdev = dev->dev_private;
 150         int rev, size;
 151         uint16_t offset = 0, check_offset;
 152
 153         if (!rdev->bios)
 154                 return 0;
 155
 156         switch (table) {
 157                 /* absolute offset tables */
 158         case COMBIOS_ASIC_INIT_1_TABLE:
 159                 check_offset = 0xc;
 160                 break;
 161         case COMBIOS_BIOS_SUPPORT_TABLE:
 162                 check_offset = 0x14;
 163                 break;
 164         case COMBIOS_DAC_PROGRAMMING_TABLE:
 165                 check_offset = 0x2a;
 166                 break;
 167         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 168                 check_offset = 0x2c;
 169                 break;
 170         case COMBIOS_CRTC_INFO_TABLE:
 171                 check_offset = 0x2e;
 172                 break;
 173         case COMBIOS_PLL_INFO_TABLE:
 174                 check_offset = 0x30;
 175                 break;
 176         case COMBIOS_TV_INFO_TABLE:
 177                 check_offset = 0x32;
 178                 break;
 179         case COMBIOS_DFP_INFO_TABLE:
 180                 check_offset = 0x34;
 181                 break;
 182         case COMBIOS_HW_CONFIG_INFO_TABLE:
 183                 check_offset = 0x36;
 184                 break;
 185         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 186                 check_offset = 0x38;
 187                 break;
 188         case COMBIOS_TV_STD_PATCH_TABLE:
 189                 check_offset = 0x3e;
 190                 break;
 191         case COMBIOS_LCD_INFO_TABLE:
 192                 check_offset = 0x40;
 193                 break;
 194         case COMBIOS_MOBILE_INFO_TABLE:
 195                 check_offset = 0x42;
 196                 break;
 197         case COMBIOS_PLL_INIT_TABLE:
 198                 check_offset = 0x46;
 199                 break;
 200         case COMBIOS_MEM_CONFIG_TABLE:
 201                 check_offset = 0x48;
 202                 break;
 203         case COMBIOS_SAVE_MASK_TABLE:
 204                 check_offset = 0x4a;
 205                 break;
 206         case COMBIOS_HARDCODED_EDID_TABLE:
 207                 check_offset = 0x4c;
 208                 break;
 209         case COMBIOS_ASIC_INIT_2_TABLE:
 210                 check_offset = 0x4e;
 211                 break;
 212         case COMBIOS_CONNECTOR_INFO_TABLE:
 213                 check_offset = 0x50;
 214                 break;
 215         case COMBIOS_DYN_CLK_1_TABLE:
 216                 check_offset = 0x52;
 217                 break;
 218         case COMBIOS_RESERVED_MEM_TABLE:
 219                 check_offset = 0x54;
 220                 break;
 221         case COMBIOS_EXT_TMDS_INFO_TABLE:
 222                 check_offset = 0x58;
 223                 break;
 224         case COMBIOS_MEM_CLK_INFO_TABLE:
 225                 check_offset = 0x5a;
 226                 break;
 227         case COMBIOS_EXT_DAC_INFO_TABLE:
 228                 check_offset = 0x5c;
 229                 break;
 230         case COMBIOS_MISC_INFO_TABLE:
 231                 check_offset = 0x5e;
 232                 break;
 233         case COMBIOS_CRT_INFO_TABLE:
 234                 check_offset = 0x60;
 235                 break;
 236         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 237                 check_offset = 0x62;
 238                 break;
 239         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 240                 check_offset = 0x64;
 241                 break;
 242         case COMBIOS_FAN_SPEED_INFO_TABLE:
 243                 check_offset = 0x66;
 244                 break;
 245         case COMBIOS_OVERDRIVE_INFO_TABLE:
 246                 check_offset = 0x68;
 247                 break;
 248         case COMBIOS_OEM_INFO_TABLE:
 249                 check_offset = 0x6a;
 250                 break;
 251         case COMBIOS_DYN_CLK_2_TABLE:
 252                 check_offset = 0x6c;
 253                 break;
 254         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 255                 check_offset = 0x6e;
 256                 break;
 257         case COMBIOS_I2C_INFO_TABLE:
 258                 check_offset = 0x70;
 259                 break;
 260                 /* relative offset tables */
 261         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 262                 check_offset =
 263                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 264                 if (check_offset) {
 265                         rev = RBIOS8(check_offset);
 266                         if (rev > 0) {
 267                                 check_offset = RBIOS16(check_offset + 0x3);
 268                                 if (check_offset)
 269                                         offset = check_offset;
 270                         }
 271                 }
 272                 break;
 273         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 274                 check_offset =
 275                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 276                 if (check_offset) {
 277                         rev = RBIOS8(check_offset);
 278                         if (rev > 0) {
 279                                 check_offset = RBIOS16(check_offset + 0x5);
 280                                 if (check_offset)
 281                                         offset = check_offset;
 282                         }
 283                 }
 284                 break;
 285         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 286                 check_offset =
 287                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 288                 if (check_offset) {
 289                         rev = RBIOS8(check_offset);
 290                         if (rev > 0) {
 291                                 check_offset = RBIOS16(check_offset + 0x7);
 292                                 if (check_offset)
 293                                         offset = check_offset;
 294                         }
 295                 }
 296                 break;
 297         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 298                 check_offset =
 299                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 300                 if (check_offset) {
 301                         rev = RBIOS8(check_offset);
 302                         if (rev == 2) {
 303                                 check_offset = RBIOS16(check_offset + 0x9);
 304                                 if (check_offset)
 305                                         offset = check_offset;
 306                         }
 307                 }
 308                 break;
 309         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 310                 check_offset =
 311                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 312                 if (check_offset) {
 313                         while (RBIOS8(check_offset++));
 314                         check_offset += 2;
 315                         if (check_offset)
 316                                 offset = check_offset;
 317                 }
 318                 break;
 319         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 320                 check_offset =
 321                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 322                 if (check_offset) {
 323                         check_offset = RBIOS16(check_offset + 0x11);
 324                         if (check_offset)
 325                                 offset = check_offset;
 326                 }
 327                 break;
 328         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 329                 check_offset =
 330                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 331                 if (check_offset) {
 332                         check_offset = RBIOS16(check_offset + 0x13);
 333                         if (check_offset)
 334                                 offset = check_offset;
 335                 }
 336                 break;
 337         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 338                 check_offset =
 339                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 340                 if (check_offset) {
 341                         check_offset = RBIOS16(check_offset + 0x15);
 342                         if (check_offset)
 343                                 offset = check_offset;
 344                 }
 345                 break;
 346         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 347                 check_offset =
 348                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 349                 if (check_offset) {
 350                         check_offset = RBIOS16(check_offset + 0x17);
 351                         if (check_offset)
 352                                 offset = check_offset;
 353                 }
 354                 break;
 355         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 356                 check_offset =
 357                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 358                 if (check_offset) {
 359                         check_offset = RBIOS16(check_offset + 0x2);
 360                         if (check_offset)
 361                                 offset = check_offset;
 362                 }
 363                 break;
 364         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 365                 check_offset =
 366                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 367                 if (check_offset) {
 368                         check_offset = RBIOS16(check_offset + 0x4);
 369                         if (check_offset)
 370                                 offset = check_offset;
 371                 }
 372                 break;
 373         default:
 374                 check_offset = 0;
 375                 break;
 376         }
 377
 378         size = RBIOS8(rdev->bios_header_start + 0x6);
 379         /* check absolute offset tables */
 380         if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)
 381                 offset = RBIOS16(rdev->bios_header_start + check_offset);
 382
 383         return offset;
 384 }
 385
 386 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
 387 {
 388         int edid_info, size;
 389         struct edid *edid;
 390         unsigned char *raw;
 391         edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
 392         if (!edid_info)
 393                 return false;
 394
 395         raw = rdev->bios + edid_info;
 396         size = EDID_LENGTH * (raw[0x7e] + 1);
 397         edid = kmalloc(size, GFP_KERNEL);
 398         if (edid == NULL)
 399                 return false;
 400
 401         memcpy((unsigned char *)edid, raw, size);
 402
 403         if (!drm_edid_is_valid(edid)) {
 404                 kfree(edid);
 405                 return false;
 406         }
 407
 408         rdev->mode_info.bios_hardcoded_edid = edid;
 409         rdev->mode_info.bios_hardcoded_edid_size = size;
 410         return true;
 411 }
 412
 413 /* this is used for atom LCDs as well */
 414 struct edid *
 415 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
 416 {
 417         struct edid *edid;
 418
 419         if (rdev->mode_info.bios_hardcoded_edid) {
 420                 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 421                 if (edid) {
 422                         memcpy((unsigned char *)edid,
 423                                (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
 424                                rdev->mode_info.bios_hardcoded_edid_size);
 425                         return edid;
 426                 }
 427         }
 428         return NULL;
 429 }
 430
 431 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
 432                                                        enum radeon_combios_ddc ddc,
 433                                                        u32 clk_mask,
 434                                                        u32 data_mask)
 435 {
 436         struct radeon_i2c_bus_rec i2c;
 437         int ddc_line = 0;
 438
 439         /* ddc id            = mask reg
 440          * DDC_NONE_DETECTED = none
 441          * DDC_DVI           = RADEON_GPIO_DVI_DDC
 442          * DDC_VGA           = RADEON_GPIO_VGA_DDC
 443          * DDC_LCD           = RADEON_GPIOPAD_MASK
 444          * DDC_GPIO          = RADEON_MDGPIO_MASK
 445          * r1xx
 446          * DDC_MONID         = RADEON_GPIO_MONID
 447          * DDC_CRT2          = RADEON_GPIO_CRT2_DDC
 448          * r200
 449          * DDC_MONID         = RADEON_GPIO_MONID
 450          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 451          * r300/r350
 452          * DDC_MONID         = RADEON_GPIO_DVI_DDC
 453          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 454          * rv2xx/rv3xx
 455          * DDC_MONID         = RADEON_GPIO_MONID
 456          * DDC_CRT2          = RADEON_GPIO_MONID
 457          * rs3xx/rs4xx
 458          * DDC_MONID         = RADEON_GPIOPAD_MASK
 459          * DDC_CRT2          = RADEON_GPIO_MONID
 460          */
 461         switch (ddc) {
 462         case DDC_NONE_DETECTED:
 463         default:
 464                 ddc_line = 0;
 465                 break;
 466         case DDC_DVI:
 467                 ddc_line = RADEON_GPIO_DVI_DDC;
 468                 break;
 469         case DDC_VGA:
 470                 ddc_line = RADEON_GPIO_VGA_DDC;
 471                 break;
 472         case DDC_LCD:
 473                 ddc_line = RADEON_GPIOPAD_MASK;
 474                 break;
 475         case DDC_GPIO:
 476                 ddc_line = RADEON_MDGPIO_MASK;
 477                 break;
 478         case DDC_MONID:
 479                 if (rdev->family == CHIP_RS300 ||
 480                     rdev->family == CHIP_RS400 ||
 481                     rdev->family == CHIP_RS480)
 482                         ddc_line = RADEON_GPIOPAD_MASK;
 483                 else if (rdev->family == CHIP_R300 ||
 484                          rdev->family == CHIP_R350) {
 485                         ddc_line = RADEON_GPIO_DVI_DDC;
 486                         ddc = DDC_DVI;
 487                 } else
 488                         ddc_line = RADEON_GPIO_MONID;
 489                 break;
 490         case DDC_CRT2:
 491                 if (rdev->family == CHIP_R200 ||
 492                     rdev->family == CHIP_R300 ||
 493                     rdev->family == CHIP_R350) {
 494                         ddc_line = RADEON_GPIO_DVI_DDC;
 495                         ddc = DDC_DVI;
 496                 } else if (rdev->family == CHIP_RS300 ||
 497                            rdev->family == CHIP_RS400 ||
 498                            rdev->family == CHIP_RS480)
 499                         ddc_line = RADEON_GPIO_MONID;
 500                 else if (rdev->family >= CHIP_RV350) {
 501                         ddc_line = RADEON_GPIO_MONID;
 502                         ddc = DDC_MONID;
 503                 } else
 504                         ddc_line = RADEON_GPIO_CRT2_DDC;
 505                 break;
 506         }
 507
 508         if (ddc_line == RADEON_GPIOPAD_MASK) {
 509                 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 510                 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 511                 i2c.a_clk_reg = RADEON_GPIOPAD_A;
 512                 i2c.a_data_reg = RADEON_GPIOPAD_A;
 513                 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
 514                 i2c.en_data_reg = RADEON_GPIOPAD_EN;
 515                 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
 516                 i2c.y_data_reg = RADEON_GPIOPAD_Y;
 517         } else if (ddc_line == RADEON_MDGPIO_MASK) {
 518                 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
 519                 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
 520                 i2c.a_clk_reg = RADEON_MDGPIO_A;
 521                 i2c.a_data_reg = RADEON_MDGPIO_A;
 522                 i2c.en_clk_reg = RADEON_MDGPIO_EN;
 523                 i2c.en_data_reg = RADEON_MDGPIO_EN;
 524                 i2c.y_clk_reg = RADEON_MDGPIO_Y;
 525                 i2c.y_data_reg = RADEON_MDGPIO_Y;
 526         } else {
 527                 i2c.mask_clk_reg = ddc_line;
 528                 i2c.mask_data_reg = ddc_line;
 529                 i2c.a_clk_reg = ddc_line;
 530                 i2c.a_data_reg = ddc_line;
 531                 i2c.en_clk_reg = ddc_line;
 532                 i2c.en_data_reg = ddc_line;
 533                 i2c.y_clk_reg = ddc_line;
 534                 i2c.y_data_reg = ddc_line;
 535         }
 536
 537         if (clk_mask && data_mask) {
 538                 /* system specific masks */
 539                 i2c.mask_clk_mask = clk_mask;
 540                 i2c.mask_data_mask = data_mask;
 541                 i2c.a_clk_mask = clk_mask;
 542                 i2c.a_data_mask = data_mask;
 543                 i2c.en_clk_mask = clk_mask;
 544                 i2c.en_data_mask = data_mask;
 545                 i2c.y_clk_mask = clk_mask;
 546                 i2c.y_data_mask = data_mask;
 547         } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
 548                    (ddc_line == RADEON_MDGPIO_MASK)) {
 549                 /* default gpiopad masks */
 550                 i2c.mask_clk_mask = (0x20 << 8);
 551                 i2c.mask_data_mask = 0x80;
 552                 i2c.a_clk_mask = (0x20 << 8);
 553                 i2c.a_data_mask = 0x80;
 554                 i2c.en_clk_mask = (0x20 << 8);
 555                 i2c.en_data_mask = 0x80;
 556                 i2c.y_clk_mask = (0x20 << 8);
 557                 i2c.y_data_mask = 0x80;
 558         } else {
 559                 /* default masks for ddc pads */
 560                 i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
 561                 i2c.mask_data_mask = RADEON_GPIO_MASK_0;
 562                 i2c.a_clk_mask = RADEON_GPIO_A_1;
 563                 i2c.a_data_mask = RADEON_GPIO_A_0;
 564                 i2c.en_clk_mask = RADEON_GPIO_EN_1;
 565                 i2c.en_data_mask = RADEON_GPIO_EN_0;
 566                 i2c.y_clk_mask = RADEON_GPIO_Y_1;
 567                 i2c.y_data_mask = RADEON_GPIO_Y_0;
 568         }
 569
 570         switch (rdev->family) {
 571         case CHIP_R100:
 572         case CHIP_RV100:
 573         case CHIP_RS100:
 574         case CHIP_RV200:
 575         case CHIP_RS200:
 576         case CHIP_RS300:
 577                 switch (ddc_line) {
 578                 case RADEON_GPIO_DVI_DDC:
 579                         i2c.hw_capable = true;
 580                         break;
 581                 default:
 582                         i2c.hw_capable = false;
 583                         break;
 584                 }
 585                 break;
 586         case CHIP_R200:
 587                 switch (ddc_line) {
 588                 case RADEON_GPIO_DVI_DDC:
 589                 case RADEON_GPIO_MONID:
 590                         i2c.hw_capable = true;
 591                         break;
 592                 default:
 593                         i2c.hw_capable = false;
 594                         break;
 595                 }
 596                 break;
 597         case CHIP_RV250:
 598         case CHIP_RV280:
 599                 switch (ddc_line) {
 600                 case RADEON_GPIO_VGA_DDC:
 601                 case RADEON_GPIO_DVI_DDC:
 602                 case RADEON_GPIO_CRT2_DDC:
 603                         i2c.hw_capable = true;
 604                         break;
 605                 default:
 606                         i2c.hw_capable = false;
 607                         break;
 608                 }
 609                 break;
 610         case CHIP_R300:
 611         case CHIP_R350:
 612                 switch (ddc_line) {
 613                 case RADEON_GPIO_VGA_DDC:
 614                 case RADEON_GPIO_DVI_DDC:
 615                         i2c.hw_capable = true;
 616                         break;
 617                 default:
 618                         i2c.hw_capable = false;
 619                         break;
 620                 }
 621                 break;
 622         case CHIP_RV350:
 623         case CHIP_RV380:
 624         case CHIP_RS400:
 625         case CHIP_RS480:
 626                 switch (ddc_line) {
 627                 case RADEON_GPIO_VGA_DDC:
 628                 case RADEON_GPIO_DVI_DDC:
 629                         i2c.hw_capable = true;
 630                         break;
 631                 case RADEON_GPIO_MONID:
 632                         /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
 633                          * reliably on some pre-r4xx hardware; not sure why.
 634                          */
 635                         i2c.hw_capable = false;
 636                         break;
 637                 default:
 638                         i2c.hw_capable = false;
 639                         break;
 640                 }
 641                 break;
 642         default:
 643                 i2c.hw_capable = false;
 644                 break;
 645         }
 646         i2c.mm_i2c = false;
 647
 648         i2c.i2c_id = ddc;
 649         i2c.hpd = RADEON_HPD_NONE;
 650
 651         if (ddc_line)
 652                 i2c.valid = true;
 653         else
 654                 i2c.valid = false;
 655
 656         return i2c;
 657 }
 658
 659 void radeon_combios_i2c_init(struct radeon_device *rdev)
 660 {
 661         struct drm_device *dev = rdev->ddev;
 662         struct radeon_i2c_bus_rec i2c;
 663
 664         /* actual hw pads
 665          * r1xx/rs2xx/rs3xx
 666          * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
 667          * r200
 668          * 0x60, 0x64, 0x68, mm
 669          * r300/r350
 670          * 0x60, 0x64, mm
 671          * rv2xx/rv3xx/rs4xx
 672          * 0x60, 0x64, 0x68, gpiopads, mm
 673          */
 674
 675         /* 0x60 */
 676         i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
 677         rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
 678         /* 0x64 */
 679         i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
 680         rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
 681
 682         /* mm i2c */
 683         i2c.valid = true;
 684         i2c.hw_capable = true;
 685         i2c.mm_i2c = true;
 686         i2c.i2c_id = 0xa0;
 687         rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
 688
 689         if (rdev->family == CHIP_R300 ||
 690             rdev->family == CHIP_R350) {
 691                 /* only 2 sw i2c pads */
 692         } else if (rdev->family == CHIP_RS300 ||
 693                    rdev->family == CHIP_RS400 ||
 694                    rdev->family == CHIP_RS480) {
 695                 u16 offset;
 696                 u8 id, blocks, clk, data;
 697                 int i;
 698
 699                 /* 0x68 */
 700                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 701                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 702
 703                 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
 704                 if (offset) {
 705                         blocks = RBIOS8(offset + 2);
 706                         for (i = 0; i < blocks; i++) {
 707                                 id = RBIOS8(offset + 3 + (i * 5) + 0);
 708                                 if (id == 136) {
 709                                         clk = RBIOS8(offset + 3 + (i * 5) + 3);
 710                                         data = RBIOS8(offset + 3 + (i * 5) + 4);
 711                                         /* gpiopad */
 712                                         i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
 713                                                                     (1 << clk), (1 << data));
 714                                         rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
 715                                         break;
 716                                 }
 717                         }
 718                 }
 719         } else if ((rdev->family == CHIP_R200) ||
 720                    (rdev->family >= CHIP_R300)) {
 721                 /* 0x68 */
 722                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 723                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 724         } else {
 725                 /* 0x68 */
 726                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 727                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 728                 /* 0x6c */
 729                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 730                 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
 731         }
 732 }
 733
 734 bool radeon_combios_get_clock_info(struct drm_device *dev)
 735 {
 736         struct radeon_device *rdev = dev->dev_private;
 737         uint16_t pll_info;
 738         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 739         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 740         struct radeon_pll *spll = &rdev->clock.spll;
 741         struct radeon_pll *mpll = &rdev->clock.mpll;
 742         int8_t rev;
 743         uint16_t sclk, mclk;
 744
 745         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 746         if (pll_info) {
 747                 rev = RBIOS8(pll_info);
 748
 749                 /* pixel clocks */
 750                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 751                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 752                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 753                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 754                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 755                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 756
 757                 if (rev > 9) {
 758                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 759                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 760                 } else {
 761                         p1pll->pll_in_min = 40;
 762                         p1pll->pll_in_max = 500;
 763                 }
 764                 *p2pll = *p1pll;
 765
 766                 /* system clock */
 767                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 768                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 769                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 770                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 771
 772                 if (rev > 10) {
 773                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 774                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 775                 } else {
 776                         /* ??? */
 777                         spll->pll_in_min = 40;
 778                         spll->pll_in_max = 500;
 779                 }
 780
 781                 /* memory clock */
 782                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 783                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 784                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 785                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 786
 787                 if (rev > 10) {
 788                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 789                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 790                 } else {
 791                         /* ??? */
 792                         mpll->pll_in_min = 40;
 793                         mpll->pll_in_max = 500;
 794                 }
 795
 796                 /* default sclk/mclk */
 797                 sclk = RBIOS16(pll_info + 0xa);
 798                 mclk = RBIOS16(pll_info + 0x8);
 799                 if (sclk == 0)
 800                         sclk = 200 * 100;
 801                 if (mclk == 0)
 802                         mclk = 200 * 100;
 803
 804                 rdev->clock.default_sclk = sclk;
 805                 rdev->clock.default_mclk = mclk;
 806
 807                 if (RBIOS32(pll_info + 0x16))
 808                         rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
 809                 else
 810                         rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
 811
 812                 return true;
 813         }
 814         return false;
 815 }
 816
 817 bool radeon_combios_sideport_present(struct radeon_device *rdev)
 818 {
 819         struct drm_device *dev = rdev->ddev;
 820         u16 igp_info;
 821
 822         /* sideport is AMD only */
 823         if (rdev->family == CHIP_RS400)
 824                 return false;
 825
 826         igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
 827
 828         if (igp_info) {
 829                 if (RBIOS16(igp_info + 0x4))
 830                         return true;
 831         }
 832         return false;
 833 }
 834
 835 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
 836         0x00000808,             /* r100  */
 837         0x00000808,             /* rv100 */
 838         0x00000808,             /* rs100 */
 839         0x00000808,             /* rv200 */
 840         0x00000808,             /* rs200 */
 841         0x00000808,             /* r200  */
 842         0x00000808,             /* rv250 */
 843         0x00000000,             /* rs300 */
 844         0x00000808,             /* rv280 */
 845         0x00000808,             /* r300  */
 846         0x00000808,             /* r350  */
 847         0x00000808,             /* rv350 */
 848         0x00000808,             /* rv380 */
 849         0x00000808,             /* r420  */
 850         0x00000808,             /* r423  */
 851         0x00000808,             /* rv410 */
 852         0x00000000,             /* rs400 */
 853         0x00000000,             /* rs480 */
 854 };
 855
 856 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
 857                                                           struct radeon_encoder_primary_dac *p_dac)
 858 {
 859         p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
 860         return;
 861 }
 862
 863 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 864                                                                        radeon_encoder
 865                                                                        *encoder)
 866 {
 867         struct drm_device *dev = encoder->base.dev;
 868         struct radeon_device *rdev = dev->dev_private;
 869         uint16_t dac_info;
 870         uint8_t rev, bg, dac;
 871         struct radeon_encoder_primary_dac *p_dac = NULL;
 872         int found = 0;
 873
 874         p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
 875                         GFP_KERNEL);
 876
 877         if (!p_dac)
 878                 return NULL;
 879
 880         /* check CRT table */
 881         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 882         if (dac_info) {
 883                 rev = RBIOS8(dac_info) & 0x3;
 884                 if (rev < 2) {
 885                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 886                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 887                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 888                 } else {
 889                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 890                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 891                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 892                 }
 893                 /* if the values are zeros, use the table */
 894                 if ((dac == 0) || (bg == 0))
 895                         found = 0;
 896                 else
 897                         found = 1;
 898         }
 899
 900         /* quirks */
 901         /* Radeon 7000 (RV100) */
 902         if (((dev->pdev->device == 0x5159) &&
 903             (dev->pdev->subsystem_vendor == 0x174B) &&
 904             (dev->pdev->subsystem_device == 0x7c28)) ||
 905         /* Radeon 9100 (R200) */
 906            ((dev->pdev->device == 0x514D) &&
 907             (dev->pdev->subsystem_vendor == 0x174B) &&
 908             (dev->pdev->subsystem_device == 0x7149))) {
 909                 /* vbios value is bad, use the default */
 910                 found = 0;
 911         }
 912
 913         if (!found) /* fallback to defaults */
 914                 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
 915
 916         return p_dac;
 917 }
 918
 919 enum radeon_tv_std
 920 radeon_combios_get_tv_info(struct radeon_device *rdev)
 921 {
 922         struct drm_device *dev = rdev->ddev;
 923         uint16_t tv_info;
 924         enum radeon_tv_std tv_std = TV_STD_NTSC;
 925
 926         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 927         if (tv_info) {
 928                 if (RBIOS8(tv_info + 6) == 'T') {
 929                         switch (RBIOS8(tv_info + 7) & 0xf) {
 930                         case 1:
 931                                 tv_std = TV_STD_NTSC;
 932                                 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
 933                                 break;
 934                         case 2:
 935                                 tv_std = TV_STD_PAL;
 936                                 DRM_DEBUG_KMS("Default TV standard: PAL\n");
 937                                 break;
 938                         case 3:
 939                                 tv_std = TV_STD_PAL_M;
 940                                 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
 941                                 break;
 942                         case 4:
 943                                 tv_std = TV_STD_PAL_60;
 944                                 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
 945                                 break;
 946                         case 5:
 947                                 tv_std = TV_STD_NTSC_J;
 948                                 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
 949                                 break;
 950                         case 6:
 951                                 tv_std = TV_STD_SCART_PAL;
 952                                 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
 953                                 break;
 954                         default:
 955                                 tv_std = TV_STD_NTSC;
 956                                 DRM_DEBUG_KMS
 957                                     ("Unknown TV standard; defaulting to NTSC\n");
 958                                 break;
 959                         }
 960
 961                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
 962                         case 0:
 963                                 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
 964                                 break;
 965                         case 1:
 966                                 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
 967                                 break;
 968                         case 2:
 969                                 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
 970                                 break;
 971                         case 3:
 972                                 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
 973                                 break;
 974                         default:
 975                                 break;
 976                         }
 977                 }
 978         }
 979         return tv_std;
 980 }
 981
 982 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
 983         0x00000000,             /* r100  */
 984         0x00280000,             /* rv100 */
 985         0x00000000,             /* rs100 */
 986         0x00880000,             /* rv200 */
 987         0x00000000,             /* rs200 */
 988         0x00000000,             /* r200  */
 989         0x00770000,             /* rv250 */
 990         0x00290000,             /* rs300 */
 991         0x00560000,             /* rv280 */
 992         0x00780000,             /* r300  */
 993         0x00770000,             /* r350  */
 994         0x00780000,             /* rv350 */
 995         0x00780000,             /* rv380 */
 996         0x01080000,             /* r420  */
 997         0x01080000,             /* r423  */
 998         0x01080000,             /* rv410 */
 999         0x00780000,             /* rs400 */
1000         0x00780000,             /* rs480 */
1001 };
1002
1003 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1004                                                      struct radeon_encoder_tv_dac *tv_dac)
1005 {
1006         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1007         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1008                 tv_dac->ps2_tvdac_adj = 0x00880000;
1009         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1010         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1011         return;
1012 }
1013
1014 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1015                                                              radeon_encoder
1016                                                              *encoder)
1017 {
1018         struct drm_device *dev = encoder->base.dev;
1019         struct radeon_device *rdev = dev->dev_private;
1020         uint16_t dac_info;
1021         uint8_t rev, bg, dac;
1022         struct radeon_encoder_tv_dac *tv_dac = NULL;
1023         int found = 0;
1024
1025         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1026         if (!tv_dac)
1027                 return NULL;
1028
1029         /* first check TV table */
1030         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1031         if (dac_info) {
1032                 rev = RBIOS8(dac_info + 0x3);
1033                 if (rev > 4) {
1034                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1035                         dac = RBIOS8(dac_info + 0xd) & 0xf;
1036                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1037
1038                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1039                         dac = RBIOS8(dac_info + 0xf) & 0xf;
1040                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1041
1042                         bg = RBIOS8(dac_info + 0x10) & 0xf;
1043                         dac = RBIOS8(dac_info + 0x11) & 0xf;
1044                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1045                         /* if the values are all zeros, use the table */
1046                         if (tv_dac->ps2_tvdac_adj)
1047                                 found = 1;
1048                 } else if (rev > 1) {
1049                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1050                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1051                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1052
1053                         bg = RBIOS8(dac_info + 0xd) & 0xf;
1054                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1055                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1056
1057                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1058                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1059                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1060                         /* if the values are all zeros, use the table */
1061                         if (tv_dac->ps2_tvdac_adj)
1062                                 found = 1;
1063                 }
1064                 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1065         }
1066         if (!found) {
1067                 /* then check CRT table */
1068                 dac_info =
1069                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1070                 if (dac_info) {
1071                         rev = RBIOS8(dac_info) & 0x3;
1072                         if (rev < 2) {
1073                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
1074                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1075                                 tv_dac->ps2_tvdac_adj =
1076                                     (bg << 16) | (dac << 20);
1077                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1078                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1079                                 /* if the values are all zeros, use the table */
1080                                 if (tv_dac->ps2_tvdac_adj)
1081                                         found = 1;
1082                         } else {
1083                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
1084                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
1085                                 tv_dac->ps2_tvdac_adj =
1086                                     (bg << 16) | (dac << 20);
1087                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1088                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1089                                 /* if the values are all zeros, use the table */
1090                                 if (tv_dac->ps2_tvdac_adj)
1091                                         found = 1;
1092                         }
1093                 } else {
1094                         DRM_INFO("No TV DAC info found in BIOS\n");
1095                 }
1096         }
1097
1098         if (!found) /* fallback to defaults */
1099                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1100
1101         return tv_dac;
1102 }
1103
1104 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1105                                                                          radeon_device
1106                                                                          *rdev)
1107 {
1108         struct radeon_encoder_lvds *lvds = NULL;
1109         uint32_t fp_vert_stretch, fp_horz_stretch;
1110         uint32_t ppll_div_sel, ppll_val;
1111         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1112
1113         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1114
1115         if (!lvds)
1116                 return NULL;
1117
1118         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1119         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1120
1121         /* These should be fail-safe defaults, fingers crossed */
1122         lvds->panel_pwr_delay = 200;
1123         lvds->panel_vcc_delay = 2000;
1124
1125         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1126         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1127         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1128
1129         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1130                 lvds->native_mode.vdisplay =
1131                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1132                      RADEON_VERT_PANEL_SHIFT) + 1;
1133         else
1134                 lvds->native_mode.vdisplay =
1135                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1136
1137         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1138                 lvds->native_mode.hdisplay =
1139                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1140                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1141         else
1142                 lvds->native_mode.hdisplay =
1143                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1144
1145         if ((lvds->native_mode.hdisplay < 640) ||
1146             (lvds->native_mode.vdisplay < 480)) {
1147                 lvds->native_mode.hdisplay = 640;
1148                 lvds->native_mode.vdisplay = 480;
1149         }
1150
1151         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1152         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1153         if ((ppll_val & 0x000707ff) == 0x1bb)
1154                 lvds->use_bios_dividers = false;
1155         else {
1156                 lvds->panel_ref_divider =
1157                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1158                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1159                 lvds->panel_fb_divider = ppll_val & 0x7ff;
1160
1161                 if ((lvds->panel_ref_divider != 0) &&
1162                     (lvds->panel_fb_divider > 3))
1163                         lvds->use_bios_dividers = true;
1164         }
1165         lvds->panel_vcc_delay = 200;
1166
1167         DRM_INFO("Panel info derived from registers\n");
1168         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1169                  lvds->native_mode.vdisplay);
1170
1171         return lvds;
1172 }
1173
1174 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1175                                                          *encoder)
1176 {
1177         struct drm_device *dev = encoder->base.dev;
1178         struct radeon_device *rdev = dev->dev_private;
1179         uint16_t lcd_info;
1180         uint32_t panel_setup;
1181         char stmp[30];
1182         int tmp, i;
1183         struct radeon_encoder_lvds *lvds = NULL;
1184
1185         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1186
1187         if (lcd_info) {
1188                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1189
1190                 if (!lvds)
1191                         return NULL;
1192
1193                 for (i = 0; i < 24; i++)
1194                         stmp[i] = RBIOS8(lcd_info + i + 1);
1195                 stmp[24] = 0;
1196
1197                 DRM_INFO("Panel ID String: %s\n", stmp);
1198
1199                 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1200                 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1201
1202                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1203                          lvds->native_mode.vdisplay);
1204
1205                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1206                 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1207
1208                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1209                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1210                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1211
1212                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1213                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1214                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1215                 if ((lvds->panel_ref_divider != 0) &&
1216                     (lvds->panel_fb_divider > 3))
1217                         lvds->use_bios_dividers = true;
1218
1219                 panel_setup = RBIOS32(lcd_info + 0x39);
1220                 lvds->lvds_gen_cntl = 0xff00;
1221                 if (panel_setup & 0x1)
1222                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1223
1224                 if ((panel_setup >> 4) & 0x1)
1225                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1226
1227                 switch ((panel_setup >> 8) & 0x7) {
1228                 case 0:
1229                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1230                         break;
1231                 case 1:
1232                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1233                         break;
1234                 case 2:
1235                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1236                         break;
1237                 default:
1238                         break;
1239                 }
1240
1241                 if ((panel_setup >> 16) & 0x1)
1242                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1243
1244                 if ((panel_setup >> 17) & 0x1)
1245                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1246
1247                 if ((panel_setup >> 18) & 0x1)
1248                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1249
1250                 if ((panel_setup >> 23) & 0x1)
1251                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1252
1253                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1254
1255                 for (i = 0; i < 32; i++) {
1256                         tmp = RBIOS16(lcd_info + 64 + i * 2);
1257                         if (tmp == 0)
1258                                 break;
1259
1260                         if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1261                             (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1262                                 u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1263
1264                                 if (hss > lvds->native_mode.hdisplay)
1265                                         hss = (10 - 1) * 8;
1266
1267                                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1268                                         (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1269                                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1270                                         hss;
1271                                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1272                                         (RBIOS8(tmp + 23) * 8);
1273
1274                                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1275                                         (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1276                                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1277                                         ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1278                                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1279                                         ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1280
1281                                 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1282                                 lvds->native_mode.flags = 0;
1283                                 /* set crtc values */
1284                                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1285
1286                         }
1287                 }
1288         } else {
1289                 DRM_INFO("No panel info found in BIOS\n");
1290                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1291         }
1292
1293         if (lvds)
1294                 encoder->native_mode = lvds->native_mode;
1295         return lvds;
1296 }
1297
1298 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1299         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
1300         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
1301         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
1302         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
1303         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
1304         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
1305         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
1306         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
1307         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
1308         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
1309         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
1310         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
1311         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
1312         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
1313         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
1314         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
1315         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS400 */
1316         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS480 */
1317 };
1318
1319 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1320                                             struct radeon_encoder_int_tmds *tmds)
1321 {
1322         struct drm_device *dev = encoder->base.dev;
1323         struct radeon_device *rdev = dev->dev_private;
1324         int i;
1325
1326         for (i = 0; i < 4; i++) {
1327                 tmds->tmds_pll[i].value =
1328                         default_tmds_pll[rdev->family][i].value;
1329                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1330         }
1331
1332         return true;
1333 }
1334
1335 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1336                                               struct radeon_encoder_int_tmds *tmds)
1337 {
1338         struct drm_device *dev = encoder->base.dev;
1339         struct radeon_device *rdev = dev->dev_private;
1340         uint16_t tmds_info;
1341         int i, n;
1342         uint8_t ver;
1343
1344         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1345
1346         if (tmds_info) {
1347                 ver = RBIOS8(tmds_info);
1348                 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1349                 if (ver == 3) {
1350                         n = RBIOS8(tmds_info + 5) + 1;
1351                         if (n > 4)
1352                                 n = 4;
1353                         for (i = 0; i < n; i++) {
1354                                 tmds->tmds_pll[i].value =
1355                                     RBIOS32(tmds_info + i * 10 + 0x08);
1356                                 tmds->tmds_pll[i].freq =
1357                                     RBIOS16(tmds_info + i * 10 + 0x10);
1358                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1359                                           tmds->tmds_pll[i].freq,
1360                                           tmds->tmds_pll[i].value);
1361                         }
1362                 } else if (ver == 4) {
1363                         int stride = 0;
1364                         n = RBIOS8(tmds_info + 5) + 1;
1365                         if (n > 4)
1366                                 n = 4;
1367                         for (i = 0; i < n; i++) {
1368                                 tmds->tmds_pll[i].value =
1369                                     RBIOS32(tmds_info + stride + 0x08);
1370                                 tmds->tmds_pll[i].freq =
1371                                     RBIOS16(tmds_info + stride + 0x10);
1372                                 if (i == 0)
1373                                         stride += 10;
1374                                 else
1375                                         stride += 6;
1376                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1377                                           tmds->tmds_pll[i].freq,
1378                                           tmds->tmds_pll[i].value);
1379                         }
1380                 }
1381         } else {
1382                 DRM_INFO("No TMDS info found in BIOS\n");
1383                 return false;
1384         }
1385         return true;
1386 }
1387
1388 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1389                                                 struct radeon_encoder_ext_tmds *tmds)
1390 {
1391         struct drm_device *dev = encoder->base.dev;
1392         struct radeon_device *rdev = dev->dev_private;
1393         struct radeon_i2c_bus_rec i2c_bus;
1394
1395         /* default for macs */
1396         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1397         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1398
1399         /* XXX some macs have duallink chips */
1400         switch (rdev->mode_info.connector_table) {
1401         case CT_POWERBOOK_EXTERNAL:
1402         case CT_MINI_EXTERNAL:
1403         default:
1404                 tmds->dvo_chip = DVO_SIL164;
1405                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1406                 break;
1407         }
1408
1409         return true;
1410 }
1411
1412 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1413                                                   struct radeon_encoder_ext_tmds *tmds)
1414 {
1415         struct drm_device *dev = encoder->base.dev;
1416         struct radeon_device *rdev = dev->dev_private;
1417         uint16_t offset;
1418         uint8_t ver;
1419         enum radeon_combios_ddc gpio;
1420         struct radeon_i2c_bus_rec i2c_bus;
1421
1422         tmds->i2c_bus = NULL;
1423         if (rdev->flags & RADEON_IS_IGP) {
1424                 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1425                 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1426                 tmds->dvo_chip = DVO_SIL164;
1427                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1428         } else {
1429                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1430                 if (offset) {
1431                         ver = RBIOS8(offset);
1432                         DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1433                         tmds->slave_addr = RBIOS8(offset + 4 + 2);
1434                         tmds->slave_addr >>= 1; /* 7 bit addressing */
1435                         gpio = RBIOS8(offset + 4 + 3);
1436                         if (gpio == DDC_LCD) {
1437                                 /* MM i2c */
1438                                 i2c_bus.valid = true;
1439                                 i2c_bus.hw_capable = true;
1440                                 i2c_bus.mm_i2c = true;
1441                                 i2c_bus.i2c_id = 0xa0;
1442                         } else
1443                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1444                         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1445                 }
1446         }
1447
1448         if (!tmds->i2c_bus) {
1449                 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1450                 return false;
1451         }
1452
1453         return true;
1454 }
1455
1456 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1457 {
1458         struct radeon_device *rdev = dev->dev_private;
1459         struct radeon_i2c_bus_rec ddc_i2c;
1460         struct radeon_hpd hpd;
1461
1462         rdev->mode_info.connector_table = radeon_connector_table;
1463         if (rdev->mode_info.connector_table == CT_NONE) {
1464 #ifdef CONFIG_PPC_PMAC
1465                 if (of_machine_is_compatible("PowerBook3,3")) {
1466                         /* powerbook with VGA */
1467                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1468                 } else if (of_machine_is_compatible("PowerBook3,4") ||
1469                            of_machine_is_compatible("PowerBook3,5")) {
1470                         /* powerbook with internal tmds */
1471                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1472                 } else if (of_machine_is_compatible("PowerBook5,1") ||
1473                            of_machine_is_compatible("PowerBook5,2") ||
1474                            of_machine_is_compatible("PowerBook5,3") ||
1475                            of_machine_is_compatible("PowerBook5,4") ||
1476                            of_machine_is_compatible("PowerBook5,5")) {
1477                         /* powerbook with external single link tmds (sil164) */
1478                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1479                 } else if (of_machine_is_compatible("PowerBook5,6")) {
1480                         /* powerbook with external dual or single link tmds */
1481                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1482                 } else if (of_machine_is_compatible("PowerBook5,7") ||
1483                            of_machine_is_compatible("PowerBook5,8") ||
1484                            of_machine_is_compatible("PowerBook5,9")) {
1485                         /* PowerBook6,2 ? */
1486                         /* powerbook with external dual link tmds (sil1178?) */
1487                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1488                 } else if (of_machine_is_compatible("PowerBook4,1") ||
1489                            of_machine_is_compatible("PowerBook4,2") ||
1490                            of_machine_is_compatible("PowerBook4,3") ||
1491                            of_machine_is_compatible("PowerBook6,3") ||
1492                            of_machine_is_compatible("PowerBook6,5") ||
1493                            of_machine_is_compatible("PowerBook6,7")) {
1494                         /* ibook */
1495                         rdev->mode_info.connector_table = CT_IBOOK;
1496                 } else if (of_machine_is_compatible("PowerMac3,5")) {
1497                         /* PowerMac G4 Silver radeon 7500 */
1498                         rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1499                 } else if (of_machine_is_compatible("PowerMac4,4")) {
1500                         /* emac */
1501                         rdev->mode_info.connector_table = CT_EMAC;
1502                 } else if (of_machine_is_compatible("PowerMac10,1")) {
1503                         /* mini with internal tmds */
1504                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1505                 } else if (of_machine_is_compatible("PowerMac10,2")) {
1506                         /* mini with external tmds */
1507                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1508                 } else if (of_machine_is_compatible("PowerMac12,1")) {
1509                         /* PowerMac8,1 ? */
1510                         /* imac g5 isight */
1511                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1512                 } else if ((rdev->pdev->device == 0x4a48) &&
1513                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1514                            (rdev->pdev->subsystem_device == 0x4a48)) {
1515                         /* Mac X800 */
1516                         rdev->mode_info.connector_table = CT_MAC_X800;
1517                 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1518                             of_machine_is_compatible("PowerMac7,3")) &&
1519                            (rdev->pdev->device == 0x4150) &&
1520                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1521                            (rdev->pdev->subsystem_device == 0x4150)) {
1522                         /* Mac G5 tower 9600 */
1523                         rdev->mode_info.connector_table = CT_MAC_G5_9600;
1524                 } else if ((rdev->pdev->device == 0x4c66) &&
1525                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1526                            (rdev->pdev->subsystem_device == 0x4c66)) {
1527                         /* SAM440ep RV250 embedded board */
1528                         rdev->mode_info.connector_table = CT_SAM440EP;
1529                 } else
1530 #endif /* CONFIG_PPC_PMAC */
1531 #ifdef CONFIG_PPC64
1532                 if (ASIC_IS_RN50(rdev))
1533                         rdev->mode_info.connector_table = CT_RN50_POWER;
1534                 else
1535 #endif
1536                         rdev->mode_info.connector_table = CT_GENERIC;
1537         }
1538
1539         switch (rdev->mode_info.connector_table) {
1540         case CT_GENERIC:
1541                 DRM_INFO("Connector Table: %d (generic)\n",
1542                          rdev->mode_info.connector_table);
1543                 /* these are the most common settings */
1544                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1545                         /* VGA - primary dac */
1546                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1547                         hpd.hpd = RADEON_HPD_NONE;
1548                         radeon_add_legacy_encoder(dev,
1549                                                   radeon_get_encoder_enum(dev,
1550                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1551                                                                         1),
1552                                                   ATOM_DEVICE_CRT1_SUPPORT);
1553                         radeon_add_legacy_connector(dev, 0,
1554                                                     ATOM_DEVICE_CRT1_SUPPORT,
1555                                                     DRM_MODE_CONNECTOR_VGA,
1556                                                     &ddc_i2c,
1557                                                     CONNECTOR_OBJECT_ID_VGA,
1558                                                     &hpd);
1559                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1560                         /* LVDS */
1561                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1562                         hpd.hpd = RADEON_HPD_NONE;
1563                         radeon_add_legacy_encoder(dev,
1564                                                   radeon_get_encoder_enum(dev,
1565                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1566                                                                         0),
1567                                                   ATOM_DEVICE_LCD1_SUPPORT);
1568                         radeon_add_legacy_connector(dev, 0,
1569                                                     ATOM_DEVICE_LCD1_SUPPORT,
1570                                                     DRM_MODE_CONNECTOR_LVDS,
1571                                                     &ddc_i2c,
1572                                                     CONNECTOR_OBJECT_ID_LVDS,
1573                                                     &hpd);
1574
1575                         /* VGA - primary dac */
1576                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1577                         hpd.hpd = RADEON_HPD_NONE;
1578                         radeon_add_legacy_encoder(dev,
1579                                                   radeon_get_encoder_enum(dev,
1580                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1581                                                                         1),
1582                                                   ATOM_DEVICE_CRT1_SUPPORT);
1583                         radeon_add_legacy_connector(dev, 1,
1584                                                     ATOM_DEVICE_CRT1_SUPPORT,
1585                                                     DRM_MODE_CONNECTOR_VGA,
1586                                                     &ddc_i2c,
1587                                                     CONNECTOR_OBJECT_ID_VGA,
1588                                                     &hpd);
1589                 } else {
1590                         /* DVI-I - tv dac, int tmds */
1591                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1592                         hpd.hpd = RADEON_HPD_1;
1593                         radeon_add_legacy_encoder(dev,
1594                                                   radeon_get_encoder_enum(dev,
1595                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1596                                                                         0),
1597                                                   ATOM_DEVICE_DFP1_SUPPORT);
1598                         radeon_add_legacy_encoder(dev,
1599                                                   radeon_get_encoder_enum(dev,
1600                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1601                                                                         2),
1602                                                   ATOM_DEVICE_CRT2_SUPPORT);
1603                         radeon_add_legacy_connector(dev, 0,
1604                                                     ATOM_DEVICE_DFP1_SUPPORT |
1605                                                     ATOM_DEVICE_CRT2_SUPPORT,
1606                                                     DRM_MODE_CONNECTOR_DVII,
1607                                                     &ddc_i2c,
1608                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1609                                                     &hpd);
1610
1611                         /* VGA - primary dac */
1612                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1613                         hpd.hpd = RADEON_HPD_NONE;
1614                         radeon_add_legacy_encoder(dev,
1615                                                   radeon_get_encoder_enum(dev,
1616                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1617                                                                         1),
1618                                                   ATOM_DEVICE_CRT1_SUPPORT);
1619                         radeon_add_legacy_connector(dev, 1,
1620                                                     ATOM_DEVICE_CRT1_SUPPORT,
1621                                                     DRM_MODE_CONNECTOR_VGA,
1622                                                     &ddc_i2c,
1623                                                     CONNECTOR_OBJECT_ID_VGA,
1624                                                     &hpd);
1625                 }
1626
1627                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1628                         /* TV - tv dac */
1629                         ddc_i2c.valid = false;
1630                         hpd.hpd = RADEON_HPD_NONE;
1631                         radeon_add_legacy_encoder(dev,
1632                                                   radeon_get_encoder_enum(dev,
1633                                                                         ATOM_DEVICE_TV1_SUPPORT,
1634                                                                         2),
1635                                                   ATOM_DEVICE_TV1_SUPPORT);
1636                         radeon_add_legacy_connector(dev, 2,
1637                                                     ATOM_DEVICE_TV1_SUPPORT,
1638                                                     DRM_MODE_CONNECTOR_SVIDEO,
1639                                                     &ddc_i2c,
1640                                                     CONNECTOR_OBJECT_ID_SVIDEO,
1641                                                     &hpd);
1642                 }
1643                 break;
1644         case CT_IBOOK:
1645                 DRM_INFO("Connector Table: %d (ibook)\n",
1646                          rdev->mode_info.connector_table);
1647                 /* LVDS */
1648                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1649                 hpd.hpd = RADEON_HPD_NONE;
1650                 radeon_add_legacy_encoder(dev,
1651                                           radeon_get_encoder_enum(dev,
1652                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1653                                                                 0),
1654                                           ATOM_DEVICE_LCD1_SUPPORT);
1655                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1656                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1657                                             CONNECTOR_OBJECT_ID_LVDS,
1658                                             &hpd);
1659                 /* VGA - TV DAC */
1660                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1661                 hpd.hpd = RADEON_HPD_NONE;
1662                 radeon_add_legacy_encoder(dev,
1663                                           radeon_get_encoder_enum(dev,
1664                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1665                                                                 2),
1666                                           ATOM_DEVICE_CRT2_SUPPORT);
1667                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1668                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1669                                             CONNECTOR_OBJECT_ID_VGA,
1670                                             &hpd);
1671                 /* TV - TV DAC */
1672                 ddc_i2c.valid = false;
1673                 hpd.hpd = RADEON_HPD_NONE;
1674                 radeon_add_legacy_encoder(dev,
1675                                           radeon_get_encoder_enum(dev,
1676                                                                 ATOM_DEVICE_TV1_SUPPORT,
1677                                                                 2),
1678                                           ATOM_DEVICE_TV1_SUPPORT);
1679                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1680                                             DRM_MODE_CONNECTOR_SVIDEO,
1681                                             &ddc_i2c,
1682                                             CONNECTOR_OBJECT_ID_SVIDEO,
1683                                             &hpd);
1684                 break;
1685         case CT_POWERBOOK_EXTERNAL:
1686                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1687                          rdev->mode_info.connector_table);
1688                 /* LVDS */
1689                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1690                 hpd.hpd = RADEON_HPD_NONE;
1691                 radeon_add_legacy_encoder(dev,
1692                                           radeon_get_encoder_enum(dev,
1693                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1694                                                                 0),
1695                                           ATOM_DEVICE_LCD1_SUPPORT);
1696                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1697                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1698                                             CONNECTOR_OBJECT_ID_LVDS,
1699                                             &hpd);
1700                 /* DVI-I - primary dac, ext tmds */
1701                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1702                 hpd.hpd = RADEON_HPD_2; /* ??? */
1703                 radeon_add_legacy_encoder(dev,
1704                                           radeon_get_encoder_enum(dev,
1705                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1706                                                                 0),
1707                                           ATOM_DEVICE_DFP2_SUPPORT);
1708                 radeon_add_legacy_encoder(dev,
1709                                           radeon_get_encoder_enum(dev,
1710                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1711                                                                 1),
1712                                           ATOM_DEVICE_CRT1_SUPPORT);
1713                 /* XXX some are SL */
1714                 radeon_add_legacy_connector(dev, 1,
1715                                             ATOM_DEVICE_DFP2_SUPPORT |
1716                                             ATOM_DEVICE_CRT1_SUPPORT,
1717                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1718                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1719                                             &hpd);
1720                 /* TV - TV DAC */
1721                 ddc_i2c.valid = false;
1722                 hpd.hpd = RADEON_HPD_NONE;
1723                 radeon_add_legacy_encoder(dev,
1724                                           radeon_get_encoder_enum(dev,
1725                                                                 ATOM_DEVICE_TV1_SUPPORT,
1726                                                                 2),
1727                                           ATOM_DEVICE_TV1_SUPPORT);
1728                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1729                                             DRM_MODE_CONNECTOR_SVIDEO,
1730                                             &ddc_i2c,
1731                                             CONNECTOR_OBJECT_ID_SVIDEO,
1732                                             &hpd);
1733                 break;
1734         case CT_POWERBOOK_INTERNAL:
1735                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1736                          rdev->mode_info.connector_table);
1737                 /* LVDS */
1738                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1739                 hpd.hpd = RADEON_HPD_NONE;
1740                 radeon_add_legacy_encoder(dev,
1741                                           radeon_get_encoder_enum(dev,
1742                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1743                                                                 0),
1744                                           ATOM_DEVICE_LCD1_SUPPORT);
1745                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1746                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1747                                             CONNECTOR_OBJECT_ID_LVDS,
1748                                             &hpd);
1749                 /* DVI-I - primary dac, int tmds */
1750                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1751                 hpd.hpd = RADEON_HPD_1; /* ??? */
1752                 radeon_add_legacy_encoder(dev,
1753                                           radeon_get_encoder_enum(dev,
1754                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1755                                                                 0),
1756                                           ATOM_DEVICE_DFP1_SUPPORT);
1757                 radeon_add_legacy_encoder(dev,
1758                                           radeon_get_encoder_enum(dev,
1759                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1760                                                                 1),
1761                                           ATOM_DEVICE_CRT1_SUPPORT);
1762                 radeon_add_legacy_connector(dev, 1,
1763                                             ATOM_DEVICE_DFP1_SUPPORT |
1764                                             ATOM_DEVICE_CRT1_SUPPORT,
1765                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1766                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1767                                             &hpd);
1768                 /* TV - TV DAC */
1769                 ddc_i2c.valid = false;
1770                 hpd.hpd = RADEON_HPD_NONE;
1771                 radeon_add_legacy_encoder(dev,
1772                                           radeon_get_encoder_enum(dev,
1773                                                                 ATOM_DEVICE_TV1_SUPPORT,
1774                                                                 2),
1775                                           ATOM_DEVICE_TV1_SUPPORT);
1776                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1777                                             DRM_MODE_CONNECTOR_SVIDEO,
1778                                             &ddc_i2c,
1779                                             CONNECTOR_OBJECT_ID_SVIDEO,
1780                                             &hpd);
1781                 break;
1782         case CT_POWERBOOK_VGA:
1783                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1784                          rdev->mode_info.connector_table);
1785                 /* LVDS */
1786                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1787                 hpd.hpd = RADEON_HPD_NONE;
1788                 radeon_add_legacy_encoder(dev,
1789                                           radeon_get_encoder_enum(dev,
1790                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1791                                                                 0),
1792                                           ATOM_DEVICE_LCD1_SUPPORT);
1793                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1794                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1795                                             CONNECTOR_OBJECT_ID_LVDS,
1796                                             &hpd);
1797                 /* VGA - primary dac */
1798                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1799                 hpd.hpd = RADEON_HPD_NONE;
1800                 radeon_add_legacy_encoder(dev,
1801                                           radeon_get_encoder_enum(dev,
1802                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1803                                                                 1),
1804                                           ATOM_DEVICE_CRT1_SUPPORT);
1805                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1806                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1807                                             CONNECTOR_OBJECT_ID_VGA,
1808                                             &hpd);
1809                 /* TV - TV DAC */
1810                 ddc_i2c.valid = false;
1811                 hpd.hpd = RADEON_HPD_NONE;
1812                 radeon_add_legacy_encoder(dev,
1813                                           radeon_get_encoder_enum(dev,
1814                                                                 ATOM_DEVICE_TV1_SUPPORT,
1815                                                                 2),
1816                                           ATOM_DEVICE_TV1_SUPPORT);
1817                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1818                                             DRM_MODE_CONNECTOR_SVIDEO,
1819                                             &ddc_i2c,
1820                                             CONNECTOR_OBJECT_ID_SVIDEO,
1821                                             &hpd);
1822                 break;
1823         case CT_MINI_EXTERNAL:
1824                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1825                          rdev->mode_info.connector_table);
1826                 /* DVI-I - tv dac, ext tmds */
1827                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1828                 hpd.hpd = RADEON_HPD_2; /* ??? */
1829                 radeon_add_legacy_encoder(dev,
1830                                           radeon_get_encoder_enum(dev,
1831                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1832                                                                 0),
1833                                           ATOM_DEVICE_DFP2_SUPPORT);
1834                 radeon_add_legacy_encoder(dev,
1835                                           radeon_get_encoder_enum(dev,
1836                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1837                                                                 2),
1838                                           ATOM_DEVICE_CRT2_SUPPORT);
1839                 /* XXX are any DL? */
1840                 radeon_add_legacy_connector(dev, 0,
1841                                             ATOM_DEVICE_DFP2_SUPPORT |
1842                                             ATOM_DEVICE_CRT2_SUPPORT,
1843                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1844                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1845                                             &hpd);
1846                 /* TV - TV DAC */
1847                 ddc_i2c.valid = false;
1848                 hpd.hpd = RADEON_HPD_NONE;
1849                 radeon_add_legacy_encoder(dev,
1850                                           radeon_get_encoder_enum(dev,
1851                                                                 ATOM_DEVICE_TV1_SUPPORT,
1852                                                                 2),
1853                                           ATOM_DEVICE_TV1_SUPPORT);
1854                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1855                                             DRM_MODE_CONNECTOR_SVIDEO,
1856                                             &ddc_i2c,
1857                                             CONNECTOR_OBJECT_ID_SVIDEO,
1858                                             &hpd);
1859                 break;
1860         case CT_MINI_INTERNAL:
1861                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1862                          rdev->mode_info.connector_table);
1863                 /* DVI-I - tv dac, int tmds */
1864                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1865                 hpd.hpd = RADEON_HPD_1; /* ??? */
1866                 radeon_add_legacy_encoder(dev,
1867                                           radeon_get_encoder_enum(dev,
1868                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1869                                                                 0),
1870                                           ATOM_DEVICE_DFP1_SUPPORT);
1871                 radeon_add_legacy_encoder(dev,
1872                                           radeon_get_encoder_enum(dev,
1873                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1874                                                                 2),
1875                                           ATOM_DEVICE_CRT2_SUPPORT);
1876                 radeon_add_legacy_connector(dev, 0,
1877                                             ATOM_DEVICE_DFP1_SUPPORT |
1878                                             ATOM_DEVICE_CRT2_SUPPORT,
1879                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1880                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1881                                             &hpd);
1882                 /* TV - TV DAC */
1883                 ddc_i2c.valid = false;
1884                 hpd.hpd = RADEON_HPD_NONE;
1885                 radeon_add_legacy_encoder(dev,
1886                                           radeon_get_encoder_enum(dev,
1887                                                                 ATOM_DEVICE_TV1_SUPPORT,
1888                                                                 2),
1889                                           ATOM_DEVICE_TV1_SUPPORT);
1890                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1891                                             DRM_MODE_CONNECTOR_SVIDEO,
1892                                             &ddc_i2c,
1893                                             CONNECTOR_OBJECT_ID_SVIDEO,
1894                                             &hpd);
1895                 break;
1896         case CT_IMAC_G5_ISIGHT:
1897                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1898                          rdev->mode_info.connector_table);
1899                 /* DVI-D - int tmds */
1900                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1901                 hpd.hpd = RADEON_HPD_1; /* ??? */
1902                 radeon_add_legacy_encoder(dev,
1903                                           radeon_get_encoder_enum(dev,
1904                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1905                                                                 0),
1906                                           ATOM_DEVICE_DFP1_SUPPORT);
1907                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1908                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1909                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1910                                             &hpd);
1911                 /* VGA - tv dac */
1912                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1913                 hpd.hpd = RADEON_HPD_NONE;
1914                 radeon_add_legacy_encoder(dev,
1915                                           radeon_get_encoder_enum(dev,
1916                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1917                                                                 2),
1918                                           ATOM_DEVICE_CRT2_SUPPORT);
1919                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1920                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1921                                             CONNECTOR_OBJECT_ID_VGA,
1922                                             &hpd);
1923                 /* TV - TV DAC */
1924                 ddc_i2c.valid = false;
1925                 hpd.hpd = RADEON_HPD_NONE;
1926                 radeon_add_legacy_encoder(dev,
1927                                           radeon_get_encoder_enum(dev,
1928                                                                 ATOM_DEVICE_TV1_SUPPORT,
1929                                                                 2),
1930                                           ATOM_DEVICE_TV1_SUPPORT);
1931                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1932                                             DRM_MODE_CONNECTOR_SVIDEO,
1933                                             &ddc_i2c,
1934                                             CONNECTOR_OBJECT_ID_SVIDEO,
1935                                             &hpd);
1936                 break;
1937         case CT_EMAC:
1938                 DRM_INFO("Connector Table: %d (emac)\n",
1939                          rdev->mode_info.connector_table);
1940                 /* VGA - primary dac */
1941                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1942                 hpd.hpd = RADEON_HPD_NONE;
1943                 radeon_add_legacy_encoder(dev,
1944                                           radeon_get_encoder_enum(dev,
1945                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1946                                                                 1),
1947                                           ATOM_DEVICE_CRT1_SUPPORT);
1948                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1949                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1950                                             CONNECTOR_OBJECT_ID_VGA,
1951                                             &hpd);
1952                 /* VGA - tv dac */
1953                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1954                 hpd.hpd = RADEON_HPD_NONE;
1955                 radeon_add_legacy_encoder(dev,
1956                                           radeon_get_encoder_enum(dev,
1957                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1958                                                                 2),
1959                                           ATOM_DEVICE_CRT2_SUPPORT);
1960                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1961                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1962                                             CONNECTOR_OBJECT_ID_VGA,
1963                                             &hpd);
1964                 /* TV - TV DAC */
1965                 ddc_i2c.valid = false;
1966                 hpd.hpd = RADEON_HPD_NONE;
1967                 radeon_add_legacy_encoder(dev,
1968                                           radeon_get_encoder_enum(dev,
1969                                                                 ATOM_DEVICE_TV1_SUPPORT,
1970                                                                 2),
1971                                           ATOM_DEVICE_TV1_SUPPORT);
1972                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1973                                             DRM_MODE_CONNECTOR_SVIDEO,
1974                                             &ddc_i2c,
1975                                             CONNECTOR_OBJECT_ID_SVIDEO,
1976                                             &hpd);
1977                 break;
1978         case CT_RN50_POWER:
1979                 DRM_INFO("Connector Table: %d (rn50-power)\n",
1980                          rdev->mode_info.connector_table);
1981                 /* VGA - primary dac */
1982                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1983                 hpd.hpd = RADEON_HPD_NONE;
1984                 radeon_add_legacy_encoder(dev,
1985                                           radeon_get_encoder_enum(dev,
1986                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1987                                                                 1),
1988                                           ATOM_DEVICE_CRT1_SUPPORT);
1989                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1990                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1991                                             CONNECTOR_OBJECT_ID_VGA,
1992                                             &hpd);
1993                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1994                 hpd.hpd = RADEON_HPD_NONE;
1995                 radeon_add_legacy_encoder(dev,
1996                                           radeon_get_encoder_enum(dev,
1997                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1998                                                                 2),
1999                                           ATOM_DEVICE_CRT2_SUPPORT);
2000                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2001                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2002                                             CONNECTOR_OBJECT_ID_VGA,
2003                                             &hpd);
2004                 break;
2005         case CT_MAC_X800:
2006                 DRM_INFO("Connector Table: %d (mac x800)\n",
2007                          rdev->mode_info.connector_table);
2008                 /* DVI - primary dac, internal tmds */
2009                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2010                 hpd.hpd = RADEON_HPD_1; /* ??? */
2011                 radeon_add_legacy_encoder(dev,
2012                                           radeon_get_encoder_enum(dev,
2013                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2014                                                                   0),
2015                                           ATOM_DEVICE_DFP1_SUPPORT);
2016                 radeon_add_legacy_encoder(dev,
2017                                           radeon_get_encoder_enum(dev,
2018                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2019                                                                   1),
2020                                           ATOM_DEVICE_CRT1_SUPPORT);
2021                 radeon_add_legacy_connector(dev, 0,
2022                                             ATOM_DEVICE_DFP1_SUPPORT |
2023                                             ATOM_DEVICE_CRT1_SUPPORT,
2024                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2025                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2026                                             &hpd);
2027                 /* DVI - tv dac, dvo */
2028                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2029                 hpd.hpd = RADEON_HPD_2; /* ??? */
2030                 radeon_add_legacy_encoder(dev,
2031                                           radeon_get_encoder_enum(dev,
2032                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2033                                                                   0),
2034                                           ATOM_DEVICE_DFP2_SUPPORT);
2035                 radeon_add_legacy_encoder(dev,
2036                                           radeon_get_encoder_enum(dev,
2037                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2038                                                                   2),
2039                                           ATOM_DEVICE_CRT2_SUPPORT);
2040                 radeon_add_legacy_connector(dev, 1,
2041                                             ATOM_DEVICE_DFP2_SUPPORT |
2042                                             ATOM_DEVICE_CRT2_SUPPORT,
2043                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2044                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2045                                             &hpd);
2046                 break;
2047         case CT_MAC_G5_9600:
2048                 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2049                          rdev->mode_info.connector_table);
2050                 /* DVI - tv dac, dvo */
2051                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2052                 hpd.hpd = RADEON_HPD_1; /* ??? */
2053                 radeon_add_legacy_encoder(dev,
2054                                           radeon_get_encoder_enum(dev,
2055                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2056                                                                   0),
2057                                           ATOM_DEVICE_DFP2_SUPPORT);
2058                 radeon_add_legacy_encoder(dev,
2059                                           radeon_get_encoder_enum(dev,
2060                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2061                                                                   2),
2062                                           ATOM_DEVICE_CRT2_SUPPORT);
2063                 radeon_add_legacy_connector(dev, 0,
2064                                             ATOM_DEVICE_DFP2_SUPPORT |
2065                                             ATOM_DEVICE_CRT2_SUPPORT,
2066                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2067                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2068                                             &hpd);
2069                 /* ADC - primary dac, internal tmds */
2070                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2071                 hpd.hpd = RADEON_HPD_2; /* ??? */
2072                 radeon_add_legacy_encoder(dev,
2073                                           radeon_get_encoder_enum(dev,
2074                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2075                                                                   0),
2076                                           ATOM_DEVICE_DFP1_SUPPORT);
2077                 radeon_add_legacy_encoder(dev,
2078                                           radeon_get_encoder_enum(dev,
2079                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2080                                                                   1),
2081                                           ATOM_DEVICE_CRT1_SUPPORT);
2082                 radeon_add_legacy_connector(dev, 1,
2083                                             ATOM_DEVICE_DFP1_SUPPORT |
2084                                             ATOM_DEVICE_CRT1_SUPPORT,
2085                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2086                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2087                                             &hpd);
2088                 /* TV - TV DAC */
2089                 ddc_i2c.valid = false;
2090                 hpd.hpd = RADEON_HPD_NONE;
2091                 radeon_add_legacy_encoder(dev,
2092                                           radeon_get_encoder_enum(dev,
2093                                                                 ATOM_DEVICE_TV1_SUPPORT,
2094                                                                 2),
2095                                           ATOM_DEVICE_TV1_SUPPORT);
2096                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2097                                             DRM_MODE_CONNECTOR_SVIDEO,
2098                                             &ddc_i2c,
2099                                             CONNECTOR_OBJECT_ID_SVIDEO,
2100                                             &hpd);
2101                 break;
2102         case CT_SAM440EP:
2103                 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2104                          rdev->mode_info.connector_table);
2105                 /* LVDS */
2106                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2107                 hpd.hpd = RADEON_HPD_NONE;
2108                 radeon_add_legacy_encoder(dev,
2109                                           radeon_get_encoder_enum(dev,
2110                                                                 ATOM_DEVICE_LCD1_SUPPORT,
2111                                                                 0),
2112                                           ATOM_DEVICE_LCD1_SUPPORT);
2113                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
2114                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
2115                                             CONNECTOR_OBJECT_ID_LVDS,
2116                                             &hpd);
2117                 /* DVI-I - secondary dac, int tmds */
2118                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2119                 hpd.hpd = RADEON_HPD_1; /* ??? */
2120                 radeon_add_legacy_encoder(dev,
2121                                           radeon_get_encoder_enum(dev,
2122                                                                 ATOM_DEVICE_DFP1_SUPPORT,
2123                                                                 0),
2124                                           ATOM_DEVICE_DFP1_SUPPORT);
2125                 radeon_add_legacy_encoder(dev,
2126                                           radeon_get_encoder_enum(dev,
2127                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2128                                                                 2),
2129                                           ATOM_DEVICE_CRT2_SUPPORT);
2130                 radeon_add_legacy_connector(dev, 1,
2131                                             ATOM_DEVICE_DFP1_SUPPORT |
2132                                             ATOM_DEVICE_CRT2_SUPPORT,
2133                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2134                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2135                                             &hpd);
2136                 /* VGA - primary dac */
2137                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2138                 hpd.hpd = RADEON_HPD_NONE;
2139                 radeon_add_legacy_encoder(dev,
2140                                           radeon_get_encoder_enum(dev,
2141                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2142                                                                 1),
2143                                           ATOM_DEVICE_CRT1_SUPPORT);
2144                 radeon_add_legacy_connector(dev, 2,
2145                                             ATOM_DEVICE_CRT1_SUPPORT,
2146                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2147                                             CONNECTOR_OBJECT_ID_VGA,
2148                                             &hpd);
2149                 /* TV - TV DAC */
2150                 ddc_i2c.valid = false;
2151                 hpd.hpd = RADEON_HPD_NONE;
2152                 radeon_add_legacy_encoder(dev,
2153                                           radeon_get_encoder_enum(dev,
2154                                                                 ATOM_DEVICE_TV1_SUPPORT,
2155                                                                 2),
2156                                           ATOM_DEVICE_TV1_SUPPORT);
2157                 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2158                                             DRM_MODE_CONNECTOR_SVIDEO,
2159                                             &ddc_i2c,
2160                                             CONNECTOR_OBJECT_ID_SVIDEO,
2161                                             &hpd);
2162                 break;
2163         case CT_MAC_G4_SILVER:
2164                 DRM_INFO("Connector Table: %d (mac g4 silver)\n",
2165                          rdev->mode_info.connector_table);
2166                 /* DVI-I - tv dac, int tmds */
2167                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2168                 hpd.hpd = RADEON_HPD_1; /* ??? */
2169                 radeon_add_legacy_encoder(dev,
2170                                           radeon_get_encoder_enum(dev,
2171                                                                 ATOM_DEVICE_DFP1_SUPPORT,
2172                                                                 0),
2173                                           ATOM_DEVICE_DFP1_SUPPORT);
2174                 radeon_add_legacy_encoder(dev,
2175                                           radeon_get_encoder_enum(dev,
2176                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2177                                                                 2),
2178                                           ATOM_DEVICE_CRT2_SUPPORT);
2179                 radeon_add_legacy_connector(dev, 0,
2180                                             ATOM_DEVICE_DFP1_SUPPORT |
2181                                             ATOM_DEVICE_CRT2_SUPPORT,
2182                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2183                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2184                                             &hpd);
2185                 /* VGA - primary dac */
2186                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2187                 hpd.hpd = RADEON_HPD_NONE;
2188                 radeon_add_legacy_encoder(dev,
2189                                           radeon_get_encoder_enum(dev,
2190                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2191                                                                 1),
2192                                           ATOM_DEVICE_CRT1_SUPPORT);
2193                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
2194                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2195                                             CONNECTOR_OBJECT_ID_VGA,
2196                                             &hpd);
2197                 /* TV - TV DAC */
2198                 ddc_i2c.valid = false;
2199                 hpd.hpd = RADEON_HPD_NONE;
2200                 radeon_add_legacy_encoder(dev,
2201                                           radeon_get_encoder_enum(dev,
2202                                                                 ATOM_DEVICE_TV1_SUPPORT,
2203                                                                 2),
2204                                           ATOM_DEVICE_TV1_SUPPORT);
2205                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2206                                             DRM_MODE_CONNECTOR_SVIDEO,
2207                                             &ddc_i2c,
2208                                             CONNECTOR_OBJECT_ID_SVIDEO,
2209                                             &hpd);
2210                 break;
2211         default:
2212                 DRM_INFO("Connector table: %d (invalid)\n",
2213                          rdev->mode_info.connector_table);
2214                 return false;
2215         }
2216
2217         radeon_link_encoder_connector(dev);
2218
2219         return true;
2220 }
2221
2222 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2223                                        int bios_index,
2224                                        enum radeon_combios_connector
2225                                        *legacy_connector,
2226                                        struct radeon_i2c_bus_rec *ddc_i2c,
2227                                        struct radeon_hpd *hpd)
2228 {
2229
2230         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2231            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2232         if (dev->pdev->device == 0x515e &&
2233             dev->pdev->subsystem_vendor == 0x1014) {
2234                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2235                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2236                         return false;
2237         }
2238
2239         /* X300 card with extra non-existent DVI port */
2240         if (dev->pdev->device == 0x5B60 &&
2241             dev->pdev->subsystem_vendor == 0x17af &&
2242             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2243                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2244                         return false;
2245         }
2246
2247         return true;
2248 }
2249
2250 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2251 {
2252         /* Acer 5102 has non-existent TV port */
2253         if (dev->pdev->device == 0x5975 &&
2254             dev->pdev->subsystem_vendor == 0x1025 &&
2255             dev->pdev->subsystem_device == 0x009f)
2256                 return false;
2257
2258         /* HP dc5750 has non-existent TV port */
2259         if (dev->pdev->device == 0x5974 &&
2260             dev->pdev->subsystem_vendor == 0x103c &&
2261             dev->pdev->subsystem_device == 0x280a)
2262                 return false;
2263
2264         /* MSI S270 has non-existent TV port */
2265         if (dev->pdev->device == 0x5955 &&
2266             dev->pdev->subsystem_vendor == 0x1462 &&
2267             dev->pdev->subsystem_device == 0x0131)
2268                 return false;
2269
2270         return true;
2271 }
2272
2273 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2274 {
2275         struct radeon_device *rdev = dev->dev_private;
2276         uint32_t ext_tmds_info;
2277
2278         if (rdev->flags & RADEON_IS_IGP) {
2279                 if (is_dvi_d)
2280                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2281                 else
2282                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2283         }
2284         ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2285         if (ext_tmds_info) {
2286                 uint8_t rev = RBIOS8(ext_tmds_info);
2287                 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2288                 if (rev >= 3) {
2289                         if (is_dvi_d)
2290                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2291                         else
2292                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2293                 } else {
2294                         if (flags & 1) {
2295                                 if (is_dvi_d)
2296                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2297                                 else
2298                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2299                         }
2300                 }
2301         }
2302         if (is_dvi_d)
2303                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2304         else
2305                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2306 }
2307
2308 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2309 {
2310         struct radeon_device *rdev = dev->dev_private;
2311         uint32_t conn_info, entry, devices;
2312         uint16_t tmp, connector_object_id;
2313         enum radeon_combios_ddc ddc_type;
2314         enum radeon_combios_connector connector;
2315         int i = 0;
2316         struct radeon_i2c_bus_rec ddc_i2c;
2317         struct radeon_hpd hpd;
2318
2319         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2320         if (conn_info) {
2321                 for (i = 0; i < 4; i++) {
2322                         entry = conn_info + 2 + i * 2;
2323
2324                         if (!RBIOS16(entry))
2325                                 break;
2326
2327                         tmp = RBIOS16(entry);
2328
2329                         connector = (tmp >> 12) & 0xf;
2330
2331                         ddc_type = (tmp >> 8) & 0xf;
2332                         ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2333
2334                         switch (connector) {
2335                         case CONNECTOR_PROPRIETARY_LEGACY:
2336                         case CONNECTOR_DVI_I_LEGACY:
2337                         case CONNECTOR_DVI_D_LEGACY:
2338                                 if ((tmp >> 4) & 0x1)
2339                                         hpd.hpd = RADEON_HPD_2;
2340                                 else
2341                                         hpd.hpd = RADEON_HPD_1;
2342                                 break;
2343                         default:
2344                                 hpd.hpd = RADEON_HPD_NONE;
2345                                 break;
2346                         }
2347
2348                         if (!radeon_apply_legacy_quirks(dev, i, &connector,
2349                                                         &ddc_i2c, &hpd))
2350                                 continue;
2351
2352                         switch (connector) {
2353                         case CONNECTOR_PROPRIETARY_LEGACY:
2354                                 if ((tmp >> 4) & 0x1)
2355                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2356                                 else
2357                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2358                                 radeon_add_legacy_encoder(dev,
2359                                                           radeon_get_encoder_enum
2360                                                           (dev, devices, 0),
2361                                                           devices);
2362                                 radeon_add_legacy_connector(dev, i, devices,
2363                                                             legacy_connector_convert
2364                                                             [connector],
2365                                                             &ddc_i2c,
2366                                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2367                                                             &hpd);
2368                                 break;
2369                         case CONNECTOR_CRT_LEGACY:
2370                                 if (tmp & 0x1) {
2371                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
2372                                         radeon_add_legacy_encoder(dev,
2373                                                                   radeon_get_encoder_enum
2374                                                                   (dev,
2375                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2376                                                                    2),
2377                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2378                                 } else {
2379                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
2380                                         radeon_add_legacy_encoder(dev,
2381                                                                   radeon_get_encoder_enum
2382                                                                   (dev,
2383                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2384                                                                    1),
2385                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2386                                 }
2387                                 radeon_add_legacy_connector(dev,
2388                                                             i,
2389                                                             devices,
2390                                                             legacy_connector_convert
2391                                                             [connector],
2392                                                             &ddc_i2c,
2393                                                             CONNECTOR_OBJECT_ID_VGA,
2394                                                             &hpd);
2395                                 break;
2396                         case CONNECTOR_DVI_I_LEGACY:
2397                                 devices = 0;
2398                                 if (tmp & 0x1) {
2399                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
2400                                         radeon_add_legacy_encoder(dev,
2401                                                                   radeon_get_encoder_enum
2402                                                                   (dev,
2403                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2404                                                                    2),
2405                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2406                                 } else {
2407                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
2408                                         radeon_add_legacy_encoder(dev,
2409                                                                   radeon_get_encoder_enum
2410                                                                   (dev,
2411                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2412                                                                    1),
2413                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2414                                 }
2415                                 /* RV100 board with external TDMS bit mis-set.
2416                                  * Actually uses internal TMDS, clear the bit.
2417                                  */
2418                                 if (dev->pdev->device == 0x5159 &&
2419                                     dev->pdev->subsystem_vendor == 0x1014 &&
2420                                     dev->pdev->subsystem_device == 0x029A) {
2421                                         tmp &= ~(1 << 4);
2422                                 }
2423                                 if ((tmp >> 4) & 0x1) {
2424                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
2425                                         radeon_add_legacy_encoder(dev,
2426                                                                   radeon_get_encoder_enum
2427                                                                   (dev,
2428                                                                    ATOM_DEVICE_DFP2_SUPPORT,
2429                                                                    0),
2430                                                                   ATOM_DEVICE_DFP2_SUPPORT);
2431                                         connector_object_id = combios_check_dl_dvi(dev, 0);
2432                                 } else {
2433                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
2434                                         radeon_add_legacy_encoder(dev,
2435                                                                   radeon_get_encoder_enum
2436                                                                   (dev,
2437                                                                    ATOM_DEVICE_DFP1_SUPPORT,
2438                                                                    0),
2439                                                                   ATOM_DEVICE_DFP1_SUPPORT);
2440                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2441                                 }
2442                                 radeon_add_legacy_connector(dev,
2443                                                             i,
2444                                                             devices,
2445                                                             legacy_connector_convert
2446                                                             [connector],
2447                                                             &ddc_i2c,
2448                                                             connector_object_id,
2449                                                             &hpd);
2450                                 break;
2451                         case CONNECTOR_DVI_D_LEGACY:
2452                                 if ((tmp >> 4) & 0x1) {
2453                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2454                                         connector_object_id = combios_check_dl_dvi(dev, 1);
2455                                 } else {
2456                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2457                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2458                                 }
2459                                 radeon_add_legacy_encoder(dev,
2460                                                           radeon_get_encoder_enum
2461                                                           (dev, devices, 0),
2462                                                           devices);
2463                                 radeon_add_legacy_connector(dev, i, devices,
2464                                                             legacy_connector_convert
2465                                                             [connector],
2466                                                             &ddc_i2c,
2467                                                             connector_object_id,
2468                                                             &hpd);
2469                                 break;
2470                         case CONNECTOR_CTV_LEGACY:
2471                         case CONNECTOR_STV_LEGACY:
2472                                 radeon_add_legacy_encoder(dev,
2473                                                           radeon_get_encoder_enum
2474                                                           (dev,
2475                                                            ATOM_DEVICE_TV1_SUPPORT,
2476                                                            2),
2477                                                           ATOM_DEVICE_TV1_SUPPORT);
2478                                 radeon_add_legacy_connector(dev, i,
2479                                                             ATOM_DEVICE_TV1_SUPPORT,
2480                                                             legacy_connector_convert
2481                                                             [connector],
2482                                                             &ddc_i2c,
2483                                                             CONNECTOR_OBJECT_ID_SVIDEO,
2484                                                             &hpd);
2485                                 break;
2486                         default:
2487                                 DRM_ERROR("Unknown connector type: %d\n",
2488                                           connector);
2489                                 continue;
2490                         }
2491
2492                 }
2493         } else {
2494                 uint16_t tmds_info =
2495                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2496                 if (tmds_info) {
2497                         DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2498
2499                         radeon_add_legacy_encoder(dev,
2500                                                   radeon_get_encoder_enum(dev,
2501                                                                         ATOM_DEVICE_CRT1_SUPPORT,
2502                                                                         1),
2503                                                   ATOM_DEVICE_CRT1_SUPPORT);
2504                         radeon_add_legacy_encoder(dev,
2505                                                   radeon_get_encoder_enum(dev,
2506                                                                         ATOM_DEVICE_DFP1_SUPPORT,
2507                                                                         0),
2508                                                   ATOM_DEVICE_DFP1_SUPPORT);
2509
2510                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2511                         hpd.hpd = RADEON_HPD_1;
2512                         radeon_add_legacy_connector(dev,
2513                                                     0,
2514                                                     ATOM_DEVICE_CRT1_SUPPORT |
2515                                                     ATOM_DEVICE_DFP1_SUPPORT,
2516                                                     DRM_MODE_CONNECTOR_DVII,
2517                                                     &ddc_i2c,
2518                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2519                                                     &hpd);
2520                 } else {
2521                         uint16_t crt_info =
2522                                 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2523                         DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2524                         if (crt_info) {
2525                                 radeon_add_legacy_encoder(dev,
2526                                                           radeon_get_encoder_enum(dev,
2527                                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2528                                                                                 1),
2529                                                           ATOM_DEVICE_CRT1_SUPPORT);
2530                                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2531                                 hpd.hpd = RADEON_HPD_NONE;
2532                                 radeon_add_legacy_connector(dev,
2533                                                             0,
2534                                                             ATOM_DEVICE_CRT1_SUPPORT,
2535                                                             DRM_MODE_CONNECTOR_VGA,
2536                                                             &ddc_i2c,
2537                                                             CONNECTOR_OBJECT_ID_VGA,
2538                                                             &hpd);
2539                         } else {
2540                                 DRM_DEBUG_KMS("No connector info found\n");
2541                                 return false;
2542                         }
2543                 }
2544         }
2545
2546         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2547                 uint16_t lcd_info =
2548                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2549                 if (lcd_info) {
2550                         uint16_t lcd_ddc_info =
2551                             combios_get_table_offset(dev,
2552                                                      COMBIOS_LCD_DDC_INFO_TABLE);
2553
2554                         radeon_add_legacy_encoder(dev,
2555                                                   radeon_get_encoder_enum(dev,
2556                                                                         ATOM_DEVICE_LCD1_SUPPORT,
2557                                                                         0),
2558                                                   ATOM_DEVICE_LCD1_SUPPORT);
2559
2560                         if (lcd_ddc_info) {
2561                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
2562                                 switch (ddc_type) {
2563                                 case DDC_LCD:
2564                                         ddc_i2c =
2565                                                 combios_setup_i2c_bus(rdev,
2566                                                                       DDC_LCD,
2567                                                                       RBIOS32(lcd_ddc_info + 3),
2568                                                                       RBIOS32(lcd_ddc_info + 7));
2569                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2570                                         break;
2571                                 case DDC_GPIO:
2572                                         ddc_i2c =
2573                                                 combios_setup_i2c_bus(rdev,
2574                                                                       DDC_GPIO,
2575                                                                       RBIOS32(lcd_ddc_info + 3),
2576                                                                       RBIOS32(lcd_ddc_info + 7));
2577                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2578                                         break;
2579                                 default:
2580                                         ddc_i2c =
2581                                                 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2582                                         break;
2583                                 }
2584                                 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2585                         } else
2586                                 ddc_i2c.valid = false;
2587
2588                         hpd.hpd = RADEON_HPD_NONE;
2589                         radeon_add_legacy_connector(dev,
2590                                                     5,
2591                                                     ATOM_DEVICE_LCD1_SUPPORT,
2592                                                     DRM_MODE_CONNECTOR_LVDS,
2593                                                     &ddc_i2c,
2594                                                     CONNECTOR_OBJECT_ID_LVDS,
2595                                                     &hpd);
2596                 }
2597         }
2598
2599         /* check TV table */
2600         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2601                 uint32_t tv_info =
2602                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2603                 if (tv_info) {
2604                         if (RBIOS8(tv_info + 6) == 'T') {
2605                                 if (radeon_apply_legacy_tv_quirks(dev)) {
2606                                         hpd.hpd = RADEON_HPD_NONE;
2607                                         ddc_i2c.valid = false;
2608                                         radeon_add_legacy_encoder(dev,
2609                                                                   radeon_get_encoder_enum
2610                                                                   (dev,
2611                                                                    ATOM_DEVICE_TV1_SUPPORT,
2612                                                                    2),
2613                                                                   ATOM_DEVICE_TV1_SUPPORT);
2614                                         radeon_add_legacy_connector(dev, 6,
2615                                                                     ATOM_DEVICE_TV1_SUPPORT,
2616                                                                     DRM_MODE_CONNECTOR_SVIDEO,
2617                                                                     &ddc_i2c,
2618                                                                     CONNECTOR_OBJECT_ID_SVIDEO,
2619                                                                     &hpd);
2620                                 }
2621                         }
2622                 }
2623         }
2624
2625         radeon_link_encoder_connector(dev);
2626
2627         return true;
2628 }
2629
2630 static const char *thermal_controller_names[] = {
2631         "NONE",
2632         "lm63",
2633         "adm1032",
2634 };
2635
2636 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2637 {
2638         struct drm_device *dev = rdev->ddev;
2639         u16 offset, misc, misc2 = 0;
2640         u8 rev, blocks, tmp;
2641         int state_index = 0;
2642         struct radeon_i2c_bus_rec i2c_bus;
2643
2644         rdev->pm.default_power_state_index = -1;
2645
2646         /* allocate 2 power states */
2647         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2648         if (rdev->pm.power_state) {
2649                 /* allocate 1 clock mode per state */
2650                 rdev->pm.power_state[0].clock_info =
2651                         kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2652                 rdev->pm.power_state[1].clock_info =
2653                         kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2654                 if (!rdev->pm.power_state[0].clock_info ||
2655                     !rdev->pm.power_state[1].clock_info)
2656                         goto pm_failed;
2657         } else
2658                 goto pm_failed;
2659
2660         /* check for a thermal chip */
2661         offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2662         if (offset) {
2663                 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2664
2665                 rev = RBIOS8(offset);
2666
2667                 if (rev == 0) {
2668                         thermal_controller = RBIOS8(offset + 3);
2669                         gpio = RBIOS8(offset + 4) & 0x3f;
2670                         i2c_addr = RBIOS8(offset + 5);
2671                 } else if (rev == 1) {
2672                         thermal_controller = RBIOS8(offset + 4);
2673                         gpio = RBIOS8(offset + 5) & 0x3f;
2674                         i2c_addr = RBIOS8(offset + 6);
2675                 } else if (rev == 2) {
2676                         thermal_controller = RBIOS8(offset + 4);
2677                         gpio = RBIOS8(offset + 5) & 0x3f;
2678                         i2c_addr = RBIOS8(offset + 6);
2679                         clk_bit = RBIOS8(offset + 0xa);
2680                         data_bit = RBIOS8(offset + 0xb);
2681                 }
2682                 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2683                         DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2684                                  thermal_controller_names[thermal_controller],
2685                                  i2c_addr >> 1);
2686                         if (gpio == DDC_LCD) {
2687                                 /* MM i2c */
2688                                 i2c_bus.valid = true;
2689                                 i2c_bus.hw_capable = true;
2690                                 i2c_bus.mm_i2c = true;
2691                                 i2c_bus.i2c_id = 0xa0;
2692                         } else if (gpio == DDC_GPIO)
2693                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2694                         else
2695                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2696                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2697                         if (rdev->pm.i2c_bus) {
2698                                 struct i2c_board_info info = { };
2699                                 const char *name = thermal_controller_names[thermal_controller];
2700                                 info.addr = i2c_addr >> 1;
2701                                 strlcpy(info.type, name, sizeof(info.type));
2702                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2703                         }
2704                 }
2705         } else {
2706                 /* boards with a thermal chip, but no overdrive table */
2707
2708                 /* Asus 9600xt has an f75375 on the monid bus */
2709                 if ((dev->pdev->device == 0x4152) &&
2710                     (dev->pdev->subsystem_vendor == 0x1043) &&
2711                     (dev->pdev->subsystem_device == 0xc002)) {
2712                         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2713                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2714                         if (rdev->pm.i2c_bus) {
2715                                 struct i2c_board_info info = { };
2716                                 const char *name = "f75375";
2717                                 info.addr = 0x28;
2718                                 strlcpy(info.type, name, sizeof(info.type));
2719                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2720                                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2721                                          name, info.addr);
2722                         }
2723                 }
2724         }
2725
2726         if (rdev->flags & RADEON_IS_MOBILITY) {
2727                 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2728                 if (offset) {
2729                         rev = RBIOS8(offset);
2730                         blocks = RBIOS8(offset + 0x2);
2731                         /* power mode 0 tends to be the only valid one */
2732                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2733                         rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2734                         rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2735                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2736                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2737                                 goto default_mode;
2738                         rdev->pm.power_state[state_index].type =
2739                                 POWER_STATE_TYPE_BATTERY;
2740                         misc = RBIOS16(offset + 0x5 + 0x0);
2741                         if (rev > 4)
2742                                 misc2 = RBIOS16(offset + 0x5 + 0xe);
2743                         rdev->pm.power_state[state_index].misc = misc;
2744                         rdev->pm.power_state[state_index].misc2 = misc2;
2745                         if (misc & 0x4) {
2746                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2747                                 if (misc & 0x8)
2748                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2749                                                 true;
2750                                 else
2751                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2752                                                 false;
2753                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2754                                 if (rev < 6) {
2755                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2756                                                 RBIOS16(offset + 0x5 + 0xb) * 4;
2757                                         tmp = RBIOS8(offset + 0x5 + 0xd);
2758                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2759                                 } else {
2760                                         u8 entries = RBIOS8(offset + 0x5 + 0xb);
2761                                         u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2762                                         if (entries && voltage_table_offset) {
2763                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2764                                                         RBIOS16(voltage_table_offset) * 4;
2765                                                 tmp = RBIOS8(voltage_table_offset + 0x2);
2766                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2767                                         } else
2768                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2769                                 }
2770                                 switch ((misc2 & 0x700) >> 8) {
2771                                 case 0:
2772                                 default:
2773                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2774                                         break;
2775                                 case 1:
2776                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2777                                         break;
2778                                 case 2:
2779                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2780                                         break;
2781                                 case 3:
2782                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2783                                         break;
2784                                 case 4:
2785                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2786                                         break;
2787                                 }
2788                         } else
2789                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2790                         if (rev > 6)
2791                                 rdev->pm.power_state[state_index].pcie_lanes =
2792                                         RBIOS8(offset + 0x5 + 0x10);
2793                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2794                         state_index++;
2795                 } else {
2796                         /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2797                 }
2798         } else {
2799                 /* XXX figure out some good default low power mode for desktop cards */
2800         }
2801
2802 default_mode:
2803         /* add the default mode */
2804         rdev->pm.power_state[state_index].type =
2805                 POWER_STATE_TYPE_DEFAULT;
2806         rdev->pm.power_state[state_index].num_clock_modes = 1;
2807         rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2808         rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2809         rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2810         if ((state_index > 0) &&
2811             (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2812                 rdev->pm.power_state[state_index].clock_info[0].voltage =
2813                         rdev->pm.power_state[0].clock_info[0].voltage;
2814         else
2815                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2816         rdev->pm.power_state[state_index].pcie_lanes = 16;
2817         rdev->pm.power_state[state_index].flags = 0;
2818         rdev->pm.default_power_state_index = state_index;
2819         rdev->pm.num_power_states = state_index + 1;
2820
2821         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2822         rdev->pm.current_clock_mode_index = 0;
2823         return;
2824
2825 pm_failed:
2826         rdev->pm.default_power_state_index = state_index;
2827         rdev->pm.num_power_states = 0;
2828
2829         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2830         rdev->pm.current_clock_mode_index = 0;
2831 }
2832
2833 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2834 {
2835         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2836         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2837
2838         if (!tmds)
2839                 return;
2840
2841         switch (tmds->dvo_chip) {
2842         case DVO_SIL164:
2843                 /* sil 164 */
2844                 radeon_i2c_put_byte(tmds->i2c_bus,
2845                                     tmds->slave_addr,
2846                                     0x08, 0x30);
2847                 radeon_i2c_put_byte(tmds->i2c_bus,
2848                                        tmds->slave_addr,
2849                                        0x09, 0x00);
2850                 radeon_i2c_put_byte(tmds->i2c_bus,
2851                                     tmds->slave_addr,
2852                                     0x0a, 0x90);
2853                 radeon_i2c_put_byte(tmds->i2c_bus,
2854                                     tmds->slave_addr,
2855                                     0x0c, 0x89);
2856                 radeon_i2c_put_byte(tmds->i2c_bus,
2857                                        tmds->slave_addr,
2858                                        0x08, 0x3b);
2859                 break;
2860         case DVO_SIL1178:
2861                 /* sil 1178 - untested */
2862                 /*
2863                  * 0x0f, 0x44
2864                  * 0x0f, 0x4c
2865                  * 0x0e, 0x01
2866                  * 0x0a, 0x80
2867                  * 0x09, 0x30
2868                  * 0x0c, 0xc9
2869                  * 0x0d, 0x70
2870                  * 0x08, 0x32
2871                  * 0x08, 0x33
2872                  */
2873                 break;
2874         default:
2875                 break;
2876         }
2877
2878 }
2879
2880 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2881 {
2882         struct drm_device *dev = encoder->dev;
2883         struct radeon_device *rdev = dev->dev_private;
2884         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2885         uint16_t offset;
2886         uint8_t blocks, slave_addr, rev;
2887         uint32_t index, id;
2888         uint32_t reg, val, and_mask, or_mask;
2889         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2890
2891         if (!tmds)
2892                 return false;
2893
2894         if (rdev->flags & RADEON_IS_IGP) {
2895                 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2896                 rev = RBIOS8(offset);
2897                 if (offset) {
2898                         rev = RBIOS8(offset);
2899                         if (rev > 1) {
2900                                 blocks = RBIOS8(offset + 3);
2901                                 index = offset + 4;
2902                                 while (blocks > 0) {
2903                                         id = RBIOS16(index);
2904                                         index += 2;
2905                                         switch (id >> 13) {
2906                                         case 0:
2907                                                 reg = (id & 0x1fff) * 4;
2908                                                 val = RBIOS32(index);
2909                                                 index += 4;
2910                                                 WREG32(reg, val);
2911                                                 break;
2912                                         case 2:
2913                                                 reg = (id & 0x1fff) * 4;
2914                                                 and_mask = RBIOS32(index);
2915                                                 index += 4;
2916                                                 or_mask = RBIOS32(index);
2917                                                 index += 4;
2918                                                 val = RREG32(reg);
2919                                                 val = (val & and_mask) | or_mask;
2920                                                 WREG32(reg, val);
2921                                                 break;
2922                                         case 3:
2923                                                 val = RBIOS16(index);
2924                                                 index += 2;
2925                                                 udelay(val);
2926                                                 break;
2927                                         case 4:
2928                                                 val = RBIOS16(index);
2929                                                 index += 2;
2930                                                 udelay(val * 1000);
2931                                                 break;
2932                                         case 6:
2933                                                 slave_addr = id & 0xff;
2934                                                 slave_addr >>= 1; /* 7 bit addressing */
2935                                                 index++;
2936                                                 reg = RBIOS8(index);
2937                                                 index++;
2938                                                 val = RBIOS8(index);
2939                                                 index++;
2940                                                 radeon_i2c_put_byte(tmds->i2c_bus,
2941                                                                     slave_addr,
2942                                                                     reg, val);
2943                                                 break;
2944                                         default:
2945                                                 DRM_ERROR("Unknown id %d\n", id >> 13);
2946                                                 break;
2947                                         }
2948                                         blocks--;
2949                                 }
2950                                 return true;
2951                         }
2952                 }
2953         } else {
2954                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2955                 if (offset) {
2956                         index = offset + 10;
2957                         id = RBIOS16(index);
2958                         while (id != 0xffff) {
2959                                 index += 2;
2960                                 switch (id >> 13) {
2961                                 case 0:
2962                                         reg = (id & 0x1fff) * 4;
2963                                         val = RBIOS32(index);
2964                                         WREG32(reg, val);
2965                                         break;
2966                                 case 2:
2967                                         reg = (id & 0x1fff) * 4;
2968                                         and_mask = RBIOS32(index);
2969                                         index += 4;
2970                                         or_mask = RBIOS32(index);
2971                                         index += 4;
2972                                         val = RREG32(reg);
2973                                         val = (val & and_mask) | or_mask;
2974                                         WREG32(reg, val);
2975                                         break;
2976                                 case 4:
2977                                         val = RBIOS16(index);
2978                                         index += 2;
2979                                         udelay(val);
2980                                         break;
2981                                 case 5:
2982                                         reg = id & 0x1fff;
2983                                         and_mask = RBIOS32(index);
2984                                         index += 4;
2985                                         or_mask = RBIOS32(index);
2986                                         index += 4;
2987                                         val = RREG32_PLL(reg);
2988                                         val = (val & and_mask) | or_mask;
2989                                         WREG32_PLL(reg, val);
2990                                         break;
2991                                 case 6:
2992                                         reg = id & 0x1fff;
2993                                         val = RBIOS8(index);
2994                                         index += 1;
2995                                         radeon_i2c_put_byte(tmds->i2c_bus,
2996                                                             tmds->slave_addr,
2997                                                             reg, val);
2998                                         break;
2999                                 default:
3000                                         DRM_ERROR("Unknown id %d\n", id >> 13);
3001                                         break;
3002                                 }
3003                                 id = RBIOS16(index);
3004                         }
3005                         return true;
3006                 }
3007         }
3008         return false;
3009 }
3010
3011 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
3012 {
3013         struct radeon_device *rdev = dev->dev_private;
3014
3015         if (offset) {
3016                 while (RBIOS16(offset)) {
3017                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
3018                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
3019                         uint32_t val, and_mask, or_mask;
3020                         uint32_t tmp;
3021
3022                         offset += 2;
3023                         switch (cmd) {
3024                         case 0:
3025                                 val = RBIOS32(offset);
3026                                 offset += 4;
3027                                 WREG32(addr, val);
3028                                 break;
3029                         case 1:
3030                                 val = RBIOS32(offset);
3031                                 offset += 4;
3032                                 WREG32(addr, val);
3033                                 break;
3034                         case 2:
3035                                 and_mask = RBIOS32(offset);
3036                                 offset += 4;
3037                                 or_mask = RBIOS32(offset);
3038                                 offset += 4;
3039                                 tmp = RREG32(addr);
3040                                 tmp &= and_mask;
3041                                 tmp |= or_mask;
3042                                 WREG32(addr, tmp);
3043                                 break;
3044                         case 3:
3045                                 and_mask = RBIOS32(offset);
3046                                 offset += 4;
3047                                 or_mask = RBIOS32(offset);
3048                                 offset += 4;
3049                                 tmp = RREG32(addr);
3050                                 tmp &= and_mask;
3051                                 tmp |= or_mask;
3052                                 WREG32(addr, tmp);
3053                                 break;
3054                         case 4:
3055                                 val = RBIOS16(offset);
3056                                 offset += 2;
3057                                 udelay(val);
3058                                 break;
3059                         case 5:
3060                                 val = RBIOS16(offset);
3061                                 offset += 2;
3062                                 switch (addr) {
3063                                 case 8:
3064                                         while (val--) {
3065                                                 if (!
3066                                                     (RREG32_PLL
3067                                                      (RADEON_CLK_PWRMGT_CNTL) &
3068                                                      RADEON_MC_BUSY))
3069                                                         break;
3070                                         }
3071                                         break;
3072                                 case 9:
3073                                         while (val--) {
3074                                                 if ((RREG32(RADEON_MC_STATUS) &
3075                                                      RADEON_MC_IDLE))
3076                                                         break;
3077                                         }
3078                                         break;
3079                                 default:
3080                                         break;
3081                                 }
3082                                 break;
3083                         default:
3084                                 break;
3085                         }
3086                 }
3087         }
3088 }
3089
3090 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3091 {
3092         struct radeon_device *rdev = dev->dev_private;
3093
3094         if (offset) {
3095                 while (RBIOS8(offset)) {
3096                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3097                         uint8_t addr = (RBIOS8(offset) & 0x3f);
3098                         uint32_t val, shift, tmp;
3099                         uint32_t and_mask, or_mask;
3100
3101                         offset++;
3102                         switch (cmd) {
3103                         case 0:
3104                                 val = RBIOS32(offset);
3105                                 offset += 4;
3106                                 WREG32_PLL(addr, val);
3107                                 break;
3108                         case 1:
3109                                 shift = RBIOS8(offset) * 8;
3110                                 offset++;
3111                                 and_mask = RBIOS8(offset) << shift;
3112                                 and_mask |= ~(0xff << shift);
3113                                 offset++;
3114                                 or_mask = RBIOS8(offset) << shift;
3115                                 offset++;
3116                                 tmp = RREG32_PLL(addr);
3117                                 tmp &= and_mask;
3118                                 tmp |= or_mask;
3119                                 WREG32_PLL(addr, tmp);
3120                                 break;
3121                         case 2:
3122                         case 3:
3123                                 tmp = 1000;
3124                                 switch (addr) {
3125                                 case 1:
3126                                         udelay(150);
3127                                         break;
3128                                 case 2:
3129                                         udelay(1000);
3130                                         break;
3131                                 case 3:
3132                                         while (tmp--) {
3133                                                 if (!
3134                                                     (RREG32_PLL
3135                                                      (RADEON_CLK_PWRMGT_CNTL) &
3136                                                      RADEON_MC_BUSY))
3137                                                         break;
3138                                         }
3139                                         break;
3140                                 case 4:
3141                                         while (tmp--) {
3142                                                 if (RREG32_PLL
3143                                                     (RADEON_CLK_PWRMGT_CNTL) &
3144                                                     RADEON_DLL_READY)
3145                                                         break;
3146                                         }
3147                                         break;
3148                                 case 5:
3149                                         tmp =
3150                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3151                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
3152 #if 0
3153                                                 uint32_t mclk_cntl =
3154                                                     RREG32_PLL
3155                                                     (RADEON_MCLK_CNTL);
3156                                                 mclk_cntl &= 0xffff0000;
3157                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
3158                                                 WREG32_PLL(RADEON_MCLK_CNTL,
3159                                                            mclk_cntl);
3160                                                 udelay(10000);
3161 #endif
3162                                                 WREG32_PLL
3163                                                     (RADEON_CLK_PWRMGT_CNTL,
3164                                                      tmp &
3165                                                      ~RADEON_CG_NO1_DEBUG_0);
3166                                                 udelay(10000);
3167                                         }
3168                                         break;
3169                                 default:
3170                                         break;
3171                                 }
3172                                 break;
3173                         default:
3174                                 break;
3175                         }
3176                 }
3177         }
3178 }
3179
3180 static void combios_parse_ram_reset_table(struct drm_device *dev,
3181                                           uint16_t offset)
3182 {
3183         struct radeon_device *rdev = dev->dev_private;
3184         uint32_t tmp;
3185
3186         if (offset) {
3187                 uint8_t val = RBIOS8(offset);
3188                 while (val != 0xff) {
3189                         offset++;
3190
3191                         if (val == 0x0f) {
3192                                 uint32_t channel_complete_mask;
3193
3194                                 if (ASIC_IS_R300(rdev))
3195                                         channel_complete_mask =
3196                                             R300_MEM_PWRUP_COMPLETE;
3197                                 else
3198                                         channel_complete_mask =
3199                                             RADEON_MEM_PWRUP_COMPLETE;
3200                                 tmp = 20000;
3201                                 while (tmp--) {
3202                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
3203                                              channel_complete_mask) ==
3204                                             channel_complete_mask)
3205                                                 break;
3206                                 }
3207                         } else {
3208                                 uint32_t or_mask = RBIOS16(offset);
3209                                 offset += 2;
3210
3211                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3212                                 tmp &= RADEON_SDRAM_MODE_MASK;
3213                                 tmp |= or_mask;
3214                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3215
3216                                 or_mask = val << 24;
3217                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3218                                 tmp &= RADEON_B3MEM_RESET_MASK;
3219                                 tmp |= or_mask;
3220                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3221                         }
3222                         val = RBIOS8(offset);
3223                 }
3224         }
3225 }
3226
3227 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3228                                    int mem_addr_mapping)
3229 {
3230         struct radeon_device *rdev = dev->dev_private;
3231         uint32_t mem_cntl;
3232         uint32_t mem_size;
3233         uint32_t addr = 0;
3234
3235         mem_cntl = RREG32(RADEON_MEM_CNTL);
3236         if (mem_cntl & RV100_HALF_MODE)
3237                 ram /= 2;
3238         mem_size = ram;
3239         mem_cntl &= ~(0xff << 8);
3240         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3241         WREG32(RADEON_MEM_CNTL, mem_cntl);
3242         RREG32(RADEON_MEM_CNTL);
3243
3244         /* sdram reset ? */
3245
3246         /* something like this????  */
3247         while (ram--) {
3248                 addr = ram * 1024 * 1024;
3249                 /* write to each page */
3250                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3251                 WREG32(RADEON_MM_DATA, 0xdeadbeef);
3252                 /* read back and verify */
3253                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3254                 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
3255                         return 0;
3256         }
3257
3258         return mem_size;
3259 }
3260
3261 static void combios_write_ram_size(struct drm_device *dev)
3262 {
3263         struct radeon_device *rdev = dev->dev_private;
3264         uint8_t rev;
3265         uint16_t offset;
3266         uint32_t mem_size = 0;
3267         uint32_t mem_cntl = 0;
3268
3269         /* should do something smarter here I guess... */
3270         if (rdev->flags & RADEON_IS_IGP)
3271                 return;
3272
3273         /* first check detected mem table */
3274         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3275         if (offset) {
3276                 rev = RBIOS8(offset);
3277                 if (rev < 3) {
3278                         mem_cntl = RBIOS32(offset + 1);
3279                         mem_size = RBIOS16(offset + 5);
3280                         if ((rdev->family < CHIP_R200) &&
3281                             !ASIC_IS_RN50(rdev))
3282                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
3283                 }
3284         }
3285
3286         if (!mem_size) {
3287                 offset =
3288                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3289                 if (offset) {
3290                         rev = RBIOS8(offset - 1);
3291                         if (rev < 1) {
3292                                 if ((rdev->family < CHIP_R200)
3293                                     && !ASIC_IS_RN50(rdev)) {
3294                                         int ram = 0;
3295                                         int mem_addr_mapping = 0;
3296
3297                                         while (RBIOS8(offset)) {
3298                                                 ram = RBIOS8(offset);
3299                                                 mem_addr_mapping =
3300                                                     RBIOS8(offset + 1);
3301                                                 if (mem_addr_mapping != 0x25)
3302                                                         ram *= 2;
3303                                                 mem_size =
3304                                                     combios_detect_ram(dev, ram,
3305                                                                        mem_addr_mapping);
3306                                                 if (mem_size)
3307                                                         break;
3308                                                 offset += 2;
3309                                         }
3310                                 } else
3311                                         mem_size = RBIOS8(offset);
3312                         } else {
3313                                 mem_size = RBIOS8(offset);
3314                                 mem_size *= 2;  /* convert to MB */
3315                         }
3316                 }
3317         }
3318
3319         mem_size *= (1024 * 1024);      /* convert to bytes */
3320         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3321 }
3322
3323 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
3324 {
3325         uint16_t dyn_clk_info =
3326             combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3327
3328         if (dyn_clk_info)
3329                 combios_parse_pll_table(dev, dyn_clk_info);
3330 }
3331
3332 void radeon_combios_asic_init(struct drm_device *dev)
3333 {
3334         struct radeon_device *rdev = dev->dev_private;
3335         uint16_t table;
3336
3337         /* port hardcoded mac stuff from radeonfb */
3338         if (rdev->bios == NULL)
3339                 return;
3340
3341         /* ASIC INIT 1 */
3342         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3343         if (table)
3344                 combios_parse_mmio_table(dev, table);
3345
3346         /* PLL INIT */
3347         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3348         if (table)
3349                 combios_parse_pll_table(dev, table);
3350
3351         /* ASIC INIT 2 */
3352         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3353         if (table)
3354                 combios_parse_mmio_table(dev, table);
3355
3356         if (!(rdev->flags & RADEON_IS_IGP)) {
3357                 /* ASIC INIT 4 */
3358                 table =
3359                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3360                 if (table)
3361                         combios_parse_mmio_table(dev, table);
3362
3363                 /* RAM RESET */
3364                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3365                 if (table)
3366                         combios_parse_ram_reset_table(dev, table);
3367
3368                 /* ASIC INIT 3 */
3369                 table =
3370                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3371                 if (table)
3372                         combios_parse_mmio_table(dev, table);
3373
3374                 /* write CONFIG_MEMSIZE */
3375                 combios_write_ram_size(dev);
3376         }
3377
3378         /* quirk for rs4xx HP nx6125 laptop to make it resume
3379          * - it hangs on resume inside the dynclk 1 table.
3380          */
3381         if (rdev->family == CHIP_RS480 &&
3382             rdev->pdev->subsystem_vendor == 0x103c &&
3383             rdev->pdev->subsystem_device == 0x308b)
3384                 return;
3385
3386         /* quirk for rs4xx HP dv5000 laptop to make it resume
3387          * - it hangs on resume inside the dynclk 1 table.
3388          */
3389         if (rdev->family == CHIP_RS480 &&
3390             rdev->pdev->subsystem_vendor == 0x103c &&
3391             rdev->pdev->subsystem_device == 0x30a4)
3392                 return;
3393
3394         /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3395          * - it hangs on resume inside the dynclk 1 table.
3396          */
3397         if (rdev->family == CHIP_RS480 &&
3398             rdev->pdev->subsystem_vendor == 0x103c &&
3399             rdev->pdev->subsystem_device == 0x30ae)
3400                 return;
3401
3402         /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume
3403          * - it hangs on resume inside the dynclk 1 table.
3404          */
3405         if (rdev->family == CHIP_RS480 &&
3406             rdev->pdev->subsystem_vendor == 0x103c &&
3407             rdev->pdev->subsystem_device == 0x280a)
3408                 return;
3409
3410         /* DYN CLK 1 */
3411         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3412         if (table)
3413                 combios_parse_pll_table(dev, table);
3414
3415 }
3416
3417 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3418 {
3419         struct radeon_device *rdev = dev->dev_private;
3420         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3421
3422         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3423         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3424         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3425
3426         /* let the bios control the backlight */
3427         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3428
3429         /* tell the bios not to handle mode switching */
3430         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3431                            RADEON_ACC_MODE_CHANGE);
3432
3433         /* tell the bios a driver is loaded */
3434         bios_7_scratch |= RADEON_DRV_LOADED;
3435
3436         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3437         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3438         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3439 }
3440
3441 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3442 {
3443         struct drm_device *dev = encoder->dev;
3444         struct radeon_device *rdev = dev->dev_private;
3445         uint32_t bios_6_scratch;
3446
3447         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3448
3449         if (lock)
3450                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3451         else
3452                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3453
3454         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3455 }
3456
3457 void
3458 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3459                                       struct drm_encoder *encoder,
3460                                       bool connected)
3461 {
3462         struct drm_device *dev = connector->dev;
3463         struct radeon_device *rdev = dev->dev_private;
3464         struct radeon_connector *radeon_connector =
3465             to_radeon_connector(connector);
3466         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3467         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3468         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3469
3470         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3471             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3472                 if (connected) {
3473                         DRM_DEBUG_KMS("TV1 connected\n");
3474                         /* fix me */
3475                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3476                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3477                         bios_5_scratch |= RADEON_TV1_ON;
3478                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
3479                 } else {
3480                         DRM_DEBUG_KMS("TV1 disconnected\n");
3481                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3482                         bios_5_scratch &= ~RADEON_TV1_ON;
3483                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3484                 }
3485         }
3486         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3487             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3488                 if (connected) {
3489                         DRM_DEBUG_KMS("LCD1 connected\n");
3490                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
3491                         bios_5_scratch |= RADEON_LCD1_ON;
3492                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3493                 } else {
3494                         DRM_DEBUG_KMS("LCD1 disconnected\n");
3495                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3496                         bios_5_scratch &= ~RADEON_LCD1_ON;
3497                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3498                 }
3499         }
3500         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3501             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3502                 if (connected) {
3503                         DRM_DEBUG_KMS("CRT1 connected\n");
3504                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3505                         bios_5_scratch |= RADEON_CRT1_ON;
3506                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3507                 } else {
3508                         DRM_DEBUG_KMS("CRT1 disconnected\n");
3509                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3510                         bios_5_scratch &= ~RADEON_CRT1_ON;
3511                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3512                 }
3513         }
3514         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3515             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3516                 if (connected) {
3517                         DRM_DEBUG_KMS("CRT2 connected\n");
3518                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3519                         bios_5_scratch |= RADEON_CRT2_ON;
3520                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3521                 } else {
3522                         DRM_DEBUG_KMS("CRT2 disconnected\n");
3523                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3524                         bios_5_scratch &= ~RADEON_CRT2_ON;
3525                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3526                 }
3527         }
3528         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3529             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3530                 if (connected) {
3531                         DRM_DEBUG_KMS("DFP1 connected\n");
3532                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
3533                         bios_5_scratch |= RADEON_DFP1_ON;
3534                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3535                 } else {
3536                         DRM_DEBUG_KMS("DFP1 disconnected\n");
3537                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3538                         bios_5_scratch &= ~RADEON_DFP1_ON;
3539                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3540                 }
3541         }
3542         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3543             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3544                 if (connected) {
3545                         DRM_DEBUG_KMS("DFP2 connected\n");
3546                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
3547                         bios_5_scratch |= RADEON_DFP2_ON;
3548                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3549                 } else {
3550                         DRM_DEBUG_KMS("DFP2 disconnected\n");
3551                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3552                         bios_5_scratch &= ~RADEON_DFP2_ON;
3553                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3554                 }
3555         }
3556         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3557         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3558 }
3559
3560 void
3561 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3562 {
3563         struct drm_device *dev = encoder->dev;
3564         struct radeon_device *rdev = dev->dev_private;
3565         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3566         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3567
3568         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3569                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3570                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3571         }
3572         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3573                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3574                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3575         }
3576         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3577                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3578                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3579         }
3580         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3581                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3582                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3583         }
3584         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3585                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3586                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3587         }
3588         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3589                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3590                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3591         }
3592         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3593 }
3594
3595 void
3596 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3597 {
3598         struct drm_device *dev = encoder->dev;
3599         struct radeon_device *rdev = dev->dev_private;
3600         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3601         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3602
3603         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3604                 if (on)
3605                         bios_6_scratch |= RADEON_TV_DPMS_ON;
3606                 else
3607                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3608         }
3609         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3610                 if (on)
3611                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
3612                 else
3613                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3614         }
3615         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3616                 if (on)
3617                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
3618                 else
3619                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3620         }
3621         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3622                 if (on)
3623                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
3624                 else
3625                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3626         }
3627         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3628 }