drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif /* CONFIG_PPC_PMAC */
  39
  40 /* from radeon_encoder.c */
  41 extern uint32_t
  42 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  43                       uint8_t dac);
  44 extern void radeon_link_encoder_connector(struct drm_device *dev);
  45
  46 /* from radeon_connector.c */
  47 extern void
  48 radeon_add_legacy_connector(struct drm_device *dev,
  49                             uint32_t connector_id,
  50                             uint32_t supported_device,
  51                             int connector_type,
  52                             struct radeon_i2c_bus_rec *i2c_bus);
  53
  54 /* from radeon_legacy_encoder.c */
  55 extern void
  56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  57                           uint32_t supported_device);
  58
  59 /* old legacy ATI BIOS routines */
  60
  61 /* COMBIOS table offsets */
  62 enum radeon_combios_table_offset {
  63         /* absolute offset tables */
  64         COMBIOS_ASIC_INIT_1_TABLE,
  65         COMBIOS_BIOS_SUPPORT_TABLE,
  66         COMBIOS_DAC_PROGRAMMING_TABLE,
  67         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  68         COMBIOS_CRTC_INFO_TABLE,
  69         COMBIOS_PLL_INFO_TABLE,
  70         COMBIOS_TV_INFO_TABLE,
  71         COMBIOS_DFP_INFO_TABLE,
  72         COMBIOS_HW_CONFIG_INFO_TABLE,
  73         COMBIOS_MULTIMEDIA_INFO_TABLE,
  74         COMBIOS_TV_STD_PATCH_TABLE,
  75         COMBIOS_LCD_INFO_TABLE,
  76         COMBIOS_MOBILE_INFO_TABLE,
  77         COMBIOS_PLL_INIT_TABLE,
  78         COMBIOS_MEM_CONFIG_TABLE,
  79         COMBIOS_SAVE_MASK_TABLE,
  80         COMBIOS_HARDCODED_EDID_TABLE,
  81         COMBIOS_ASIC_INIT_2_TABLE,
  82         COMBIOS_CONNECTOR_INFO_TABLE,
  83         COMBIOS_DYN_CLK_1_TABLE,
  84         COMBIOS_RESERVED_MEM_TABLE,
  85         COMBIOS_EXT_TMDS_INFO_TABLE,
  86         COMBIOS_MEM_CLK_INFO_TABLE,
  87         COMBIOS_EXT_DAC_INFO_TABLE,
  88         COMBIOS_MISC_INFO_TABLE,
  89         COMBIOS_CRT_INFO_TABLE,
  90         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  91         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  92         COMBIOS_FAN_SPEED_INFO_TABLE,
  93         COMBIOS_OVERDRIVE_INFO_TABLE,
  94         COMBIOS_OEM_INFO_TABLE,
  95         COMBIOS_DYN_CLK_2_TABLE,
  96         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  97         COMBIOS_I2C_INFO_TABLE,
  98         /* relative offset tables */
  99         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
 100         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
 101         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
 102         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
 103         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
 104         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
 105         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
 106         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
 107         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
 108         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
 109         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
 110 };
 111
 112 enum radeon_combios_ddc {
 113         DDC_NONE_DETECTED,
 114         DDC_MONID,
 115         DDC_DVI,
 116         DDC_VGA,
 117         DDC_CRT2,
 118         DDC_LCD,
 119         DDC_GPIO,
 120 };
 121
 122 enum radeon_combios_connector {
 123         CONNECTOR_NONE_LEGACY,
 124         CONNECTOR_PROPRIETARY_LEGACY,
 125         CONNECTOR_CRT_LEGACY,
 126         CONNECTOR_DVI_I_LEGACY,
 127         CONNECTOR_DVI_D_LEGACY,
 128         CONNECTOR_CTV_LEGACY,
 129         CONNECTOR_STV_LEGACY,
 130         CONNECTOR_UNSUPPORTED_LEGACY
 131 };
 132
 133 const int legacy_connector_convert[] = {
 134         DRM_MODE_CONNECTOR_Unknown,
 135         DRM_MODE_CONNECTOR_DVID,
 136         DRM_MODE_CONNECTOR_VGA,
 137         DRM_MODE_CONNECTOR_DVII,
 138         DRM_MODE_CONNECTOR_DVID,
 139         DRM_MODE_CONNECTOR_Composite,
 140         DRM_MODE_CONNECTOR_SVIDEO,
 141         DRM_MODE_CONNECTOR_Unknown,
 142 };
 143
 144 static uint16_t combios_get_table_offset(struct drm_device *dev,
 145                                          enum radeon_combios_table_offset table)
 146 {
 147         struct radeon_device *rdev = dev->dev_private;
 148         int rev;
 149         uint16_t offset = 0, check_offset;
 150
 151         switch (table) {
 152                 /* absolute offset tables */
 153         case COMBIOS_ASIC_INIT_1_TABLE:
 154                 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
 155                 if (check_offset)
 156                         offset = check_offset;
 157                 break;
 158         case COMBIOS_BIOS_SUPPORT_TABLE:
 159                 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
 160                 if (check_offset)
 161                         offset = check_offset;
 162                 break;
 163         case COMBIOS_DAC_PROGRAMMING_TABLE:
 164                 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
 165                 if (check_offset)
 166                         offset = check_offset;
 167                 break;
 168         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 169                 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
 170                 if (check_offset)
 171                         offset = check_offset;
 172                 break;
 173         case COMBIOS_CRTC_INFO_TABLE:
 174                 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
 175                 if (check_offset)
 176                         offset = check_offset;
 177                 break;
 178         case COMBIOS_PLL_INFO_TABLE:
 179                 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
 180                 if (check_offset)
 181                         offset = check_offset;
 182                 break;
 183         case COMBIOS_TV_INFO_TABLE:
 184                 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
 185                 if (check_offset)
 186                         offset = check_offset;
 187                 break;
 188         case COMBIOS_DFP_INFO_TABLE:
 189                 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
 190                 if (check_offset)
 191                         offset = check_offset;
 192                 break;
 193         case COMBIOS_HW_CONFIG_INFO_TABLE:
 194                 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
 195                 if (check_offset)
 196                         offset = check_offset;
 197                 break;
 198         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 199                 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
 200                 if (check_offset)
 201                         offset = check_offset;
 202                 break;
 203         case COMBIOS_TV_STD_PATCH_TABLE:
 204                 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
 205                 if (check_offset)
 206                         offset = check_offset;
 207                 break;
 208         case COMBIOS_LCD_INFO_TABLE:
 209                 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
 210                 if (check_offset)
 211                         offset = check_offset;
 212                 break;
 213         case COMBIOS_MOBILE_INFO_TABLE:
 214                 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
 215                 if (check_offset)
 216                         offset = check_offset;
 217                 break;
 218         case COMBIOS_PLL_INIT_TABLE:
 219                 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
 220                 if (check_offset)
 221                         offset = check_offset;
 222                 break;
 223         case COMBIOS_MEM_CONFIG_TABLE:
 224                 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
 225                 if (check_offset)
 226                         offset = check_offset;
 227                 break;
 228         case COMBIOS_SAVE_MASK_TABLE:
 229                 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
 230                 if (check_offset)
 231                         offset = check_offset;
 232                 break;
 233         case COMBIOS_HARDCODED_EDID_TABLE:
 234                 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
 235                 if (check_offset)
 236                         offset = check_offset;
 237                 break;
 238         case COMBIOS_ASIC_INIT_2_TABLE:
 239                 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
 240                 if (check_offset)
 241                         offset = check_offset;
 242                 break;
 243         case COMBIOS_CONNECTOR_INFO_TABLE:
 244                 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
 245                 if (check_offset)
 246                         offset = check_offset;
 247                 break;
 248         case COMBIOS_DYN_CLK_1_TABLE:
 249                 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
 250                 if (check_offset)
 251                         offset = check_offset;
 252                 break;
 253         case COMBIOS_RESERVED_MEM_TABLE:
 254                 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
 255                 if (check_offset)
 256                         offset = check_offset;
 257                 break;
 258         case COMBIOS_EXT_TMDS_INFO_TABLE:
 259                 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
 260                 if (check_offset)
 261                         offset = check_offset;
 262                 break;
 263         case COMBIOS_MEM_CLK_INFO_TABLE:
 264                 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
 265                 if (check_offset)
 266                         offset = check_offset;
 267                 break;
 268         case COMBIOS_EXT_DAC_INFO_TABLE:
 269                 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
 270                 if (check_offset)
 271                         offset = check_offset;
 272                 break;
 273         case COMBIOS_MISC_INFO_TABLE:
 274                 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
 275                 if (check_offset)
 276                         offset = check_offset;
 277                 break;
 278         case COMBIOS_CRT_INFO_TABLE:
 279                 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
 280                 if (check_offset)
 281                         offset = check_offset;
 282                 break;
 283         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 284                 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
 285                 if (check_offset)
 286                         offset = check_offset;
 287                 break;
 288         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 289                 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
 290                 if (check_offset)
 291                         offset = check_offset;
 292                 break;
 293         case COMBIOS_FAN_SPEED_INFO_TABLE:
 294                 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
 295                 if (check_offset)
 296                         offset = check_offset;
 297                 break;
 298         case COMBIOS_OVERDRIVE_INFO_TABLE:
 299                 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
 300                 if (check_offset)
 301                         offset = check_offset;
 302                 break;
 303         case COMBIOS_OEM_INFO_TABLE:
 304                 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
 305                 if (check_offset)
 306                         offset = check_offset;
 307                 break;
 308         case COMBIOS_DYN_CLK_2_TABLE:
 309                 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
 310                 if (check_offset)
 311                         offset = check_offset;
 312                 break;
 313         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 314                 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
 315                 if (check_offset)
 316                         offset = check_offset;
 317                 break;
 318         case COMBIOS_I2C_INFO_TABLE:
 319                 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
 320                 if (check_offset)
 321                         offset = check_offset;
 322                 break;
 323                 /* relative offset tables */
 324         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 325                 check_offset =
 326                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 327                 if (check_offset) {
 328                         rev = RBIOS8(check_offset);
 329                         if (rev > 0) {
 330                                 check_offset = RBIOS16(check_offset + 0x3);
 331                                 if (check_offset)
 332                                         offset = check_offset;
 333                         }
 334                 }
 335                 break;
 336         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 337                 check_offset =
 338                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 339                 if (check_offset) {
 340                         rev = RBIOS8(check_offset);
 341                         if (rev > 0) {
 342                                 check_offset = RBIOS16(check_offset + 0x5);
 343                                 if (check_offset)
 344                                         offset = check_offset;
 345                         }
 346                 }
 347                 break;
 348         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 349                 check_offset =
 350                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 351                 if (check_offset) {
 352                         rev = RBIOS8(check_offset);
 353                         if (rev > 0) {
 354                                 check_offset = RBIOS16(check_offset + 0x7);
 355                                 if (check_offset)
 356                                         offset = check_offset;
 357                         }
 358                 }
 359                 break;
 360         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 361                 check_offset =
 362                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 363                 if (check_offset) {
 364                         rev = RBIOS8(check_offset);
 365                         if (rev == 2) {
 366                                 check_offset = RBIOS16(check_offset + 0x9);
 367                                 if (check_offset)
 368                                         offset = check_offset;
 369                         }
 370                 }
 371                 break;
 372         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 373                 check_offset =
 374                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 375                 if (check_offset) {
 376                         while (RBIOS8(check_offset++));
 377                         check_offset += 2;
 378                         if (check_offset)
 379                                 offset = check_offset;
 380                 }
 381                 break;
 382         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 383                 check_offset =
 384                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 385                 if (check_offset) {
 386                         check_offset = RBIOS16(check_offset + 0x11);
 387                         if (check_offset)
 388                                 offset = check_offset;
 389                 }
 390                 break;
 391         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 392                 check_offset =
 393                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 394                 if (check_offset) {
 395                         check_offset = RBIOS16(check_offset + 0x13);
 396                         if (check_offset)
 397                                 offset = check_offset;
 398                 }
 399                 break;
 400         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 401                 check_offset =
 402                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 403                 if (check_offset) {
 404                         check_offset = RBIOS16(check_offset + 0x15);
 405                         if (check_offset)
 406                                 offset = check_offset;
 407                 }
 408                 break;
 409         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 410                 check_offset =
 411                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 412                 if (check_offset) {
 413                         check_offset = RBIOS16(check_offset + 0x17);
 414                         if (check_offset)
 415                                 offset = check_offset;
 416                 }
 417                 break;
 418         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 419                 check_offset =
 420                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 421                 if (check_offset) {
 422                         check_offset = RBIOS16(check_offset + 0x2);
 423                         if (check_offset)
 424                                 offset = check_offset;
 425                 }
 426                 break;
 427         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 428                 check_offset =
 429                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 430                 if (check_offset) {
 431                         check_offset = RBIOS16(check_offset + 0x4);
 432                         if (check_offset)
 433                                 offset = check_offset;
 434                 }
 435                 break;
 436         default:
 437                 break;
 438         }
 439
 440         return offset;
 441
 442 }
 443
 444 struct radeon_i2c_bus_rec combios_setup_i2c_bus(int ddc_line)
 445 {
 446         struct radeon_i2c_bus_rec i2c;
 447
 448         i2c.mask_clk_mask = RADEON_GPIO_EN_1;
 449         i2c.mask_data_mask = RADEON_GPIO_EN_0;
 450         i2c.a_clk_mask = RADEON_GPIO_A_1;
 451         i2c.a_data_mask = RADEON_GPIO_A_0;
 452         i2c.put_clk_mask = RADEON_GPIO_EN_1;
 453         i2c.put_data_mask = RADEON_GPIO_EN_0;
 454         i2c.get_clk_mask = RADEON_GPIO_Y_1;
 455         i2c.get_data_mask = RADEON_GPIO_Y_0;
 456         if ((ddc_line == RADEON_LCD_GPIO_MASK) ||
 457             (ddc_line == RADEON_MDGPIO_EN_REG)) {
 458                 i2c.mask_clk_reg = ddc_line;
 459                 i2c.mask_data_reg = ddc_line;
 460                 i2c.a_clk_reg = ddc_line;
 461                 i2c.a_data_reg = ddc_line;
 462                 i2c.put_clk_reg = ddc_line;
 463                 i2c.put_data_reg = ddc_line;
 464                 i2c.get_clk_reg = ddc_line + 4;
 465                 i2c.get_data_reg = ddc_line + 4;
 466         } else {
 467                 i2c.mask_clk_reg = ddc_line;
 468                 i2c.mask_data_reg = ddc_line;
 469                 i2c.a_clk_reg = ddc_line;
 470                 i2c.a_data_reg = ddc_line;
 471                 i2c.put_clk_reg = ddc_line;
 472                 i2c.put_data_reg = ddc_line;
 473                 i2c.get_clk_reg = ddc_line;
 474                 i2c.get_data_reg = ddc_line;
 475         }
 476
 477         if (ddc_line)
 478                 i2c.valid = true;
 479         else
 480                 i2c.valid = false;
 481
 482         return i2c;
 483 }
 484
 485 bool radeon_combios_get_clock_info(struct drm_device *dev)
 486 {
 487         struct radeon_device *rdev = dev->dev_private;
 488         uint16_t pll_info;
 489         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 490         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 491         struct radeon_pll *spll = &rdev->clock.spll;
 492         struct radeon_pll *mpll = &rdev->clock.mpll;
 493         int8_t rev;
 494         uint16_t sclk, mclk;
 495
 496         if (rdev->bios == NULL)
 497                 return NULL;
 498
 499         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 500         if (pll_info) {
 501                 rev = RBIOS8(pll_info);
 502
 503                 /* pixel clocks */
 504                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 505                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 506                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 507                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 508
 509                 if (rev > 9) {
 510                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 511                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 512                 } else {
 513                         p1pll->pll_in_min = 40;
 514                         p1pll->pll_in_max = 500;
 515                 }
 516                 *p2pll = *p1pll;
 517
 518                 /* system clock */
 519                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 520                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 521                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 522                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 523
 524                 if (rev > 10) {
 525                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 526                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 527                 } else {
 528                         /* ??? */
 529                         spll->pll_in_min = 40;
 530                         spll->pll_in_max = 500;
 531                 }
 532
 533                 /* memory clock */
 534                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 535                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 536                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 537                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 538
 539                 if (rev > 10) {
 540                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 541                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 542                 } else {
 543                         /* ??? */
 544                         mpll->pll_in_min = 40;
 545                         mpll->pll_in_max = 500;
 546                 }
 547
 548                 /* default sclk/mclk */
 549                 sclk = RBIOS16(pll_info + 0xa);
 550                 mclk = RBIOS16(pll_info + 0x8);
 551                 if (sclk == 0)
 552                         sclk = 200 * 100;
 553                 if (mclk == 0)
 554                         mclk = 200 * 100;
 555
 556                 rdev->clock.default_sclk = sclk;
 557                 rdev->clock.default_mclk = mclk;
 558
 559                 return true;
 560         }
 561         return false;
 562 }
 563
 564 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 565                                                                        radeon_encoder
 566                                                                        *encoder)
 567 {
 568         struct drm_device *dev = encoder->base.dev;
 569         struct radeon_device *rdev = dev->dev_private;
 570         uint16_t dac_info;
 571         uint8_t rev, bg, dac;
 572         struct radeon_encoder_primary_dac *p_dac = NULL;
 573
 574         if (rdev->bios == NULL)
 575                 return NULL;
 576
 577         /* check CRT table */
 578         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 579         if (dac_info) {
 580                 p_dac =
 581                     kzalloc(sizeof(struct radeon_encoder_primary_dac),
 582                             GFP_KERNEL);
 583
 584                 if (!p_dac)
 585                         return NULL;
 586
 587                 rev = RBIOS8(dac_info) & 0x3;
 588                 if (rev < 2) {
 589                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 590                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 591                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 592                 } else {
 593                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 594                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 595                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 596                 }
 597
 598         }
 599
 600         return p_dac;
 601 }
 602
 603 static enum radeon_tv_std
 604 radeon_combios_get_tv_info(struct radeon_encoder *encoder)
 605 {
 606         struct drm_device *dev = encoder->base.dev;
 607         struct radeon_device *rdev = dev->dev_private;
 608         uint16_t tv_info;
 609         enum radeon_tv_std tv_std = TV_STD_NTSC;
 610
 611         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 612         if (tv_info) {
 613                 if (RBIOS8(tv_info + 6) == 'T') {
 614                         switch (RBIOS8(tv_info + 7) & 0xf) {
 615                         case 1:
 616                                 tv_std = TV_STD_NTSC;
 617                                 DRM_INFO("Default TV standard: NTSC\n");
 618                                 break;
 619                         case 2:
 620                                 tv_std = TV_STD_PAL;
 621                                 DRM_INFO("Default TV standard: PAL\n");
 622                                 break;
 623                         case 3:
 624                                 tv_std = TV_STD_PAL_M;
 625                                 DRM_INFO("Default TV standard: PAL-M\n");
 626                                 break;
 627                         case 4:
 628                                 tv_std = TV_STD_PAL_60;
 629                                 DRM_INFO("Default TV standard: PAL-60\n");
 630                                 break;
 631                         case 5:
 632                                 tv_std = TV_STD_NTSC_J;
 633                                 DRM_INFO("Default TV standard: NTSC-J\n");
 634                                 break;
 635                         case 6:
 636                                 tv_std = TV_STD_SCART_PAL;
 637                                 DRM_INFO("Default TV standard: SCART-PAL\n");
 638                                 break;
 639                         default:
 640                                 tv_std = TV_STD_NTSC;
 641                                 DRM_INFO
 642                                     ("Unknown TV standard; defaulting to NTSC\n");
 643                                 break;
 644                         }
 645
 646                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
 647                         case 0:
 648                                 DRM_INFO("29.498928713 MHz TV ref clk\n");
 649                                 break;
 650                         case 1:
 651                                 DRM_INFO("28.636360000 MHz TV ref clk\n");
 652                                 break;
 653                         case 2:
 654                                 DRM_INFO("14.318180000 MHz TV ref clk\n");
 655                                 break;
 656                         case 3:
 657                                 DRM_INFO("27.000000000 MHz TV ref clk\n");
 658                                 break;
 659                         default:
 660                                 break;
 661                         }
 662                 }
 663         }
 664         return tv_std;
 665 }
 666
 667 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
 668         0x00000000,             /* r100  */
 669         0x00280000,             /* rv100 */
 670         0x00000000,             /* rs100 */
 671         0x00880000,             /* rv200 */
 672         0x00000000,             /* rs200 */
 673         0x00000000,             /* r200  */
 674         0x00770000,             /* rv250 */
 675         0x00290000,             /* rs300 */
 676         0x00560000,             /* rv280 */
 677         0x00780000,             /* r300  */
 678         0x00770000,             /* r350  */
 679         0x00780000,             /* rv350 */
 680         0x00780000,             /* rv380 */
 681         0x01080000,             /* r420  */
 682         0x01080000,             /* r423  */
 683         0x01080000,             /* rv410 */
 684         0x00780000,             /* rs400 */
 685         0x00780000,             /* rs480 */
 686 };
 687
 688 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
 689                                                      struct radeon_encoder_tv_dac *tv_dac)
 690 {
 691         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
 692         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
 693                 tv_dac->ps2_tvdac_adj = 0x00880000;
 694         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 695         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 696         return;
 697 }
 698
 699 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
 700                                                              radeon_encoder
 701                                                              *encoder)
 702 {
 703         struct drm_device *dev = encoder->base.dev;
 704         struct radeon_device *rdev = dev->dev_private;
 705         uint16_t dac_info;
 706         uint8_t rev, bg, dac;
 707         struct radeon_encoder_tv_dac *tv_dac = NULL;
 708         int found = 0;
 709
 710         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
 711         if (!tv_dac)
 712                 return NULL;
 713
 714         if (rdev->bios == NULL)
 715                 goto out;
 716
 717         /* first check TV table */
 718         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 719         if (dac_info) {
 720                 rev = RBIOS8(dac_info + 0x3);
 721                 if (rev > 4) {
 722                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 723                         dac = RBIOS8(dac_info + 0xd) & 0xf;
 724                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 725
 726                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 727                         dac = RBIOS8(dac_info + 0xf) & 0xf;
 728                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 729
 730                         bg = RBIOS8(dac_info + 0x10) & 0xf;
 731                         dac = RBIOS8(dac_info + 0x11) & 0xf;
 732                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 733                         found = 1;
 734                 } else if (rev > 1) {
 735                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 736                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
 737                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 738
 739                         bg = RBIOS8(dac_info + 0xd) & 0xf;
 740                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
 741                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 742
 743                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 744                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
 745                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 746                         found = 1;
 747                 }
 748                 tv_dac->tv_std = radeon_combios_get_tv_info(encoder);
 749         }
 750         if (!found) {
 751                 /* then check CRT table */
 752                 dac_info =
 753                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 754                 if (dac_info) {
 755                         rev = RBIOS8(dac_info) & 0x3;
 756                         if (rev < 2) {
 757                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
 758                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
 759                                 tv_dac->ps2_tvdac_adj =
 760                                     (bg << 16) | (dac << 20);
 761                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 762                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 763                                 found = 1;
 764                         } else {
 765                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
 766                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
 767                                 tv_dac->ps2_tvdac_adj =
 768                                     (bg << 16) | (dac << 20);
 769                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 770                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 771                                 found = 1;
 772                         }
 773                 } else {
 774                         DRM_INFO("No TV DAC info found in BIOS\n");
 775                 }
 776         }
 777
 778 out:
 779         if (!found) /* fallback to defaults */
 780                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
 781
 782         return tv_dac;
 783 }
 784
 785 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
 786                                                                          radeon_device
 787                                                                          *rdev)
 788 {
 789         struct radeon_encoder_lvds *lvds = NULL;
 790         uint32_t fp_vert_stretch, fp_horz_stretch;
 791         uint32_t ppll_div_sel, ppll_val;
 792         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
 793
 794         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
 795
 796         if (!lvds)
 797                 return NULL;
 798
 799         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
 800         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
 801
 802         /* These should be fail-safe defaults, fingers crossed */
 803         lvds->panel_pwr_delay = 200;
 804         lvds->panel_vcc_delay = 2000;
 805
 806         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 807         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
 808         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
 809
 810         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
 811                 lvds->native_mode.panel_yres =
 812                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
 813                      RADEON_VERT_PANEL_SHIFT) + 1;
 814         else
 815                 lvds->native_mode.panel_yres =
 816                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
 817
 818         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
 819                 lvds->native_mode.panel_xres =
 820                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
 821                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
 822         else
 823                 lvds->native_mode.panel_xres =
 824                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
 825
 826         if ((lvds->native_mode.panel_xres < 640) ||
 827             (lvds->native_mode.panel_yres < 480)) {
 828                 lvds->native_mode.panel_xres = 640;
 829                 lvds->native_mode.panel_yres = 480;
 830         }
 831
 832         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
 833         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
 834         if ((ppll_val & 0x000707ff) == 0x1bb)
 835                 lvds->use_bios_dividers = false;
 836         else {
 837                 lvds->panel_ref_divider =
 838                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
 839                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
 840                 lvds->panel_fb_divider = ppll_val & 0x7ff;
 841
 842                 if ((lvds->panel_ref_divider != 0) &&
 843                     (lvds->panel_fb_divider > 3))
 844                         lvds->use_bios_dividers = true;
 845         }
 846         lvds->panel_vcc_delay = 200;
 847
 848         DRM_INFO("Panel info derived from registers\n");
 849         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres,
 850                  lvds->native_mode.panel_yres);
 851
 852         return lvds;
 853 }
 854
 855 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
 856                                                          *encoder)
 857 {
 858         struct drm_device *dev = encoder->base.dev;
 859         struct radeon_device *rdev = dev->dev_private;
 860         uint16_t lcd_info;
 861         uint32_t panel_setup;
 862         char stmp[30];
 863         int tmp, i;
 864         struct radeon_encoder_lvds *lvds = NULL;
 865
 866         if (rdev->bios == NULL)
 867                 return radeon_legacy_get_lvds_info_from_regs(rdev);
 868
 869         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
 870
 871         if (lcd_info) {
 872                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
 873
 874                 if (!lvds)
 875                         return NULL;
 876
 877                 for (i = 0; i < 24; i++)
 878                         stmp[i] = RBIOS8(lcd_info + i + 1);
 879                 stmp[24] = 0;
 880
 881                 DRM_INFO("Panel ID String: %s\n", stmp);
 882
 883                 lvds->native_mode.panel_xres = RBIOS16(lcd_info + 0x19);
 884                 lvds->native_mode.panel_yres = RBIOS16(lcd_info + 0x1b);
 885
 886                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres,
 887                          lvds->native_mode.panel_yres);
 888
 889                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
 890                 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0)
 891                         lvds->panel_vcc_delay = 2000;
 892
 893                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
 894                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
 895                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
 896
 897                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
 898                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
 899                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
 900                 if ((lvds->panel_ref_divider != 0) &&
 901                     (lvds->panel_fb_divider > 3))
 902                         lvds->use_bios_dividers = true;
 903
 904                 panel_setup = RBIOS32(lcd_info + 0x39);
 905                 lvds->lvds_gen_cntl = 0xff00;
 906                 if (panel_setup & 0x1)
 907                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
 908
 909                 if ((panel_setup >> 4) & 0x1)
 910                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
 911
 912                 switch ((panel_setup >> 8) & 0x7) {
 913                 case 0:
 914                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
 915                         break;
 916                 case 1:
 917                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
 918                         break;
 919                 case 2:
 920                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
 921                         break;
 922                 default:
 923                         break;
 924                 }
 925
 926                 if ((panel_setup >> 16) & 0x1)
 927                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
 928
 929                 if ((panel_setup >> 17) & 0x1)
 930                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
 931
 932                 if ((panel_setup >> 18) & 0x1)
 933                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
 934
 935                 if ((panel_setup >> 23) & 0x1)
 936                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
 937
 938                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
 939
 940                 for (i = 0; i < 32; i++) {
 941                         tmp = RBIOS16(lcd_info + 64 + i * 2);
 942                         if (tmp == 0)
 943                                 break;
 944
 945                         if ((RBIOS16(tmp) == lvds->native_mode.panel_xres) &&
 946                             (RBIOS16(tmp + 2) ==
 947                              lvds->native_mode.panel_yres)) {
 948                                 lvds->native_mode.hblank =
 949                                     (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
 950                                 lvds->native_mode.hoverplus =
 951                                     (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) -
 952                                      1) * 8;
 953                                 lvds->native_mode.hsync_width =
 954                                     RBIOS8(tmp + 23) * 8;
 955
 956                                 lvds->native_mode.vblank = (RBIOS16(tmp + 24) -
 957                                                             RBIOS16(tmp + 26));
 958                                 lvds->native_mode.voverplus =
 959                                     ((RBIOS16(tmp + 28) & 0x7ff) -
 960                                      RBIOS16(tmp + 26));
 961                                 lvds->native_mode.vsync_width =
 962                                     ((RBIOS16(tmp + 28) & 0xf800) >> 11);
 963                                 lvds->native_mode.dotclock =
 964                                     RBIOS16(tmp + 9) * 10;
 965                                 lvds->native_mode.flags = 0;
 966                         }
 967                 }
 968                 encoder->native_mode = lvds->native_mode;
 969         } else {
 970                 DRM_INFO("No panel info found in BIOS\n");
 971                 return radeon_legacy_get_lvds_info_from_regs(rdev);
 972         }
 973         return lvds;
 974 }
 975
 976 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
 977         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
 978         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
 979         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
 980         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
 981         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
 982         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
 983         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
 984         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
 985         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
 986         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
 987         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
 988         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
 989         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
 990         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
 991         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
 992         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
 993         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RS400 */
 994         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RS480 */
 995 };
 996
 997 static struct radeon_encoder_int_tmds
 998     *radeon_legacy_get_tmds_info_from_table(struct radeon_device *rdev)
 999 {
1000         int i;
1001         struct radeon_encoder_int_tmds *tmds = NULL;
1002
1003         tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1004
1005         if (!tmds)
1006                 return NULL;
1007
1008         for (i = 0; i < 4; i++) {
1009                 tmds->tmds_pll[i].value =
1010                     default_tmds_pll[rdev->family][i].value;
1011                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1012         }
1013
1014         return tmds;
1015 }
1016
1017 struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct
1018                                                              radeon_encoder
1019                                                              *encoder)
1020 {
1021         struct drm_device *dev = encoder->base.dev;
1022         struct radeon_device *rdev = dev->dev_private;
1023         uint16_t tmds_info;
1024         int i, n;
1025         uint8_t ver;
1026         struct radeon_encoder_int_tmds *tmds = NULL;
1027
1028         if (rdev->bios == NULL)
1029                 return radeon_legacy_get_tmds_info_from_table(rdev);
1030
1031         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1032
1033         if (tmds_info) {
1034                 tmds =
1035                     kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1036
1037                 if (!tmds)
1038                         return NULL;
1039
1040                 ver = RBIOS8(tmds_info);
1041                 DRM_INFO("DFP table revision: %d\n", ver);
1042                 if (ver == 3) {
1043                         n = RBIOS8(tmds_info + 5) + 1;
1044                         if (n > 4)
1045                                 n = 4;
1046                         for (i = 0; i < n; i++) {
1047                                 tmds->tmds_pll[i].value =
1048                                     RBIOS32(tmds_info + i * 10 + 0x08);
1049                                 tmds->tmds_pll[i].freq =
1050                                     RBIOS16(tmds_info + i * 10 + 0x10);
1051                                 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1052                                           tmds->tmds_pll[i].freq,
1053                                           tmds->tmds_pll[i].value);
1054                         }
1055                 } else if (ver == 4) {
1056                         int stride = 0;
1057                         n = RBIOS8(tmds_info + 5) + 1;
1058                         if (n > 4)
1059                                 n = 4;
1060                         for (i = 0; i < n; i++) {
1061                                 tmds->tmds_pll[i].value =
1062                                     RBIOS32(tmds_info + stride + 0x08);
1063                                 tmds->tmds_pll[i].freq =
1064                                     RBIOS16(tmds_info + stride + 0x10);
1065                                 if (i == 0)
1066                                         stride += 10;
1067                                 else
1068                                         stride += 6;
1069                                 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1070                                           tmds->tmds_pll[i].freq,
1071                                           tmds->tmds_pll[i].value);
1072                         }
1073                 }
1074         } else
1075                 DRM_INFO("No TMDS info found in BIOS\n");
1076         return tmds;
1077 }
1078
1079 void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder)
1080 {
1081         struct drm_device *dev = encoder->base.dev;
1082         struct radeon_device *rdev = dev->dev_private;
1083         uint16_t ext_tmds_info;
1084         uint8_t ver;
1085
1086         if (rdev->bios == NULL)
1087                 return;
1088
1089         ext_tmds_info =
1090             combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1091         if (ext_tmds_info) {
1092                 ver = RBIOS8(ext_tmds_info);
1093                 DRM_INFO("External TMDS Table revision: %d\n", ver);
1094                 // TODO
1095         }
1096 }
1097
1098 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1099 {
1100         struct radeon_device *rdev = dev->dev_private;
1101         struct radeon_i2c_bus_rec ddc_i2c;
1102
1103         rdev->mode_info.connector_table = radeon_connector_table;
1104         if (rdev->mode_info.connector_table == CT_NONE) {
1105 #ifdef CONFIG_PPC_PMAC
1106                 if (machine_is_compatible("PowerBook3,3")) {
1107                         /* powerbook with VGA */
1108                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1109                 } else if (machine_is_compatible("PowerBook3,4") ||
1110                            machine_is_compatible("PowerBook3,5")) {
1111                         /* powerbook with internal tmds */
1112                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1113                 } else if (machine_is_compatible("PowerBook5,1") ||
1114                            machine_is_compatible("PowerBook5,2") ||
1115                            machine_is_compatible("PowerBook5,3") ||
1116                            machine_is_compatible("PowerBook5,4") ||
1117                            machine_is_compatible("PowerBook5,5")) {
1118                         /* powerbook with external single link tmds (sil164) */
1119                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1120                 } else if (machine_is_compatible("PowerBook5,6")) {
1121                         /* powerbook with external dual or single link tmds */
1122                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1123                 } else if (machine_is_compatible("PowerBook5,7") ||
1124                            machine_is_compatible("PowerBook5,8") ||
1125                            machine_is_compatible("PowerBook5,9")) {
1126                         /* PowerBook6,2 ? */
1127                         /* powerbook with external dual link tmds (sil1178?) */
1128                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1129                 } else if (machine_is_compatible("PowerBook4,1") ||
1130                            machine_is_compatible("PowerBook4,2") ||
1131                            machine_is_compatible("PowerBook4,3") ||
1132                            machine_is_compatible("PowerBook6,3") ||
1133                            machine_is_compatible("PowerBook6,5") ||
1134                            machine_is_compatible("PowerBook6,7")) {
1135                         /* ibook */
1136                         rdev->mode_info.connector_table = CT_IBOOK;
1137                 } else if (machine_is_compatible("PowerMac4,4")) {
1138                         /* emac */
1139                         rdev->mode_info.connector_table = CT_EMAC;
1140                 } else if (machine_is_compatible("PowerMac10,1")) {
1141                         /* mini with internal tmds */
1142                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1143                 } else if (machine_is_compatible("PowerMac10,2")) {
1144                         /* mini with external tmds */
1145                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1146                 } else if (machine_is_compatible("PowerMac12,1")) {
1147                         /* PowerMac8,1 ? */
1148                         /* imac g5 isight */
1149                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1150                 } else
1151 #endif /* CONFIG_PPC_PMAC */
1152                         rdev->mode_info.connector_table = CT_GENERIC;
1153         }
1154
1155         switch (rdev->mode_info.connector_table) {
1156         case CT_GENERIC:
1157                 DRM_INFO("Connector Table: %d (generic)\n",
1158                          rdev->mode_info.connector_table);
1159                 /* these are the most common settings */
1160                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1161                         /* VGA - primary dac */
1162                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1163                         radeon_add_legacy_encoder(dev,
1164                                                   radeon_get_encoder_id(dev,
1165                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1166                                                                         1),
1167                                                   ATOM_DEVICE_CRT1_SUPPORT);
1168                         radeon_add_legacy_connector(dev, 0,
1169                                                     ATOM_DEVICE_CRT1_SUPPORT,
1170                                                     DRM_MODE_CONNECTOR_VGA,
1171                                                     &ddc_i2c);
1172                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1173                         /* LVDS */
1174                         ddc_i2c = combios_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
1175                         radeon_add_legacy_encoder(dev,
1176                                                   radeon_get_encoder_id(dev,
1177                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1178                                                                         0),
1179                                                   ATOM_DEVICE_LCD1_SUPPORT);
1180                         radeon_add_legacy_connector(dev, 0,
1181                                                     ATOM_DEVICE_LCD1_SUPPORT,
1182                                                     DRM_MODE_CONNECTOR_LVDS,
1183                                                     &ddc_i2c);
1184
1185                         /* VGA - primary dac */
1186                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1187                         radeon_add_legacy_encoder(dev,
1188                                                   radeon_get_encoder_id(dev,
1189                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1190                                                                         1),
1191                                                   ATOM_DEVICE_CRT1_SUPPORT);
1192                         radeon_add_legacy_connector(dev, 1,
1193                                                     ATOM_DEVICE_CRT1_SUPPORT,
1194                                                     DRM_MODE_CONNECTOR_VGA,
1195                                                     &ddc_i2c);
1196                 } else {
1197                         /* DVI-I - tv dac, int tmds */
1198                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1199                         radeon_add_legacy_encoder(dev,
1200                                                   radeon_get_encoder_id(dev,
1201                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1202                                                                         0),
1203                                                   ATOM_DEVICE_DFP1_SUPPORT);
1204                         radeon_add_legacy_encoder(dev,
1205                                                   radeon_get_encoder_id(dev,
1206                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1207                                                                         2),
1208                                                   ATOM_DEVICE_CRT2_SUPPORT);
1209                         radeon_add_legacy_connector(dev, 0,
1210                                                     ATOM_DEVICE_DFP1_SUPPORT |
1211                                                     ATOM_DEVICE_CRT2_SUPPORT,
1212                                                     DRM_MODE_CONNECTOR_DVII,
1213                                                     &ddc_i2c);
1214
1215                         /* VGA - primary dac */
1216                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1217                         radeon_add_legacy_encoder(dev,
1218                                                   radeon_get_encoder_id(dev,
1219                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1220                                                                         1),
1221                                                   ATOM_DEVICE_CRT1_SUPPORT);
1222                         radeon_add_legacy_connector(dev, 1,
1223                                                     ATOM_DEVICE_CRT1_SUPPORT,
1224                                                     DRM_MODE_CONNECTOR_VGA,
1225                                                     &ddc_i2c);
1226                 }
1227
1228                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1229                         /* TV - tv dac */
1230                         radeon_add_legacy_encoder(dev,
1231                                                   radeon_get_encoder_id(dev,
1232                                                                         ATOM_DEVICE_TV1_SUPPORT,
1233                                                                         2),
1234                                                   ATOM_DEVICE_TV1_SUPPORT);
1235                         radeon_add_legacy_connector(dev, 2,
1236                                                     ATOM_DEVICE_TV1_SUPPORT,
1237                                                     DRM_MODE_CONNECTOR_SVIDEO,
1238                                                     &ddc_i2c);
1239                 }
1240                 break;
1241         case CT_IBOOK:
1242                 DRM_INFO("Connector Table: %d (ibook)\n",
1243                          rdev->mode_info.connector_table);
1244                 /* LVDS */
1245                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1246                 radeon_add_legacy_encoder(dev,
1247                                           radeon_get_encoder_id(dev,
1248                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1249                                                                 0),
1250                                           ATOM_DEVICE_LCD1_SUPPORT);
1251                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1252                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1253                 /* VGA - TV DAC */
1254                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1255                 radeon_add_legacy_encoder(dev,
1256                                           radeon_get_encoder_id(dev,
1257                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1258                                                                 2),
1259                                           ATOM_DEVICE_CRT2_SUPPORT);
1260                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1261                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1262                 /* TV - TV DAC */
1263                 radeon_add_legacy_encoder(dev,
1264                                           radeon_get_encoder_id(dev,
1265                                                                 ATOM_DEVICE_TV1_SUPPORT,
1266                                                                 2),
1267                                           ATOM_DEVICE_TV1_SUPPORT);
1268                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1269                                             DRM_MODE_CONNECTOR_SVIDEO,
1270                                             &ddc_i2c);
1271                 break;
1272         case CT_POWERBOOK_EXTERNAL:
1273                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1274                          rdev->mode_info.connector_table);
1275                 /* LVDS */
1276                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1277                 radeon_add_legacy_encoder(dev,
1278                                           radeon_get_encoder_id(dev,
1279                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1280                                                                 0),
1281                                           ATOM_DEVICE_LCD1_SUPPORT);
1282                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1283                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1284                 /* DVI-I - primary dac, ext tmds */
1285                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1286                 radeon_add_legacy_encoder(dev,
1287                                           radeon_get_encoder_id(dev,
1288                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1289                                                                 0),
1290                                           ATOM_DEVICE_DFP2_SUPPORT);
1291                 radeon_add_legacy_encoder(dev,
1292                                           radeon_get_encoder_id(dev,
1293                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1294                                                                 1),
1295                                           ATOM_DEVICE_CRT1_SUPPORT);
1296                 radeon_add_legacy_connector(dev, 1,
1297                                             ATOM_DEVICE_DFP2_SUPPORT |
1298                                             ATOM_DEVICE_CRT1_SUPPORT,
1299                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1300                 /* TV - TV DAC */
1301                 radeon_add_legacy_encoder(dev,
1302                                           radeon_get_encoder_id(dev,
1303                                                                 ATOM_DEVICE_TV1_SUPPORT,
1304                                                                 2),
1305                                           ATOM_DEVICE_TV1_SUPPORT);
1306                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1307                                             DRM_MODE_CONNECTOR_SVIDEO,
1308                                             &ddc_i2c);
1309                 break;
1310         case CT_POWERBOOK_INTERNAL:
1311                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1312                          rdev->mode_info.connector_table);
1313                 /* LVDS */
1314                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1315                 radeon_add_legacy_encoder(dev,
1316                                           radeon_get_encoder_id(dev,
1317                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1318                                                                 0),
1319                                           ATOM_DEVICE_LCD1_SUPPORT);
1320                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1321                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1322                 /* DVI-I - primary dac, int tmds */
1323                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1324                 radeon_add_legacy_encoder(dev,
1325                                           radeon_get_encoder_id(dev,
1326                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1327                                                                 0),
1328                                           ATOM_DEVICE_DFP1_SUPPORT);
1329                 radeon_add_legacy_encoder(dev,
1330                                           radeon_get_encoder_id(dev,
1331                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1332                                                                 1),
1333                                           ATOM_DEVICE_CRT1_SUPPORT);
1334                 radeon_add_legacy_connector(dev, 1,
1335                                             ATOM_DEVICE_DFP1_SUPPORT |
1336                                             ATOM_DEVICE_CRT1_SUPPORT,
1337                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1338                 /* TV - TV DAC */
1339                 radeon_add_legacy_encoder(dev,
1340                                           radeon_get_encoder_id(dev,
1341                                                                 ATOM_DEVICE_TV1_SUPPORT,
1342                                                                 2),
1343                                           ATOM_DEVICE_TV1_SUPPORT);
1344                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1345                                             DRM_MODE_CONNECTOR_SVIDEO,
1346                                             &ddc_i2c);
1347                 break;
1348         case CT_POWERBOOK_VGA:
1349                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1350                          rdev->mode_info.connector_table);
1351                 /* LVDS */
1352                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1353                 radeon_add_legacy_encoder(dev,
1354                                           radeon_get_encoder_id(dev,
1355                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1356                                                                 0),
1357                                           ATOM_DEVICE_LCD1_SUPPORT);
1358                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1359                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1360                 /* VGA - primary dac */
1361                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1362                 radeon_add_legacy_encoder(dev,
1363                                           radeon_get_encoder_id(dev,
1364                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1365                                                                 1),
1366                                           ATOM_DEVICE_CRT1_SUPPORT);
1367                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1368                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1369                 /* TV - TV DAC */
1370                 radeon_add_legacy_encoder(dev,
1371                                           radeon_get_encoder_id(dev,
1372                                                                 ATOM_DEVICE_TV1_SUPPORT,
1373                                                                 2),
1374                                           ATOM_DEVICE_TV1_SUPPORT);
1375                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1376                                             DRM_MODE_CONNECTOR_SVIDEO,
1377                                             &ddc_i2c);
1378                 break;
1379         case CT_MINI_EXTERNAL:
1380                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1381                          rdev->mode_info.connector_table);
1382                 /* DVI-I - tv dac, ext tmds */
1383                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1384                 radeon_add_legacy_encoder(dev,
1385                                           radeon_get_encoder_id(dev,
1386                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1387                                                                 0),
1388                                           ATOM_DEVICE_DFP2_SUPPORT);
1389                 radeon_add_legacy_encoder(dev,
1390                                           radeon_get_encoder_id(dev,
1391                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1392                                                                 2),
1393                                           ATOM_DEVICE_CRT2_SUPPORT);
1394                 radeon_add_legacy_connector(dev, 0,
1395                                             ATOM_DEVICE_DFP2_SUPPORT |
1396                                             ATOM_DEVICE_CRT2_SUPPORT,
1397                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1398                 /* TV - TV DAC */
1399                 radeon_add_legacy_encoder(dev,
1400                                           radeon_get_encoder_id(dev,
1401                                                                 ATOM_DEVICE_TV1_SUPPORT,
1402                                                                 2),
1403                                           ATOM_DEVICE_TV1_SUPPORT);
1404                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1405                                             DRM_MODE_CONNECTOR_SVIDEO,
1406                                             &ddc_i2c);
1407                 break;
1408         case CT_MINI_INTERNAL:
1409                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1410                          rdev->mode_info.connector_table);
1411                 /* DVI-I - tv dac, int tmds */
1412                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1413                 radeon_add_legacy_encoder(dev,
1414                                           radeon_get_encoder_id(dev,
1415                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1416                                                                 0),
1417                                           ATOM_DEVICE_DFP1_SUPPORT);
1418                 radeon_add_legacy_encoder(dev,
1419                                           radeon_get_encoder_id(dev,
1420                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1421                                                                 2),
1422                                           ATOM_DEVICE_CRT2_SUPPORT);
1423                 radeon_add_legacy_connector(dev, 0,
1424                                             ATOM_DEVICE_DFP1_SUPPORT |
1425                                             ATOM_DEVICE_CRT2_SUPPORT,
1426                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1427                 /* TV - TV DAC */
1428                 radeon_add_legacy_encoder(dev,
1429                                           radeon_get_encoder_id(dev,
1430                                                                 ATOM_DEVICE_TV1_SUPPORT,
1431                                                                 2),
1432                                           ATOM_DEVICE_TV1_SUPPORT);
1433                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1434                                             DRM_MODE_CONNECTOR_SVIDEO,
1435                                             &ddc_i2c);
1436                 break;
1437         case CT_IMAC_G5_ISIGHT:
1438                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1439                          rdev->mode_info.connector_table);
1440                 /* DVI-D - int tmds */
1441                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1442                 radeon_add_legacy_encoder(dev,
1443                                           radeon_get_encoder_id(dev,
1444                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1445                                                                 0),
1446                                           ATOM_DEVICE_DFP1_SUPPORT);
1447                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1448                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c);
1449                 /* VGA - tv dac */
1450                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1451                 radeon_add_legacy_encoder(dev,
1452                                           radeon_get_encoder_id(dev,
1453                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1454                                                                 2),
1455                                           ATOM_DEVICE_CRT2_SUPPORT);
1456                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1457                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1458                 /* TV - TV DAC */
1459                 radeon_add_legacy_encoder(dev,
1460                                           radeon_get_encoder_id(dev,
1461                                                                 ATOM_DEVICE_TV1_SUPPORT,
1462                                                                 2),
1463                                           ATOM_DEVICE_TV1_SUPPORT);
1464                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1465                                             DRM_MODE_CONNECTOR_SVIDEO,
1466                                             &ddc_i2c);
1467                 break;
1468         case CT_EMAC:
1469                 DRM_INFO("Connector Table: %d (emac)\n",
1470                          rdev->mode_info.connector_table);
1471                 /* VGA - primary dac */
1472                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1473                 radeon_add_legacy_encoder(dev,
1474                                           radeon_get_encoder_id(dev,
1475                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1476                                                                 1),
1477                                           ATOM_DEVICE_CRT1_SUPPORT);
1478                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1479                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1480                 /* VGA - tv dac */
1481                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1482                 radeon_add_legacy_encoder(dev,
1483                                           radeon_get_encoder_id(dev,
1484                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1485                                                                 2),
1486                                           ATOM_DEVICE_CRT2_SUPPORT);
1487                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1488                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1489                 /* TV - TV DAC */
1490                 radeon_add_legacy_encoder(dev,
1491                                           radeon_get_encoder_id(dev,
1492                                                                 ATOM_DEVICE_TV1_SUPPORT,
1493                                                                 2),
1494                                           ATOM_DEVICE_TV1_SUPPORT);
1495                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1496                                             DRM_MODE_CONNECTOR_SVIDEO,
1497                                             &ddc_i2c);
1498                 break;
1499         default:
1500                 DRM_INFO("Connector table: %d (invalid)\n",
1501                          rdev->mode_info.connector_table);
1502                 return false;
1503         }
1504
1505         radeon_link_encoder_connector(dev);
1506
1507         return true;
1508 }
1509
1510 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1511                                        int bios_index,
1512                                        enum radeon_combios_connector
1513                                        *legacy_connector,
1514                                        struct radeon_i2c_bus_rec *ddc_i2c)
1515 {
1516         struct radeon_device *rdev = dev->dev_private;
1517
1518         /* XPRESS DDC quirks */
1519         if ((rdev->family == CHIP_RS400 ||
1520              rdev->family == CHIP_RS480) &&
1521             ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1522                 *ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1523         else if ((rdev->family == CHIP_RS400 ||
1524                   rdev->family == CHIP_RS480) &&
1525                  ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1526                 ddc_i2c->valid = true;
1527                 ddc_i2c->mask_clk_mask = (0x20 << 8);
1528                 ddc_i2c->mask_data_mask = 0x80;
1529                 ddc_i2c->a_clk_mask = (0x20 << 8);
1530                 ddc_i2c->a_data_mask = 0x80;
1531                 ddc_i2c->put_clk_mask = (0x20 << 8);
1532                 ddc_i2c->put_data_mask = 0x80;
1533                 ddc_i2c->get_clk_mask = (0x20 << 8);
1534                 ddc_i2c->get_data_mask = 0x80;
1535                 ddc_i2c->mask_clk_reg = RADEON_GPIOPAD_MASK;
1536                 ddc_i2c->mask_data_reg = RADEON_GPIOPAD_MASK;
1537                 ddc_i2c->a_clk_reg = RADEON_GPIOPAD_A;
1538                 ddc_i2c->a_data_reg = RADEON_GPIOPAD_A;
1539                 ddc_i2c->put_clk_reg = RADEON_GPIOPAD_EN;
1540                 ddc_i2c->put_data_reg = RADEON_GPIOPAD_EN;
1541                 ddc_i2c->get_clk_reg = RADEON_LCD_GPIO_Y_REG;
1542                 ddc_i2c->get_data_reg = RADEON_LCD_GPIO_Y_REG;
1543         }
1544
1545         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1546            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1547         if (dev->pdev->device == 0x515e &&
1548             dev->pdev->subsystem_vendor == 0x1014) {
1549                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1550                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1551                         return false;
1552         }
1553
1554         /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1555         if (dev->pdev->device == 0x5159 &&
1556             dev->pdev->subsystem_vendor == 0x1002 &&
1557             dev->pdev->subsystem_device == 0x013a) {
1558                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1559                         *legacy_connector = CONNECTOR_CRT_LEGACY;
1560
1561         }
1562
1563         /* X300 card with extra non-existent DVI port */
1564         if (dev->pdev->device == 0x5B60 &&
1565             dev->pdev->subsystem_vendor == 0x17af &&
1566             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1567                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1568                         return false;
1569         }
1570
1571         return true;
1572 }
1573
1574 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1575 {
1576         struct radeon_device *rdev = dev->dev_private;
1577         uint32_t conn_info, entry, devices;
1578         uint16_t tmp;
1579         enum radeon_combios_ddc ddc_type;
1580         enum radeon_combios_connector connector;
1581         int i = 0;
1582         struct radeon_i2c_bus_rec ddc_i2c;
1583
1584         if (rdev->bios == NULL)
1585                 return false;
1586
1587         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1588         if (conn_info) {
1589                 for (i = 0; i < 4; i++) {
1590                         entry = conn_info + 2 + i * 2;
1591
1592                         if (!RBIOS16(entry))
1593                                 break;
1594
1595                         tmp = RBIOS16(entry);
1596
1597                         connector = (tmp >> 12) & 0xf;
1598
1599                         ddc_type = (tmp >> 8) & 0xf;
1600                         switch (ddc_type) {
1601                         case DDC_MONID:
1602                                 ddc_i2c =
1603                                     combios_setup_i2c_bus(RADEON_GPIO_MONID);
1604                                 break;
1605                         case DDC_DVI:
1606                                 ddc_i2c =
1607                                     combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1608                                 break;
1609                         case DDC_VGA:
1610                                 ddc_i2c =
1611                                     combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1612                                 break;
1613                         case DDC_CRT2:
1614                                 ddc_i2c =
1615                                     combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1616                                 break;
1617                         default:
1618                                 break;
1619                         }
1620
1621                         radeon_apply_legacy_quirks(dev, i, &connector,
1622                                                    &ddc_i2c);
1623
1624                         switch (connector) {
1625                         case CONNECTOR_PROPRIETARY_LEGACY:
1626                                 if ((tmp >> 4) & 0x1)
1627                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
1628                                 else
1629                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
1630                                 radeon_add_legacy_encoder(dev,
1631                                                           radeon_get_encoder_id
1632                                                           (dev, devices, 0),
1633                                                           devices);
1634                                 radeon_add_legacy_connector(dev, i, devices,
1635                                                             legacy_connector_convert
1636                                                             [connector],
1637                                                             &ddc_i2c);
1638                                 break;
1639                         case CONNECTOR_CRT_LEGACY:
1640                                 if (tmp & 0x1) {
1641                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
1642                                         radeon_add_legacy_encoder(dev,
1643                                                                   radeon_get_encoder_id
1644                                                                   (dev,
1645                                                                    ATOM_DEVICE_CRT2_SUPPORT,
1646                                                                    2),
1647                                                                   ATOM_DEVICE_CRT2_SUPPORT);
1648                                 } else {
1649                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
1650                                         radeon_add_legacy_encoder(dev,
1651                                                                   radeon_get_encoder_id
1652                                                                   (dev,
1653                                                                    ATOM_DEVICE_CRT1_SUPPORT,
1654                                                                    1),
1655                                                                   ATOM_DEVICE_CRT1_SUPPORT);
1656                                 }
1657                                 radeon_add_legacy_connector(dev,
1658                                                             i,
1659                                                             devices,
1660                                                             legacy_connector_convert
1661                                                             [connector],
1662                                                             &ddc_i2c);
1663                                 break;
1664                         case CONNECTOR_DVI_I_LEGACY:
1665                                 devices = 0;
1666                                 if (tmp & 0x1) {
1667                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
1668                                         radeon_add_legacy_encoder(dev,
1669                                                                   radeon_get_encoder_id
1670                                                                   (dev,
1671                                                                    ATOM_DEVICE_CRT2_SUPPORT,
1672                                                                    2),
1673                                                                   ATOM_DEVICE_CRT2_SUPPORT);
1674                                 } else {
1675                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
1676                                         radeon_add_legacy_encoder(dev,
1677                                                                   radeon_get_encoder_id
1678                                                                   (dev,
1679                                                                    ATOM_DEVICE_CRT1_SUPPORT,
1680                                                                    1),
1681                                                                   ATOM_DEVICE_CRT1_SUPPORT);
1682                                 }
1683                                 if ((tmp >> 4) & 0x1) {
1684                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
1685                                         radeon_add_legacy_encoder(dev,
1686                                                                   radeon_get_encoder_id
1687                                                                   (dev,
1688                                                                    ATOM_DEVICE_DFP2_SUPPORT,
1689                                                                    0),
1690                                                                   ATOM_DEVICE_DFP2_SUPPORT);
1691                                 } else {
1692                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
1693                                         radeon_add_legacy_encoder(dev,
1694                                                                   radeon_get_encoder_id
1695                                                                   (dev,
1696                                                                    ATOM_DEVICE_DFP1_SUPPORT,
1697                                                                    0),
1698                                                                   ATOM_DEVICE_DFP1_SUPPORT);
1699                                 }
1700                                 radeon_add_legacy_connector(dev,
1701                                                             i,
1702                                                             devices,
1703                                                             legacy_connector_convert
1704                                                             [connector],
1705                                                             &ddc_i2c);
1706                                 break;
1707                         case CONNECTOR_DVI_D_LEGACY:
1708                                 if ((tmp >> 4) & 0x1)
1709                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
1710                                 else
1711                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
1712                                 radeon_add_legacy_encoder(dev,
1713                                                           radeon_get_encoder_id
1714                                                           (dev, devices, 0),
1715                                                           devices);
1716                                 radeon_add_legacy_connector(dev, i, devices,
1717                                                             legacy_connector_convert
1718                                                             [connector],
1719                                                             &ddc_i2c);
1720                                 break;
1721                         case CONNECTOR_CTV_LEGACY:
1722                         case CONNECTOR_STV_LEGACY:
1723                                 radeon_add_legacy_encoder(dev,
1724                                                           radeon_get_encoder_id
1725                                                           (dev,
1726                                                            ATOM_DEVICE_TV1_SUPPORT,
1727                                                            2),
1728                                                           ATOM_DEVICE_TV1_SUPPORT);
1729                                 radeon_add_legacy_connector(dev, i,
1730                                                             ATOM_DEVICE_TV1_SUPPORT,
1731                                                             legacy_connector_convert
1732                                                             [connector],
1733                                                             &ddc_i2c);
1734                                 break;
1735                         default:
1736                                 DRM_ERROR("Unknown connector type: %d\n",
1737                                           connector);
1738                                 continue;
1739                         }
1740
1741                 }
1742         } else {
1743                 uint16_t tmds_info =
1744                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1745                 if (tmds_info) {
1746                         DRM_DEBUG("Found DFP table, assuming DVI connector\n");
1747
1748                         radeon_add_legacy_encoder(dev,
1749                                                   radeon_get_encoder_id(dev,
1750                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1751                                                                         1),
1752                                                   ATOM_DEVICE_CRT1_SUPPORT);
1753                         radeon_add_legacy_encoder(dev,
1754                                                   radeon_get_encoder_id(dev,
1755                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1756                                                                         0),
1757                                                   ATOM_DEVICE_DFP1_SUPPORT);
1758
1759                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1760                         radeon_add_legacy_connector(dev,
1761                                                     0,
1762                                                     ATOM_DEVICE_CRT1_SUPPORT |
1763                                                     ATOM_DEVICE_DFP1_SUPPORT,
1764                                                     DRM_MODE_CONNECTOR_DVII,
1765                                                     &ddc_i2c);
1766                 } else {
1767                         DRM_DEBUG("No connector info found\n");
1768                         return false;
1769                 }
1770         }
1771
1772         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
1773                 uint16_t lcd_info =
1774                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1775                 if (lcd_info) {
1776                         uint16_t lcd_ddc_info =
1777                             combios_get_table_offset(dev,
1778                                                      COMBIOS_LCD_DDC_INFO_TABLE);
1779
1780                         radeon_add_legacy_encoder(dev,
1781                                                   radeon_get_encoder_id(dev,
1782                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1783                                                                         0),
1784                                                   ATOM_DEVICE_LCD1_SUPPORT);
1785
1786                         if (lcd_ddc_info) {
1787                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
1788                                 switch (ddc_type) {
1789                                 case DDC_MONID:
1790                                         ddc_i2c =
1791                                             combios_setup_i2c_bus
1792                                             (RADEON_GPIO_MONID);
1793                                         break;
1794                                 case DDC_DVI:
1795                                         ddc_i2c =
1796                                             combios_setup_i2c_bus
1797                                             (RADEON_GPIO_DVI_DDC);
1798                                         break;
1799                                 case DDC_VGA:
1800                                         ddc_i2c =
1801                                             combios_setup_i2c_bus
1802                                             (RADEON_GPIO_VGA_DDC);
1803                                         break;
1804                                 case DDC_CRT2:
1805                                         ddc_i2c =
1806                                             combios_setup_i2c_bus
1807                                             (RADEON_GPIO_CRT2_DDC);
1808                                         break;
1809                                 case DDC_LCD:
1810                                         ddc_i2c =
1811                                             combios_setup_i2c_bus
1812                                             (RADEON_LCD_GPIO_MASK);
1813                                         ddc_i2c.mask_clk_mask =
1814                                             RBIOS32(lcd_ddc_info + 3);
1815                                         ddc_i2c.mask_data_mask =
1816                                             RBIOS32(lcd_ddc_info + 7);
1817                                         ddc_i2c.a_clk_mask =
1818                                             RBIOS32(lcd_ddc_info + 3);
1819                                         ddc_i2c.a_data_mask =
1820                                             RBIOS32(lcd_ddc_info + 7);
1821                                         ddc_i2c.put_clk_mask =
1822                                             RBIOS32(lcd_ddc_info + 3);
1823                                         ddc_i2c.put_data_mask =
1824                                             RBIOS32(lcd_ddc_info + 7);
1825                                         ddc_i2c.get_clk_mask =
1826                                             RBIOS32(lcd_ddc_info + 3);
1827                                         ddc_i2c.get_data_mask =
1828                                             RBIOS32(lcd_ddc_info + 7);
1829                                         break;
1830                                 case DDC_GPIO:
1831                                         ddc_i2c =
1832                                             combios_setup_i2c_bus
1833                                             (RADEON_MDGPIO_EN_REG);
1834                                         ddc_i2c.mask_clk_mask =
1835                                             RBIOS32(lcd_ddc_info + 3);
1836                                         ddc_i2c.mask_data_mask =
1837                                             RBIOS32(lcd_ddc_info + 7);
1838                                         ddc_i2c.a_clk_mask =
1839                                             RBIOS32(lcd_ddc_info + 3);
1840                                         ddc_i2c.a_data_mask =
1841                                             RBIOS32(lcd_ddc_info + 7);
1842                                         ddc_i2c.put_clk_mask =
1843                                             RBIOS32(lcd_ddc_info + 3);
1844                                         ddc_i2c.put_data_mask =
1845                                             RBIOS32(lcd_ddc_info + 7);
1846                                         ddc_i2c.get_clk_mask =
1847                                             RBIOS32(lcd_ddc_info + 3);
1848                                         ddc_i2c.get_data_mask =
1849                                             RBIOS32(lcd_ddc_info + 7);
1850                                         break;
1851                                 default:
1852                                         ddc_i2c.valid = false;
1853                                         break;
1854                                 }
1855                                 DRM_DEBUG("LCD DDC Info Table found!\n");
1856                         } else
1857                                 ddc_i2c.valid = false;
1858
1859                         radeon_add_legacy_connector(dev,
1860                                                     5,
1861                                                     ATOM_DEVICE_LCD1_SUPPORT,
1862                                                     DRM_MODE_CONNECTOR_LVDS,
1863                                                     &ddc_i2c);
1864                 }
1865         }
1866
1867         /* check TV table */
1868         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1869                 uint32_t tv_info =
1870                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1871                 if (tv_info) {
1872                         if (RBIOS8(tv_info + 6) == 'T') {
1873                                 radeon_add_legacy_encoder(dev,
1874                                                           radeon_get_encoder_id
1875                                                           (dev,
1876                                                            ATOM_DEVICE_TV1_SUPPORT,
1877                                                            2),
1878                                                           ATOM_DEVICE_TV1_SUPPORT);
1879                                 radeon_add_legacy_connector(dev, 6,
1880                                                             ATOM_DEVICE_TV1_SUPPORT,
1881                                                             DRM_MODE_CONNECTOR_SVIDEO,
1882                                                             &ddc_i2c);
1883                         }
1884                 }
1885         }
1886
1887         radeon_link_encoder_connector(dev);
1888
1889         return true;
1890 }
1891
1892 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
1893 {
1894         struct radeon_device *rdev = dev->dev_private;
1895
1896         if (offset) {
1897                 while (RBIOS16(offset)) {
1898                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
1899                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
1900                         uint32_t val, and_mask, or_mask;
1901                         uint32_t tmp;
1902
1903                         offset += 2;
1904                         switch (cmd) {
1905                         case 0:
1906                                 val = RBIOS32(offset);
1907                                 offset += 4;
1908                                 WREG32(addr, val);
1909                                 break;
1910                         case 1:
1911                                 val = RBIOS32(offset);
1912                                 offset += 4;
1913                                 WREG32(addr, val);
1914                                 break;
1915                         case 2:
1916                                 and_mask = RBIOS32(offset);
1917                                 offset += 4;
1918                                 or_mask = RBIOS32(offset);
1919                                 offset += 4;
1920                                 tmp = RREG32(addr);
1921                                 tmp &= and_mask;
1922                                 tmp |= or_mask;
1923                                 WREG32(addr, tmp);
1924                                 break;
1925                         case 3:
1926                                 and_mask = RBIOS32(offset);
1927                                 offset += 4;
1928                                 or_mask = RBIOS32(offset);
1929                                 offset += 4;
1930                                 tmp = RREG32(addr);
1931                                 tmp &= and_mask;
1932                                 tmp |= or_mask;
1933                                 WREG32(addr, tmp);
1934                                 break;
1935                         case 4:
1936                                 val = RBIOS16(offset);
1937                                 offset += 2;
1938                                 udelay(val);
1939                                 break;
1940                         case 5:
1941                                 val = RBIOS16(offset);
1942                                 offset += 2;
1943                                 switch (addr) {
1944                                 case 8:
1945                                         while (val--) {
1946                                                 if (!
1947                                                     (RREG32_PLL
1948                                                      (RADEON_CLK_PWRMGT_CNTL) &
1949                                                      RADEON_MC_BUSY))
1950                                                         break;
1951                                         }
1952                                         break;
1953                                 case 9:
1954                                         while (val--) {
1955                                                 if ((RREG32(RADEON_MC_STATUS) &
1956                                                      RADEON_MC_IDLE))
1957                                                         break;
1958                                         }
1959                                         break;
1960                                 default:
1961                                         break;
1962                                 }
1963                                 break;
1964                         default:
1965                                 break;
1966                         }
1967                 }
1968         }
1969 }
1970
1971 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
1972 {
1973         struct radeon_device *rdev = dev->dev_private;
1974
1975         if (offset) {
1976                 while (RBIOS8(offset)) {
1977                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
1978                         uint8_t addr = (RBIOS8(offset) & 0x3f);
1979                         uint32_t val, shift, tmp;
1980                         uint32_t and_mask, or_mask;
1981
1982                         offset++;
1983                         switch (cmd) {
1984                         case 0:
1985                                 val = RBIOS32(offset);
1986                                 offset += 4;
1987                                 WREG32_PLL(addr, val);
1988                                 break;
1989                         case 1:
1990                                 shift = RBIOS8(offset) * 8;
1991                                 offset++;
1992                                 and_mask = RBIOS8(offset) << shift;
1993                                 and_mask |= ~(0xff << shift);
1994                                 offset++;
1995                                 or_mask = RBIOS8(offset) << shift;
1996                                 offset++;
1997                                 tmp = RREG32_PLL(addr);
1998                                 tmp &= and_mask;
1999                                 tmp |= or_mask;
2000                                 WREG32_PLL(addr, tmp);
2001                                 break;
2002                         case 2:
2003                         case 3:
2004                                 tmp = 1000;
2005                                 switch (addr) {
2006                                 case 1:
2007                                         udelay(150);
2008                                         break;
2009                                 case 2:
2010                                         udelay(1000);
2011                                         break;
2012                                 case 3:
2013                                         while (tmp--) {
2014                                                 if (!
2015                                                     (RREG32_PLL
2016                                                      (RADEON_CLK_PWRMGT_CNTL) &
2017                                                      RADEON_MC_BUSY))
2018                                                         break;
2019                                         }
2020                                         break;
2021                                 case 4:
2022                                         while (tmp--) {
2023                                                 if (RREG32_PLL
2024                                                     (RADEON_CLK_PWRMGT_CNTL) &
2025                                                     RADEON_DLL_READY)
2026                                                         break;
2027                                         }
2028                                         break;
2029                                 case 5:
2030                                         tmp =
2031                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2032                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
2033 #if 0
2034                                                 uint32_t mclk_cntl =
2035                                                     RREG32_PLL
2036                                                     (RADEON_MCLK_CNTL);
2037                                                 mclk_cntl &= 0xffff0000;
2038                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
2039                                                 WREG32_PLL(RADEON_MCLK_CNTL,
2040                                                            mclk_cntl);
2041                                                 udelay(10000);
2042 #endif
2043                                                 WREG32_PLL
2044                                                     (RADEON_CLK_PWRMGT_CNTL,
2045                                                      tmp &
2046                                                      ~RADEON_CG_NO1_DEBUG_0);
2047                                                 udelay(10000);
2048                                         }
2049                                         break;
2050                                 default:
2051                                         break;
2052                                 }
2053                                 break;
2054                         default:
2055                                 break;
2056                         }
2057                 }
2058         }
2059 }
2060
2061 static void combios_parse_ram_reset_table(struct drm_device *dev,
2062                                           uint16_t offset)
2063 {
2064         struct radeon_device *rdev = dev->dev_private;
2065         uint32_t tmp;
2066
2067         if (offset) {
2068                 uint8_t val = RBIOS8(offset);
2069                 while (val != 0xff) {
2070                         offset++;
2071
2072                         if (val == 0x0f) {
2073                                 uint32_t channel_complete_mask;
2074
2075                                 if (ASIC_IS_R300(rdev))
2076                                         channel_complete_mask =
2077                                             R300_MEM_PWRUP_COMPLETE;
2078                                 else
2079                                         channel_complete_mask =
2080                                             RADEON_MEM_PWRUP_COMPLETE;
2081                                 tmp = 20000;
2082                                 while (tmp--) {
2083                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
2084                                              channel_complete_mask) ==
2085                                             channel_complete_mask)
2086                                                 break;
2087                                 }
2088                         } else {
2089                                 uint32_t or_mask = RBIOS16(offset);
2090                                 offset += 2;
2091
2092                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2093                                 tmp &= RADEON_SDRAM_MODE_MASK;
2094                                 tmp |= or_mask;
2095                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2096
2097                                 or_mask = val << 24;
2098                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2099                                 tmp &= RADEON_B3MEM_RESET_MASK;
2100                                 tmp |= or_mask;
2101                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2102                         }
2103                         val = RBIOS8(offset);
2104                 }
2105         }
2106 }
2107
2108 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2109                                    int mem_addr_mapping)
2110 {
2111         struct radeon_device *rdev = dev->dev_private;
2112         uint32_t mem_cntl;
2113         uint32_t mem_size;
2114         uint32_t addr = 0;
2115
2116         mem_cntl = RREG32(RADEON_MEM_CNTL);
2117         if (mem_cntl & RV100_HALF_MODE)
2118                 ram /= 2;
2119         mem_size = ram;
2120         mem_cntl &= ~(0xff << 8);
2121         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2122         WREG32(RADEON_MEM_CNTL, mem_cntl);
2123         RREG32(RADEON_MEM_CNTL);
2124
2125         /* sdram reset ? */
2126
2127         /* something like this????  */
2128         while (ram--) {
2129                 addr = ram * 1024 * 1024;
2130                 /* write to each page */
2131                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2132                 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2133                 /* read back and verify */
2134                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2135                 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2136                         return 0;
2137         }
2138
2139         return mem_size;
2140 }
2141
2142 static void combios_write_ram_size(struct drm_device *dev)
2143 {
2144         struct radeon_device *rdev = dev->dev_private;
2145         uint8_t rev;
2146         uint16_t offset;
2147         uint32_t mem_size = 0;
2148         uint32_t mem_cntl = 0;
2149
2150         /* should do something smarter here I guess... */
2151         if (rdev->flags & RADEON_IS_IGP)
2152                 return;
2153
2154         /* first check detected mem table */
2155         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2156         if (offset) {
2157                 rev = RBIOS8(offset);
2158                 if (rev < 3) {
2159                         mem_cntl = RBIOS32(offset + 1);
2160                         mem_size = RBIOS16(offset + 5);
2161                         if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2162                             ((dev->pdev->device != 0x515e)
2163                              && (dev->pdev->device != 0x5969)))
2164                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
2165                 }
2166         }
2167
2168         if (!mem_size) {
2169                 offset =
2170                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2171                 if (offset) {
2172                         rev = RBIOS8(offset - 1);
2173                         if (rev < 1) {
2174                                 if (((rdev->flags & RADEON_FAMILY_MASK) <
2175                                      CHIP_R200)
2176                                     && ((dev->pdev->device != 0x515e)
2177                                         && (dev->pdev->device != 0x5969))) {
2178                                         int ram = 0;
2179                                         int mem_addr_mapping = 0;
2180
2181                                         while (RBIOS8(offset)) {
2182                                                 ram = RBIOS8(offset);
2183                                                 mem_addr_mapping =
2184                                                     RBIOS8(offset + 1);
2185                                                 if (mem_addr_mapping != 0x25)
2186                                                         ram *= 2;
2187                                                 mem_size =
2188                                                     combios_detect_ram(dev, ram,
2189                                                                        mem_addr_mapping);
2190                                                 if (mem_size)
2191                                                         break;
2192                                                 offset += 2;
2193                                         }
2194                                 } else
2195                                         mem_size = RBIOS8(offset);
2196                         } else {
2197                                 mem_size = RBIOS8(offset);
2198                                 mem_size *= 2;  /* convert to MB */
2199                         }
2200                 }
2201         }
2202
2203         mem_size *= (1024 * 1024);      /* convert to bytes */
2204         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2205 }
2206
2207 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2208 {
2209         uint16_t dyn_clk_info =
2210             combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2211
2212         if (dyn_clk_info)
2213                 combios_parse_pll_table(dev, dyn_clk_info);
2214 }
2215
2216 void radeon_combios_asic_init(struct drm_device *dev)
2217 {
2218         struct radeon_device *rdev = dev->dev_private;
2219         uint16_t table;
2220
2221         /* port hardcoded mac stuff from radeonfb */
2222         if (rdev->bios == NULL)
2223                 return;
2224
2225         /* ASIC INIT 1 */
2226         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2227         if (table)
2228                 combios_parse_mmio_table(dev, table);
2229
2230         /* PLL INIT */
2231         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2232         if (table)
2233                 combios_parse_pll_table(dev, table);
2234
2235         /* ASIC INIT 2 */
2236         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2237         if (table)
2238                 combios_parse_mmio_table(dev, table);
2239
2240         if (!(rdev->flags & RADEON_IS_IGP)) {
2241                 /* ASIC INIT 4 */
2242                 table =
2243                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
2244                 if (table)
2245                         combios_parse_mmio_table(dev, table);
2246
2247                 /* RAM RESET */
2248                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
2249                 if (table)
2250                         combios_parse_ram_reset_table(dev, table);
2251
2252                 /* ASIC INIT 3 */
2253                 table =
2254                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
2255                 if (table)
2256                         combios_parse_mmio_table(dev, table);
2257
2258                 /* write CONFIG_MEMSIZE */
2259                 combios_write_ram_size(dev);
2260         }
2261
2262         /* DYN CLK 1 */
2263         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2264         if (table)
2265                 combios_parse_pll_table(dev, table);
2266
2267 }
2268
2269 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
2270 {
2271         struct radeon_device *rdev = dev->dev_private;
2272         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
2273
2274         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2275         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2276         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
2277
2278         /* let the bios control the backlight */
2279         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
2280
2281         /* tell the bios not to handle mode switching */
2282         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
2283                            RADEON_ACC_MODE_CHANGE);
2284
2285         /* tell the bios a driver is loaded */
2286         bios_7_scratch |= RADEON_DRV_LOADED;
2287
2288         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2289         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2290         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
2291 }
2292
2293 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
2294 {
2295         struct drm_device *dev = encoder->dev;
2296         struct radeon_device *rdev = dev->dev_private;
2297         uint32_t bios_6_scratch;
2298
2299         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2300
2301         if (lock)
2302                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
2303         else
2304                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
2305
2306         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2307 }
2308
2309 void
2310 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
2311                                       struct drm_encoder *encoder,
2312                                       bool connected)
2313 {
2314         struct drm_device *dev = connector->dev;
2315         struct radeon_device *rdev = dev->dev_private;
2316         struct radeon_connector *radeon_connector =
2317             to_radeon_connector(connector);
2318         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2319         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
2320         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2321
2322         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2323             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2324                 if (connected) {
2325                         DRM_DEBUG("TV1 connected\n");
2326                         /* fix me */
2327                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
2328                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
2329                         bios_5_scratch |= RADEON_TV1_ON;
2330                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
2331                 } else {
2332                         DRM_DEBUG("TV1 disconnected\n");
2333                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
2334                         bios_5_scratch &= ~RADEON_TV1_ON;
2335                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
2336                 }
2337         }
2338         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2339             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2340                 if (connected) {
2341                         DRM_DEBUG("LCD1 connected\n");
2342                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
2343                         bios_5_scratch |= RADEON_LCD1_ON;
2344                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
2345                 } else {
2346                         DRM_DEBUG("LCD1 disconnected\n");
2347                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
2348                         bios_5_scratch &= ~RADEON_LCD1_ON;
2349                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
2350                 }
2351         }
2352         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2353             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2354                 if (connected) {
2355                         DRM_DEBUG("CRT1 connected\n");
2356                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
2357                         bios_5_scratch |= RADEON_CRT1_ON;
2358                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
2359                 } else {
2360                         DRM_DEBUG("CRT1 disconnected\n");
2361                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
2362                         bios_5_scratch &= ~RADEON_CRT1_ON;
2363                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
2364                 }
2365         }
2366         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2367             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2368                 if (connected) {
2369                         DRM_DEBUG("CRT2 connected\n");
2370                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
2371                         bios_5_scratch |= RADEON_CRT2_ON;
2372                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
2373                 } else {
2374                         DRM_DEBUG("CRT2 disconnected\n");
2375                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
2376                         bios_5_scratch &= ~RADEON_CRT2_ON;
2377                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
2378                 }
2379         }
2380         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2381             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2382                 if (connected) {
2383                         DRM_DEBUG("DFP1 connected\n");
2384                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
2385                         bios_5_scratch |= RADEON_DFP1_ON;
2386                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
2387                 } else {
2388                         DRM_DEBUG("DFP1 disconnected\n");
2389                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
2390                         bios_5_scratch &= ~RADEON_DFP1_ON;
2391                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
2392                 }
2393         }
2394         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2395             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2396                 if (connected) {
2397                         DRM_DEBUG("DFP2 connected\n");
2398                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
2399                         bios_5_scratch |= RADEON_DFP2_ON;
2400                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
2401                 } else {
2402                         DRM_DEBUG("DFP2 disconnected\n");
2403                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
2404                         bios_5_scratch &= ~RADEON_DFP2_ON;
2405                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
2406                 }
2407         }
2408         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
2409         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2410 }
2411
2412 void
2413 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2414 {
2415         struct drm_device *dev = encoder->dev;
2416         struct radeon_device *rdev = dev->dev_private;
2417         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2418         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2419
2420         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2421                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
2422                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
2423         }
2424         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2425                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
2426                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
2427         }
2428         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2429                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
2430                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
2431         }
2432         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2433                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
2434                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
2435         }
2436         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2437                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
2438                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
2439         }
2440         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2441                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
2442                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
2443         }
2444         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2445 }
2446
2447 void
2448 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2449 {
2450         struct drm_device *dev = encoder->dev;
2451         struct radeon_device *rdev = dev->dev_private;
2452         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2453         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2454
2455         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
2456                 if (on)
2457                         bios_6_scratch |= RADEON_TV_DPMS_ON;
2458                 else
2459                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
2460         }
2461         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2462                 if (on)
2463                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
2464                 else
2465                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
2466         }
2467         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2468                 if (on)
2469                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
2470                 else
2471                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
2472         }
2473         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
2474                 if (on)
2475                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
2476                 else
2477                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
2478         }
2479         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2480 }