drivers/gpu/drm/radeon/radeon_bios.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "radeon_reg.h"
  30 #include "radeon.h"
  31 #include "atom.h"
  32
  33 #include <linux/vga_switcheroo.h>
  34 #include <linux/slab.h>
  35 #include <linux/acpi.h>
  36 /*
  37  * BIOS.
  38  */
  39
  40 /* If you boot an IGP board with a discrete card as the primary,
  41  * the IGP rom is not accessible via the rom bar as the IGP rom is
  42  * part of the system bios.  On boot, the system bios puts a
  43  * copy of the igp rom at the start of vram if a discrete card is
  44  * present.
  45  */
  46 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
  47 {
  48         uint8_t __iomem *bios;
  49         resource_size_t vram_base;
  50         resource_size_t size = 256 * 1024; /* ??? */
  51
  52         if (!(rdev->flags & RADEON_IS_IGP))
  53                 if (!radeon_card_posted(rdev))
  54                         return false;
  55
  56         rdev->bios = NULL;
  57         vram_base = pci_resource_start(rdev->pdev, 0);
  58         bios = ioremap(vram_base, size);
  59         if (!bios) {
  60                 return false;
  61         }
  62
  63         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  64                 iounmap(bios);
  65                 return false;
  66         }
  67         rdev->bios = kmalloc(size, GFP_KERNEL);
  68         if (rdev->bios == NULL) {
  69                 iounmap(bios);
  70                 return false;
  71         }
  72         memcpy_fromio(rdev->bios, bios, size);
  73         iounmap(bios);
  74         return true;
  75 }
  76
  77 static bool radeon_read_bios(struct radeon_device *rdev)
  78 {
  79         uint8_t __iomem *bios, val1, val2;
  80         size_t size;
  81
  82         rdev->bios = NULL;
  83         /* XXX: some cards may return 0 for rom size? ddx has a workaround */
  84         bios = pci_map_rom(rdev->pdev, &size);
  85         if (!bios) {
  86                 return false;
  87         }
  88
  89         val1 = readb(&bios[0]);
  90         val2 = readb(&bios[1]);
  91
  92         if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
  93                 pci_unmap_rom(rdev->pdev, bios);
  94                 return false;
  95         }
  96         rdev->bios = kzalloc(size, GFP_KERNEL);
  97         if (rdev->bios == NULL) {
  98                 pci_unmap_rom(rdev->pdev, bios);
  99                 return false;
 100         }
 101         memcpy_fromio(rdev->bios, bios, size);
 102         pci_unmap_rom(rdev->pdev, bios);
 103         return true;
 104 }
 105
 106 #ifdef CONFIG_ACPI
 107 /* ATRM is used to get the BIOS on the discrete cards in
 108  * dual-gpu systems.
 109  */
 110 /* retrieve the ROM in 4k blocks */
 111 #define ATRM_BIOS_PAGE 4096
 112 /**
 113  * radeon_atrm_call - fetch a chunk of the vbios
 114  *
 115  * @atrm_handle: acpi ATRM handle
 116  * @bios: vbios image pointer
 117  * @offset: offset of vbios image data to fetch
 118  * @len: length of vbios image data to fetch
 119  *
 120  * Executes ATRM to fetch a chunk of the discrete
 121  * vbios image on PX systems (all asics).
 122  * Returns the length of the buffer fetched.
 123  */
 124 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
 125                             int offset, int len)
 126 {
 127         acpi_status status;
 128         union acpi_object atrm_arg_elements[2], *obj;
 129         struct acpi_object_list atrm_arg;
 130         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
 131
 132         atrm_arg.count = 2;
 133         atrm_arg.pointer = &atrm_arg_elements[0];
 134
 135         atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
 136         atrm_arg_elements[0].integer.value = offset;
 137
 138         atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
 139         atrm_arg_elements[1].integer.value = len;
 140
 141         status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
 142         if (ACPI_FAILURE(status)) {
 143                 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
 144                 return -ENODEV;
 145         }
 146
 147         obj = (union acpi_object *)buffer.pointer;
 148         memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
 149         len = obj->buffer.length;
 150         kfree(buffer.pointer);
 151         return len;
 152 }
 153
 154 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
 155 {
 156         int ret;
 157         int size = 256 * 1024;
 158         int i;
 159         struct pci_dev *pdev = NULL;
 160         acpi_handle dhandle, atrm_handle;
 161         acpi_status status;
 162         bool found = false;
 163
 164         /* ATRM is for the discrete card only */
 165         if (rdev->flags & RADEON_IS_IGP)
 166                 return false;
 167
 168         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
 169                 dhandle = DEVICE_ACPI_HANDLE(&pdev->dev);
 170                 if (!dhandle)
 171                         continue;
 172
 173                 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
 174                 if (!ACPI_FAILURE(status)) {
 175                         found = true;
 176                         break;
 177                 }
 178         }
 179
 180         if (!found) {
 181                 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
 182                         dhandle = DEVICE_ACPI_HANDLE(&pdev->dev);
 183                         if (!dhandle)
 184                                 continue;
 185
 186                         status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
 187                         if (!ACPI_FAILURE(status)) {
 188                                 found = true;
 189                                 break;
 190                         }
 191                 }
 192         }
 193
 194         if (!found)
 195                 return false;
 196
 197         rdev->bios = kmalloc(size, GFP_KERNEL);
 198         if (!rdev->bios) {
 199                 DRM_ERROR("Unable to allocate bios\n");
 200                 return false;
 201         }
 202
 203         for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
 204                 ret = radeon_atrm_call(atrm_handle,
 205                                        rdev->bios,
 206                                        (i * ATRM_BIOS_PAGE),
 207                                        ATRM_BIOS_PAGE);
 208                 if (ret < ATRM_BIOS_PAGE)
 209                         break;
 210         }
 211
 212         if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 213                 kfree(rdev->bios);
 214                 return false;
 215         }
 216         return true;
 217 }
 218 #else
 219 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
 220 {
 221         return false;
 222 }
 223 #endif
 224
 225 static bool ni_read_disabled_bios(struct radeon_device *rdev)
 226 {
 227         u32 bus_cntl;
 228         u32 d1vga_control;
 229         u32 d2vga_control;
 230         u32 vga_render_control;
 231         u32 rom_cntl;
 232         bool r;
 233
 234         bus_cntl = RREG32(R600_BUS_CNTL);
 235         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 236         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 237         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 238         rom_cntl = RREG32(R600_ROM_CNTL);
 239
 240         /* enable the rom */
 241         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 242         /* Disable VGA mode */
 243         WREG32(AVIVO_D1VGA_CONTROL,
 244                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 245                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 246         WREG32(AVIVO_D2VGA_CONTROL,
 247                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 248                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 249         WREG32(AVIVO_VGA_RENDER_CONTROL,
 250                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 251         WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
 252
 253         r = radeon_read_bios(rdev);
 254
 255         /* restore regs */
 256         WREG32(R600_BUS_CNTL, bus_cntl);
 257         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 258         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 259         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 260         WREG32(R600_ROM_CNTL, rom_cntl);
 261         return r;
 262 }
 263
 264 static bool r700_read_disabled_bios(struct radeon_device *rdev)
 265 {
 266         uint32_t viph_control;
 267         uint32_t bus_cntl;
 268         uint32_t d1vga_control;
 269         uint32_t d2vga_control;
 270         uint32_t vga_render_control;
 271         uint32_t rom_cntl;
 272         uint32_t cg_spll_func_cntl = 0;
 273         uint32_t cg_spll_status;
 274         bool r;
 275
 276         viph_control = RREG32(RADEON_VIPH_CONTROL);
 277         bus_cntl = RREG32(R600_BUS_CNTL);
 278         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 279         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 280         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 281         rom_cntl = RREG32(R600_ROM_CNTL);
 282
 283         /* disable VIP */
 284         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 285         /* enable the rom */
 286         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 287         /* Disable VGA mode */
 288         WREG32(AVIVO_D1VGA_CONTROL,
 289                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 290                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 291         WREG32(AVIVO_D2VGA_CONTROL,
 292                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 293                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 294         WREG32(AVIVO_VGA_RENDER_CONTROL,
 295                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 296
 297         if (rdev->family == CHIP_RV730) {
 298                 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
 299
 300                 /* enable bypass mode */
 301                 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
 302                                                 R600_SPLL_BYPASS_EN));
 303
 304                 /* wait for SPLL_CHG_STATUS to change to 1 */
 305                 cg_spll_status = 0;
 306                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 307                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 308
 309                 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
 310         } else
 311                 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
 312
 313         r = radeon_read_bios(rdev);
 314
 315         /* restore regs */
 316         if (rdev->family == CHIP_RV730) {
 317                 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
 318
 319                 /* wait for SPLL_CHG_STATUS to change to 1 */
 320                 cg_spll_status = 0;
 321                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 322                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 323         }
 324         WREG32(RADEON_VIPH_CONTROL, viph_control);
 325         WREG32(R600_BUS_CNTL, bus_cntl);
 326         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 327         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 328         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 329         WREG32(R600_ROM_CNTL, rom_cntl);
 330         return r;
 331 }
 332
 333 static bool r600_read_disabled_bios(struct radeon_device *rdev)
 334 {
 335         uint32_t viph_control;
 336         uint32_t bus_cntl;
 337         uint32_t d1vga_control;
 338         uint32_t d2vga_control;
 339         uint32_t vga_render_control;
 340         uint32_t rom_cntl;
 341         uint32_t general_pwrmgt;
 342         uint32_t low_vid_lower_gpio_cntl;
 343         uint32_t medium_vid_lower_gpio_cntl;
 344         uint32_t high_vid_lower_gpio_cntl;
 345         uint32_t ctxsw_vid_lower_gpio_cntl;
 346         uint32_t lower_gpio_enable;
 347         bool r;
 348
 349         viph_control = RREG32(RADEON_VIPH_CONTROL);
 350         bus_cntl = RREG32(R600_BUS_CNTL);
 351         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 352         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 353         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 354         rom_cntl = RREG32(R600_ROM_CNTL);
 355         general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
 356         low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
 357         medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
 358         high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
 359         ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
 360         lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
 361
 362         /* disable VIP */
 363         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 364         /* enable the rom */
 365         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 366         /* Disable VGA mode */
 367         WREG32(AVIVO_D1VGA_CONTROL,
 368                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 369                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 370         WREG32(AVIVO_D2VGA_CONTROL,
 371                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 372                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 373         WREG32(AVIVO_VGA_RENDER_CONTROL,
 374                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 375
 376         WREG32(R600_ROM_CNTL,
 377                ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
 378                 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
 379                 R600_SCK_OVERWRITE));
 380
 381         WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
 382         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
 383                (low_vid_lower_gpio_cntl & ~0x400));
 384         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
 385                (medium_vid_lower_gpio_cntl & ~0x400));
 386         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
 387                (high_vid_lower_gpio_cntl & ~0x400));
 388         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
 389                (ctxsw_vid_lower_gpio_cntl & ~0x400));
 390         WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
 391
 392         r = radeon_read_bios(rdev);
 393
 394         /* restore regs */
 395         WREG32(RADEON_VIPH_CONTROL, viph_control);
 396         WREG32(R600_BUS_CNTL, bus_cntl);
 397         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 398         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 399         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 400         WREG32(R600_ROM_CNTL, rom_cntl);
 401         WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
 402         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
 403         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
 404         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
 405         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
 406         WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
 407         return r;
 408 }
 409
 410 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
 411 {
 412         uint32_t seprom_cntl1;
 413         uint32_t viph_control;
 414         uint32_t bus_cntl;
 415         uint32_t d1vga_control;
 416         uint32_t d2vga_control;
 417         uint32_t vga_render_control;
 418         uint32_t gpiopad_a;
 419         uint32_t gpiopad_en;
 420         uint32_t gpiopad_mask;
 421         bool r;
 422
 423         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 424         viph_control = RREG32(RADEON_VIPH_CONTROL);
 425         bus_cntl = RREG32(RV370_BUS_CNTL);
 426         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 427         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 428         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 429         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
 430         gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
 431         gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
 432
 433         WREG32(RADEON_SEPROM_CNTL1,
 434                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 435                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 436         WREG32(RADEON_GPIOPAD_A, 0);
 437         WREG32(RADEON_GPIOPAD_EN, 0);
 438         WREG32(RADEON_GPIOPAD_MASK, 0);
 439
 440         /* disable VIP */
 441         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 442
 443         /* enable the rom */
 444         WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 445
 446         /* Disable VGA mode */
 447         WREG32(AVIVO_D1VGA_CONTROL,
 448                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 449                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 450         WREG32(AVIVO_D2VGA_CONTROL,
 451                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 452                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 453         WREG32(AVIVO_VGA_RENDER_CONTROL,
 454                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 455
 456         r = radeon_read_bios(rdev);
 457
 458         /* restore regs */
 459         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 460         WREG32(RADEON_VIPH_CONTROL, viph_control);
 461         WREG32(RV370_BUS_CNTL, bus_cntl);
 462         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 463         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 464         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 465         WREG32(RADEON_GPIOPAD_A, gpiopad_a);
 466         WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
 467         WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
 468         return r;
 469 }
 470
 471 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
 472 {
 473         uint32_t seprom_cntl1;
 474         uint32_t viph_control;
 475         uint32_t bus_cntl;
 476         uint32_t crtc_gen_cntl;
 477         uint32_t crtc2_gen_cntl;
 478         uint32_t crtc_ext_cntl;
 479         uint32_t fp2_gen_cntl;
 480         bool r;
 481
 482         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 483         viph_control = RREG32(RADEON_VIPH_CONTROL);
 484         if (rdev->flags & RADEON_IS_PCIE)
 485                 bus_cntl = RREG32(RV370_BUS_CNTL);
 486         else
 487                 bus_cntl = RREG32(RADEON_BUS_CNTL);
 488         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
 489         crtc2_gen_cntl = 0;
 490         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 491         fp2_gen_cntl = 0;
 492
 493         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 494                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 495         }
 496
 497         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 498                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 499         }
 500
 501         WREG32(RADEON_SEPROM_CNTL1,
 502                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 503                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 504
 505         /* disable VIP */
 506         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 507
 508         /* enable the rom */
 509         if (rdev->flags & RADEON_IS_PCIE)
 510                 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 511         else
 512                 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 513
 514         /* Turn off mem requests and CRTC for both controllers */
 515         WREG32(RADEON_CRTC_GEN_CNTL,
 516                ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
 517                 (RADEON_CRTC_DISP_REQ_EN_B |
 518                  RADEON_CRTC_EXT_DISP_EN)));
 519         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 520                 WREG32(RADEON_CRTC2_GEN_CNTL,
 521                        ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
 522                         RADEON_CRTC2_DISP_REQ_EN_B));
 523         }
 524         /* Turn off CRTC */
 525         WREG32(RADEON_CRTC_EXT_CNTL,
 526                ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
 527                 (RADEON_CRTC_SYNC_TRISTAT |
 528                  RADEON_CRTC_DISPLAY_DIS)));
 529
 530         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 531                 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
 532         }
 533
 534         r = radeon_read_bios(rdev);
 535
 536         /* restore regs */
 537         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 538         WREG32(RADEON_VIPH_CONTROL, viph_control);
 539         if (rdev->flags & RADEON_IS_PCIE)
 540                 WREG32(RV370_BUS_CNTL, bus_cntl);
 541         else
 542                 WREG32(RADEON_BUS_CNTL, bus_cntl);
 543         WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 544         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 545                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 546         }
 547         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 548         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 549                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 550         }
 551         return r;
 552 }
 553
 554 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
 555 {
 556         if (rdev->flags & RADEON_IS_IGP)
 557                 return igp_read_bios_from_vram(rdev);
 558         else if (rdev->family >= CHIP_BARTS)
 559                 return ni_read_disabled_bios(rdev);
 560         else if (rdev->family >= CHIP_RV770)
 561                 return r700_read_disabled_bios(rdev);
 562         else if (rdev->family >= CHIP_R600)
 563                 return r600_read_disabled_bios(rdev);
 564         else if (rdev->family >= CHIP_RS600)
 565                 return avivo_read_disabled_bios(rdev);
 566         else
 567                 return legacy_read_disabled_bios(rdev);
 568 }
 569
 570 #ifdef CONFIG_ACPI
 571 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
 572 {
 573         bool ret = false;
 574         struct acpi_table_header *hdr;
 575         acpi_size tbl_size;
 576         UEFI_ACPI_VFCT *vfct;
 577         GOP_VBIOS_CONTENT *vbios;
 578         VFCT_IMAGE_HEADER *vhdr;
 579
 580         if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size)))
 581                 return false;
 582         if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
 583                 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
 584                 goto out_unmap;
 585         }
 586
 587         vfct = (UEFI_ACPI_VFCT *)hdr;
 588         if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
 589                 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
 590                 goto out_unmap;
 591         }
 592
 593         vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
 594         vhdr = &vbios->VbiosHeader;
 595         DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
 596                         vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
 597                         vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
 598
 599         if (vhdr->PCIBus != rdev->pdev->bus->number ||
 600             vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) ||
 601             vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) ||
 602             vhdr->VendorID != rdev->pdev->vendor ||
 603             vhdr->DeviceID != rdev->pdev->device) {
 604                 DRM_INFO("ACPI VFCT table is not for this card\n");
 605                 goto out_unmap;
 606         };
 607
 608         if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
 609                 DRM_ERROR("ACPI VFCT image truncated\n");
 610                 goto out_unmap;
 611         }
 612
 613         rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL);
 614         ret = !!rdev->bios;
 615
 616 out_unmap:
 617         return ret;
 618 }
 619 #else
 620 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
 621 {
 622         return false;
 623 }
 624 #endif
 625
 626 bool radeon_get_bios(struct radeon_device *rdev)
 627 {
 628         bool r;
 629         uint16_t tmp;
 630
 631         r = radeon_atrm_get_bios(rdev);
 632         if (r == false)
 633                 r = radeon_acpi_vfct_bios(rdev);
 634         if (r == false)
 635                 r = igp_read_bios_from_vram(rdev);
 636         if (r == false)
 637                 r = radeon_read_bios(rdev);
 638         if (r == false) {
 639                 r = radeon_read_disabled_bios(rdev);
 640         }
 641         if (r == false || rdev->bios == NULL) {
 642                 DRM_ERROR("Unable to locate a BIOS ROM\n");
 643                 rdev->bios = NULL;
 644                 return false;
 645         }
 646         if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 647                 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
 648                 goto free_bios;
 649         }
 650
 651         tmp = RBIOS16(0x18);
 652         if (RBIOS8(tmp + 0x14) != 0x0) {
 653                 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
 654                 goto free_bios;
 655         }
 656
 657         rdev->bios_header_start = RBIOS16(0x48);
 658         if (!rdev->bios_header_start) {
 659                 goto free_bios;
 660         }
 661         tmp = rdev->bios_header_start + 4;
 662         if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
 663             !memcmp(rdev->bios + tmp, "MOTA", 4)) {
 664                 rdev->is_atom_bios = true;
 665         } else {
 666                 rdev->is_atom_bios = false;
 667         }
 668
 669         DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
 670         return true;
 671 free_bios:
 672         kfree(rdev->bios);
 673         rdev->bios = NULL;
 674         return false;
 675 }