drivers/gpu/drm/radeon/radeon_bios.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "radeon_reg.h"
  30 #include "radeon.h"
  31 #include "atom.h"
  32
  33 #include <linux/vga_switcheroo.h>
  34 #include <linux/slab.h>
  35 #include <linux/acpi.h>
  36 /*
  37  * BIOS.
  38  */
  39
  40 /* If you boot an IGP board with a discrete card as the primary,
  41  * the IGP rom is not accessible via the rom bar as the IGP rom is
  42  * part of the system bios.  On boot, the system bios puts a
  43  * copy of the igp rom at the start of vram if a discrete card is
  44  * present.
  45  */
  46 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
  47 {
  48         uint8_t __iomem *bios;
  49         resource_size_t vram_base;
  50         resource_size_t size = 256 * 1024; /* ??? */
  51
  52         if (!(rdev->flags & RADEON_IS_IGP))
  53                 if (!radeon_card_posted(rdev))
  54                         return false;
  55
  56         rdev->bios = NULL;
  57         vram_base = pci_resource_start(rdev->pdev, 0);
  58         bios = ioremap(vram_base, size);
  59         if (!bios) {
  60                 return false;
  61         }
  62
  63         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  64                 iounmap(bios);
  65                 return false;
  66         }
  67         rdev->bios = kmalloc(size, GFP_KERNEL);
  68         if (rdev->bios == NULL) {
  69                 iounmap(bios);
  70                 return false;
  71         }
  72         memcpy_fromio(rdev->bios, bios, size);
  73         iounmap(bios);
  74         return true;
  75 }
  76
  77 static bool radeon_read_bios(struct radeon_device *rdev)
  78 {
  79         uint8_t __iomem *bios;
  80         size_t size;
  81
  82         rdev->bios = NULL;
  83         /* XXX: some cards may return 0 for rom size? ddx has a workaround */
  84         bios = pci_map_rom(rdev->pdev, &size);
  85         if (!bios) {
  86                 return false;
  87         }
  88
  89         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  90                 pci_unmap_rom(rdev->pdev, bios);
  91                 return false;
  92         }
  93         rdev->bios = kmemdup(bios, size, GFP_KERNEL);
  94         if (rdev->bios == NULL) {
  95                 pci_unmap_rom(rdev->pdev, bios);
  96                 return false;
  97         }
  98         pci_unmap_rom(rdev->pdev, bios);
  99         return true;
 100 }
 101
 102 /* ATRM is used to get the BIOS on the discrete cards in
 103  * dual-gpu systems.
 104  */
 105 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
 106 {
 107         int ret;
 108         int size = 256 * 1024;
 109         int i;
 110
 111         if (!radeon_atrm_supported(rdev->pdev))
 112                 return false;
 113
 114         rdev->bios = kmalloc(size, GFP_KERNEL);
 115         if (!rdev->bios) {
 116                 DRM_ERROR("Unable to allocate bios\n");
 117                 return false;
 118         }
 119
 120         for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
 121                 ret = radeon_atrm_get_bios_chunk(rdev->bios,
 122                                                  (i * ATRM_BIOS_PAGE),
 123                                                  ATRM_BIOS_PAGE);
 124                 if (ret < ATRM_BIOS_PAGE)
 125                         break;
 126         }
 127
 128         if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 129                 kfree(rdev->bios);
 130                 return false;
 131         }
 132         return true;
 133 }
 134
 135 static bool ni_read_disabled_bios(struct radeon_device *rdev)
 136 {
 137         u32 bus_cntl;
 138         u32 d1vga_control;
 139         u32 d2vga_control;
 140         u32 vga_render_control;
 141         u32 rom_cntl;
 142         bool r;
 143
 144         bus_cntl = RREG32(R600_BUS_CNTL);
 145         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 146         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 147         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 148         rom_cntl = RREG32(R600_ROM_CNTL);
 149
 150         /* enable the rom */
 151         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 152         /* Disable VGA mode */
 153         WREG32(AVIVO_D1VGA_CONTROL,
 154                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 155                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 156         WREG32(AVIVO_D2VGA_CONTROL,
 157                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 158                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 159         WREG32(AVIVO_VGA_RENDER_CONTROL,
 160                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 161         WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
 162
 163         r = radeon_read_bios(rdev);
 164
 165         /* restore regs */
 166         WREG32(R600_BUS_CNTL, bus_cntl);
 167         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 168         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 169         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 170         WREG32(R600_ROM_CNTL, rom_cntl);
 171         return r;
 172 }
 173
 174 static bool r700_read_disabled_bios(struct radeon_device *rdev)
 175 {
 176         uint32_t viph_control;
 177         uint32_t bus_cntl;
 178         uint32_t d1vga_control;
 179         uint32_t d2vga_control;
 180         uint32_t vga_render_control;
 181         uint32_t rom_cntl;
 182         uint32_t cg_spll_func_cntl = 0;
 183         uint32_t cg_spll_status;
 184         bool r;
 185
 186         viph_control = RREG32(RADEON_VIPH_CONTROL);
 187         bus_cntl = RREG32(R600_BUS_CNTL);
 188         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 189         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 190         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 191         rom_cntl = RREG32(R600_ROM_CNTL);
 192
 193         /* disable VIP */
 194         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 195         /* enable the rom */
 196         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 197         /* Disable VGA mode */
 198         WREG32(AVIVO_D1VGA_CONTROL,
 199                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 200                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 201         WREG32(AVIVO_D2VGA_CONTROL,
 202                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 203                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 204         WREG32(AVIVO_VGA_RENDER_CONTROL,
 205                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 206
 207         if (rdev->family == CHIP_RV730) {
 208                 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
 209
 210                 /* enable bypass mode */
 211                 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
 212                                                 R600_SPLL_BYPASS_EN));
 213
 214                 /* wait for SPLL_CHG_STATUS to change to 1 */
 215                 cg_spll_status = 0;
 216                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 217                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 218
 219                 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
 220         } else
 221                 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
 222
 223         r = radeon_read_bios(rdev);
 224
 225         /* restore regs */
 226         if (rdev->family == CHIP_RV730) {
 227                 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
 228
 229                 /* wait for SPLL_CHG_STATUS to change to 1 */
 230                 cg_spll_status = 0;
 231                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 232                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 233         }
 234         WREG32(RADEON_VIPH_CONTROL, viph_control);
 235         WREG32(R600_BUS_CNTL, bus_cntl);
 236         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 237         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 238         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 239         WREG32(R600_ROM_CNTL, rom_cntl);
 240         return r;
 241 }
 242
 243 static bool r600_read_disabled_bios(struct radeon_device *rdev)
 244 {
 245         uint32_t viph_control;
 246         uint32_t bus_cntl;
 247         uint32_t d1vga_control;
 248         uint32_t d2vga_control;
 249         uint32_t vga_render_control;
 250         uint32_t rom_cntl;
 251         uint32_t general_pwrmgt;
 252         uint32_t low_vid_lower_gpio_cntl;
 253         uint32_t medium_vid_lower_gpio_cntl;
 254         uint32_t high_vid_lower_gpio_cntl;
 255         uint32_t ctxsw_vid_lower_gpio_cntl;
 256         uint32_t lower_gpio_enable;
 257         bool r;
 258
 259         viph_control = RREG32(RADEON_VIPH_CONTROL);
 260         bus_cntl = RREG32(R600_BUS_CNTL);
 261         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 262         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 263         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 264         rom_cntl = RREG32(R600_ROM_CNTL);
 265         general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
 266         low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
 267         medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
 268         high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
 269         ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
 270         lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
 271
 272         /* disable VIP */
 273         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 274         /* enable the rom */
 275         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 276         /* Disable VGA mode */
 277         WREG32(AVIVO_D1VGA_CONTROL,
 278                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 279                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 280         WREG32(AVIVO_D2VGA_CONTROL,
 281                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 282                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 283         WREG32(AVIVO_VGA_RENDER_CONTROL,
 284                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 285
 286         WREG32(R600_ROM_CNTL,
 287                ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
 288                 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
 289                 R600_SCK_OVERWRITE));
 290
 291         WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
 292         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
 293                (low_vid_lower_gpio_cntl & ~0x400));
 294         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
 295                (medium_vid_lower_gpio_cntl & ~0x400));
 296         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
 297                (high_vid_lower_gpio_cntl & ~0x400));
 298         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
 299                (ctxsw_vid_lower_gpio_cntl & ~0x400));
 300         WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
 301
 302         r = radeon_read_bios(rdev);
 303
 304         /* restore regs */
 305         WREG32(RADEON_VIPH_CONTROL, viph_control);
 306         WREG32(R600_BUS_CNTL, bus_cntl);
 307         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 308         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 309         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 310         WREG32(R600_ROM_CNTL, rom_cntl);
 311         WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
 312         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
 313         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
 314         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
 315         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
 316         WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
 317         return r;
 318 }
 319
 320 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
 321 {
 322         uint32_t seprom_cntl1;
 323         uint32_t viph_control;
 324         uint32_t bus_cntl;
 325         uint32_t d1vga_control;
 326         uint32_t d2vga_control;
 327         uint32_t vga_render_control;
 328         uint32_t gpiopad_a;
 329         uint32_t gpiopad_en;
 330         uint32_t gpiopad_mask;
 331         bool r;
 332
 333         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 334         viph_control = RREG32(RADEON_VIPH_CONTROL);
 335         bus_cntl = RREG32(RV370_BUS_CNTL);
 336         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 337         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 338         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 339         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
 340         gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
 341         gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
 342
 343         WREG32(RADEON_SEPROM_CNTL1,
 344                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 345                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 346         WREG32(RADEON_GPIOPAD_A, 0);
 347         WREG32(RADEON_GPIOPAD_EN, 0);
 348         WREG32(RADEON_GPIOPAD_MASK, 0);
 349
 350         /* disable VIP */
 351         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 352
 353         /* enable the rom */
 354         WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 355
 356         /* Disable VGA mode */
 357         WREG32(AVIVO_D1VGA_CONTROL,
 358                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 359                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 360         WREG32(AVIVO_D2VGA_CONTROL,
 361                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 362                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 363         WREG32(AVIVO_VGA_RENDER_CONTROL,
 364                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 365
 366         r = radeon_read_bios(rdev);
 367
 368         /* restore regs */
 369         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 370         WREG32(RADEON_VIPH_CONTROL, viph_control);
 371         WREG32(RV370_BUS_CNTL, bus_cntl);
 372         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 373         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 374         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 375         WREG32(RADEON_GPIOPAD_A, gpiopad_a);
 376         WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
 377         WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
 378         return r;
 379 }
 380
 381 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
 382 {
 383         uint32_t seprom_cntl1;
 384         uint32_t viph_control;
 385         uint32_t bus_cntl;
 386         uint32_t crtc_gen_cntl;
 387         uint32_t crtc2_gen_cntl;
 388         uint32_t crtc_ext_cntl;
 389         uint32_t fp2_gen_cntl;
 390         bool r;
 391
 392         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 393         viph_control = RREG32(RADEON_VIPH_CONTROL);
 394         if (rdev->flags & RADEON_IS_PCIE)
 395                 bus_cntl = RREG32(RV370_BUS_CNTL);
 396         else
 397                 bus_cntl = RREG32(RADEON_BUS_CNTL);
 398         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
 399         crtc2_gen_cntl = 0;
 400         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 401         fp2_gen_cntl = 0;
 402
 403         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 404                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 405         }
 406
 407         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 408                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 409         }
 410
 411         WREG32(RADEON_SEPROM_CNTL1,
 412                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 413                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 414
 415         /* disable VIP */
 416         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 417
 418         /* enable the rom */
 419         if (rdev->flags & RADEON_IS_PCIE)
 420                 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 421         else
 422                 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 423
 424         /* Turn off mem requests and CRTC for both controllers */
 425         WREG32(RADEON_CRTC_GEN_CNTL,
 426                ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
 427                 (RADEON_CRTC_DISP_REQ_EN_B |
 428                  RADEON_CRTC_EXT_DISP_EN)));
 429         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 430                 WREG32(RADEON_CRTC2_GEN_CNTL,
 431                        ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
 432                         RADEON_CRTC2_DISP_REQ_EN_B));
 433         }
 434         /* Turn off CRTC */
 435         WREG32(RADEON_CRTC_EXT_CNTL,
 436                ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
 437                 (RADEON_CRTC_SYNC_TRISTAT |
 438                  RADEON_CRTC_DISPLAY_DIS)));
 439
 440         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 441                 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
 442         }
 443
 444         r = radeon_read_bios(rdev);
 445
 446         /* restore regs */
 447         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 448         WREG32(RADEON_VIPH_CONTROL, viph_control);
 449         if (rdev->flags & RADEON_IS_PCIE)
 450                 WREG32(RV370_BUS_CNTL, bus_cntl);
 451         else
 452                 WREG32(RADEON_BUS_CNTL, bus_cntl);
 453         WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 454         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 455                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 456         }
 457         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 458         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 459                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 460         }
 461         return r;
 462 }
 463
 464 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
 465 {
 466         if (rdev->flags & RADEON_IS_IGP)
 467                 return igp_read_bios_from_vram(rdev);
 468         else if (rdev->family >= CHIP_BARTS)
 469                 return ni_read_disabled_bios(rdev);
 470         else if (rdev->family >= CHIP_RV770)
 471                 return r700_read_disabled_bios(rdev);
 472         else if (rdev->family >= CHIP_R600)
 473                 return r600_read_disabled_bios(rdev);
 474         else if (rdev->family >= CHIP_RS600)
 475                 return avivo_read_disabled_bios(rdev);
 476         else
 477                 return legacy_read_disabled_bios(rdev);
 478 }
 479
 480 #ifdef CONFIG_ACPI
 481 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
 482 {
 483         bool ret = false;
 484         struct acpi_table_header *hdr;
 485         acpi_size tbl_size;
 486         UEFI_ACPI_VFCT *vfct;
 487         GOP_VBIOS_CONTENT *vbios;
 488         VFCT_IMAGE_HEADER *vhdr;
 489
 490         if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size)))
 491                 return false;
 492         if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
 493                 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
 494                 goto out_unmap;
 495         }
 496
 497         vfct = (UEFI_ACPI_VFCT *)hdr;
 498         if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
 499                 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
 500                 goto out_unmap;
 501         }
 502
 503         vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
 504         vhdr = &vbios->VbiosHeader;
 505         DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
 506                         vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
 507                         vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
 508
 509         if (vhdr->PCIBus != rdev->pdev->bus->number ||
 510             vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) ||
 511             vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) ||
 512             vhdr->VendorID != rdev->pdev->vendor ||
 513             vhdr->DeviceID != rdev->pdev->device) {
 514                 DRM_INFO("ACPI VFCT table is not for this card\n");
 515                 goto out_unmap;
 516         };
 517
 518         if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
 519                 DRM_ERROR("ACPI VFCT image truncated\n");
 520                 goto out_unmap;
 521         }
 522
 523         rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL);
 524         ret = !!rdev->bios;
 525
 526 out_unmap:
 527         return ret;
 528 }
 529 #else
 530 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
 531 {
 532         return false;
 533 }
 534 #endif
 535
 536 bool radeon_get_bios(struct radeon_device *rdev)
 537 {
 538         bool r;
 539         uint16_t tmp;
 540
 541         r = radeon_atrm_get_bios(rdev);
 542         if (r == false)
 543                 r = radeon_acpi_vfct_bios(rdev);
 544         if (r == false)
 545                 r = igp_read_bios_from_vram(rdev);
 546         if (r == false)
 547                 r = radeon_read_bios(rdev);
 548         if (r == false) {
 549                 r = radeon_read_disabled_bios(rdev);
 550         }
 551         if (r == false || rdev->bios == NULL) {
 552                 DRM_ERROR("Unable to locate a BIOS ROM\n");
 553                 rdev->bios = NULL;
 554                 return false;
 555         }
 556         if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 557                 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
 558                 goto free_bios;
 559         }
 560
 561         tmp = RBIOS16(0x18);
 562         if (RBIOS8(tmp + 0x14) != 0x0) {
 563                 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
 564                 goto free_bios;
 565         }
 566
 567         rdev->bios_header_start = RBIOS16(0x48);
 568         if (!rdev->bios_header_start) {
 569                 goto free_bios;
 570         }
 571         tmp = rdev->bios_header_start + 4;
 572         if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
 573             !memcmp(rdev->bios + tmp, "MOTA", 4)) {
 574                 rdev->is_atom_bios = true;
 575         } else {
 576                 rdev->is_atom_bios = false;
 577         }
 578
 579         DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
 580         return true;
 581 free_bios:
 582         kfree(rdev->bios);
 583         rdev->bios = NULL;
 584         return false;
 585 }