drivers/gpu/drm/radeon/radeon_bios.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "radeon_reg.h"
  30 #include "radeon.h"
  31 #include "atom.h"
  32
  33 #include <linux/vga_switcheroo.h>
  34 #include <linux/slab.h>
  35 #include <linux/acpi.h>
  36 /*
  37  * BIOS.
  38  */
  39
  40 /* If you boot an IGP board with a discrete card as the primary,
  41  * the IGP rom is not accessible via the rom bar as the IGP rom is
  42  * part of the system bios.  On boot, the system bios puts a
  43  * copy of the igp rom at the start of vram if a discrete card is
  44  * present.
  45  */
  46 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
  47 {
  48         uint8_t __iomem *bios;
  49         resource_size_t vram_base;
  50         resource_size_t size = 256 * 1024; /* ??? */
  51
  52         if (!(rdev->flags & RADEON_IS_IGP))
  53                 if (!radeon_card_posted(rdev))
  54                         return false;
  55
  56         rdev->bios = NULL;
  57         vram_base = pci_resource_start(rdev->pdev, 0);
  58         bios = ioremap(vram_base, size);
  59         if (!bios) {
  60                 return false;
  61         }
  62
  63         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  64                 iounmap(bios);
  65                 return false;
  66         }
  67         rdev->bios = kmalloc(size, GFP_KERNEL);
  68         if (rdev->bios == NULL) {
  69                 iounmap(bios);
  70                 return false;
  71         }
  72         memcpy_fromio(rdev->bios, bios, size);
  73         iounmap(bios);
  74         return true;
  75 }
  76
  77 static bool radeon_read_bios(struct radeon_device *rdev)
  78 {
  79         uint8_t __iomem *bios;
  80         size_t size;
  81
  82         rdev->bios = NULL;
  83         /* XXX: some cards may return 0 for rom size? ddx has a workaround */
  84         bios = pci_map_rom(rdev->pdev, &size);
  85         if (!bios) {
  86                 return false;
  87         }
  88
  89         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  90                 pci_unmap_rom(rdev->pdev, bios);
  91                 return false;
  92         }
  93         rdev->bios = kmemdup(bios, size, GFP_KERNEL);
  94         if (rdev->bios == NULL) {
  95                 pci_unmap_rom(rdev->pdev, bios);
  96                 return false;
  97         }
  98         pci_unmap_rom(rdev->pdev, bios);
  99         return true;
 100 }
 101
 102 #ifdef CONFIG_ACPI
 103 /* ATRM is used to get the BIOS on the discrete cards in
 104  * dual-gpu systems.
 105  */
 106 /* retrieve the ROM in 4k blocks */
 107 #define ATRM_BIOS_PAGE 4096
 108 /**
 109  * radeon_atrm_call - fetch a chunk of the vbios
 110  *
 111  * @atrm_handle: acpi ATRM handle
 112  * @bios: vbios image pointer
 113  * @offset: offset of vbios image data to fetch
 114  * @len: length of vbios image data to fetch
 115  *
 116  * Executes ATRM to fetch a chunk of the discrete
 117  * vbios image on PX systems (all asics).
 118  * Returns the length of the buffer fetched.
 119  */
 120 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
 121                             int offset, int len)
 122 {
 123         acpi_status status;
 124         union acpi_object atrm_arg_elements[2], *obj;
 125         struct acpi_object_list atrm_arg;
 126         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
 127
 128         atrm_arg.count = 2;
 129         atrm_arg.pointer = &atrm_arg_elements[0];
 130
 131         atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
 132         atrm_arg_elements[0].integer.value = offset;
 133
 134         atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
 135         atrm_arg_elements[1].integer.value = len;
 136
 137         status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
 138         if (ACPI_FAILURE(status)) {
 139                 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
 140                 return -ENODEV;
 141         }
 142
 143         obj = (union acpi_object *)buffer.pointer;
 144         memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
 145         len = obj->buffer.length;
 146         kfree(buffer.pointer);
 147         return len;
 148 }
 149
 150 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
 151 {
 152         int ret;
 153         int size = 256 * 1024;
 154         int i;
 155         struct pci_dev *pdev = NULL;
 156         acpi_handle dhandle, atrm_handle;
 157         acpi_status status;
 158         bool found = false;
 159
 160         /* ATRM is for the discrete card only */
 161         if (rdev->flags & RADEON_IS_IGP)
 162                 return false;
 163
 164         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
 165                 dhandle = DEVICE_ACPI_HANDLE(&pdev->dev);
 166                 if (!dhandle)
 167                         continue;
 168
 169                 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
 170                 if (!ACPI_FAILURE(status)) {
 171                         found = true;
 172                         break;
 173                 }
 174         }
 175
 176         if (!found) {
 177                 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
 178                         dhandle = DEVICE_ACPI_HANDLE(&pdev->dev);
 179                         if (!dhandle)
 180                                 continue;
 181
 182                         status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
 183                         if (!ACPI_FAILURE(status)) {
 184                                 found = true;
 185                                 break;
 186                         }
 187                 }
 188         }
 189
 190         if (!found)
 191                 return false;
 192
 193         rdev->bios = kmalloc(size, GFP_KERNEL);
 194         if (!rdev->bios) {
 195                 DRM_ERROR("Unable to allocate bios\n");
 196                 return false;
 197         }
 198
 199         for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
 200                 ret = radeon_atrm_call(atrm_handle,
 201                                        rdev->bios,
 202                                        (i * ATRM_BIOS_PAGE),
 203                                        ATRM_BIOS_PAGE);
 204                 if (ret < ATRM_BIOS_PAGE)
 205                         break;
 206         }
 207
 208         if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 209                 kfree(rdev->bios);
 210                 return false;
 211         }
 212         return true;
 213 }
 214 #else
 215 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
 216 {
 217         return false;
 218 }
 219 #endif
 220
 221 static bool ni_read_disabled_bios(struct radeon_device *rdev)
 222 {
 223         u32 bus_cntl;
 224         u32 d1vga_control;
 225         u32 d2vga_control;
 226         u32 vga_render_control;
 227         u32 rom_cntl;
 228         bool r;
 229
 230         bus_cntl = RREG32(R600_BUS_CNTL);
 231         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 232         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 233         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 234         rom_cntl = RREG32(R600_ROM_CNTL);
 235
 236         /* enable the rom */
 237         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 238         /* Disable VGA mode */
 239         WREG32(AVIVO_D1VGA_CONTROL,
 240                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 241                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 242         WREG32(AVIVO_D2VGA_CONTROL,
 243                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 244                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 245         WREG32(AVIVO_VGA_RENDER_CONTROL,
 246                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 247         WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
 248
 249         r = radeon_read_bios(rdev);
 250
 251         /* restore regs */
 252         WREG32(R600_BUS_CNTL, bus_cntl);
 253         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 254         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 255         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 256         WREG32(R600_ROM_CNTL, rom_cntl);
 257         return r;
 258 }
 259
 260 static bool r700_read_disabled_bios(struct radeon_device *rdev)
 261 {
 262         uint32_t viph_control;
 263         uint32_t bus_cntl;
 264         uint32_t d1vga_control;
 265         uint32_t d2vga_control;
 266         uint32_t vga_render_control;
 267         uint32_t rom_cntl;
 268         uint32_t cg_spll_func_cntl = 0;
 269         uint32_t cg_spll_status;
 270         bool r;
 271
 272         viph_control = RREG32(RADEON_VIPH_CONTROL);
 273         bus_cntl = RREG32(R600_BUS_CNTL);
 274         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 275         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 276         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 277         rom_cntl = RREG32(R600_ROM_CNTL);
 278
 279         /* disable VIP */
 280         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 281         /* enable the rom */
 282         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 283         /* Disable VGA mode */
 284         WREG32(AVIVO_D1VGA_CONTROL,
 285                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 286                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 287         WREG32(AVIVO_D2VGA_CONTROL,
 288                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 289                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 290         WREG32(AVIVO_VGA_RENDER_CONTROL,
 291                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 292
 293         if (rdev->family == CHIP_RV730) {
 294                 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
 295
 296                 /* enable bypass mode */
 297                 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
 298                                                 R600_SPLL_BYPASS_EN));
 299
 300                 /* wait for SPLL_CHG_STATUS to change to 1 */
 301                 cg_spll_status = 0;
 302                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 303                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 304
 305                 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
 306         } else
 307                 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
 308
 309         r = radeon_read_bios(rdev);
 310
 311         /* restore regs */
 312         if (rdev->family == CHIP_RV730) {
 313                 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
 314
 315                 /* wait for SPLL_CHG_STATUS to change to 1 */
 316                 cg_spll_status = 0;
 317                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 318                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 319         }
 320         WREG32(RADEON_VIPH_CONTROL, viph_control);
 321         WREG32(R600_BUS_CNTL, bus_cntl);
 322         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 323         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 324         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 325         WREG32(R600_ROM_CNTL, rom_cntl);
 326         return r;
 327 }
 328
 329 static bool r600_read_disabled_bios(struct radeon_device *rdev)
 330 {
 331         uint32_t viph_control;
 332         uint32_t bus_cntl;
 333         uint32_t d1vga_control;
 334         uint32_t d2vga_control;
 335         uint32_t vga_render_control;
 336         uint32_t rom_cntl;
 337         uint32_t general_pwrmgt;
 338         uint32_t low_vid_lower_gpio_cntl;
 339         uint32_t medium_vid_lower_gpio_cntl;
 340         uint32_t high_vid_lower_gpio_cntl;
 341         uint32_t ctxsw_vid_lower_gpio_cntl;
 342         uint32_t lower_gpio_enable;
 343         bool r;
 344
 345         viph_control = RREG32(RADEON_VIPH_CONTROL);
 346         bus_cntl = RREG32(R600_BUS_CNTL);
 347         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 348         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 349         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 350         rom_cntl = RREG32(R600_ROM_CNTL);
 351         general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
 352         low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
 353         medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
 354         high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
 355         ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
 356         lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
 357
 358         /* disable VIP */
 359         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 360         /* enable the rom */
 361         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 362         /* Disable VGA mode */
 363         WREG32(AVIVO_D1VGA_CONTROL,
 364                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 365                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 366         WREG32(AVIVO_D2VGA_CONTROL,
 367                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 368                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 369         WREG32(AVIVO_VGA_RENDER_CONTROL,
 370                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 371
 372         WREG32(R600_ROM_CNTL,
 373                ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
 374                 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
 375                 R600_SCK_OVERWRITE));
 376
 377         WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
 378         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
 379                (low_vid_lower_gpio_cntl & ~0x400));
 380         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
 381                (medium_vid_lower_gpio_cntl & ~0x400));
 382         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
 383                (high_vid_lower_gpio_cntl & ~0x400));
 384         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
 385                (ctxsw_vid_lower_gpio_cntl & ~0x400));
 386         WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
 387
 388         r = radeon_read_bios(rdev);
 389
 390         /* restore regs */
 391         WREG32(RADEON_VIPH_CONTROL, viph_control);
 392         WREG32(R600_BUS_CNTL, bus_cntl);
 393         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 394         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 395         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 396         WREG32(R600_ROM_CNTL, rom_cntl);
 397         WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
 398         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
 399         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
 400         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
 401         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
 402         WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
 403         return r;
 404 }
 405
 406 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
 407 {
 408         uint32_t seprom_cntl1;
 409         uint32_t viph_control;
 410         uint32_t bus_cntl;
 411         uint32_t d1vga_control;
 412         uint32_t d2vga_control;
 413         uint32_t vga_render_control;
 414         uint32_t gpiopad_a;
 415         uint32_t gpiopad_en;
 416         uint32_t gpiopad_mask;
 417         bool r;
 418
 419         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 420         viph_control = RREG32(RADEON_VIPH_CONTROL);
 421         bus_cntl = RREG32(RV370_BUS_CNTL);
 422         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 423         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 424         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 425         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
 426         gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
 427         gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
 428
 429         WREG32(RADEON_SEPROM_CNTL1,
 430                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 431                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 432         WREG32(RADEON_GPIOPAD_A, 0);
 433         WREG32(RADEON_GPIOPAD_EN, 0);
 434         WREG32(RADEON_GPIOPAD_MASK, 0);
 435
 436         /* disable VIP */
 437         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 438
 439         /* enable the rom */
 440         WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 441
 442         /* Disable VGA mode */
 443         WREG32(AVIVO_D1VGA_CONTROL,
 444                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 445                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 446         WREG32(AVIVO_D2VGA_CONTROL,
 447                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 448                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 449         WREG32(AVIVO_VGA_RENDER_CONTROL,
 450                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 451
 452         r = radeon_read_bios(rdev);
 453
 454         /* restore regs */
 455         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 456         WREG32(RADEON_VIPH_CONTROL, viph_control);
 457         WREG32(RV370_BUS_CNTL, bus_cntl);
 458         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 459         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 460         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 461         WREG32(RADEON_GPIOPAD_A, gpiopad_a);
 462         WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
 463         WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
 464         return r;
 465 }
 466
 467 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
 468 {
 469         uint32_t seprom_cntl1;
 470         uint32_t viph_control;
 471         uint32_t bus_cntl;
 472         uint32_t crtc_gen_cntl;
 473         uint32_t crtc2_gen_cntl;
 474         uint32_t crtc_ext_cntl;
 475         uint32_t fp2_gen_cntl;
 476         bool r;
 477
 478         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 479         viph_control = RREG32(RADEON_VIPH_CONTROL);
 480         if (rdev->flags & RADEON_IS_PCIE)
 481                 bus_cntl = RREG32(RV370_BUS_CNTL);
 482         else
 483                 bus_cntl = RREG32(RADEON_BUS_CNTL);
 484         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
 485         crtc2_gen_cntl = 0;
 486         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 487         fp2_gen_cntl = 0;
 488
 489         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 490                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 491         }
 492
 493         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 494                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 495         }
 496
 497         WREG32(RADEON_SEPROM_CNTL1,
 498                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 499                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 500
 501         /* disable VIP */
 502         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 503
 504         /* enable the rom */
 505         if (rdev->flags & RADEON_IS_PCIE)
 506                 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 507         else
 508                 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 509
 510         /* Turn off mem requests and CRTC for both controllers */
 511         WREG32(RADEON_CRTC_GEN_CNTL,
 512                ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
 513                 (RADEON_CRTC_DISP_REQ_EN_B |
 514                  RADEON_CRTC_EXT_DISP_EN)));
 515         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 516                 WREG32(RADEON_CRTC2_GEN_CNTL,
 517                        ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
 518                         RADEON_CRTC2_DISP_REQ_EN_B));
 519         }
 520         /* Turn off CRTC */
 521         WREG32(RADEON_CRTC_EXT_CNTL,
 522                ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
 523                 (RADEON_CRTC_SYNC_TRISTAT |
 524                  RADEON_CRTC_DISPLAY_DIS)));
 525
 526         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 527                 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
 528         }
 529
 530         r = radeon_read_bios(rdev);
 531
 532         /* restore regs */
 533         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 534         WREG32(RADEON_VIPH_CONTROL, viph_control);
 535         if (rdev->flags & RADEON_IS_PCIE)
 536                 WREG32(RV370_BUS_CNTL, bus_cntl);
 537         else
 538                 WREG32(RADEON_BUS_CNTL, bus_cntl);
 539         WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 540         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 541                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 542         }
 543         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 544         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 545                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 546         }
 547         return r;
 548 }
 549
 550 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
 551 {
 552         if (rdev->flags & RADEON_IS_IGP)
 553                 return igp_read_bios_from_vram(rdev);
 554         else if (rdev->family >= CHIP_BARTS)
 555                 return ni_read_disabled_bios(rdev);
 556         else if (rdev->family >= CHIP_RV770)
 557                 return r700_read_disabled_bios(rdev);
 558         else if (rdev->family >= CHIP_R600)
 559                 return r600_read_disabled_bios(rdev);
 560         else if (rdev->family >= CHIP_RS600)
 561                 return avivo_read_disabled_bios(rdev);
 562         else
 563                 return legacy_read_disabled_bios(rdev);
 564 }
 565
 566 #ifdef CONFIG_ACPI
 567 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
 568 {
 569         bool ret = false;
 570         struct acpi_table_header *hdr;
 571         acpi_size tbl_size;
 572         UEFI_ACPI_VFCT *vfct;
 573         GOP_VBIOS_CONTENT *vbios;
 574         VFCT_IMAGE_HEADER *vhdr;
 575
 576         if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size)))
 577                 return false;
 578         if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
 579                 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
 580                 goto out_unmap;
 581         }
 582
 583         vfct = (UEFI_ACPI_VFCT *)hdr;
 584         if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
 585                 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
 586                 goto out_unmap;
 587         }
 588
 589         vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
 590         vhdr = &vbios->VbiosHeader;
 591         DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
 592                         vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
 593                         vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
 594
 595         if (vhdr->PCIBus != rdev->pdev->bus->number ||
 596             vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) ||
 597             vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) ||
 598             vhdr->VendorID != rdev->pdev->vendor ||
 599             vhdr->DeviceID != rdev->pdev->device) {
 600                 DRM_INFO("ACPI VFCT table is not for this card\n");
 601                 goto out_unmap;
 602         };
 603
 604         if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
 605                 DRM_ERROR("ACPI VFCT image truncated\n");
 606                 goto out_unmap;
 607         }
 608
 609         rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL);
 610         ret = !!rdev->bios;
 611
 612 out_unmap:
 613         return ret;
 614 }
 615 #else
 616 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
 617 {
 618         return false;
 619 }
 620 #endif
 621
 622 bool radeon_get_bios(struct radeon_device *rdev)
 623 {
 624         bool r;
 625         uint16_t tmp;
 626
 627         r = radeon_atrm_get_bios(rdev);
 628         if (r == false)
 629                 r = radeon_acpi_vfct_bios(rdev);
 630         if (r == false)
 631                 r = igp_read_bios_from_vram(rdev);
 632         if (r == false)
 633                 r = radeon_read_bios(rdev);
 634         if (r == false) {
 635                 r = radeon_read_disabled_bios(rdev);
 636         }
 637         if (r == false || rdev->bios == NULL) {
 638                 DRM_ERROR("Unable to locate a BIOS ROM\n");
 639                 rdev->bios = NULL;
 640                 return false;
 641         }
 642         if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 643                 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
 644                 goto free_bios;
 645         }
 646
 647         tmp = RBIOS16(0x18);
 648         if (RBIOS8(tmp + 0x14) != 0x0) {
 649                 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
 650                 goto free_bios;
 651         }
 652
 653         rdev->bios_header_start = RBIOS16(0x48);
 654         if (!rdev->bios_header_start) {
 655                 goto free_bios;
 656         }
 657         tmp = rdev->bios_header_start + 4;
 658         if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
 659             !memcmp(rdev->bios + tmp, "MOTA", 4)) {
 660                 rdev->is_atom_bios = true;
 661         } else {
 662                 rdev->is_atom_bios = false;
 663         }
 664
 665         DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
 666         return true;
 667 free_bios:
 668         kfree(rdev->bios);
 669         rdev->bios = NULL;
 670         return false;
 671 }