drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  36                         uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
  40                         uint32_t supported_device, u16 caps);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd,
  52                           struct radeon_router *router);
  53
  54 /* from radeon_legacy_encoder.c */
  55 extern void
  56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  57                           uint32_t supported_device);
  58
  59 /* local */
  60 static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
  61                                     u16 voltage_id, u16 *voltage);
  62
  63 union atom_supported_devices {
  64         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  65         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  66         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  67 };
  68
  69 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
  70                                           ATOM_GPIO_I2C_ASSIGMENT *gpio,
  71                                           u8 index)
  72 {
  73         /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
  74         if ((rdev->family == CHIP_R420) ||
  75             (rdev->family == CHIP_R423) ||
  76             (rdev->family == CHIP_RV410)) {
  77                 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
  78                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
  79                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
  80                         gpio->ucClkMaskShift = 0x19;
  81                         gpio->ucDataMaskShift = 0x18;
  82                 }
  83         }
  84
  85         /* some evergreen boards have bad data for this entry */
  86         if (ASIC_IS_DCE4(rdev)) {
  87                 if ((index == 7) &&
  88                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
  89                     (gpio->sucI2cId.ucAccess == 0)) {
  90                         gpio->sucI2cId.ucAccess = 0x97;
  91                         gpio->ucDataMaskShift = 8;
  92                         gpio->ucDataEnShift = 8;
  93                         gpio->ucDataY_Shift = 8;
  94                         gpio->ucDataA_Shift = 8;
  95                 }
  96         }
  97
  98         /* some DCE3 boards have bad data for this entry */
  99         if (ASIC_IS_DCE3(rdev)) {
 100                 if ((index == 4) &&
 101                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
 102                     (gpio->sucI2cId.ucAccess == 0x94))
 103                         gpio->sucI2cId.ucAccess = 0x14;
 104         }
 105 }
 106
 107 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
 108 {
 109         struct radeon_i2c_bus_rec i2c;
 110
 111         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 112
 113         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 114         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 115         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 116         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 117         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 118         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 119         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 120         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 121         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 122         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 123         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 124         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 125         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 126         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 127         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 128         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 129
 130         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 131                 i2c.hw_capable = true;
 132         else
 133                 i2c.hw_capable = false;
 134
 135         if (gpio->sucI2cId.ucAccess == 0xa0)
 136                 i2c.mm_i2c = true;
 137         else
 138                 i2c.mm_i2c = false;
 139
 140         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 141
 142         if (i2c.mask_clk_reg)
 143                 i2c.valid = true;
 144         else
 145                 i2c.valid = false;
 146
 147         return i2c;
 148 }
 149
 150 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
 151                                                                uint8_t id)
 152 {
 153         struct atom_context *ctx = rdev->mode_info.atom_context;
 154         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 155         struct radeon_i2c_bus_rec i2c;
 156         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 157         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 158         uint16_t data_offset, size;
 159         int i, num_indices;
 160
 161         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 162         i2c.valid = false;
 163
 164         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 165                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 166
 167                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 168                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 169
 170                 for (i = 0; i < num_indices; i++) {
 171                         gpio = &i2c_info->asGPIO_Info[i];
 172
 173                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 174
 175                         if (gpio->sucI2cId.ucAccess == id) {
 176                                 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 177                                 break;
 178                         }
 179                 }
 180         }
 181
 182         return i2c;
 183 }
 184
 185 void radeon_atombios_i2c_init(struct radeon_device *rdev)
 186 {
 187         struct atom_context *ctx = rdev->mode_info.atom_context;
 188         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 189         struct radeon_i2c_bus_rec i2c;
 190         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 191         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 192         uint16_t data_offset, size;
 193         int i, num_indices;
 194         char stmp[32];
 195
 196         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 197                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 198
 199                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 200                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 201
 202                 for (i = 0; i < num_indices; i++) {
 203                         gpio = &i2c_info->asGPIO_Info[i];
 204
 205                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 206
 207                         i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 208
 209                         if (i2c.valid) {
 210                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 211                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
 212                         }
 213                 }
 214         }
 215 }
 216
 217 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 218                                                         u8 id)
 219 {
 220         struct atom_context *ctx = rdev->mode_info.atom_context;
 221         struct radeon_gpio_rec gpio;
 222         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 223         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 224         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 225         u16 data_offset, size;
 226         int i, num_indices;
 227
 228         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 229         gpio.valid = false;
 230
 231         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 232                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 233
 234                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 235                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 236
 237                 for (i = 0; i < num_indices; i++) {
 238                         pin = &gpio_info->asGPIO_Pin[i];
 239                         if (id == pin->ucGPIO_ID) {
 240                                 gpio.id = pin->ucGPIO_ID;
 241                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
 242                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 243                                 gpio.valid = true;
 244                                 break;
 245                         }
 246                 }
 247         }
 248
 249         return gpio;
 250 }
 251
 252 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 253                                                             struct radeon_gpio_rec *gpio)
 254 {
 255         struct radeon_hpd hpd;
 256         u32 reg;
 257
 258         memset(&hpd, 0, sizeof(struct radeon_hpd));
 259
 260         if (ASIC_IS_DCE6(rdev))
 261                 reg = SI_DC_GPIO_HPD_A;
 262         else if (ASIC_IS_DCE4(rdev))
 263                 reg = EVERGREEN_DC_GPIO_HPD_A;
 264         else
 265                 reg = AVIVO_DC_GPIO_HPD_A;
 266
 267         hpd.gpio = *gpio;
 268         if (gpio->reg == reg) {
 269                 switch(gpio->mask) {
 270                 case (1 << 0):
 271                         hpd.hpd = RADEON_HPD_1;
 272                         break;
 273                 case (1 << 8):
 274                         hpd.hpd = RADEON_HPD_2;
 275                         break;
 276                 case (1 << 16):
 277                         hpd.hpd = RADEON_HPD_3;
 278                         break;
 279                 case (1 << 24):
 280                         hpd.hpd = RADEON_HPD_4;
 281                         break;
 282                 case (1 << 26):
 283                         hpd.hpd = RADEON_HPD_5;
 284                         break;
 285                 case (1 << 28):
 286                         hpd.hpd = RADEON_HPD_6;
 287                         break;
 288                 default:
 289                         hpd.hpd = RADEON_HPD_NONE;
 290                         break;
 291                 }
 292         } else
 293                 hpd.hpd = RADEON_HPD_NONE;
 294         return hpd;
 295 }
 296
 297 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 298                                      uint32_t supported_device,
 299                                      int *connector_type,
 300                                      struct radeon_i2c_bus_rec *i2c_bus,
 301                                      uint16_t *line_mux,
 302                                      struct radeon_hpd *hpd)
 303 {
 304
 305         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 306         if ((dev->pdev->device == 0x791e) &&
 307             (dev->pdev->subsystem_vendor == 0x1043) &&
 308             (dev->pdev->subsystem_device == 0x826d)) {
 309                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 310                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 311                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 312         }
 313
 314         /* Asrock RS600 board lists the DVI port as HDMI */
 315         if ((dev->pdev->device == 0x7941) &&
 316             (dev->pdev->subsystem_vendor == 0x1849) &&
 317             (dev->pdev->subsystem_device == 0x7941)) {
 318                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 319                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 320                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 321         }
 322
 323         /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
 324         if ((dev->pdev->device == 0x796e) &&
 325             (dev->pdev->subsystem_vendor == 0x1462) &&
 326             (dev->pdev->subsystem_device == 0x7302)) {
 327                 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 328                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 329                         return false;
 330         }
 331
 332         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 333         if ((dev->pdev->device == 0x7941) &&
 334             (dev->pdev->subsystem_vendor == 0x147b) &&
 335             (dev->pdev->subsystem_device == 0x2412)) {
 336                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 337                         return false;
 338         }
 339
 340         /* Falcon NW laptop lists vga ddc line for LVDS */
 341         if ((dev->pdev->device == 0x5653) &&
 342             (dev->pdev->subsystem_vendor == 0x1462) &&
 343             (dev->pdev->subsystem_device == 0x0291)) {
 344                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 345                         i2c_bus->valid = false;
 346                         *line_mux = 53;
 347                 }
 348         }
 349
 350         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 351         if ((dev->pdev->device == 0x7146) &&
 352             (dev->pdev->subsystem_vendor == 0x17af) &&
 353             (dev->pdev->subsystem_device == 0x2058)) {
 354                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 355                         return false;
 356         }
 357
 358         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 359         if ((dev->pdev->device == 0x7142) &&
 360             (dev->pdev->subsystem_vendor == 0x1458) &&
 361             (dev->pdev->subsystem_device == 0x2134)) {
 362                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 363                         return false;
 364         }
 365
 366
 367         /* Funky macbooks */
 368         if ((dev->pdev->device == 0x71C5) &&
 369             (dev->pdev->subsystem_vendor == 0x106b) &&
 370             (dev->pdev->subsystem_device == 0x0080)) {
 371                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 372                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 373                         return false;
 374                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 375                         *line_mux = 0x90;
 376         }
 377
 378         /* mac rv630, rv730, others */
 379         if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
 380             (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
 381                 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
 382                 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
 383         }
 384
 385         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 386         if ((dev->pdev->device == 0x9598) &&
 387             (dev->pdev->subsystem_vendor == 0x1043) &&
 388             (dev->pdev->subsystem_device == 0x01da)) {
 389                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 390                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 391                 }
 392         }
 393
 394         /* ASUS HD 3600 board lists the DVI port as HDMI */
 395         if ((dev->pdev->device == 0x9598) &&
 396             (dev->pdev->subsystem_vendor == 0x1043) &&
 397             (dev->pdev->subsystem_device == 0x01e4)) {
 398                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 399                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 400                 }
 401         }
 402
 403         /* ASUS HD 3450 board lists the DVI port as HDMI */
 404         if ((dev->pdev->device == 0x95C5) &&
 405             (dev->pdev->subsystem_vendor == 0x1043) &&
 406             (dev->pdev->subsystem_device == 0x01e2)) {
 407                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 408                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 409                 }
 410         }
 411
 412         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 413          * HDMI + VGA reporting as HDMI
 414          */
 415         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 416                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 417                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 418                         *line_mux = 0;
 419                 }
 420         }
 421
 422         /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
 423          * on the laptop and a DVI port on the docking station and
 424          * both share the same encoder, hpd pin, and ddc line.
 425          * So while the bios table is technically correct,
 426          * we drop the DVI port here since xrandr has no concept of
 427          * encoders and will try and drive both connectors
 428          * with different crtcs which isn't possible on the hardware
 429          * side and leaves no crtcs for LVDS or VGA.
 430          */
 431         if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
 432             (dev->pdev->subsystem_vendor == 0x1025) &&
 433             (dev->pdev->subsystem_device == 0x013c)) {
 434                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 435                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 436                         /* actually it's a DVI-D port not DVI-I */
 437                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 438                         return false;
 439                 }
 440         }
 441
 442         /* XFX Pine Group device rv730 reports no VGA DDC lines
 443          * even though they are wired up to record 0x93
 444          */
 445         if ((dev->pdev->device == 0x9498) &&
 446             (dev->pdev->subsystem_vendor == 0x1682) &&
 447             (dev->pdev->subsystem_device == 0x2452) &&
 448             (i2c_bus->valid == false) &&
 449             !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
 450                 struct radeon_device *rdev = dev->dev_private;
 451                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 452         }
 453
 454         /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
 455         if ((dev->pdev->device == 0x9802) &&
 456             (dev->pdev->subsystem_vendor == 0x1734) &&
 457             (dev->pdev->subsystem_device == 0x11bd)) {
 458                 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
 459                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 460                         *line_mux = 0x3103;
 461                 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
 462                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 463                 }
 464         }
 465
 466
 467         return true;
 468 }
 469
 470 const int supported_devices_connector_convert[] = {
 471         DRM_MODE_CONNECTOR_Unknown,
 472         DRM_MODE_CONNECTOR_VGA,
 473         DRM_MODE_CONNECTOR_DVII,
 474         DRM_MODE_CONNECTOR_DVID,
 475         DRM_MODE_CONNECTOR_DVIA,
 476         DRM_MODE_CONNECTOR_SVIDEO,
 477         DRM_MODE_CONNECTOR_Composite,
 478         DRM_MODE_CONNECTOR_LVDS,
 479         DRM_MODE_CONNECTOR_Unknown,
 480         DRM_MODE_CONNECTOR_Unknown,
 481         DRM_MODE_CONNECTOR_HDMIA,
 482         DRM_MODE_CONNECTOR_HDMIB,
 483         DRM_MODE_CONNECTOR_Unknown,
 484         DRM_MODE_CONNECTOR_Unknown,
 485         DRM_MODE_CONNECTOR_9PinDIN,
 486         DRM_MODE_CONNECTOR_DisplayPort
 487 };
 488
 489 const uint16_t supported_devices_connector_object_id_convert[] = {
 490         CONNECTOR_OBJECT_ID_NONE,
 491         CONNECTOR_OBJECT_ID_VGA,
 492         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 493         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 494         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 495         CONNECTOR_OBJECT_ID_COMPOSITE,
 496         CONNECTOR_OBJECT_ID_SVIDEO,
 497         CONNECTOR_OBJECT_ID_LVDS,
 498         CONNECTOR_OBJECT_ID_9PIN_DIN,
 499         CONNECTOR_OBJECT_ID_9PIN_DIN,
 500         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 501         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 502         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 503         CONNECTOR_OBJECT_ID_SVIDEO
 504 };
 505
 506 const int object_connector_convert[] = {
 507         DRM_MODE_CONNECTOR_Unknown,
 508         DRM_MODE_CONNECTOR_DVII,
 509         DRM_MODE_CONNECTOR_DVII,
 510         DRM_MODE_CONNECTOR_DVID,
 511         DRM_MODE_CONNECTOR_DVID,
 512         DRM_MODE_CONNECTOR_VGA,
 513         DRM_MODE_CONNECTOR_Composite,
 514         DRM_MODE_CONNECTOR_SVIDEO,
 515         DRM_MODE_CONNECTOR_Unknown,
 516         DRM_MODE_CONNECTOR_Unknown,
 517         DRM_MODE_CONNECTOR_9PinDIN,
 518         DRM_MODE_CONNECTOR_Unknown,
 519         DRM_MODE_CONNECTOR_HDMIA,
 520         DRM_MODE_CONNECTOR_HDMIB,
 521         DRM_MODE_CONNECTOR_LVDS,
 522         DRM_MODE_CONNECTOR_9PinDIN,
 523         DRM_MODE_CONNECTOR_Unknown,
 524         DRM_MODE_CONNECTOR_Unknown,
 525         DRM_MODE_CONNECTOR_Unknown,
 526         DRM_MODE_CONNECTOR_DisplayPort,
 527         DRM_MODE_CONNECTOR_eDP,
 528         DRM_MODE_CONNECTOR_Unknown
 529 };
 530
 531 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 532 {
 533         struct radeon_device *rdev = dev->dev_private;
 534         struct radeon_mode_info *mode_info = &rdev->mode_info;
 535         struct atom_context *ctx = mode_info->atom_context;
 536         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 537         u16 size, data_offset;
 538         u8 frev, crev;
 539         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 540         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 541         ATOM_OBJECT_TABLE *router_obj;
 542         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 543         ATOM_OBJECT_HEADER *obj_header;
 544         int i, j, k, path_size, device_support;
 545         int connector_type;
 546         u16 igp_lane_info, conn_id, connector_object_id;
 547         struct radeon_i2c_bus_rec ddc_bus;
 548         struct radeon_router router;
 549         struct radeon_gpio_rec gpio;
 550         struct radeon_hpd hpd;
 551
 552         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 553                 return false;
 554
 555         if (crev < 2)
 556                 return false;
 557
 558         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 559         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 560             (ctx->bios + data_offset +
 561              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 562         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 563             (ctx->bios + data_offset +
 564              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 565         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 566             (ctx->bios + data_offset +
 567              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 568         router_obj = (ATOM_OBJECT_TABLE *)
 569                 (ctx->bios + data_offset +
 570                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 571         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 572
 573         path_size = 0;
 574         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 575                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 576                 ATOM_DISPLAY_OBJECT_PATH *path;
 577                 addr += path_size;
 578                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 579                 path_size += le16_to_cpu(path->usSize);
 580
 581                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 582                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 583
 584                         con_obj_id =
 585                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 586                             >> OBJECT_ID_SHIFT;
 587                         con_obj_num =
 588                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 589                             >> ENUM_ID_SHIFT;
 590                         con_obj_type =
 591                             (le16_to_cpu(path->usConnObjectId) &
 592                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 593
 594                         /* TODO CV support */
 595                         if (le16_to_cpu(path->usDeviceTag) ==
 596                                 ATOM_DEVICE_CV_SUPPORT)
 597                                 continue;
 598
 599                         /* IGP chips */
 600                         if ((rdev->flags & RADEON_IS_IGP) &&
 601                             (con_obj_id ==
 602                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 603                                 uint16_t igp_offset = 0;
 604                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 605
 606                                 index =
 607                                     GetIndexIntoMasterTable(DATA,
 608                                                             IntegratedSystemInfo);
 609
 610                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 611                                                            &crev, &igp_offset)) {
 612
 613                                         if (crev >= 2) {
 614                                                 igp_obj =
 615                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 616                                                          *) (ctx->bios + igp_offset);
 617
 618                                                 if (igp_obj) {
 619                                                         uint32_t slot_config, ct;
 620
 621                                                         if (con_obj_num == 1)
 622                                                                 slot_config =
 623                                                                         igp_obj->
 624                                                                         ulDDISlot1Config;
 625                                                         else
 626                                                                 slot_config =
 627                                                                         igp_obj->
 628                                                                         ulDDISlot2Config;
 629
 630                                                         ct = (slot_config >> 16) & 0xff;
 631                                                         connector_type =
 632                                                                 object_connector_convert
 633                                                                 [ct];
 634                                                         connector_object_id = ct;
 635                                                         igp_lane_info =
 636                                                                 slot_config & 0xffff;
 637                                                 } else
 638                                                         continue;
 639                                         } else
 640                                                 continue;
 641                                 } else {
 642                                         igp_lane_info = 0;
 643                                         connector_type =
 644                                                 object_connector_convert[con_obj_id];
 645                                         connector_object_id = con_obj_id;
 646                                 }
 647                         } else {
 648                                 igp_lane_info = 0;
 649                                 connector_type =
 650                                     object_connector_convert[con_obj_id];
 651                                 connector_object_id = con_obj_id;
 652                         }
 653
 654                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 655                                 continue;
 656
 657                         router.ddc_valid = false;
 658                         router.cd_valid = false;
 659                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 660                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 661
 662                                 grph_obj_id =
 663                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 664                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 665                                 grph_obj_num =
 666                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 667                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 668                                 grph_obj_type =
 669                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 670                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 671
 672                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 673                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 674                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 675                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 676                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 677                                                                 (ctx->bios + data_offset +
 678                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 679                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 680                                                         u16 caps = 0;
 681
 682                                                         while (record->ucRecordSize > 0 &&
 683                                                                record->ucRecordType > 0 &&
 684                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 685                                                                 switch (record->ucRecordType) {
 686                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 687                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 688                                                                                 record;
 689                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 690                                                                         break;
 691                                                                 }
 692                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 693                                                                         ((char *)record + record->ucRecordSize);
 694                                                         }
 695                                                         radeon_add_atom_encoder(dev,
 696                                                                                 encoder_obj,
 697                                                                                 le16_to_cpu
 698                                                                                 (path->
 699                                                                                  usDeviceTag),
 700                                                                                 caps);
 701                                                 }
 702                                         }
 703                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 704                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 705                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 706                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 707                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 708                                                                 (ctx->bios + data_offset +
 709                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 710                                                         ATOM_I2C_RECORD *i2c_record;
 711                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 712                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 713                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 714                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 715                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 716                                                                 (ctx->bios + data_offset +
 717                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 718                                                         int enum_id;
 719
 720                                                         router.router_id = router_obj_id;
 721                                                         for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
 722                                                              enum_id++) {
 723                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 724                                                                     le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
 725                                                                         break;
 726                                                         }
 727
 728                                                         while (record->ucRecordSize > 0 &&
 729                                                                record->ucRecordType > 0 &&
 730                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 731                                                                 switch (record->ucRecordType) {
 732                                                                 case ATOM_I2C_RECORD_TYPE:
 733                                                                         i2c_record =
 734                                                                                 (ATOM_I2C_RECORD *)
 735                                                                                 record;
 736                                                                         i2c_config =
 737                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 738                                                                                 &i2c_record->sucI2cId;
 739                                                                         router.i2c_info =
 740                                                                                 radeon_lookup_i2c_gpio(rdev,
 741                                                                                                        i2c_config->
 742                                                                                                        ucAccess);
 743                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 744                                                                         break;
 745                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 746                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 747                                                                                 record;
 748                                                                         router.ddc_valid = true;
 749                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 750                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 751                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 752                                                                         break;
 753                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 754                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 755                                                                                 record;
 756                                                                         router.cd_valid = true;
 757                                                                         router.cd_mux_type = cd_path->ucMuxType;
 758                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 759                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 760                                                                         break;
 761                                                                 }
 762                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 763                                                                         ((char *)record + record->ucRecordSize);
 764                                                         }
 765                                                 }
 766                                         }
 767                                 }
 768                         }
 769
 770                         /* look up gpio for ddc, hpd */
 771                         ddc_bus.valid = false;
 772                         hpd.hpd = RADEON_HPD_NONE;
 773                         if ((le16_to_cpu(path->usDeviceTag) &
 774                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 775                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 776                                         if (le16_to_cpu(path->usConnObjectId) ==
 777                                             le16_to_cpu(con_obj->asObjects[j].
 778                                                         usObjectID)) {
 779                                                 ATOM_COMMON_RECORD_HEADER
 780                                                     *record =
 781                                                     (ATOM_COMMON_RECORD_HEADER
 782                                                      *)
 783                                                     (ctx->bios + data_offset +
 784                                                      le16_to_cpu(con_obj->
 785                                                                  asObjects[j].
 786                                                                  usRecordOffset));
 787                                                 ATOM_I2C_RECORD *i2c_record;
 788                                                 ATOM_HPD_INT_RECORD *hpd_record;
 789                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 790
 791                                                 while (record->ucRecordSize > 0 &&
 792                                                        record->ucRecordType > 0 &&
 793                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 794                                                         switch (record->ucRecordType) {
 795                                                         case ATOM_I2C_RECORD_TYPE:
 796                                                                 i2c_record =
 797                                                                     (ATOM_I2C_RECORD *)
 798                                                                         record;
 799                                                                 i2c_config =
 800                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 801                                                                         &i2c_record->sucI2cId;
 802                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 803                                                                                                  i2c_config->
 804                                                                                                  ucAccess);
 805                                                                 break;
 806                                                         case ATOM_HPD_INT_RECORD_TYPE:
 807                                                                 hpd_record =
 808                                                                         (ATOM_HPD_INT_RECORD *)
 809                                                                         record;
 810                                                                 gpio = radeon_lookup_gpio(rdev,
 811                                                                                           hpd_record->ucHPDIntGPIOID);
 812                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 813                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 814                                                                 break;
 815                                                         }
 816                                                         record =
 817                                                             (ATOM_COMMON_RECORD_HEADER
 818                                                              *) ((char *)record
 819                                                                  +
 820                                                                  record->
 821                                                                  ucRecordSize);
 822                                                 }
 823                                                 break;
 824                                         }
 825                                 }
 826                         }
 827
 828                         /* needed for aux chan transactions */
 829                         ddc_bus.hpd = hpd.hpd;
 830
 831                         conn_id = le16_to_cpu(path->usConnObjectId);
 832
 833                         if (!radeon_atom_apply_quirks
 834                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 835                              &ddc_bus, &conn_id, &hpd))
 836                                 continue;
 837
 838                         radeon_add_atom_connector(dev,
 839                                                   conn_id,
 840                                                   le16_to_cpu(path->
 841                                                               usDeviceTag),
 842                                                   connector_type, &ddc_bus,
 843                                                   igp_lane_info,
 844                                                   connector_object_id,
 845                                                   &hpd,
 846                                                   &router);
 847
 848                 }
 849         }
 850
 851         radeon_link_encoder_connector(dev);
 852
 853         return true;
 854 }
 855
 856 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 857                                                  int connector_type,
 858                                                  uint16_t devices)
 859 {
 860         struct radeon_device *rdev = dev->dev_private;
 861
 862         if (rdev->flags & RADEON_IS_IGP) {
 863                 return supported_devices_connector_object_id_convert
 864                         [connector_type];
 865         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 866                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 867                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 868                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 869                 struct atom_context *ctx = mode_info->atom_context;
 870                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 871                 uint16_t size, data_offset;
 872                 uint8_t frev, crev;
 873                 ATOM_XTMDS_INFO *xtmds;
 874
 875                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 876                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 877
 878                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 879                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 880                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 881                                 else
 882                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 883                         } else {
 884                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 885                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 886                                 else
 887                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 888                         }
 889                 } else
 890                         return supported_devices_connector_object_id_convert
 891                                 [connector_type];
 892         } else {
 893                 return supported_devices_connector_object_id_convert
 894                         [connector_type];
 895         }
 896 }
 897
 898 struct bios_connector {
 899         bool valid;
 900         uint16_t line_mux;
 901         uint16_t devices;
 902         int connector_type;
 903         struct radeon_i2c_bus_rec ddc_bus;
 904         struct radeon_hpd hpd;
 905 };
 906
 907 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 908                                                                  drm_device
 909                                                                  *dev)
 910 {
 911         struct radeon_device *rdev = dev->dev_private;
 912         struct radeon_mode_info *mode_info = &rdev->mode_info;
 913         struct atom_context *ctx = mode_info->atom_context;
 914         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 915         uint16_t size, data_offset;
 916         uint8_t frev, crev;
 917         uint16_t device_support;
 918         uint8_t dac;
 919         union atom_supported_devices *supported_devices;
 920         int i, j, max_device;
 921         struct bios_connector *bios_connectors;
 922         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 923         struct radeon_router router;
 924
 925         router.ddc_valid = false;
 926         router.cd_valid = false;
 927
 928         bios_connectors = kzalloc(bc_size, GFP_KERNEL);
 929         if (!bios_connectors)
 930                 return false;
 931
 932         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 933                                     &data_offset)) {
 934                 kfree(bios_connectors);
 935                 return false;
 936         }
 937
 938         supported_devices =
 939             (union atom_supported_devices *)(ctx->bios + data_offset);
 940
 941         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 942
 943         if (frev > 1)
 944                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 945         else
 946                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 947
 948         for (i = 0; i < max_device; i++) {
 949                 ATOM_CONNECTOR_INFO_I2C ci =
 950                     supported_devices->info.asConnInfo[i];
 951
 952                 bios_connectors[i].valid = false;
 953
 954                 if (!(device_support & (1 << i))) {
 955                         continue;
 956                 }
 957
 958                 if (i == ATOM_DEVICE_CV_INDEX) {
 959                         DRM_DEBUG_KMS("Skipping Component Video\n");
 960                         continue;
 961                 }
 962
 963                 bios_connectors[i].connector_type =
 964                     supported_devices_connector_convert[ci.sucConnectorInfo.
 965                                                         sbfAccess.
 966                                                         bfConnectorType];
 967
 968                 if (bios_connectors[i].connector_type ==
 969                     DRM_MODE_CONNECTOR_Unknown)
 970                         continue;
 971
 972                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 973
 974                 bios_connectors[i].line_mux =
 975                         ci.sucI2cId.ucAccess;
 976
 977                 /* give tv unique connector ids */
 978                 if (i == ATOM_DEVICE_TV1_INDEX) {
 979                         bios_connectors[i].ddc_bus.valid = false;
 980                         bios_connectors[i].line_mux = 50;
 981                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 982                         bios_connectors[i].ddc_bus.valid = false;
 983                         bios_connectors[i].line_mux = 51;
 984                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 985                         bios_connectors[i].ddc_bus.valid = false;
 986                         bios_connectors[i].line_mux = 52;
 987                 } else
 988                         bios_connectors[i].ddc_bus =
 989                             radeon_lookup_i2c_gpio(rdev,
 990                                                    bios_connectors[i].line_mux);
 991
 992                 if ((crev > 1) && (frev > 1)) {
 993                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 994                         switch (isb) {
 995                         case 0x4:
 996                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 997                                 break;
 998                         case 0xa:
 999                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1000                                 break;
1001                         default:
1002                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1003                                 break;
1004                         }
1005                 } else {
1006                         if (i == ATOM_DEVICE_DFP1_INDEX)
1007                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1008                         else if (i == ATOM_DEVICE_DFP2_INDEX)
1009                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1010                         else
1011                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1012                 }
1013
1014                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1015                  * shared with a DVI port, we'll pick up the DVI connector when we
1016                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
1017                  */
1018                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1019                         bios_connectors[i].connector_type =
1020                             DRM_MODE_CONNECTOR_VGA;
1021
1022                 if (!radeon_atom_apply_quirks
1023                     (dev, (1 << i), &bios_connectors[i].connector_type,
1024                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1025                      &bios_connectors[i].hpd))
1026                         continue;
1027
1028                 bios_connectors[i].valid = true;
1029                 bios_connectors[i].devices = (1 << i);
1030
1031                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1032                         radeon_add_atom_encoder(dev,
1033                                                 radeon_get_encoder_enum(dev,
1034                                                                       (1 << i),
1035                                                                       dac),
1036                                                 (1 << i),
1037                                                 0);
1038                 else
1039                         radeon_add_legacy_encoder(dev,
1040                                                   radeon_get_encoder_enum(dev,
1041                                                                         (1 << i),
1042                                                                         dac),
1043                                                   (1 << i));
1044         }
1045
1046         /* combine shared connectors */
1047         for (i = 0; i < max_device; i++) {
1048                 if (bios_connectors[i].valid) {
1049                         for (j = 0; j < max_device; j++) {
1050                                 if (bios_connectors[j].valid && (i != j)) {
1051                                         if (bios_connectors[i].line_mux ==
1052                                             bios_connectors[j].line_mux) {
1053                                                 /* make sure not to combine LVDS */
1054                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1055                                                         bios_connectors[i].line_mux = 53;
1056                                                         bios_connectors[i].ddc_bus.valid = false;
1057                                                         continue;
1058                                                 }
1059                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1060                                                         bios_connectors[j].line_mux = 53;
1061                                                         bios_connectors[j].ddc_bus.valid = false;
1062                                                         continue;
1063                                                 }
1064                                                 /* combine analog and digital for DVI-I */
1065                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1066                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1067                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1068                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1069                                                         bios_connectors[i].devices |=
1070                                                                 bios_connectors[j].devices;
1071                                                         bios_connectors[i].connector_type =
1072                                                                 DRM_MODE_CONNECTOR_DVII;
1073                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1074                                                                 bios_connectors[i].hpd =
1075                                                                         bios_connectors[j].hpd;
1076                                                         bios_connectors[j].valid = false;
1077                                                 }
1078                                         }
1079                                 }
1080                         }
1081                 }
1082         }
1083
1084         /* add the connectors */
1085         for (i = 0; i < max_device; i++) {
1086                 if (bios_connectors[i].valid) {
1087                         uint16_t connector_object_id =
1088                                 atombios_get_connector_object_id(dev,
1089                                                       bios_connectors[i].connector_type,
1090                                                       bios_connectors[i].devices);
1091                         radeon_add_atom_connector(dev,
1092                                                   bios_connectors[i].line_mux,
1093                                                   bios_connectors[i].devices,
1094                                                   bios_connectors[i].
1095                                                   connector_type,
1096                                                   &bios_connectors[i].ddc_bus,
1097                                                   0,
1098                                                   connector_object_id,
1099                                                   &bios_connectors[i].hpd,
1100                                                   &router);
1101                 }
1102         }
1103
1104         radeon_link_encoder_connector(dev);
1105
1106         kfree(bios_connectors);
1107         return true;
1108 }
1109
1110 union firmware_info {
1111         ATOM_FIRMWARE_INFO info;
1112         ATOM_FIRMWARE_INFO_V1_2 info_12;
1113         ATOM_FIRMWARE_INFO_V1_3 info_13;
1114         ATOM_FIRMWARE_INFO_V1_4 info_14;
1115         ATOM_FIRMWARE_INFO_V2_1 info_21;
1116         ATOM_FIRMWARE_INFO_V2_2 info_22;
1117 };
1118
1119 bool radeon_atom_get_clock_info(struct drm_device *dev)
1120 {
1121         struct radeon_device *rdev = dev->dev_private;
1122         struct radeon_mode_info *mode_info = &rdev->mode_info;
1123         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1124         union firmware_info *firmware_info;
1125         uint8_t frev, crev;
1126         struct radeon_pll *p1pll = &rdev->clock.p1pll;
1127         struct radeon_pll *p2pll = &rdev->clock.p2pll;
1128         struct radeon_pll *dcpll = &rdev->clock.dcpll;
1129         struct radeon_pll *spll = &rdev->clock.spll;
1130         struct radeon_pll *mpll = &rdev->clock.mpll;
1131         uint16_t data_offset;
1132
1133         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1134                                    &frev, &crev, &data_offset)) {
1135                 firmware_info =
1136                         (union firmware_info *)(mode_info->atom_context->bios +
1137                                                 data_offset);
1138                 /* pixel clocks */
1139                 p1pll->reference_freq =
1140                     le16_to_cpu(firmware_info->info.usReferenceClock);
1141                 p1pll->reference_div = 0;
1142
1143                 if (crev < 2)
1144                         p1pll->pll_out_min =
1145                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1146                 else
1147                         p1pll->pll_out_min =
1148                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1149                 p1pll->pll_out_max =
1150                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1151
1152                 if (crev >= 4) {
1153                         p1pll->lcd_pll_out_min =
1154                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1155                         if (p1pll->lcd_pll_out_min == 0)
1156                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1157                         p1pll->lcd_pll_out_max =
1158                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1159                         if (p1pll->lcd_pll_out_max == 0)
1160                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1161                 } else {
1162                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1163                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1164                 }
1165
1166                 if (p1pll->pll_out_min == 0) {
1167                         if (ASIC_IS_AVIVO(rdev))
1168                                 p1pll->pll_out_min = 64800;
1169                         else
1170                                 p1pll->pll_out_min = 20000;
1171                 }
1172
1173                 p1pll->pll_in_min =
1174                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1175                 p1pll->pll_in_max =
1176                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1177
1178                 *p2pll = *p1pll;
1179
1180                 /* system clock */
1181                 if (ASIC_IS_DCE4(rdev))
1182                         spll->reference_freq =
1183                                 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1184                 else
1185                         spll->reference_freq =
1186                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1187                 spll->reference_div = 0;
1188
1189                 spll->pll_out_min =
1190                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1191                 spll->pll_out_max =
1192                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1193
1194                 /* ??? */
1195                 if (spll->pll_out_min == 0) {
1196                         if (ASIC_IS_AVIVO(rdev))
1197                                 spll->pll_out_min = 64800;
1198                         else
1199                                 spll->pll_out_min = 20000;
1200                 }
1201
1202                 spll->pll_in_min =
1203                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1204                 spll->pll_in_max =
1205                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1206
1207                 /* memory clock */
1208                 if (ASIC_IS_DCE4(rdev))
1209                         mpll->reference_freq =
1210                                 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1211                 else
1212                         mpll->reference_freq =
1213                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1214                 mpll->reference_div = 0;
1215
1216                 mpll->pll_out_min =
1217                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1218                 mpll->pll_out_max =
1219                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1220
1221                 /* ??? */
1222                 if (mpll->pll_out_min == 0) {
1223                         if (ASIC_IS_AVIVO(rdev))
1224                                 mpll->pll_out_min = 64800;
1225                         else
1226                                 mpll->pll_out_min = 20000;
1227                 }
1228
1229                 mpll->pll_in_min =
1230                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1231                 mpll->pll_in_max =
1232                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1233
1234                 rdev->clock.default_sclk =
1235                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1236                 rdev->clock.default_mclk =
1237                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1238
1239                 if (ASIC_IS_DCE4(rdev)) {
1240                         rdev->clock.default_dispclk =
1241                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1242                         if (rdev->clock.default_dispclk == 0) {
1243                                 if (ASIC_IS_DCE5(rdev))
1244                                         rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1245                                 else
1246                                         rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1247                         }
1248                         rdev->clock.dp_extclk =
1249                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1250                 }
1251                 *dcpll = *p1pll;
1252
1253                 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1254                 if (rdev->clock.max_pixel_clock == 0)
1255                         rdev->clock.max_pixel_clock = 40000;
1256
1257                 return true;
1258         }
1259
1260         return false;
1261 }
1262
1263 union igp_info {
1264         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1265         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1266 };
1267
1268 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1269 {
1270         struct radeon_mode_info *mode_info = &rdev->mode_info;
1271         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1272         union igp_info *igp_info;
1273         u8 frev, crev;
1274         u16 data_offset;
1275
1276         /* sideport is AMD only */
1277         if (rdev->family == CHIP_RS600)
1278                 return false;
1279
1280         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1281                                    &frev, &crev, &data_offset)) {
1282                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1283                                       data_offset);
1284                 switch (crev) {
1285                 case 1:
1286                         if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1287                                 return true;
1288                         break;
1289                 case 2:
1290                         if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1291                                 return true;
1292                         break;
1293                 default:
1294                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1295                         break;
1296                 }
1297         }
1298         return false;
1299 }
1300
1301 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1302                                    struct radeon_encoder_int_tmds *tmds)
1303 {
1304         struct drm_device *dev = encoder->base.dev;
1305         struct radeon_device *rdev = dev->dev_private;
1306         struct radeon_mode_info *mode_info = &rdev->mode_info;
1307         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1308         uint16_t data_offset;
1309         struct _ATOM_TMDS_INFO *tmds_info;
1310         uint8_t frev, crev;
1311         uint16_t maxfreq;
1312         int i;
1313
1314         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1315                                    &frev, &crev, &data_offset)) {
1316                 tmds_info =
1317                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1318                                                    data_offset);
1319
1320                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1321                 for (i = 0; i < 4; i++) {
1322                         tmds->tmds_pll[i].freq =
1323                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1324                         tmds->tmds_pll[i].value =
1325                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1326                         tmds->tmds_pll[i].value |=
1327                             (tmds_info->asMiscInfo[i].
1328                              ucPLL_VCO_Gain & 0x3f) << 6;
1329                         tmds->tmds_pll[i].value |=
1330                             (tmds_info->asMiscInfo[i].
1331                              ucPLL_DutyCycle & 0xf) << 12;
1332                         tmds->tmds_pll[i].value |=
1333                             (tmds_info->asMiscInfo[i].
1334                              ucPLL_VoltageSwing & 0xf) << 16;
1335
1336                         DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1337                                   tmds->tmds_pll[i].freq,
1338                                   tmds->tmds_pll[i].value);
1339
1340                         if (maxfreq == tmds->tmds_pll[i].freq) {
1341                                 tmds->tmds_pll[i].freq = 0xffffffff;
1342                                 break;
1343                         }
1344                 }
1345                 return true;
1346         }
1347         return false;
1348 }
1349
1350 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1351                                       struct radeon_atom_ss *ss,
1352                                       int id)
1353 {
1354         struct radeon_mode_info *mode_info = &rdev->mode_info;
1355         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1356         uint16_t data_offset, size;
1357         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1358         uint8_t frev, crev;
1359         int i, num_indices;
1360
1361         memset(ss, 0, sizeof(struct radeon_atom_ss));
1362         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1363                                    &frev, &crev, &data_offset)) {
1364                 ss_info =
1365                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1366
1367                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1368                         sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1369
1370                 for (i = 0; i < num_indices; i++) {
1371                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1372                                 ss->percentage =
1373                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1374                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1375                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1376                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1377                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1378                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1379                                 return true;
1380                         }
1381                 }
1382         }
1383         return false;
1384 }
1385
1386 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1387                                                  struct radeon_atom_ss *ss,
1388                                                  int id)
1389 {
1390         struct radeon_mode_info *mode_info = &rdev->mode_info;
1391         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1392         u16 data_offset, size;
1393         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1394         u8 frev, crev;
1395         u16 percentage = 0, rate = 0;
1396
1397         /* get any igp specific overrides */
1398         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1399                                    &frev, &crev, &data_offset)) {
1400                 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1401                         (mode_info->atom_context->bios + data_offset);
1402                 switch (id) {
1403                 case ASIC_INTERNAL_SS_ON_TMDS:
1404                         percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1405                         rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1406                         break;
1407                 case ASIC_INTERNAL_SS_ON_HDMI:
1408                         percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1409                         rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1410                         break;
1411                 case ASIC_INTERNAL_SS_ON_LVDS:
1412                         percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1413                         rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1414                         break;
1415                 }
1416                 if (percentage)
1417                         ss->percentage = percentage;
1418                 if (rate)
1419                         ss->rate = rate;
1420         }
1421 }
1422
1423 union asic_ss_info {
1424         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1425         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1426         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1427 };
1428
1429 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1430                                       struct radeon_atom_ss *ss,
1431                                       int id, u32 clock)
1432 {
1433         struct radeon_mode_info *mode_info = &rdev->mode_info;
1434         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1435         uint16_t data_offset, size;
1436         union asic_ss_info *ss_info;
1437         uint8_t frev, crev;
1438         int i, num_indices;
1439
1440         memset(ss, 0, sizeof(struct radeon_atom_ss));
1441         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1442                                    &frev, &crev, &data_offset)) {
1443
1444                 ss_info =
1445                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1446
1447                 switch (frev) {
1448                 case 1:
1449                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1450                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1451
1452                         for (i = 0; i < num_indices; i++) {
1453                                 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1454                                     (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1455                                         ss->percentage =
1456                                                 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1457                                         ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1458                                         ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1459                                         return true;
1460                                 }
1461                         }
1462                         break;
1463                 case 2:
1464                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1465                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1466                         for (i = 0; i < num_indices; i++) {
1467                                 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1468                                     (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1469                                         ss->percentage =
1470                                                 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1471                                         ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1472                                         ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1473                                         return true;
1474                                 }
1475                         }
1476                         break;
1477                 case 3:
1478                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1479                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1480                         for (i = 0; i < num_indices; i++) {
1481                                 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1482                                     (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1483                                         ss->percentage =
1484                                                 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1485                                         ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1486                                         ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1487                                         if (rdev->flags & RADEON_IS_IGP)
1488                                                 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1489                                         return true;
1490                                 }
1491                         }
1492                         break;
1493                 default:
1494                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1495                         break;
1496                 }
1497
1498         }
1499         return false;
1500 }
1501
1502 union lvds_info {
1503         struct _ATOM_LVDS_INFO info;
1504         struct _ATOM_LVDS_INFO_V12 info_12;
1505 };
1506
1507 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1508                                                               radeon_encoder
1509                                                               *encoder)
1510 {
1511         struct drm_device *dev = encoder->base.dev;
1512         struct radeon_device *rdev = dev->dev_private;
1513         struct radeon_mode_info *mode_info = &rdev->mode_info;
1514         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1515         uint16_t data_offset, misc;
1516         union lvds_info *lvds_info;
1517         uint8_t frev, crev;
1518         struct radeon_encoder_atom_dig *lvds = NULL;
1519         int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1520
1521         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1522                                    &frev, &crev, &data_offset)) {
1523                 lvds_info =
1524                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1525                 lvds =
1526                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1527
1528                 if (!lvds)
1529                         return NULL;
1530
1531                 lvds->native_mode.clock =
1532                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1533                 lvds->native_mode.hdisplay =
1534                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1535                 lvds->native_mode.vdisplay =
1536                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1537                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1538                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1539                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1540                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1541                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1542                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1543                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1544                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1545                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1546                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1547                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1548                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1549                 lvds->panel_pwr_delay =
1550                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1551                 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1552
1553                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1554                 if (misc & ATOM_VSYNC_POLARITY)
1555                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1556                 if (misc & ATOM_HSYNC_POLARITY)
1557                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1558                 if (misc & ATOM_COMPOSITESYNC)
1559                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1560                 if (misc & ATOM_INTERLACE)
1561                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1562                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1563                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1564
1565                 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1566                 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1567
1568                 /* set crtc values */
1569                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1570
1571                 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1572
1573                 encoder->native_mode = lvds->native_mode;
1574
1575                 if (encoder_enum == 2)
1576                         lvds->linkb = true;
1577                 else
1578                         lvds->linkb = false;
1579
1580                 /* parse the lcd record table */
1581                 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1582                         ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1583                         ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1584                         bool bad_record = false;
1585                         u8 *record;
1586
1587                         if ((frev == 1) && (crev < 2))
1588                                 /* absolute */
1589                                 record = (u8 *)(mode_info->atom_context->bios +
1590                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1591                         else
1592                                 /* relative */
1593                                 record = (u8 *)(mode_info->atom_context->bios +
1594                                                 data_offset +
1595                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1596                         while (*record != ATOM_RECORD_END_TYPE) {
1597                                 switch (*record) {
1598                                 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1599                                         record += sizeof(ATOM_PATCH_RECORD_MODE);
1600                                         break;
1601                                 case LCD_RTS_RECORD_TYPE:
1602                                         record += sizeof(ATOM_LCD_RTS_RECORD);
1603                                         break;
1604                                 case LCD_CAP_RECORD_TYPE:
1605                                         record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1606                                         break;
1607                                 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1608                                         fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1609                                         if (fake_edid_record->ucFakeEDIDLength) {
1610                                                 struct edid *edid;
1611                                                 int edid_size =
1612                                                         max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1613                                                 edid = kmalloc(edid_size, GFP_KERNEL);
1614                                                 if (edid) {
1615                                                         memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1616                                                                fake_edid_record->ucFakeEDIDLength);
1617
1618                                                         if (drm_edid_is_valid(edid)) {
1619                                                                 rdev->mode_info.bios_hardcoded_edid = edid;
1620                                                                 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1621                                                         } else
1622                                                                 kfree(edid);
1623                                                 }
1624                                         }
1625                                         record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1626                                         break;
1627                                 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1628                                         panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1629                                         lvds->native_mode.width_mm = panel_res_record->usHSize;
1630                                         lvds->native_mode.height_mm = panel_res_record->usVSize;
1631                                         record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1632                                         break;
1633                                 default:
1634                                         DRM_ERROR("Bad LCD record %d\n", *record);
1635                                         bad_record = true;
1636                                         break;
1637                                 }
1638                                 if (bad_record)
1639                                         break;
1640                         }
1641                 }
1642         }
1643         return lvds;
1644 }
1645
1646 struct radeon_encoder_primary_dac *
1647 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1648 {
1649         struct drm_device *dev = encoder->base.dev;
1650         struct radeon_device *rdev = dev->dev_private;
1651         struct radeon_mode_info *mode_info = &rdev->mode_info;
1652         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1653         uint16_t data_offset;
1654         struct _COMPASSIONATE_DATA *dac_info;
1655         uint8_t frev, crev;
1656         uint8_t bg, dac;
1657         struct radeon_encoder_primary_dac *p_dac = NULL;
1658
1659         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1660                                    &frev, &crev, &data_offset)) {
1661                 dac_info = (struct _COMPASSIONATE_DATA *)
1662                         (mode_info->atom_context->bios + data_offset);
1663
1664                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1665
1666                 if (!p_dac)
1667                         return NULL;
1668
1669                 bg = dac_info->ucDAC1_BG_Adjustment;
1670                 dac = dac_info->ucDAC1_DAC_Adjustment;
1671                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1672
1673         }
1674         return p_dac;
1675 }
1676
1677 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1678                                 struct drm_display_mode *mode)
1679 {
1680         struct radeon_mode_info *mode_info = &rdev->mode_info;
1681         ATOM_ANALOG_TV_INFO *tv_info;
1682         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1683         ATOM_DTD_FORMAT *dtd_timings;
1684         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1685         u8 frev, crev;
1686         u16 data_offset, misc;
1687
1688         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1689                                     &frev, &crev, &data_offset))
1690                 return false;
1691
1692         switch (crev) {
1693         case 1:
1694                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1695                 if (index >= MAX_SUPPORTED_TV_TIMING)
1696                         return false;
1697
1698                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1699                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1700                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1701                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1702                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1703
1704                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1705                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1706                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1707                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1708                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1709
1710                 mode->flags = 0;
1711                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1712                 if (misc & ATOM_VSYNC_POLARITY)
1713                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1714                 if (misc & ATOM_HSYNC_POLARITY)
1715                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1716                 if (misc & ATOM_COMPOSITESYNC)
1717                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1718                 if (misc & ATOM_INTERLACE)
1719                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1720                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1721                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1722
1723                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1724
1725                 if (index == 1) {
1726                         /* PAL timings appear to have wrong values for totals */
1727                         mode->crtc_htotal -= 1;
1728                         mode->crtc_vtotal -= 1;
1729                 }
1730                 break;
1731         case 2:
1732                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1733                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1734                         return false;
1735
1736                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1737                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1738                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1739                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1740                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1741                         le16_to_cpu(dtd_timings->usHSyncOffset);
1742                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1743                         le16_to_cpu(dtd_timings->usHSyncWidth);
1744
1745                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1746                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1747                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1748                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1749                         le16_to_cpu(dtd_timings->usVSyncOffset);
1750                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1751                         le16_to_cpu(dtd_timings->usVSyncWidth);
1752
1753                 mode->flags = 0;
1754                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1755                 if (misc & ATOM_VSYNC_POLARITY)
1756                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1757                 if (misc & ATOM_HSYNC_POLARITY)
1758                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1759                 if (misc & ATOM_COMPOSITESYNC)
1760                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1761                 if (misc & ATOM_INTERLACE)
1762                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1763                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1764                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1765
1766                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1767                 break;
1768         }
1769         return true;
1770 }
1771
1772 enum radeon_tv_std
1773 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1774 {
1775         struct radeon_mode_info *mode_info = &rdev->mode_info;
1776         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1777         uint16_t data_offset;
1778         uint8_t frev, crev;
1779         struct _ATOM_ANALOG_TV_INFO *tv_info;
1780         enum radeon_tv_std tv_std = TV_STD_NTSC;
1781
1782         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1783                                    &frev, &crev, &data_offset)) {
1784
1785                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1786                         (mode_info->atom_context->bios + data_offset);
1787
1788                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1789                 case ATOM_TV_NTSC:
1790                         tv_std = TV_STD_NTSC;
1791                         DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1792                         break;
1793                 case ATOM_TV_NTSCJ:
1794                         tv_std = TV_STD_NTSC_J;
1795                         DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1796                         break;
1797                 case ATOM_TV_PAL:
1798                         tv_std = TV_STD_PAL;
1799                         DRM_DEBUG_KMS("Default TV standard: PAL\n");
1800                         break;
1801                 case ATOM_TV_PALM:
1802                         tv_std = TV_STD_PAL_M;
1803                         DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1804                         break;
1805                 case ATOM_TV_PALN:
1806                         tv_std = TV_STD_PAL_N;
1807                         DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1808                         break;
1809                 case ATOM_TV_PALCN:
1810                         tv_std = TV_STD_PAL_CN;
1811                         DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1812                         break;
1813                 case ATOM_TV_PAL60:
1814                         tv_std = TV_STD_PAL_60;
1815                         DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1816                         break;
1817                 case ATOM_TV_SECAM:
1818                         tv_std = TV_STD_SECAM;
1819                         DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1820                         break;
1821                 default:
1822                         tv_std = TV_STD_NTSC;
1823                         DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1824                         break;
1825                 }
1826         }
1827         return tv_std;
1828 }
1829
1830 struct radeon_encoder_tv_dac *
1831 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1832 {
1833         struct drm_device *dev = encoder->base.dev;
1834         struct radeon_device *rdev = dev->dev_private;
1835         struct radeon_mode_info *mode_info = &rdev->mode_info;
1836         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1837         uint16_t data_offset;
1838         struct _COMPASSIONATE_DATA *dac_info;
1839         uint8_t frev, crev;
1840         uint8_t bg, dac;
1841         struct radeon_encoder_tv_dac *tv_dac = NULL;
1842
1843         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1844                                    &frev, &crev, &data_offset)) {
1845
1846                 dac_info = (struct _COMPASSIONATE_DATA *)
1847                         (mode_info->atom_context->bios + data_offset);
1848
1849                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1850
1851                 if (!tv_dac)
1852                         return NULL;
1853
1854                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1855                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1856                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1857
1858                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1859                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1860                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1861
1862                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1863                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1864                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1865
1866                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1867         }
1868         return tv_dac;
1869 }
1870
1871 static const char *thermal_controller_names[] = {
1872         "NONE",
1873         "lm63",
1874         "adm1032",
1875         "adm1030",
1876         "max6649",
1877         "lm64",
1878         "f75375",
1879         "asc7xxx",
1880 };
1881
1882 static const char *pp_lib_thermal_controller_names[] = {
1883         "NONE",
1884         "lm63",
1885         "adm1032",
1886         "adm1030",
1887         "max6649",
1888         "lm64",
1889         "f75375",
1890         "RV6xx",
1891         "RV770",
1892         "adt7473",
1893         "NONE",
1894         "External GPIO",
1895         "Evergreen",
1896         "emc2103",
1897         "Sumo",
1898         "Northern Islands",
1899         "Southern Islands",
1900         "lm96163",
1901 };
1902
1903 union power_info {
1904         struct _ATOM_POWERPLAY_INFO info;
1905         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1906         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1907         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1908         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1909         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1910 };
1911
1912 union pplib_clock_info {
1913         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1914         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1915         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1916         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1917         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
1918 };
1919
1920 union pplib_power_state {
1921         struct _ATOM_PPLIB_STATE v1;
1922         struct _ATOM_PPLIB_STATE_V2 v2;
1923 };
1924
1925 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1926                                                  int state_index,
1927                                                  u32 misc, u32 misc2)
1928 {
1929         rdev->pm.power_state[state_index].misc = misc;
1930         rdev->pm.power_state[state_index].misc2 = misc2;
1931         /* order matters! */
1932         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1933                 rdev->pm.power_state[state_index].type =
1934                         POWER_STATE_TYPE_POWERSAVE;
1935         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1936                 rdev->pm.power_state[state_index].type =
1937                         POWER_STATE_TYPE_BATTERY;
1938         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1939                 rdev->pm.power_state[state_index].type =
1940                         POWER_STATE_TYPE_BATTERY;
1941         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1942                 rdev->pm.power_state[state_index].type =
1943                         POWER_STATE_TYPE_BALANCED;
1944         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1945                 rdev->pm.power_state[state_index].type =
1946                         POWER_STATE_TYPE_PERFORMANCE;
1947                 rdev->pm.power_state[state_index].flags &=
1948                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1949         }
1950         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1951                 rdev->pm.power_state[state_index].type =
1952                         POWER_STATE_TYPE_BALANCED;
1953         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1954                 rdev->pm.power_state[state_index].type =
1955                         POWER_STATE_TYPE_DEFAULT;
1956                 rdev->pm.default_power_state_index = state_index;
1957                 rdev->pm.power_state[state_index].default_clock_mode =
1958                         &rdev->pm.power_state[state_index].clock_info[0];
1959         } else if (state_index == 0) {
1960                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1961                         RADEON_PM_MODE_NO_DISPLAY;
1962         }
1963 }
1964
1965 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1966 {
1967         struct radeon_mode_info *mode_info = &rdev->mode_info;
1968         u32 misc, misc2 = 0;
1969         int num_modes = 0, i;
1970         int state_index = 0;
1971         struct radeon_i2c_bus_rec i2c_bus;
1972         union power_info *power_info;
1973         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1974         u16 data_offset;
1975         u8 frev, crev;
1976
1977         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1978                                    &frev, &crev, &data_offset))
1979                 return state_index;
1980         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1981
1982         /* add the i2c bus for thermal/fan chip */
1983         if (power_info->info.ucOverdriveThermalController > 0) {
1984                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1985                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
1986                          power_info->info.ucOverdriveControllerAddress >> 1);
1987                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1988                 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1989                 if (rdev->pm.i2c_bus) {
1990                         struct i2c_board_info info = { };
1991                         const char *name = thermal_controller_names[power_info->info.
1992                                                                     ucOverdriveThermalController];
1993                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1994                         strlcpy(info.type, name, sizeof(info.type));
1995                         i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1996                 }
1997         }
1998         num_modes = power_info->info.ucNumOfPowerModeEntries;
1999         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2000                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2001         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2002         if (!rdev->pm.power_state)
2003                 return state_index;
2004         /* last mode is usually default, array is low to high */
2005         for (i = 0; i < num_modes; i++) {
2006                 rdev->pm.power_state[state_index].clock_info =
2007                         kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2008                 if (!rdev->pm.power_state[state_index].clock_info)
2009                         return state_index;
2010                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2011                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2012                 switch (frev) {
2013                 case 1:
2014                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2015                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2016                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2017                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2018                         /* skip invalid modes */
2019                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2020                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2021                                 continue;
2022                         rdev->pm.power_state[state_index].pcie_lanes =
2023                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2024                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2025                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2026                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2027                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2028                                         VOLTAGE_GPIO;
2029                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2030                                         radeon_lookup_gpio(rdev,
2031                                                            power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2032                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2033                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2034                                                 true;
2035                                 else
2036                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2037                                                 false;
2038                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2039                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2040                                         VOLTAGE_VDDC;
2041                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2042                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2043                         }
2044                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2045                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2046                         state_index++;
2047                         break;
2048                 case 2:
2049                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2050                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2051                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2052                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2053                         /* skip invalid modes */
2054                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2055                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2056                                 continue;
2057                         rdev->pm.power_state[state_index].pcie_lanes =
2058                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2059                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2060                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2061                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2062                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2063                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2064                                         VOLTAGE_GPIO;
2065                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2066                                         radeon_lookup_gpio(rdev,
2067                                                            power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2068                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2069                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2070                                                 true;
2071                                 else
2072                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2073                                                 false;
2074                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2075                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2076                                         VOLTAGE_VDDC;
2077                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2078                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2079                         }
2080                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2081                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2082                         state_index++;
2083                         break;
2084                 case 3:
2085                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2086                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2087                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2088                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2089                         /* skip invalid modes */
2090                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2091                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2092                                 continue;
2093                         rdev->pm.power_state[state_index].pcie_lanes =
2094                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2095                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2096                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2097                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2098                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2099                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2100                                         VOLTAGE_GPIO;
2101                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2102                                         radeon_lookup_gpio(rdev,
2103                                                            power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2104                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2105                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2106                                                 true;
2107                                 else
2108                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2109                                                 false;
2110                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2111                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2112                                         VOLTAGE_VDDC;
2113                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2114                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2115                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2116                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2117                                                 true;
2118                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2119                                                 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2120                                 }
2121                         }
2122                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2123                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2124                         state_index++;
2125                         break;
2126                 }
2127         }
2128         /* last mode is usually default */
2129         if (rdev->pm.default_power_state_index == -1) {
2130                 rdev->pm.power_state[state_index - 1].type =
2131                         POWER_STATE_TYPE_DEFAULT;
2132                 rdev->pm.default_power_state_index = state_index - 1;
2133                 rdev->pm.power_state[state_index - 1].default_clock_mode =
2134                         &rdev->pm.power_state[state_index - 1].clock_info[0];
2135                 rdev->pm.power_state[state_index].flags &=
2136                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2137                 rdev->pm.power_state[state_index].misc = 0;
2138                 rdev->pm.power_state[state_index].misc2 = 0;
2139         }
2140         return state_index;
2141 }
2142
2143 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2144                                                          ATOM_PPLIB_THERMALCONTROLLER *controller)
2145 {
2146         struct radeon_i2c_bus_rec i2c_bus;
2147
2148         /* add the i2c bus for thermal/fan chip */
2149         if (controller->ucType > 0) {
2150                 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2151                         DRM_INFO("Internal thermal controller %s fan control\n",
2152                                  (controller->ucFanParameters &
2153                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2154                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2155                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2156                         DRM_INFO("Internal thermal controller %s fan control\n",
2157                                  (controller->ucFanParameters &
2158                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2159                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2160                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2161                         DRM_INFO("Internal thermal controller %s fan control\n",
2162                                  (controller->ucFanParameters &
2163                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2164                         rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2165                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2166                         DRM_INFO("Internal thermal controller %s fan control\n",
2167                                  (controller->ucFanParameters &
2168                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2169                         rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2170                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2171                         DRM_INFO("Internal thermal controller %s fan control\n",
2172                                  (controller->ucFanParameters &
2173                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2174                         rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2175                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2176                         DRM_INFO("Internal thermal controller %s fan control\n",
2177                                  (controller->ucFanParameters &
2178                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2179                         rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2180                 } else if ((controller->ucType ==
2181                             ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2182                            (controller->ucType ==
2183                             ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2184                            (controller->ucType ==
2185                             ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2186                         DRM_INFO("Special thermal controller config\n");
2187                 } else {
2188                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2189                                  pp_lib_thermal_controller_names[controller->ucType],
2190                                  controller->ucI2cAddress >> 1,
2191                                  (controller->ucFanParameters &
2192                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2193                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2194                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2195                         if (rdev->pm.i2c_bus) {
2196                                 struct i2c_board_info info = { };
2197                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2198                                 info.addr = controller->ucI2cAddress >> 1;
2199                                 strlcpy(info.type, name, sizeof(info.type));
2200                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2201                         }
2202                 }
2203         }
2204 }
2205
2206 static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2207                                                  u16 *vddc, u16 *vddci)
2208 {
2209         struct radeon_mode_info *mode_info = &rdev->mode_info;
2210         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2211         u8 frev, crev;
2212         u16 data_offset;
2213         union firmware_info *firmware_info;
2214
2215         *vddc = 0;
2216         *vddci = 0;
2217
2218         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2219                                    &frev, &crev, &data_offset)) {
2220                 firmware_info =
2221                         (union firmware_info *)(mode_info->atom_context->bios +
2222                                                 data_offset);
2223                 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2224                 if ((frev == 2) && (crev >= 2))
2225                         *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2226         }
2227 }
2228
2229 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2230                                                        int state_index, int mode_index,
2231                                                        struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2232 {
2233         int j;
2234         u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2235         u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2236         u16 vddc, vddci;
2237
2238         radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2239
2240         rdev->pm.power_state[state_index].misc = misc;
2241         rdev->pm.power_state[state_index].misc2 = misc2;
2242         rdev->pm.power_state[state_index].pcie_lanes =
2243                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2244                  ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2245         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2246         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2247                 rdev->pm.power_state[state_index].type =
2248                         POWER_STATE_TYPE_BATTERY;
2249                 break;
2250         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2251                 rdev->pm.power_state[state_index].type =
2252                         POWER_STATE_TYPE_BALANCED;
2253                 break;
2254         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2255                 rdev->pm.power_state[state_index].type =
2256                         POWER_STATE_TYPE_PERFORMANCE;
2257                 break;
2258         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2259                 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2260                         rdev->pm.power_state[state_index].type =
2261                                 POWER_STATE_TYPE_PERFORMANCE;
2262                 break;
2263         }
2264         rdev->pm.power_state[state_index].flags = 0;
2265         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2266                 rdev->pm.power_state[state_index].flags |=
2267                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2268         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2269                 rdev->pm.power_state[state_index].type =
2270                         POWER_STATE_TYPE_DEFAULT;
2271                 rdev->pm.default_power_state_index = state_index;
2272                 rdev->pm.power_state[state_index].default_clock_mode =
2273                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2274                 if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2275                         /* NI chips post without MC ucode, so default clocks are strobe mode only */
2276                         rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2277                         rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2278                         rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2279                         rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2280                 } else {
2281                         /* patch the table values with the default slck/mclk from firmware info */
2282                         for (j = 0; j < mode_index; j++) {
2283                                 rdev->pm.power_state[state_index].clock_info[j].mclk =
2284                                         rdev->clock.default_mclk;
2285                                 rdev->pm.power_state[state_index].clock_info[j].sclk =
2286                                         rdev->clock.default_sclk;
2287                                 if (vddc)
2288                                         rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2289                                                 vddc;
2290                         }
2291                 }
2292         }
2293 }
2294
2295 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2296                                                    int state_index, int mode_index,
2297                                                    union pplib_clock_info *clock_info)
2298 {
2299         u32 sclk, mclk;
2300         u16 vddc;
2301
2302         if (rdev->flags & RADEON_IS_IGP) {
2303                 if (rdev->family >= CHIP_PALM) {
2304                         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2305                         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2306                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2307                 } else {
2308                         sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2309                         sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2310                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2311                 }
2312         } else if (ASIC_IS_DCE6(rdev)) {
2313                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2314                 sclk |= clock_info->si.ucEngineClockHigh << 16;
2315                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2316                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2317                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2318                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2319                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2320                         VOLTAGE_SW;
2321                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2322                         le16_to_cpu(clock_info->si.usVDDC);
2323                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2324                         le16_to_cpu(clock_info->si.usVDDCI);
2325         } else if (ASIC_IS_DCE4(rdev)) {
2326                 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2327                 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2328                 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2329                 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2330                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2331                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2332                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2333                         VOLTAGE_SW;
2334                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2335                         le16_to_cpu(clock_info->evergreen.usVDDC);
2336                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2337                         le16_to_cpu(clock_info->evergreen.usVDDCI);
2338         } else {
2339                 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2340                 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2341                 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2342                 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2343                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2344                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2345                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2346                         VOLTAGE_SW;
2347                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2348                         le16_to_cpu(clock_info->r600.usVDDC);
2349         }
2350
2351         /* patch up vddc if necessary */
2352         switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2353         case ATOM_VIRTUAL_VOLTAGE_ID0:
2354         case ATOM_VIRTUAL_VOLTAGE_ID1:
2355         case ATOM_VIRTUAL_VOLTAGE_ID2:
2356         case ATOM_VIRTUAL_VOLTAGE_ID3:
2357                 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2358                                              rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2359                                              &vddc) == 0)
2360                         rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2361                 break;
2362         default:
2363                 break;
2364         }
2365
2366         if (rdev->flags & RADEON_IS_IGP) {
2367                 /* skip invalid modes */
2368                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2369                         return false;
2370         } else {
2371                 /* skip invalid modes */
2372                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2373                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2374                         return false;
2375         }
2376         return true;
2377 }
2378
2379 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2380 {
2381         struct radeon_mode_info *mode_info = &rdev->mode_info;
2382         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2383         union pplib_power_state *power_state;
2384         int i, j;
2385         int state_index = 0, mode_index = 0;
2386         union pplib_clock_info *clock_info;
2387         bool valid;
2388         union power_info *power_info;
2389         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2390         u16 data_offset;
2391         u8 frev, crev;
2392
2393         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2394                                    &frev, &crev, &data_offset))
2395                 return state_index;
2396         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2397
2398         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2399         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2400                                        power_info->pplib.ucNumStates, GFP_KERNEL);
2401         if (!rdev->pm.power_state)
2402                 return state_index;
2403         /* first mode is usually default, followed by low to high */
2404         for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2405                 mode_index = 0;
2406                 power_state = (union pplib_power_state *)
2407                         (mode_info->atom_context->bios + data_offset +
2408                          le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2409                          i * power_info->pplib.ucStateEntrySize);
2410                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2411                         (mode_info->atom_context->bios + data_offset +
2412                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2413                          (power_state->v1.ucNonClockStateIndex *
2414                           power_info->pplib.ucNonClockSize));
2415                 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2416                                                              ((power_info->pplib.ucStateEntrySize - 1) ?
2417                                                               (power_info->pplib.ucStateEntrySize - 1) : 1),
2418                                                              GFP_KERNEL);
2419                 if (!rdev->pm.power_state[i].clock_info)
2420                         return state_index;
2421                 if (power_info->pplib.ucStateEntrySize - 1) {
2422                         for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2423                                 clock_info = (union pplib_clock_info *)
2424                                         (mode_info->atom_context->bios + data_offset +
2425                                          le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2426                                          (power_state->v1.ucClockStateIndices[j] *
2427                                           power_info->pplib.ucClockInfoSize));
2428                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2429                                                                                state_index, mode_index,
2430                                                                                clock_info);
2431                                 if (valid)
2432                                         mode_index++;
2433                         }
2434                 } else {
2435                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2436                                 rdev->clock.default_mclk;
2437                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2438                                 rdev->clock.default_sclk;
2439                         mode_index++;
2440                 }
2441                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2442                 if (mode_index) {
2443                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2444                                                                    non_clock_info);
2445                         state_index++;
2446                 }
2447         }
2448         /* if multiple clock modes, mark the lowest as no display */
2449         for (i = 0; i < state_index; i++) {
2450                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2451                         rdev->pm.power_state[i].clock_info[0].flags |=
2452                                 RADEON_PM_MODE_NO_DISPLAY;
2453         }
2454         /* first mode is usually default */
2455         if (rdev->pm.default_power_state_index == -1) {
2456                 rdev->pm.power_state[0].type =
2457                         POWER_STATE_TYPE_DEFAULT;
2458                 rdev->pm.default_power_state_index = 0;
2459                 rdev->pm.power_state[0].default_clock_mode =
2460                         &rdev->pm.power_state[0].clock_info[0];
2461         }
2462         return state_index;
2463 }
2464
2465 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2466 {
2467         struct radeon_mode_info *mode_info = &rdev->mode_info;
2468         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2469         union pplib_power_state *power_state;
2470         int i, j, non_clock_array_index, clock_array_index;
2471         int state_index = 0, mode_index = 0;
2472         union pplib_clock_info *clock_info;
2473         struct _StateArray *state_array;
2474         struct _ClockInfoArray *clock_info_array;
2475         struct _NonClockInfoArray *non_clock_info_array;
2476         bool valid;
2477         union power_info *power_info;
2478         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2479         u16 data_offset;
2480         u8 frev, crev;
2481
2482         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2483                                    &frev, &crev, &data_offset))
2484                 return state_index;
2485         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2486
2487         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2488         state_array = (struct _StateArray *)
2489                 (mode_info->atom_context->bios + data_offset +
2490                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2491         clock_info_array = (struct _ClockInfoArray *)
2492                 (mode_info->atom_context->bios + data_offset +
2493                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2494         non_clock_info_array = (struct _NonClockInfoArray *)
2495                 (mode_info->atom_context->bios + data_offset +
2496                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2497         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2498                                        state_array->ucNumEntries, GFP_KERNEL);
2499         if (!rdev->pm.power_state)
2500                 return state_index;
2501         for (i = 0; i < state_array->ucNumEntries; i++) {
2502                 mode_index = 0;
2503                 power_state = (union pplib_power_state *)&state_array->states[i];
2504                 /* XXX this might be an inagua bug... */
2505                 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2506                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2507                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2508                 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2509                                                              (power_state->v2.ucNumDPMLevels ?
2510                                                               power_state->v2.ucNumDPMLevels : 1),
2511                                                              GFP_KERNEL);
2512                 if (!rdev->pm.power_state[i].clock_info)
2513                         return state_index;
2514                 if (power_state->v2.ucNumDPMLevels) {
2515                         for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2516                                 clock_array_index = power_state->v2.clockInfoIndex[j];
2517                                 /* XXX this might be an inagua bug... */
2518                                 if (clock_array_index >= clock_info_array->ucNumEntries)
2519                                         continue;
2520                                 clock_info = (union pplib_clock_info *)
2521                                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2522                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2523                                                                                state_index, mode_index,
2524                                                                                clock_info);
2525                                 if (valid)
2526                                         mode_index++;
2527                         }
2528                 } else {
2529                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2530                                 rdev->clock.default_mclk;
2531                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2532                                 rdev->clock.default_sclk;
2533                         mode_index++;
2534                 }
2535                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2536                 if (mode_index) {
2537                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2538                                                                    non_clock_info);
2539                         state_index++;
2540                 }
2541         }
2542         /* if multiple clock modes, mark the lowest as no display */
2543         for (i = 0; i < state_index; i++) {
2544                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2545                         rdev->pm.power_state[i].clock_info[0].flags |=
2546                                 RADEON_PM_MODE_NO_DISPLAY;
2547         }
2548         /* first mode is usually default */
2549         if (rdev->pm.default_power_state_index == -1) {
2550                 rdev->pm.power_state[0].type =
2551                         POWER_STATE_TYPE_DEFAULT;
2552                 rdev->pm.default_power_state_index = 0;
2553                 rdev->pm.power_state[0].default_clock_mode =
2554                         &rdev->pm.power_state[0].clock_info[0];
2555         }
2556         return state_index;
2557 }
2558
2559 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2560 {
2561         struct radeon_mode_info *mode_info = &rdev->mode_info;
2562         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2563         u16 data_offset;
2564         u8 frev, crev;
2565         int state_index = 0;
2566
2567         rdev->pm.default_power_state_index = -1;
2568
2569         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2570                                    &frev, &crev, &data_offset)) {
2571                 switch (frev) {
2572                 case 1:
2573                 case 2:
2574                 case 3:
2575                         state_index = radeon_atombios_parse_power_table_1_3(rdev);
2576                         break;
2577                 case 4:
2578                 case 5:
2579                         state_index = radeon_atombios_parse_power_table_4_5(rdev);
2580                         break;
2581                 case 6:
2582                         state_index = radeon_atombios_parse_power_table_6(rdev);
2583                         break;
2584                 default:
2585                         break;
2586                 }
2587         } else {
2588                 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2589                 if (rdev->pm.power_state) {
2590                         rdev->pm.power_state[0].clock_info =
2591                                 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2592                         if (rdev->pm.power_state[0].clock_info) {
2593                                 /* add the default mode */
2594                                 rdev->pm.power_state[state_index].type =
2595                                         POWER_STATE_TYPE_DEFAULT;
2596                                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2597                                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2598                                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2599                                 rdev->pm.power_state[state_index].default_clock_mode =
2600                                         &rdev->pm.power_state[state_index].clock_info[0];
2601                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2602                                 rdev->pm.power_state[state_index].pcie_lanes = 16;
2603                                 rdev->pm.default_power_state_index = state_index;
2604                                 rdev->pm.power_state[state_index].flags = 0;
2605                                 state_index++;
2606                         }
2607                 }
2608         }
2609
2610         rdev->pm.num_power_states = state_index;
2611
2612         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2613         rdev->pm.current_clock_mode_index = 0;
2614         if (rdev->pm.default_power_state_index >= 0)
2615                 rdev->pm.current_vddc =
2616                         rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2617         else
2618                 rdev->pm.current_vddc = 0;
2619 }
2620
2621 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2622 {
2623         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2624         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2625
2626         args.ucEnable = enable;
2627
2628         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2629 }
2630
2631 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2632 {
2633         GET_ENGINE_CLOCK_PS_ALLOCATION args;
2634         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2635
2636         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2637         return le32_to_cpu(args.ulReturnEngineClock);
2638 }
2639
2640 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2641 {
2642         GET_MEMORY_CLOCK_PS_ALLOCATION args;
2643         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2644
2645         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2646         return le32_to_cpu(args.ulReturnMemoryClock);
2647 }
2648
2649 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2650                                   uint32_t eng_clock)
2651 {
2652         SET_ENGINE_CLOCK_PS_ALLOCATION args;
2653         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2654
2655         args.ulTargetEngineClock = cpu_to_le32(eng_clock);      /* 10 khz */
2656
2657         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2658 }
2659
2660 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2661                                   uint32_t mem_clock)
2662 {
2663         SET_MEMORY_CLOCK_PS_ALLOCATION args;
2664         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2665
2666         if (rdev->flags & RADEON_IS_IGP)
2667                 return;
2668
2669         args.ulTargetMemoryClock = cpu_to_le32(mem_clock);      /* 10 khz */
2670
2671         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2672 }
2673
2674 union set_voltage {
2675         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2676         struct _SET_VOLTAGE_PARAMETERS v1;
2677         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2678         struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
2679 };
2680
2681 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2682 {
2683         union set_voltage args;
2684         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2685         u8 frev, crev, volt_index = voltage_level;
2686
2687         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2688                 return;
2689
2690         /* 0xff01 is a flag rather then an actual voltage */
2691         if (voltage_level == 0xff01)
2692                 return;
2693
2694         switch (crev) {
2695         case 1:
2696                 args.v1.ucVoltageType = voltage_type;
2697                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2698                 args.v1.ucVoltageIndex = volt_index;
2699                 break;
2700         case 2:
2701                 args.v2.ucVoltageType = voltage_type;
2702                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2703                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2704                 break;
2705         case 3:
2706                 args.v3.ucVoltageType = voltage_type;
2707                 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
2708                 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
2709                 break;
2710         default:
2711                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2712                 return;
2713         }
2714
2715         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2716 }
2717
2718 static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
2719                                     u16 voltage_id, u16 *voltage)
2720 {
2721         union set_voltage args;
2722         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2723         u8 frev, crev;
2724
2725         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2726                 return -EINVAL;
2727
2728         switch (crev) {
2729         case 1:
2730                 return -EINVAL;
2731         case 2:
2732                 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2733                 args.v2.ucVoltageMode = 0;
2734                 args.v2.usVoltageLevel = 0;
2735
2736                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2737
2738                 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2739                 break;
2740         case 3:
2741                 args.v3.ucVoltageType = voltage_type;
2742                 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
2743                 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
2744
2745                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2746
2747                 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
2748                 break;
2749         default:
2750                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2751                 return -EINVAL;
2752         }
2753
2754         return 0;
2755 }
2756
2757 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2758 {
2759         struct radeon_device *rdev = dev->dev_private;
2760         uint32_t bios_2_scratch, bios_6_scratch;
2761
2762         if (rdev->family >= CHIP_R600) {
2763                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2764                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2765         } else {
2766                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2767                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2768         }
2769
2770         /* let the bios control the backlight */
2771         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2772
2773         /* tell the bios not to handle mode switching */
2774         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2775
2776         if (rdev->family >= CHIP_R600) {
2777                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2778                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2779         } else {
2780                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2781                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2782         }
2783
2784 }
2785
2786 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2787 {
2788         uint32_t scratch_reg;
2789         int i;
2790
2791         if (rdev->family >= CHIP_R600)
2792                 scratch_reg = R600_BIOS_0_SCRATCH;
2793         else
2794                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2795
2796         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2797                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2798 }
2799
2800 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2801 {
2802         uint32_t scratch_reg;
2803         int i;
2804
2805         if (rdev->family >= CHIP_R600)
2806                 scratch_reg = R600_BIOS_0_SCRATCH;
2807         else
2808                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2809
2810         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2811                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2812 }
2813
2814 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2815 {
2816         struct drm_device *dev = encoder->dev;
2817         struct radeon_device *rdev = dev->dev_private;
2818         uint32_t bios_6_scratch;
2819
2820         if (rdev->family >= CHIP_R600)
2821                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2822         else
2823                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2824
2825         if (lock) {
2826                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2827                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2828         } else {
2829                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2830                 bios_6_scratch |= ATOM_S6_ACC_MODE;
2831         }
2832
2833         if (rdev->family >= CHIP_R600)
2834                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2835         else
2836                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2837 }
2838
2839 /* at some point we may want to break this out into individual functions */
2840 void
2841 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2842                                        struct drm_encoder *encoder,
2843                                        bool connected)
2844 {
2845         struct drm_device *dev = connector->dev;
2846         struct radeon_device *rdev = dev->dev_private;
2847         struct radeon_connector *radeon_connector =
2848             to_radeon_connector(connector);
2849         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2850         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2851
2852         if (rdev->family >= CHIP_R600) {
2853                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2854                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2855                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2856         } else {
2857                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2858                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2859                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2860         }
2861
2862         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2863             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2864                 if (connected) {
2865                         DRM_DEBUG_KMS("TV1 connected\n");
2866                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2867                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2868                 } else {
2869                         DRM_DEBUG_KMS("TV1 disconnected\n");
2870                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2871                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2872                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2873                 }
2874         }
2875         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2876             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2877                 if (connected) {
2878                         DRM_DEBUG_KMS("CV connected\n");
2879                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2880                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2881                 } else {
2882                         DRM_DEBUG_KMS("CV disconnected\n");
2883                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
2884                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2885                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2886                 }
2887         }
2888         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2889             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2890                 if (connected) {
2891                         DRM_DEBUG_KMS("LCD1 connected\n");
2892                         bios_0_scratch |= ATOM_S0_LCD1;
2893                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2894                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2895                 } else {
2896                         DRM_DEBUG_KMS("LCD1 disconnected\n");
2897                         bios_0_scratch &= ~ATOM_S0_LCD1;
2898                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2899                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2900                 }
2901         }
2902         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2903             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2904                 if (connected) {
2905                         DRM_DEBUG_KMS("CRT1 connected\n");
2906                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2907                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2908                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2909                 } else {
2910                         DRM_DEBUG_KMS("CRT1 disconnected\n");
2911                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2912                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2913                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2914                 }
2915         }
2916         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2917             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2918                 if (connected) {
2919                         DRM_DEBUG_KMS("CRT2 connected\n");
2920                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2921                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2922                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2923                 } else {
2924                         DRM_DEBUG_KMS("CRT2 disconnected\n");
2925                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2926                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2927                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2928                 }
2929         }
2930         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2931             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2932                 if (connected) {
2933                         DRM_DEBUG_KMS("DFP1 connected\n");
2934                         bios_0_scratch |= ATOM_S0_DFP1;
2935                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2936                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2937                 } else {
2938                         DRM_DEBUG_KMS("DFP1 disconnected\n");
2939                         bios_0_scratch &= ~ATOM_S0_DFP1;
2940                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2941                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2942                 }
2943         }
2944         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2945             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2946                 if (connected) {
2947                         DRM_DEBUG_KMS("DFP2 connected\n");
2948                         bios_0_scratch |= ATOM_S0_DFP2;
2949                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2950                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2951                 } else {
2952                         DRM_DEBUG_KMS("DFP2 disconnected\n");
2953                         bios_0_scratch &= ~ATOM_S0_DFP2;
2954                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2955                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2956                 }
2957         }
2958         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2959             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2960                 if (connected) {
2961                         DRM_DEBUG_KMS("DFP3 connected\n");
2962                         bios_0_scratch |= ATOM_S0_DFP3;
2963                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2964                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2965                 } else {
2966                         DRM_DEBUG_KMS("DFP3 disconnected\n");
2967                         bios_0_scratch &= ~ATOM_S0_DFP3;
2968                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2969                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2970                 }
2971         }
2972         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2973             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2974                 if (connected) {
2975                         DRM_DEBUG_KMS("DFP4 connected\n");
2976                         bios_0_scratch |= ATOM_S0_DFP4;
2977                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2978                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2979                 } else {
2980                         DRM_DEBUG_KMS("DFP4 disconnected\n");
2981                         bios_0_scratch &= ~ATOM_S0_DFP4;
2982                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2983                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2984                 }
2985         }
2986         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2987             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2988                 if (connected) {
2989                         DRM_DEBUG_KMS("DFP5 connected\n");
2990                         bios_0_scratch |= ATOM_S0_DFP5;
2991                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2992                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2993                 } else {
2994                         DRM_DEBUG_KMS("DFP5 disconnected\n");
2995                         bios_0_scratch &= ~ATOM_S0_DFP5;
2996                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2997                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2998                 }
2999         }
3000         if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
3001             (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
3002                 if (connected) {
3003                         DRM_DEBUG_KMS("DFP6 connected\n");
3004                         bios_0_scratch |= ATOM_S0_DFP6;
3005                         bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
3006                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
3007                 } else {
3008                         DRM_DEBUG_KMS("DFP6 disconnected\n");
3009                         bios_0_scratch &= ~ATOM_S0_DFP6;
3010                         bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
3011                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
3012                 }
3013         }
3014
3015         if (rdev->family >= CHIP_R600) {
3016                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
3017                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3018                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
3019         } else {
3020                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3021                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3022                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3023         }
3024 }
3025
3026 void
3027 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3028 {
3029         struct drm_device *dev = encoder->dev;
3030         struct radeon_device *rdev = dev->dev_private;
3031         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3032         uint32_t bios_3_scratch;
3033
3034         if (ASIC_IS_DCE4(rdev))
3035                 return;
3036
3037         if (rdev->family >= CHIP_R600)
3038                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
3039         else
3040                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
3041
3042         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3043                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
3044                 bios_3_scratch |= (crtc << 18);
3045         }
3046         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3047                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
3048                 bios_3_scratch |= (crtc << 24);
3049         }
3050         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3051                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
3052                 bios_3_scratch |= (crtc << 16);
3053         }
3054         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3055                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
3056                 bios_3_scratch |= (crtc << 20);
3057         }
3058         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3059                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
3060                 bios_3_scratch |= (crtc << 17);
3061         }
3062         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3063                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
3064                 bios_3_scratch |= (crtc << 19);
3065         }
3066         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3067                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
3068                 bios_3_scratch |= (crtc << 23);
3069         }
3070         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3071                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
3072                 bios_3_scratch |= (crtc << 25);
3073         }
3074
3075         if (rdev->family >= CHIP_R600)
3076                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3077         else
3078                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3079 }
3080
3081 void
3082 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3083 {
3084         struct drm_device *dev = encoder->dev;
3085         struct radeon_device *rdev = dev->dev_private;
3086         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3087         uint32_t bios_2_scratch;
3088
3089         if (ASIC_IS_DCE4(rdev))
3090                 return;
3091
3092         if (rdev->family >= CHIP_R600)
3093                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3094         else
3095                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3096
3097         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3098                 if (on)
3099                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
3100                 else
3101                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
3102         }
3103         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3104                 if (on)
3105                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3106                 else
3107                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3108         }
3109         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3110                 if (on)
3111                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3112                 else
3113                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3114         }
3115         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3116                 if (on)
3117                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3118                 else
3119                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3120         }
3121         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3122                 if (on)
3123                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3124                 else
3125                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3126         }
3127         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3128                 if (on)
3129                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3130                 else
3131                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3132         }
3133         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3134                 if (on)
3135                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3136                 else
3137                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3138         }
3139         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3140                 if (on)
3141                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3142                 else
3143                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3144         }
3145         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3146                 if (on)
3147                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3148                 else
3149                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3150         }
3151         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3152                 if (on)
3153                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3154                 else
3155                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3156         }
3157
3158         if (rdev->family >= CHIP_R600)
3159                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3160         else
3161                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3162 }