drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  36                       uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
  40                         uint32_t supported_device);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           bool linkb, uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd);
  52
  53 /* from radeon_legacy_encoder.c */
  54 extern void
  55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  56                           uint32_t supported_device);
  57
  58 union atom_supported_devices {
  59         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  60         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  62 };
  63
  64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
  65                                                                uint8_t id)
  66 {
  67         struct atom_context *ctx = rdev->mode_info.atom_context;
  68         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  69         struct radeon_i2c_bus_rec i2c;
  70         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  71         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  72         uint16_t data_offset;
  73         int i;
  74
  75         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  76         i2c.valid = false;
  77
  78         atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
  79
  80         i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  81
  82
  83         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
  84                 gpio = &i2c_info->asGPIO_Info[i];
  85
  86                 if (gpio->sucI2cId.ucAccess == id) {
  87                         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
  88                         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
  89                         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
  90                         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
  91                         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
  92                         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
  93                         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
  94                         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
  95                         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  96                         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
  97                         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
  98                         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
  99                         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 100                         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 101                         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 102                         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 103
 104                         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 105                                 i2c.hw_capable = true;
 106                         else
 107                                 i2c.hw_capable = false;
 108
 109                         if (gpio->sucI2cId.ucAccess == 0xa0)
 110                                 i2c.mm_i2c = true;
 111                         else
 112                                 i2c.mm_i2c = false;
 113
 114                         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 115
 116                         i2c.valid = true;
 117                         break;
 118                 }
 119         }
 120
 121         return i2c;
 122 }
 123
 124 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 125                                                         u8 id)
 126 {
 127         struct atom_context *ctx = rdev->mode_info.atom_context;
 128         struct radeon_gpio_rec gpio;
 129         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 130         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 131         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 132         u16 data_offset, size;
 133         int i, num_indices;
 134
 135         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 136         gpio.valid = false;
 137
 138         atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset);
 139
 140         gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 141
 142         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 143
 144         for (i = 0; i < num_indices; i++) {
 145                 pin = &gpio_info->asGPIO_Pin[i];
 146                 if (id == pin->ucGPIO_ID) {
 147                         gpio.id = pin->ucGPIO_ID;
 148                         gpio.reg = pin->usGpioPin_AIndex * 4;
 149                         gpio.mask = (1 << pin->ucGpioPinBitShift);
 150                         gpio.valid = true;
 151                         break;
 152                 }
 153         }
 154
 155         return gpio;
 156 }
 157
 158 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 159                                                             struct radeon_gpio_rec *gpio)
 160 {
 161         struct radeon_hpd hpd;
 162         u32 reg;
 163
 164         if (ASIC_IS_DCE4(rdev))
 165                 reg = EVERGREEN_DC_GPIO_HPD_A;
 166         else
 167                 reg = AVIVO_DC_GPIO_HPD_A;
 168
 169         hpd.gpio = *gpio;
 170         if (gpio->reg == reg) {
 171                 switch(gpio->mask) {
 172                 case (1 << 0):
 173                         hpd.hpd = RADEON_HPD_1;
 174                         break;
 175                 case (1 << 8):
 176                         hpd.hpd = RADEON_HPD_2;
 177                         break;
 178                 case (1 << 16):
 179                         hpd.hpd = RADEON_HPD_3;
 180                         break;
 181                 case (1 << 24):
 182                         hpd.hpd = RADEON_HPD_4;
 183                         break;
 184                 case (1 << 26):
 185                         hpd.hpd = RADEON_HPD_5;
 186                         break;
 187                 case (1 << 28):
 188                         hpd.hpd = RADEON_HPD_6;
 189                         break;
 190                 default:
 191                         hpd.hpd = RADEON_HPD_NONE;
 192                         break;
 193                 }
 194         } else
 195                 hpd.hpd = RADEON_HPD_NONE;
 196         return hpd;
 197 }
 198
 199 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 200                                      uint32_t supported_device,
 201                                      int *connector_type,
 202                                      struct radeon_i2c_bus_rec *i2c_bus,
 203                                      uint16_t *line_mux,
 204                                      struct radeon_hpd *hpd)
 205 {
 206
 207         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 208         if ((dev->pdev->device == 0x791e) &&
 209             (dev->pdev->subsystem_vendor == 0x1043) &&
 210             (dev->pdev->subsystem_device == 0x826d)) {
 211                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 212                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 213                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 214         }
 215
 216         /* Asrock RS600 board lists the DVI port as HDMI */
 217         if ((dev->pdev->device == 0x7941) &&
 218             (dev->pdev->subsystem_vendor == 0x1849) &&
 219             (dev->pdev->subsystem_device == 0x7941)) {
 220                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 221                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 222                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 223         }
 224
 225         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 226         if ((dev->pdev->device == 0x7941) &&
 227             (dev->pdev->subsystem_vendor == 0x147b) &&
 228             (dev->pdev->subsystem_device == 0x2412)) {
 229                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 230                         return false;
 231         }
 232
 233         /* Falcon NW laptop lists vga ddc line for LVDS */
 234         if ((dev->pdev->device == 0x5653) &&
 235             (dev->pdev->subsystem_vendor == 0x1462) &&
 236             (dev->pdev->subsystem_device == 0x0291)) {
 237                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 238                         i2c_bus->valid = false;
 239                         *line_mux = 53;
 240                 }
 241         }
 242
 243         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 244         if ((dev->pdev->device == 0x7146) &&
 245             (dev->pdev->subsystem_vendor == 0x17af) &&
 246             (dev->pdev->subsystem_device == 0x2058)) {
 247                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 248                         return false;
 249         }
 250
 251         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 252         if ((dev->pdev->device == 0x7142) &&
 253             (dev->pdev->subsystem_vendor == 0x1458) &&
 254             (dev->pdev->subsystem_device == 0x2134)) {
 255                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 256                         return false;
 257         }
 258
 259
 260         /* Funky macbooks */
 261         if ((dev->pdev->device == 0x71C5) &&
 262             (dev->pdev->subsystem_vendor == 0x106b) &&
 263             (dev->pdev->subsystem_device == 0x0080)) {
 264                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 265                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 266                         return false;
 267         }
 268
 269         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 270         if ((dev->pdev->device == 0x9598) &&
 271             (dev->pdev->subsystem_vendor == 0x1043) &&
 272             (dev->pdev->subsystem_device == 0x01da)) {
 273                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 274                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 275                 }
 276         }
 277
 278         /* ASUS HD 3450 board lists the DVI port as HDMI */
 279         if ((dev->pdev->device == 0x95C5) &&
 280             (dev->pdev->subsystem_vendor == 0x1043) &&
 281             (dev->pdev->subsystem_device == 0x01e2)) {
 282                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 283                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 284                 }
 285         }
 286
 287         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 288          * HDMI + VGA reporting as HDMI
 289          */
 290         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 291                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 292                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 293                         *line_mux = 0;
 294                 }
 295         }
 296
 297         /* Acer laptop reports DVI-D as DVI-I */
 298         if ((dev->pdev->device == 0x95c4) &&
 299             (dev->pdev->subsystem_vendor == 0x1025) &&
 300             (dev->pdev->subsystem_device == 0x013c)) {
 301                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 302                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
 303                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 304         }
 305
 306         /* XFX Pine Group device rv730 reports no VGA DDC lines
 307          * even though they are wired up to record 0x93
 308          */
 309         if ((dev->pdev->device == 0x9498) &&
 310             (dev->pdev->subsystem_vendor == 0x1682) &&
 311             (dev->pdev->subsystem_device == 0x2452)) {
 312                 struct radeon_device *rdev = dev->dev_private;
 313                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 314         }
 315         return true;
 316 }
 317
 318 const int supported_devices_connector_convert[] = {
 319         DRM_MODE_CONNECTOR_Unknown,
 320         DRM_MODE_CONNECTOR_VGA,
 321         DRM_MODE_CONNECTOR_DVII,
 322         DRM_MODE_CONNECTOR_DVID,
 323         DRM_MODE_CONNECTOR_DVIA,
 324         DRM_MODE_CONNECTOR_SVIDEO,
 325         DRM_MODE_CONNECTOR_Composite,
 326         DRM_MODE_CONNECTOR_LVDS,
 327         DRM_MODE_CONNECTOR_Unknown,
 328         DRM_MODE_CONNECTOR_Unknown,
 329         DRM_MODE_CONNECTOR_HDMIA,
 330         DRM_MODE_CONNECTOR_HDMIB,
 331         DRM_MODE_CONNECTOR_Unknown,
 332         DRM_MODE_CONNECTOR_Unknown,
 333         DRM_MODE_CONNECTOR_9PinDIN,
 334         DRM_MODE_CONNECTOR_DisplayPort
 335 };
 336
 337 const uint16_t supported_devices_connector_object_id_convert[] = {
 338         CONNECTOR_OBJECT_ID_NONE,
 339         CONNECTOR_OBJECT_ID_VGA,
 340         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 341         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 342         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 343         CONNECTOR_OBJECT_ID_COMPOSITE,
 344         CONNECTOR_OBJECT_ID_SVIDEO,
 345         CONNECTOR_OBJECT_ID_LVDS,
 346         CONNECTOR_OBJECT_ID_9PIN_DIN,
 347         CONNECTOR_OBJECT_ID_9PIN_DIN,
 348         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 349         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 350         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 351         CONNECTOR_OBJECT_ID_SVIDEO
 352 };
 353
 354 const int object_connector_convert[] = {
 355         DRM_MODE_CONNECTOR_Unknown,
 356         DRM_MODE_CONNECTOR_DVII,
 357         DRM_MODE_CONNECTOR_DVII,
 358         DRM_MODE_CONNECTOR_DVID,
 359         DRM_MODE_CONNECTOR_DVID,
 360         DRM_MODE_CONNECTOR_VGA,
 361         DRM_MODE_CONNECTOR_Composite,
 362         DRM_MODE_CONNECTOR_SVIDEO,
 363         DRM_MODE_CONNECTOR_Unknown,
 364         DRM_MODE_CONNECTOR_Unknown,
 365         DRM_MODE_CONNECTOR_9PinDIN,
 366         DRM_MODE_CONNECTOR_Unknown,
 367         DRM_MODE_CONNECTOR_HDMIA,
 368         DRM_MODE_CONNECTOR_HDMIB,
 369         DRM_MODE_CONNECTOR_LVDS,
 370         DRM_MODE_CONNECTOR_9PinDIN,
 371         DRM_MODE_CONNECTOR_Unknown,
 372         DRM_MODE_CONNECTOR_Unknown,
 373         DRM_MODE_CONNECTOR_Unknown,
 374         DRM_MODE_CONNECTOR_DisplayPort,
 375         DRM_MODE_CONNECTOR_eDP,
 376         DRM_MODE_CONNECTOR_Unknown
 377 };
 378
 379 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 380 {
 381         struct radeon_device *rdev = dev->dev_private;
 382         struct radeon_mode_info *mode_info = &rdev->mode_info;
 383         struct atom_context *ctx = mode_info->atom_context;
 384         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 385         u16 size, data_offset;
 386         u8 frev, crev;
 387         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 388         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 389         ATOM_OBJECT_HEADER *obj_header;
 390         int i, j, path_size, device_support;
 391         int connector_type;
 392         u16 igp_lane_info, conn_id, connector_object_id;
 393         bool linkb;
 394         struct radeon_i2c_bus_rec ddc_bus;
 395         struct radeon_gpio_rec gpio;
 396         struct radeon_hpd hpd;
 397
 398         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 399
 400         if (data_offset == 0)
 401                 return false;
 402
 403         if (crev < 2)
 404                 return false;
 405
 406         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 407         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 408             (ctx->bios + data_offset +
 409              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 410         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 411             (ctx->bios + data_offset +
 412              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 413         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 414
 415         path_size = 0;
 416         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 417                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 418                 ATOM_DISPLAY_OBJECT_PATH *path;
 419                 addr += path_size;
 420                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 421                 path_size += le16_to_cpu(path->usSize);
 422                 linkb = false;
 423                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 424                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 425
 426                         con_obj_id =
 427                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 428                             >> OBJECT_ID_SHIFT;
 429                         con_obj_num =
 430                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 431                             >> ENUM_ID_SHIFT;
 432                         con_obj_type =
 433                             (le16_to_cpu(path->usConnObjectId) &
 434                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 435
 436                         /* TODO CV support */
 437                         if (le16_to_cpu(path->usDeviceTag) ==
 438                                 ATOM_DEVICE_CV_SUPPORT)
 439                                 continue;
 440
 441                         /* IGP chips */
 442                         if ((rdev->flags & RADEON_IS_IGP) &&
 443                             (con_obj_id ==
 444                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 445                                 uint16_t igp_offset = 0;
 446                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 447
 448                                 index =
 449                                     GetIndexIntoMasterTable(DATA,
 450                                                             IntegratedSystemInfo);
 451
 452                                 atom_parse_data_header(ctx, index, &size, &frev,
 453                                                        &crev, &igp_offset);
 454
 455                                 if (crev >= 2) {
 456                                         igp_obj =
 457                                             (ATOM_INTEGRATED_SYSTEM_INFO_V2
 458                                              *) (ctx->bios + igp_offset);
 459
 460                                         if (igp_obj) {
 461                                                 uint32_t slot_config, ct;
 462
 463                                                 if (con_obj_num == 1)
 464                                                         slot_config =
 465                                                             igp_obj->
 466                                                             ulDDISlot1Config;
 467                                                 else
 468                                                         slot_config =
 469                                                             igp_obj->
 470                                                             ulDDISlot2Config;
 471
 472                                                 ct = (slot_config >> 16) & 0xff;
 473                                                 connector_type =
 474                                                     object_connector_convert
 475                                                     [ct];
 476                                                 connector_object_id = ct;
 477                                                 igp_lane_info =
 478                                                     slot_config & 0xffff;
 479                                         } else
 480                                                 continue;
 481                                 } else
 482                                         continue;
 483                         } else {
 484                                 igp_lane_info = 0;
 485                                 connector_type =
 486                                     object_connector_convert[con_obj_id];
 487                                 connector_object_id = con_obj_id;
 488                         }
 489
 490                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 491                                 continue;
 492
 493                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
 494                              j++) {
 495                                 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
 496
 497                                 enc_obj_id =
 498                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 499                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 500                                 enc_obj_num =
 501                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 502                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 503                                 enc_obj_type =
 504                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 505                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 506
 507                                 /* FIXME: add support for router objects */
 508                                 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 509                                         if (enc_obj_num == 2)
 510                                                 linkb = true;
 511                                         else
 512                                                 linkb = false;
 513
 514                                         radeon_add_atom_encoder(dev,
 515                                                                 enc_obj_id,
 516                                                                 le16_to_cpu
 517                                                                 (path->
 518                                                                  usDeviceTag));
 519
 520                                 }
 521                         }
 522
 523                         /* look up gpio for ddc, hpd */
 524                         if ((le16_to_cpu(path->usDeviceTag) &
 525                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 526                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 527                                         if (le16_to_cpu(path->usConnObjectId) ==
 528                                             le16_to_cpu(con_obj->asObjects[j].
 529                                                         usObjectID)) {
 530                                                 ATOM_COMMON_RECORD_HEADER
 531                                                     *record =
 532                                                     (ATOM_COMMON_RECORD_HEADER
 533                                                      *)
 534                                                     (ctx->bios + data_offset +
 535                                                      le16_to_cpu(con_obj->
 536                                                                  asObjects[j].
 537                                                                  usRecordOffset));
 538                                                 ATOM_I2C_RECORD *i2c_record;
 539                                                 ATOM_HPD_INT_RECORD *hpd_record;
 540                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 541                                                 hpd.hpd = RADEON_HPD_NONE;
 542
 543                                                 while (record->ucRecordType > 0
 544                                                        && record->
 545                                                        ucRecordType <=
 546                                                        ATOM_MAX_OBJECT_RECORD_NUMBER) {
 547                                                         switch (record->ucRecordType) {
 548                                                         case ATOM_I2C_RECORD_TYPE:
 549                                                                 i2c_record =
 550                                                                     (ATOM_I2C_RECORD *)
 551                                                                         record;
 552                                                                 i2c_config =
 553                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 554                                                                         &i2c_record->sucI2cId;
 555                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 556                                                                                                  i2c_config->
 557                                                                                                  ucAccess);
 558                                                                 break;
 559                                                         case ATOM_HPD_INT_RECORD_TYPE:
 560                                                                 hpd_record =
 561                                                                         (ATOM_HPD_INT_RECORD *)
 562                                                                         record;
 563                                                                 gpio = radeon_lookup_gpio(rdev,
 564                                                                                           hpd_record->ucHPDIntGPIOID);
 565                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 566                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 567                                                                 break;
 568                                                         }
 569                                                         record =
 570                                                             (ATOM_COMMON_RECORD_HEADER
 571                                                              *) ((char *)record
 572                                                                  +
 573                                                                  record->
 574                                                                  ucRecordSize);
 575                                                 }
 576                                                 break;
 577                                         }
 578                                 }
 579                         } else {
 580                                 hpd.hpd = RADEON_HPD_NONE;
 581                                 ddc_bus.valid = false;
 582                         }
 583
 584                         /* needed for aux chan transactions */
 585                         ddc_bus.hpd_id = hpd.hpd ? (hpd.hpd - 1) : 0;
 586
 587                         conn_id = le16_to_cpu(path->usConnObjectId);
 588
 589                         if (!radeon_atom_apply_quirks
 590                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 591                              &ddc_bus, &conn_id, &hpd))
 592                                 continue;
 593
 594                         radeon_add_atom_connector(dev,
 595                                                   conn_id,
 596                                                   le16_to_cpu(path->
 597                                                               usDeviceTag),
 598                                                   connector_type, &ddc_bus,
 599                                                   linkb, igp_lane_info,
 600                                                   connector_object_id,
 601                                                   &hpd);
 602
 603                 }
 604         }
 605
 606         radeon_link_encoder_connector(dev);
 607
 608         return true;
 609 }
 610
 611 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 612                                                  int connector_type,
 613                                                  uint16_t devices)
 614 {
 615         struct radeon_device *rdev = dev->dev_private;
 616
 617         if (rdev->flags & RADEON_IS_IGP) {
 618                 return supported_devices_connector_object_id_convert
 619                         [connector_type];
 620         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 621                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 622                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 623                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 624                 struct atom_context *ctx = mode_info->atom_context;
 625                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 626                 uint16_t size, data_offset;
 627                 uint8_t frev, crev;
 628                 ATOM_XTMDS_INFO *xtmds;
 629
 630                 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 631                 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 632
 633                 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 634                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
 635                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 636                         else
 637                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 638                 } else {
 639                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
 640                                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 641                         else
 642                                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 643                 }
 644         } else {
 645                 return supported_devices_connector_object_id_convert
 646                         [connector_type];
 647         }
 648 }
 649
 650 struct bios_connector {
 651         bool valid;
 652         uint16_t line_mux;
 653         uint16_t devices;
 654         int connector_type;
 655         struct radeon_i2c_bus_rec ddc_bus;
 656         struct radeon_hpd hpd;
 657 };
 658
 659 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 660                                                                  drm_device
 661                                                                  *dev)
 662 {
 663         struct radeon_device *rdev = dev->dev_private;
 664         struct radeon_mode_info *mode_info = &rdev->mode_info;
 665         struct atom_context *ctx = mode_info->atom_context;
 666         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 667         uint16_t size, data_offset;
 668         uint8_t frev, crev;
 669         uint16_t device_support;
 670         uint8_t dac;
 671         union atom_supported_devices *supported_devices;
 672         int i, j, max_device;
 673         struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
 674
 675         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 676
 677         supported_devices =
 678             (union atom_supported_devices *)(ctx->bios + data_offset);
 679
 680         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 681
 682         if (frev > 1)
 683                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 684         else
 685                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 686
 687         for (i = 0; i < max_device; i++) {
 688                 ATOM_CONNECTOR_INFO_I2C ci =
 689                     supported_devices->info.asConnInfo[i];
 690
 691                 bios_connectors[i].valid = false;
 692
 693                 if (!(device_support & (1 << i))) {
 694                         continue;
 695                 }
 696
 697                 if (i == ATOM_DEVICE_CV_INDEX) {
 698                         DRM_DEBUG("Skipping Component Video\n");
 699                         continue;
 700                 }
 701
 702                 bios_connectors[i].connector_type =
 703                     supported_devices_connector_convert[ci.sucConnectorInfo.
 704                                                         sbfAccess.
 705                                                         bfConnectorType];
 706
 707                 if (bios_connectors[i].connector_type ==
 708                     DRM_MODE_CONNECTOR_Unknown)
 709                         continue;
 710
 711                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 712
 713                 bios_connectors[i].line_mux =
 714                         ci.sucI2cId.ucAccess;
 715
 716                 /* give tv unique connector ids */
 717                 if (i == ATOM_DEVICE_TV1_INDEX) {
 718                         bios_connectors[i].ddc_bus.valid = false;
 719                         bios_connectors[i].line_mux = 50;
 720                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 721                         bios_connectors[i].ddc_bus.valid = false;
 722                         bios_connectors[i].line_mux = 51;
 723                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 724                         bios_connectors[i].ddc_bus.valid = false;
 725                         bios_connectors[i].line_mux = 52;
 726                 } else
 727                         bios_connectors[i].ddc_bus =
 728                             radeon_lookup_i2c_gpio(rdev,
 729                                                    bios_connectors[i].line_mux);
 730
 731                 if ((crev > 1) && (frev > 1)) {
 732                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 733                         switch (isb) {
 734                         case 0x4:
 735                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 736                                 break;
 737                         case 0xa:
 738                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 739                                 break;
 740                         default:
 741                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 742                                 break;
 743                         }
 744                 } else {
 745                         if (i == ATOM_DEVICE_DFP1_INDEX)
 746                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 747                         else if (i == ATOM_DEVICE_DFP2_INDEX)
 748                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 749                         else
 750                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 751                 }
 752
 753                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 754                  * shared with a DVI port, we'll pick up the DVI connector when we
 755                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 756                  */
 757                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 758                         bios_connectors[i].connector_type =
 759                             DRM_MODE_CONNECTOR_VGA;
 760
 761                 if (!radeon_atom_apply_quirks
 762                     (dev, (1 << i), &bios_connectors[i].connector_type,
 763                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
 764                      &bios_connectors[i].hpd))
 765                         continue;
 766
 767                 bios_connectors[i].valid = true;
 768                 bios_connectors[i].devices = (1 << i);
 769
 770                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
 771                         radeon_add_atom_encoder(dev,
 772                                                 radeon_get_encoder_id(dev,
 773                                                                       (1 << i),
 774                                                                       dac),
 775                                                 (1 << i));
 776                 else
 777                         radeon_add_legacy_encoder(dev,
 778                                                   radeon_get_encoder_id(dev,
 779                                                                         (1 << i),
 780                                                                         dac),
 781                                                   (1 << i));
 782         }
 783
 784         /* combine shared connectors */
 785         for (i = 0; i < max_device; i++) {
 786                 if (bios_connectors[i].valid) {
 787                         for (j = 0; j < max_device; j++) {
 788                                 if (bios_connectors[j].valid && (i != j)) {
 789                                         if (bios_connectors[i].line_mux ==
 790                                             bios_connectors[j].line_mux) {
 791                                                 /* make sure not to combine LVDS */
 792                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 793                                                         bios_connectors[i].line_mux = 53;
 794                                                         bios_connectors[i].ddc_bus.valid = false;
 795                                                         continue;
 796                                                 }
 797                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 798                                                         bios_connectors[j].line_mux = 53;
 799                                                         bios_connectors[j].ddc_bus.valid = false;
 800                                                         continue;
 801                                                 }
 802                                                 /* combine analog and digital for DVI-I */
 803                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 804                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
 805                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 806                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
 807                                                         bios_connectors[i].devices |=
 808                                                                 bios_connectors[j].devices;
 809                                                         bios_connectors[i].connector_type =
 810                                                                 DRM_MODE_CONNECTOR_DVII;
 811                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
 812                                                                 bios_connectors[i].hpd =
 813                                                                         bios_connectors[j].hpd;
 814                                                         bios_connectors[j].valid = false;
 815                                                 }
 816                                         }
 817                                 }
 818                         }
 819                 }
 820         }
 821
 822         /* add the connectors */
 823         for (i = 0; i < max_device; i++) {
 824                 if (bios_connectors[i].valid) {
 825                         uint16_t connector_object_id =
 826                                 atombios_get_connector_object_id(dev,
 827                                                       bios_connectors[i].connector_type,
 828                                                       bios_connectors[i].devices);
 829                         radeon_add_atom_connector(dev,
 830                                                   bios_connectors[i].line_mux,
 831                                                   bios_connectors[i].devices,
 832                                                   bios_connectors[i].
 833                                                   connector_type,
 834                                                   &bios_connectors[i].ddc_bus,
 835                                                   false, 0,
 836                                                   connector_object_id,
 837                                                   &bios_connectors[i].hpd);
 838                 }
 839         }
 840
 841         radeon_link_encoder_connector(dev);
 842
 843         return true;
 844 }
 845
 846 union firmware_info {
 847         ATOM_FIRMWARE_INFO info;
 848         ATOM_FIRMWARE_INFO_V1_2 info_12;
 849         ATOM_FIRMWARE_INFO_V1_3 info_13;
 850         ATOM_FIRMWARE_INFO_V1_4 info_14;
 851         ATOM_FIRMWARE_INFO_V2_1 info_21;
 852 };
 853
 854 bool radeon_atom_get_clock_info(struct drm_device *dev)
 855 {
 856         struct radeon_device *rdev = dev->dev_private;
 857         struct radeon_mode_info *mode_info = &rdev->mode_info;
 858         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 859         union firmware_info *firmware_info;
 860         uint8_t frev, crev;
 861         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 862         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 863         struct radeon_pll *dcpll = &rdev->clock.dcpll;
 864         struct radeon_pll *spll = &rdev->clock.spll;
 865         struct radeon_pll *mpll = &rdev->clock.mpll;
 866         uint16_t data_offset;
 867
 868         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 869                                &crev, &data_offset);
 870
 871         firmware_info =
 872             (union firmware_info *)(mode_info->atom_context->bios +
 873                                     data_offset);
 874
 875         if (firmware_info) {
 876                 /* pixel clocks */
 877                 p1pll->reference_freq =
 878                     le16_to_cpu(firmware_info->info.usReferenceClock);
 879                 p1pll->reference_div = 0;
 880
 881                 if (crev < 2)
 882                         p1pll->pll_out_min =
 883                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
 884                 else
 885                         p1pll->pll_out_min =
 886                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 887                 p1pll->pll_out_max =
 888                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 889
 890                 if (p1pll->pll_out_min == 0) {
 891                         if (ASIC_IS_AVIVO(rdev))
 892                                 p1pll->pll_out_min = 64800;
 893                         else
 894                                 p1pll->pll_out_min = 20000;
 895                 } else if (p1pll->pll_out_min > 64800) {
 896                         /* Limiting the pll output range is a good thing generally as
 897                          * it limits the number of possible pll combinations for a given
 898                          * frequency presumably to the ones that work best on each card.
 899                          * However, certain duallink DVI monitors seem to like
 900                          * pll combinations that would be limited by this at least on
 901                          * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per
 902                          * family.
 903                          */
 904                         if (!radeon_new_pll)
 905                                 p1pll->pll_out_min = 64800;
 906                 }
 907
 908                 p1pll->pll_in_min =
 909                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 910                 p1pll->pll_in_max =
 911                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 912
 913                 *p2pll = *p1pll;
 914
 915                 /* system clock */
 916                 spll->reference_freq =
 917                     le16_to_cpu(firmware_info->info.usReferenceClock);
 918                 spll->reference_div = 0;
 919
 920                 spll->pll_out_min =
 921                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 922                 spll->pll_out_max =
 923                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 924
 925                 /* ??? */
 926                 if (spll->pll_out_min == 0) {
 927                         if (ASIC_IS_AVIVO(rdev))
 928                                 spll->pll_out_min = 64800;
 929                         else
 930                                 spll->pll_out_min = 20000;
 931                 }
 932
 933                 spll->pll_in_min =
 934                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 935                 spll->pll_in_max =
 936                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 937
 938                 /* memory clock */
 939                 mpll->reference_freq =
 940                     le16_to_cpu(firmware_info->info.usReferenceClock);
 941                 mpll->reference_div = 0;
 942
 943                 mpll->pll_out_min =
 944                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 945                 mpll->pll_out_max =
 946                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 947
 948                 /* ??? */
 949                 if (mpll->pll_out_min == 0) {
 950                         if (ASIC_IS_AVIVO(rdev))
 951                                 mpll->pll_out_min = 64800;
 952                         else
 953                                 mpll->pll_out_min = 20000;
 954                 }
 955
 956                 mpll->pll_in_min =
 957                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 958                 mpll->pll_in_max =
 959                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 960
 961                 rdev->clock.default_sclk =
 962                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 963                 rdev->clock.default_mclk =
 964                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 965
 966                 if (ASIC_IS_DCE4(rdev)) {
 967                         rdev->clock.default_dispclk =
 968                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
 969                         if (rdev->clock.default_dispclk == 0)
 970                                 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
 971                         rdev->clock.dp_extclk =
 972                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
 973                 }
 974                 *dcpll = *p1pll;
 975
 976                 return true;
 977         }
 978
 979         return false;
 980 }
 981
 982 union igp_info {
 983         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
 984         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
 985 };
 986
 987 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
 988 {
 989         struct radeon_mode_info *mode_info = &rdev->mode_info;
 990         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
 991         union igp_info *igp_info;
 992         u8 frev, crev;
 993         u16 data_offset;
 994
 995         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 996                                &crev, &data_offset);
 997
 998         igp_info = (union igp_info *)(mode_info->atom_context->bios +
 999                                       data_offset);
1000
1001         if (igp_info) {
1002                 switch (crev) {
1003                 case 1:
1004                         if (igp_info->info.ucMemoryType & 0xf0)
1005                                 return true;
1006                         break;
1007                 case 2:
1008                         if (igp_info->info_2.ucMemoryType & 0x0f)
1009                                 return true;
1010                         break;
1011                 default:
1012                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1013                         break;
1014                 }
1015         }
1016         return false;
1017 }
1018
1019 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1020                                    struct radeon_encoder_int_tmds *tmds)
1021 {
1022         struct drm_device *dev = encoder->base.dev;
1023         struct radeon_device *rdev = dev->dev_private;
1024         struct radeon_mode_info *mode_info = &rdev->mode_info;
1025         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1026         uint16_t data_offset;
1027         struct _ATOM_TMDS_INFO *tmds_info;
1028         uint8_t frev, crev;
1029         uint16_t maxfreq;
1030         int i;
1031
1032         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1033                                &crev, &data_offset);
1034
1035         tmds_info =
1036             (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1037                                        data_offset);
1038
1039         if (tmds_info) {
1040                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1041                 for (i = 0; i < 4; i++) {
1042                         tmds->tmds_pll[i].freq =
1043                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1044                         tmds->tmds_pll[i].value =
1045                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1046                         tmds->tmds_pll[i].value |=
1047                             (tmds_info->asMiscInfo[i].
1048                              ucPLL_VCO_Gain & 0x3f) << 6;
1049                         tmds->tmds_pll[i].value |=
1050                             (tmds_info->asMiscInfo[i].
1051                              ucPLL_DutyCycle & 0xf) << 12;
1052                         tmds->tmds_pll[i].value |=
1053                             (tmds_info->asMiscInfo[i].
1054                              ucPLL_VoltageSwing & 0xf) << 16;
1055
1056                         DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
1057                                   tmds->tmds_pll[i].freq,
1058                                   tmds->tmds_pll[i].value);
1059
1060                         if (maxfreq == tmds->tmds_pll[i].freq) {
1061                                 tmds->tmds_pll[i].freq = 0xffffffff;
1062                                 break;
1063                         }
1064                 }
1065                 return true;
1066         }
1067         return false;
1068 }
1069
1070 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1071                                                           radeon_encoder
1072                                                           *encoder,
1073                                                           int id)
1074 {
1075         struct drm_device *dev = encoder->base.dev;
1076         struct radeon_device *rdev = dev->dev_private;
1077         struct radeon_mode_info *mode_info = &rdev->mode_info;
1078         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1079         uint16_t data_offset;
1080         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1081         uint8_t frev, crev;
1082         struct radeon_atom_ss *ss = NULL;
1083         int i;
1084
1085         if (id > ATOM_MAX_SS_ENTRY)
1086                 return NULL;
1087
1088         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1089                                &crev, &data_offset);
1090
1091         ss_info =
1092             (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1093
1094         if (ss_info) {
1095                 ss =
1096                     kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1097
1098                 if (!ss)
1099                         return NULL;
1100
1101                 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1102                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1103                                 ss->percentage =
1104                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1105                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1106                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1107                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1108                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1109                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1110                                 break;
1111                         }
1112                 }
1113         }
1114         return ss;
1115 }
1116
1117 static void radeon_atom_apply_lvds_quirks(struct drm_device *dev,
1118                                           struct radeon_encoder_atom_dig *lvds)
1119 {
1120
1121         /* Toshiba A300-1BU laptop panel doesn't like new pll divider algo */
1122         if ((dev->pdev->device == 0x95c4) &&
1123             (dev->pdev->subsystem_vendor == 0x1179) &&
1124             (dev->pdev->subsystem_device == 0xff50)) {
1125                 if ((lvds->native_mode.hdisplay == 1280) &&
1126                     (lvds->native_mode.vdisplay == 800))
1127                         lvds->pll_algo = PLL_ALGO_LEGACY;
1128         }
1129
1130         /* Dell Studio 15 laptop panel doesn't like new pll divider algo */
1131         if ((dev->pdev->device == 0x95c4) &&
1132             (dev->pdev->subsystem_vendor == 0x1028) &&
1133             (dev->pdev->subsystem_device == 0x029f)) {
1134                 if ((lvds->native_mode.hdisplay == 1280) &&
1135                     (lvds->native_mode.vdisplay == 800))
1136                         lvds->pll_algo = PLL_ALGO_LEGACY;
1137         }
1138
1139 }
1140
1141 union lvds_info {
1142         struct _ATOM_LVDS_INFO info;
1143         struct _ATOM_LVDS_INFO_V12 info_12;
1144 };
1145
1146 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1147                                                               radeon_encoder
1148                                                               *encoder)
1149 {
1150         struct drm_device *dev = encoder->base.dev;
1151         struct radeon_device *rdev = dev->dev_private;
1152         struct radeon_mode_info *mode_info = &rdev->mode_info;
1153         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1154         uint16_t data_offset, misc;
1155         union lvds_info *lvds_info;
1156         uint8_t frev, crev;
1157         struct radeon_encoder_atom_dig *lvds = NULL;
1158
1159         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1160                                &crev, &data_offset);
1161
1162         lvds_info =
1163             (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1164
1165         if (lvds_info) {
1166                 lvds =
1167                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1168
1169                 if (!lvds)
1170                         return NULL;
1171
1172                 lvds->native_mode.clock =
1173                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1174                 lvds->native_mode.hdisplay =
1175                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1176                 lvds->native_mode.vdisplay =
1177                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1178                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1179                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1180                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1181                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1182                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1183                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1184                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1185                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1186                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1187                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1188                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1189                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1190                 lvds->panel_pwr_delay =
1191                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1192                 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1193
1194                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1195                 if (misc & ATOM_VSYNC_POLARITY)
1196                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1197                 if (misc & ATOM_HSYNC_POLARITY)
1198                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1199                 if (misc & ATOM_COMPOSITESYNC)
1200                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1201                 if (misc & ATOM_INTERLACE)
1202                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1203                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1204                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1205
1206                 /* set crtc values */
1207                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1208
1209                 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1210
1211                 if (ASIC_IS_AVIVO(rdev)) {
1212                         if (radeon_new_pll == 0)
1213                                 lvds->pll_algo = PLL_ALGO_LEGACY;
1214                         else
1215                                 lvds->pll_algo = PLL_ALGO_NEW;
1216                 } else {
1217                         if (radeon_new_pll == 1)
1218                                 lvds->pll_algo = PLL_ALGO_NEW;
1219                         else
1220                                 lvds->pll_algo = PLL_ALGO_LEGACY;
1221                 }
1222
1223                 /* LVDS quirks */
1224                 radeon_atom_apply_lvds_quirks(dev, lvds);
1225
1226                 encoder->native_mode = lvds->native_mode;
1227         }
1228         return lvds;
1229 }
1230
1231 struct radeon_encoder_primary_dac *
1232 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1233 {
1234         struct drm_device *dev = encoder->base.dev;
1235         struct radeon_device *rdev = dev->dev_private;
1236         struct radeon_mode_info *mode_info = &rdev->mode_info;
1237         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1238         uint16_t data_offset;
1239         struct _COMPASSIONATE_DATA *dac_info;
1240         uint8_t frev, crev;
1241         uint8_t bg, dac;
1242         struct radeon_encoder_primary_dac *p_dac = NULL;
1243
1244         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1245
1246         dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1247
1248         if (dac_info) {
1249                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1250
1251                 if (!p_dac)
1252                         return NULL;
1253
1254                 bg = dac_info->ucDAC1_BG_Adjustment;
1255                 dac = dac_info->ucDAC1_DAC_Adjustment;
1256                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1257
1258         }
1259         return p_dac;
1260 }
1261
1262 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1263                                 struct drm_display_mode *mode)
1264 {
1265         struct radeon_mode_info *mode_info = &rdev->mode_info;
1266         ATOM_ANALOG_TV_INFO *tv_info;
1267         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1268         ATOM_DTD_FORMAT *dtd_timings;
1269         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1270         u8 frev, crev;
1271         u16 data_offset, misc;
1272
1273         atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
1274
1275         switch (crev) {
1276         case 1:
1277                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1278                 if (index > MAX_SUPPORTED_TV_TIMING)
1279                         return false;
1280
1281                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1282                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1283                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1284                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1285                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1286
1287                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1288                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1289                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1290                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1291                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1292
1293                 mode->flags = 0;
1294                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1295                 if (misc & ATOM_VSYNC_POLARITY)
1296                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1297                 if (misc & ATOM_HSYNC_POLARITY)
1298                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1299                 if (misc & ATOM_COMPOSITESYNC)
1300                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1301                 if (misc & ATOM_INTERLACE)
1302                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1303                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1304                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1305
1306                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1307
1308                 if (index == 1) {
1309                         /* PAL timings appear to have wrong values for totals */
1310                         mode->crtc_htotal -= 1;
1311                         mode->crtc_vtotal -= 1;
1312                 }
1313                 break;
1314         case 2:
1315                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1316                 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1317                         return false;
1318
1319                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1320                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1321                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1322                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1323                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1324                         le16_to_cpu(dtd_timings->usHSyncOffset);
1325                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1326                         le16_to_cpu(dtd_timings->usHSyncWidth);
1327
1328                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1329                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1330                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1331                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1332                         le16_to_cpu(dtd_timings->usVSyncOffset);
1333                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1334                         le16_to_cpu(dtd_timings->usVSyncWidth);
1335
1336                 mode->flags = 0;
1337                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1338                 if (misc & ATOM_VSYNC_POLARITY)
1339                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1340                 if (misc & ATOM_HSYNC_POLARITY)
1341                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1342                 if (misc & ATOM_COMPOSITESYNC)
1343                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1344                 if (misc & ATOM_INTERLACE)
1345                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1346                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1347                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1348
1349                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1350                 break;
1351         }
1352         return true;
1353 }
1354
1355 enum radeon_tv_std
1356 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1357 {
1358         struct radeon_mode_info *mode_info = &rdev->mode_info;
1359         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1360         uint16_t data_offset;
1361         uint8_t frev, crev;
1362         struct _ATOM_ANALOG_TV_INFO *tv_info;
1363         enum radeon_tv_std tv_std = TV_STD_NTSC;
1364
1365         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1366
1367         tv_info = (struct _ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1368
1369         switch (tv_info->ucTV_BootUpDefaultStandard) {
1370         case ATOM_TV_NTSC:
1371                 tv_std = TV_STD_NTSC;
1372                 DRM_INFO("Default TV standard: NTSC\n");
1373                 break;
1374         case ATOM_TV_NTSCJ:
1375                 tv_std = TV_STD_NTSC_J;
1376                 DRM_INFO("Default TV standard: NTSC-J\n");
1377                 break;
1378         case ATOM_TV_PAL:
1379                 tv_std = TV_STD_PAL;
1380                 DRM_INFO("Default TV standard: PAL\n");
1381                 break;
1382         case ATOM_TV_PALM:
1383                 tv_std = TV_STD_PAL_M;
1384                 DRM_INFO("Default TV standard: PAL-M\n");
1385                 break;
1386         case ATOM_TV_PALN:
1387                 tv_std = TV_STD_PAL_N;
1388                 DRM_INFO("Default TV standard: PAL-N\n");
1389                 break;
1390         case ATOM_TV_PALCN:
1391                 tv_std = TV_STD_PAL_CN;
1392                 DRM_INFO("Default TV standard: PAL-CN\n");
1393                 break;
1394         case ATOM_TV_PAL60:
1395                 tv_std = TV_STD_PAL_60;
1396                 DRM_INFO("Default TV standard: PAL-60\n");
1397                 break;
1398         case ATOM_TV_SECAM:
1399                 tv_std = TV_STD_SECAM;
1400                 DRM_INFO("Default TV standard: SECAM\n");
1401                 break;
1402         default:
1403                 tv_std = TV_STD_NTSC;
1404                 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1405                 break;
1406         }
1407         return tv_std;
1408 }
1409
1410 struct radeon_encoder_tv_dac *
1411 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1412 {
1413         struct drm_device *dev = encoder->base.dev;
1414         struct radeon_device *rdev = dev->dev_private;
1415         struct radeon_mode_info *mode_info = &rdev->mode_info;
1416         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1417         uint16_t data_offset;
1418         struct _COMPASSIONATE_DATA *dac_info;
1419         uint8_t frev, crev;
1420         uint8_t bg, dac;
1421         struct radeon_encoder_tv_dac *tv_dac = NULL;
1422
1423         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1424
1425         dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1426
1427         if (dac_info) {
1428                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1429
1430                 if (!tv_dac)
1431                         return NULL;
1432
1433                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1434                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1435                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1436
1437                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1438                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1439                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1440
1441                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1442                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1443                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1444
1445                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1446         }
1447         return tv_dac;
1448 }
1449
1450 union power_info {
1451         struct _ATOM_POWERPLAY_INFO info;
1452         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1453         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1454         struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1455 };
1456
1457 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1458 {
1459         struct radeon_mode_info *mode_info = &rdev->mode_info;
1460         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1461         u16 data_offset;
1462         u8 frev, crev;
1463         u32 misc, misc2 = 0, sclk, mclk;
1464         union power_info *power_info;
1465         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1466         struct _ATOM_PPLIB_STATE *power_state;
1467         int num_modes = 0, i, j;
1468         int state_index = 0, mode_index = 0;
1469
1470         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1471
1472         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1473
1474         rdev->pm.default_power_state = NULL;
1475
1476         if (power_info) {
1477                 if (frev < 4) {
1478                         num_modes = power_info->info.ucNumOfPowerModeEntries;
1479                         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1480                                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1481                         for (i = 0; i < num_modes; i++) {
1482                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1483                                 switch (frev) {
1484                                 case 1:
1485                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1486                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1487                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1488                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1489                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1490                                         /* skip invalid modes */
1491                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1492                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1493                                                 continue;
1494                                         /* skip overclock modes for now */
1495                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1496                                              rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1497                                             (rdev->pm.power_state[state_index].clock_info[0].sclk >
1498                                              rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1499                                                 continue;
1500                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1501                                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1502                                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1503                                         if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1504                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1505                                                         VOLTAGE_GPIO;
1506                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1507                                                         radeon_lookup_gpio(rdev,
1508                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1509                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1510                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1511                                                                 true;
1512                                                 else
1513                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1514                                                                 false;
1515                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1516                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1517                                                         VOLTAGE_VDDC;
1518                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1519                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1520                                         }
1521                                         /* order matters! */
1522                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1523                                                 rdev->pm.power_state[state_index].type =
1524                                                         POWER_STATE_TYPE_POWERSAVE;
1525                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1526                                                 rdev->pm.power_state[state_index].type =
1527                                                         POWER_STATE_TYPE_BATTERY;
1528                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1529                                                 rdev->pm.power_state[state_index].type =
1530                                                         POWER_STATE_TYPE_BATTERY;
1531                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1532                                                 rdev->pm.power_state[state_index].type =
1533                                                         POWER_STATE_TYPE_BALANCED;
1534                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1535                                                 rdev->pm.power_state[state_index].type =
1536                                                         POWER_STATE_TYPE_PERFORMANCE;
1537                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1538                                                 rdev->pm.power_state[state_index].type =
1539                                                         POWER_STATE_TYPE_DEFAULT;
1540                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1541                                                 rdev->pm.power_state[state_index].default_clock_mode =
1542                                                         &rdev->pm.power_state[state_index].clock_info[0];
1543                                         }
1544                                         state_index++;
1545                                         break;
1546                                 case 2:
1547                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1548                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1549                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1550                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1551                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1552                                         /* skip invalid modes */
1553                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1554                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1555                                                 continue;
1556                                         /* skip overclock modes for now */
1557                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1558                                              rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1559                                             (rdev->pm.power_state[state_index].clock_info[0].sclk >
1560                                              rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1561                                                 continue;
1562                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1563                                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1564                                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1565                                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1566                                         if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1567                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1568                                                         VOLTAGE_GPIO;
1569                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1570                                                         radeon_lookup_gpio(rdev,
1571                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1572                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1573                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1574                                                                 true;
1575                                                 else
1576                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1577                                                                 false;
1578                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1579                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1580                                                         VOLTAGE_VDDC;
1581                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1582                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1583                                         }
1584                                         /* order matters! */
1585                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1586                                                 rdev->pm.power_state[state_index].type =
1587                                                         POWER_STATE_TYPE_POWERSAVE;
1588                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1589                                                 rdev->pm.power_state[state_index].type =
1590                                                         POWER_STATE_TYPE_BATTERY;
1591                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1592                                                 rdev->pm.power_state[state_index].type =
1593                                                         POWER_STATE_TYPE_BATTERY;
1594                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1595                                                 rdev->pm.power_state[state_index].type =
1596                                                         POWER_STATE_TYPE_BALANCED;
1597                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1598                                                 rdev->pm.power_state[state_index].type =
1599                                                         POWER_STATE_TYPE_PERFORMANCE;
1600                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1601                                                 rdev->pm.power_state[state_index].type =
1602                                                         POWER_STATE_TYPE_BALANCED;
1603                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1604                                                 rdev->pm.power_state[state_index].type =
1605                                                         POWER_STATE_TYPE_DEFAULT;
1606                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1607                                                 rdev->pm.power_state[state_index].default_clock_mode =
1608                                                         &rdev->pm.power_state[state_index].clock_info[0];
1609                                         }
1610                                         state_index++;
1611                                         break;
1612                                 case 3:
1613                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1614                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1615                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1616                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1617                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1618                                         /* skip invalid modes */
1619                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1620                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1621                                                 continue;
1622                                         /* skip overclock modes for now */
1623                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1624                                              rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1625                                             (rdev->pm.power_state[state_index].clock_info[0].sclk >
1626                                              rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1627                                                 continue;
1628                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1629                                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1630                                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1631                                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1632                                         if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1633                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1634                                                         VOLTAGE_GPIO;
1635                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1636                                                         radeon_lookup_gpio(rdev,
1637                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1638                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1639                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1640                                                                 true;
1641                                                 else
1642                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1643                                                                 false;
1644                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1645                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1646                                                         VOLTAGE_VDDC;
1647                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1648                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1649                                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1650                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1651                                                                 true;
1652                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1653                                                         power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1654                                                 }
1655                                         }
1656                                         /* order matters! */
1657                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1658                                                 rdev->pm.power_state[state_index].type =
1659                                                         POWER_STATE_TYPE_POWERSAVE;
1660                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1661                                                 rdev->pm.power_state[state_index].type =
1662                                                         POWER_STATE_TYPE_BATTERY;
1663                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1664                                                 rdev->pm.power_state[state_index].type =
1665                                                         POWER_STATE_TYPE_BATTERY;
1666                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1667                                                 rdev->pm.power_state[state_index].type =
1668                                                         POWER_STATE_TYPE_BALANCED;
1669                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1670                                                 rdev->pm.power_state[state_index].type =
1671                                                         POWER_STATE_TYPE_PERFORMANCE;
1672                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1673                                                 rdev->pm.power_state[state_index].type =
1674                                                         POWER_STATE_TYPE_BALANCED;
1675                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1676                                                 rdev->pm.power_state[state_index].type =
1677                                                         POWER_STATE_TYPE_DEFAULT;
1678                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1679                                                 rdev->pm.power_state[state_index].default_clock_mode =
1680                                                         &rdev->pm.power_state[state_index].clock_info[0];
1681                                         }
1682                                         state_index++;
1683                                         break;
1684                                 }
1685                         }
1686                 } else if (frev == 4) {
1687                         for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1688                                 mode_index = 0;
1689                                 power_state = (struct _ATOM_PPLIB_STATE *)
1690                                         (mode_info->atom_context->bios +
1691                                          data_offset +
1692                                          le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1693                                          i * power_info->info_4.ucStateEntrySize);
1694                                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1695                                         (mode_info->atom_context->bios +
1696                                          data_offset +
1697                                          le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1698                                          (power_state->ucNonClockStateIndex *
1699                                           power_info->info_4.ucNonClockSize));
1700                                 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1701                                         if (rdev->flags & RADEON_IS_IGP) {
1702                                                 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1703                                                         (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1704                                                         (mode_info->atom_context->bios +
1705                                                          data_offset +
1706                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1707                                                          (power_state->ucClockStateIndices[j] *
1708                                                           power_info->info_4.ucClockInfoSize));
1709                                                 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1710                                                 sclk |= clock_info->ucLowEngineClockHigh << 16;
1711                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1712                                                 /* skip invalid modes */
1713                                                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1714                                                         continue;
1715                                                 /* skip overclock modes for now */
1716                                                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1717                                                     rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)
1718                                                         continue;
1719                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1720                                                         VOLTAGE_SW;
1721                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1722                                                         clock_info->usVDDC;
1723                                                 mode_index++;
1724                                         } else {
1725                                                 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
1726                                                         (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
1727                                                         (mode_info->atom_context->bios +
1728                                                          data_offset +
1729                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1730                                                          (power_state->ucClockStateIndices[j] *
1731                                                           power_info->info_4.ucClockInfoSize));
1732                                                 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1733                                                 sclk |= clock_info->ucEngineClockHigh << 16;
1734                                                 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1735                                                 mclk |= clock_info->ucMemoryClockHigh << 16;
1736                                                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1737                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1738                                                 /* skip invalid modes */
1739                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1740                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1741                                                         continue;
1742                                                 /* skip overclock modes for now */
1743                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk >
1744                                                      rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1745                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1746                                                      rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1747                                                         continue;
1748                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1749                                                         VOLTAGE_SW;
1750                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1751                                                         clock_info->usVDDC;
1752                                                 mode_index++;
1753                                         }
1754                                 }
1755                                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1756                                 if (mode_index) {
1757                                         misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1758                                         misc2 = le16_to_cpu(non_clock_info->usClassification);
1759                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1760                                                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1761                                                 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
1762                                         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1763                                         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1764                                                 rdev->pm.power_state[state_index].type =
1765                                                         POWER_STATE_TYPE_BATTERY;
1766                                                 break;
1767                                         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1768                                                 rdev->pm.power_state[state_index].type =
1769                                                         POWER_STATE_TYPE_BALANCED;
1770                                                 break;
1771                                         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1772                                                 rdev->pm.power_state[state_index].type =
1773                                                         POWER_STATE_TYPE_PERFORMANCE;
1774                                                 break;
1775                                         }
1776                                         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1777                                                 rdev->pm.power_state[state_index].type =
1778                                                         POWER_STATE_TYPE_DEFAULT;
1779                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1780                                                 rdev->pm.power_state[state_index].default_clock_mode =
1781                                                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1782                                         }
1783                                         state_index++;
1784                                 }
1785                         }
1786                 }
1787         } else {
1788                 /* XXX figure out some good default low power mode for cards w/out power tables */
1789         }
1790
1791         if (rdev->pm.default_power_state == NULL) {
1792                 /* add the default mode */
1793                 rdev->pm.power_state[state_index].type =
1794                         POWER_STATE_TYPE_DEFAULT;
1795                 rdev->pm.power_state[state_index].num_clock_modes = 1;
1796                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
1797                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
1798                 rdev->pm.power_state[state_index].default_clock_mode =
1799                         &rdev->pm.power_state[state_index].clock_info[0];
1800                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1801                 if (rdev->asic->get_pcie_lanes)
1802                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
1803                 else
1804                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
1805                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1806                 state_index++;
1807         }
1808         rdev->pm.num_power_states = state_index;
1809
1810         rdev->pm.current_power_state = rdev->pm.default_power_state;
1811         rdev->pm.current_clock_mode =
1812                 rdev->pm.default_power_state->default_clock_mode;
1813 }
1814
1815 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1816 {
1817         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1818         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1819
1820         args.ucEnable = enable;
1821
1822         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1823 }
1824
1825 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1826 {
1827         GET_ENGINE_CLOCK_PS_ALLOCATION args;
1828         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1829
1830         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1831         return args.ulReturnEngineClock;
1832 }
1833
1834 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1835 {
1836         GET_MEMORY_CLOCK_PS_ALLOCATION args;
1837         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1838
1839         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1840         return args.ulReturnMemoryClock;
1841 }
1842
1843 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1844                                   uint32_t eng_clock)
1845 {
1846         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1847         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1848
1849         args.ulTargetEngineClock = eng_clock;   /* 10 khz */
1850
1851         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1852 }
1853
1854 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1855                                   uint32_t mem_clock)
1856 {
1857         SET_MEMORY_CLOCK_PS_ALLOCATION args;
1858         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1859
1860         if (rdev->flags & RADEON_IS_IGP)
1861                 return;
1862
1863         args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
1864
1865         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1866 }
1867
1868 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1869 {
1870         struct radeon_device *rdev = dev->dev_private;
1871         uint32_t bios_2_scratch, bios_6_scratch;
1872
1873         if (rdev->family >= CHIP_R600) {
1874                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1875                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1876         } else {
1877                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1878                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1879         }
1880
1881         /* let the bios control the backlight */
1882         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1883
1884         /* tell the bios not to handle mode switching */
1885         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1886
1887         if (rdev->family >= CHIP_R600) {
1888                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1889                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1890         } else {
1891                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1892                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1893         }
1894
1895 }
1896
1897 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1898 {
1899         uint32_t scratch_reg;
1900         int i;
1901
1902         if (rdev->family >= CHIP_R600)
1903                 scratch_reg = R600_BIOS_0_SCRATCH;
1904         else
1905                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1906
1907         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1908                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1909 }
1910
1911 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1912 {
1913         uint32_t scratch_reg;
1914         int i;
1915
1916         if (rdev->family >= CHIP_R600)
1917                 scratch_reg = R600_BIOS_0_SCRATCH;
1918         else
1919                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1920
1921         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1922                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1923 }
1924
1925 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1926 {
1927         struct drm_device *dev = encoder->dev;
1928         struct radeon_device *rdev = dev->dev_private;
1929         uint32_t bios_6_scratch;
1930
1931         if (rdev->family >= CHIP_R600)
1932                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1933         else
1934                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1935
1936         if (lock)
1937                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1938         else
1939                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1940
1941         if (rdev->family >= CHIP_R600)
1942                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1943         else
1944                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1945 }
1946
1947 /* at some point we may want to break this out into individual functions */
1948 void
1949 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1950                                        struct drm_encoder *encoder,
1951                                        bool connected)
1952 {
1953         struct drm_device *dev = connector->dev;
1954         struct radeon_device *rdev = dev->dev_private;
1955         struct radeon_connector *radeon_connector =
1956             to_radeon_connector(connector);
1957         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1958         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1959
1960         if (rdev->family >= CHIP_R600) {
1961                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1962                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1963                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1964         } else {
1965                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1966                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1967                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1968         }
1969
1970         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1971             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1972                 if (connected) {
1973                         DRM_DEBUG("TV1 connected\n");
1974                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1975                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1976                 } else {
1977                         DRM_DEBUG("TV1 disconnected\n");
1978                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1979                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1980                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1981                 }
1982         }
1983         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1984             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1985                 if (connected) {
1986                         DRM_DEBUG("CV connected\n");
1987                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1988                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1989                 } else {
1990                         DRM_DEBUG("CV disconnected\n");
1991                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
1992                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1993                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1994                 }
1995         }
1996         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1997             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1998                 if (connected) {
1999                         DRM_DEBUG("LCD1 connected\n");
2000                         bios_0_scratch |= ATOM_S0_LCD1;
2001                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2002                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2003                 } else {
2004                         DRM_DEBUG("LCD1 disconnected\n");
2005                         bios_0_scratch &= ~ATOM_S0_LCD1;
2006                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2007                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2008                 }
2009         }
2010         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2011             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2012                 if (connected) {
2013                         DRM_DEBUG("CRT1 connected\n");
2014                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2015                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2016                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2017                 } else {
2018                         DRM_DEBUG("CRT1 disconnected\n");
2019                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2020                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2021                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2022                 }
2023         }
2024         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2025             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2026                 if (connected) {
2027                         DRM_DEBUG("CRT2 connected\n");
2028                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2029                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2030                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2031                 } else {
2032                         DRM_DEBUG("CRT2 disconnected\n");
2033                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2034                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2035                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2036                 }
2037         }
2038         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2039             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2040                 if (connected) {
2041                         DRM_DEBUG("DFP1 connected\n");
2042                         bios_0_scratch |= ATOM_S0_DFP1;
2043                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2044                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2045                 } else {
2046                         DRM_DEBUG("DFP1 disconnected\n");
2047                         bios_0_scratch &= ~ATOM_S0_DFP1;
2048                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2049                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2050                 }
2051         }
2052         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2053             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2054                 if (connected) {
2055                         DRM_DEBUG("DFP2 connected\n");
2056                         bios_0_scratch |= ATOM_S0_DFP2;
2057                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2058                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2059                 } else {
2060                         DRM_DEBUG("DFP2 disconnected\n");
2061                         bios_0_scratch &= ~ATOM_S0_DFP2;
2062                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2063                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2064                 }
2065         }
2066         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2067             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2068                 if (connected) {
2069                         DRM_DEBUG("DFP3 connected\n");
2070                         bios_0_scratch |= ATOM_S0_DFP3;
2071                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2072                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2073                 } else {
2074                         DRM_DEBUG("DFP3 disconnected\n");
2075                         bios_0_scratch &= ~ATOM_S0_DFP3;
2076                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2077                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2078                 }
2079         }
2080         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2081             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2082                 if (connected) {
2083                         DRM_DEBUG("DFP4 connected\n");
2084                         bios_0_scratch |= ATOM_S0_DFP4;
2085                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2086                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2087                 } else {
2088                         DRM_DEBUG("DFP4 disconnected\n");
2089                         bios_0_scratch &= ~ATOM_S0_DFP4;
2090                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2091                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2092                 }
2093         }
2094         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2095             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2096                 if (connected) {
2097                         DRM_DEBUG("DFP5 connected\n");
2098                         bios_0_scratch |= ATOM_S0_DFP5;
2099                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2100                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2101                 } else {
2102                         DRM_DEBUG("DFP5 disconnected\n");
2103                         bios_0_scratch &= ~ATOM_S0_DFP5;
2104                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2105                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2106                 }
2107         }
2108
2109         if (rdev->family >= CHIP_R600) {
2110                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2111                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2112                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2113         } else {
2114                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2115                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2116                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2117         }
2118 }
2119
2120 void
2121 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2122 {
2123         struct drm_device *dev = encoder->dev;
2124         struct radeon_device *rdev = dev->dev_private;
2125         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2126         uint32_t bios_3_scratch;
2127
2128         if (rdev->family >= CHIP_R600)
2129                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2130         else
2131                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2132
2133         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2134                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2135                 bios_3_scratch |= (crtc << 18);
2136         }
2137         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2138                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2139                 bios_3_scratch |= (crtc << 24);
2140         }
2141         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2142                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2143                 bios_3_scratch |= (crtc << 16);
2144         }
2145         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2146                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2147                 bios_3_scratch |= (crtc << 20);
2148         }
2149         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2150                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2151                 bios_3_scratch |= (crtc << 17);
2152         }
2153         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2154                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2155                 bios_3_scratch |= (crtc << 19);
2156         }
2157         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2158                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2159                 bios_3_scratch |= (crtc << 23);
2160         }
2161         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2162                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2163                 bios_3_scratch |= (crtc << 25);
2164         }
2165
2166         if (rdev->family >= CHIP_R600)
2167                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2168         else
2169                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2170 }
2171
2172 void
2173 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2174 {
2175         struct drm_device *dev = encoder->dev;
2176         struct radeon_device *rdev = dev->dev_private;
2177         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2178         uint32_t bios_2_scratch;
2179
2180         if (rdev->family >= CHIP_R600)
2181                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2182         else
2183                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2184
2185         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2186                 if (on)
2187                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2188                 else
2189                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2190         }
2191         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2192                 if (on)
2193                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2194                 else
2195                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2196         }
2197         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2198                 if (on)
2199                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2200                 else
2201                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2202         }
2203         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2204                 if (on)
2205                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2206                 else
2207                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2208         }
2209         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2210                 if (on)
2211                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2212                 else
2213                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2214         }
2215         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2216                 if (on)
2217                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2218                 else
2219                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2220         }
2221         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2222                 if (on)
2223                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2224                 else
2225                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2226         }
2227         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2228                 if (on)
2229                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2230                 else
2231                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2232         }
2233         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2234                 if (on)
2235                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2236                 else
2237                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2238         }
2239         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2240                 if (on)
2241                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2242                 else
2243                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2244         }
2245
2246         if (rdev->family >= CHIP_R600)
2247                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2248         else
2249                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2250 }