drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  36                         uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
  40                         uint32_t supported_device);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd,
  52                           struct radeon_router *router);
  53
  54 /* from radeon_legacy_encoder.c */
  55 extern void
  56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  57                           uint32_t supported_device);
  58
  59 union atom_supported_devices {
  60         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  62         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  63 };
  64
  65 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
  66                                                                uint8_t id)
  67 {
  68         struct atom_context *ctx = rdev->mode_info.atom_context;
  69         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  70         struct radeon_i2c_bus_rec i2c;
  71         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  72         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  73         uint16_t data_offset, size;
  74         int i, num_indices;
  75
  76         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  77         i2c.valid = false;
  78
  79         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
  80                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  81
  82                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
  83                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
  84
  85                 for (i = 0; i < num_indices; i++) {
  86                         gpio = &i2c_info->asGPIO_Info[i];
  87
  88                         /* some evergreen boards have bad data for this entry */
  89                         if (ASIC_IS_DCE4(rdev)) {
  90                                 if ((i == 7) &&
  91                                     (gpio->usClkMaskRegisterIndex == 0x1936) &&
  92                                     (gpio->sucI2cId.ucAccess == 0)) {
  93                                         gpio->sucI2cId.ucAccess = 0x97;
  94                                         gpio->ucDataMaskShift = 8;
  95                                         gpio->ucDataEnShift = 8;
  96                                         gpio->ucDataY_Shift = 8;
  97                                         gpio->ucDataA_Shift = 8;
  98                                 }
  99                         }
 100
 101                         if (gpio->sucI2cId.ucAccess == id) {
 102                                 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 103                                 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 104                                 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 105                                 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 106                                 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 107                                 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 108                                 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 109                                 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 110                                 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 111                                 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 112                                 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 113                                 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 114                                 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 115                                 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 116                                 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 117                                 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 118
 119                                 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 120                                         i2c.hw_capable = true;
 121                                 else
 122                                         i2c.hw_capable = false;
 123
 124                                 if (gpio->sucI2cId.ucAccess == 0xa0)
 125                                         i2c.mm_i2c = true;
 126                                 else
 127                                         i2c.mm_i2c = false;
 128
 129                                 i2c.i2c_id = gpio->sucI2cId.ucAccess;
 130
 131                                 if (i2c.mask_clk_reg)
 132                                         i2c.valid = true;
 133                                 break;
 134                         }
 135                 }
 136         }
 137
 138         return i2c;
 139 }
 140
 141 void radeon_atombios_i2c_init(struct radeon_device *rdev)
 142 {
 143         struct atom_context *ctx = rdev->mode_info.atom_context;
 144         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 145         struct radeon_i2c_bus_rec i2c;
 146         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 147         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 148         uint16_t data_offset, size;
 149         int i, num_indices;
 150         char stmp[32];
 151
 152         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 153
 154         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 155                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 156
 157                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 158                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 159
 160                 for (i = 0; i < num_indices; i++) {
 161                         gpio = &i2c_info->asGPIO_Info[i];
 162                         i2c.valid = false;
 163
 164                         /* some evergreen boards have bad data for this entry */
 165                         if (ASIC_IS_DCE4(rdev)) {
 166                                 if ((i == 7) &&
 167                                     (gpio->usClkMaskRegisterIndex == 0x1936) &&
 168                                     (gpio->sucI2cId.ucAccess == 0)) {
 169                                         gpio->sucI2cId.ucAccess = 0x97;
 170                                         gpio->ucDataMaskShift = 8;
 171                                         gpio->ucDataEnShift = 8;
 172                                         gpio->ucDataY_Shift = 8;
 173                                         gpio->ucDataA_Shift = 8;
 174                                 }
 175                         }
 176
 177                         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 178                         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 179                         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 180                         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 181                         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 182                         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 183                         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 184                         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 185                         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 186                         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 187                         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 188                         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 189                         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 190                         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 191                         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 192                         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 193
 194                         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 195                                 i2c.hw_capable = true;
 196                         else
 197                                 i2c.hw_capable = false;
 198
 199                         if (gpio->sucI2cId.ucAccess == 0xa0)
 200                                 i2c.mm_i2c = true;
 201                         else
 202                                 i2c.mm_i2c = false;
 203
 204                         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 205
 206                         if (i2c.mask_clk_reg) {
 207                                 i2c.valid = true;
 208                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 209                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
 210                         }
 211                 }
 212         }
 213 }
 214
 215 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 216                                                         u8 id)
 217 {
 218         struct atom_context *ctx = rdev->mode_info.atom_context;
 219         struct radeon_gpio_rec gpio;
 220         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 221         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 222         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 223         u16 data_offset, size;
 224         int i, num_indices;
 225
 226         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 227         gpio.valid = false;
 228
 229         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 230                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 231
 232                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 233                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 234
 235                 for (i = 0; i < num_indices; i++) {
 236                         pin = &gpio_info->asGPIO_Pin[i];
 237                         if (id == pin->ucGPIO_ID) {
 238                                 gpio.id = pin->ucGPIO_ID;
 239                                 gpio.reg = pin->usGpioPin_AIndex * 4;
 240                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 241                                 gpio.valid = true;
 242                                 break;
 243                         }
 244                 }
 245         }
 246
 247         return gpio;
 248 }
 249
 250 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 251                                                             struct radeon_gpio_rec *gpio)
 252 {
 253         struct radeon_hpd hpd;
 254         u32 reg;
 255
 256         memset(&hpd, 0, sizeof(struct radeon_hpd));
 257
 258         if (ASIC_IS_DCE4(rdev))
 259                 reg = EVERGREEN_DC_GPIO_HPD_A;
 260         else
 261                 reg = AVIVO_DC_GPIO_HPD_A;
 262
 263         hpd.gpio = *gpio;
 264         if (gpio->reg == reg) {
 265                 switch(gpio->mask) {
 266                 case (1 << 0):
 267                         hpd.hpd = RADEON_HPD_1;
 268                         break;
 269                 case (1 << 8):
 270                         hpd.hpd = RADEON_HPD_2;
 271                         break;
 272                 case (1 << 16):
 273                         hpd.hpd = RADEON_HPD_3;
 274                         break;
 275                 case (1 << 24):
 276                         hpd.hpd = RADEON_HPD_4;
 277                         break;
 278                 case (1 << 26):
 279                         hpd.hpd = RADEON_HPD_5;
 280                         break;
 281                 case (1 << 28):
 282                         hpd.hpd = RADEON_HPD_6;
 283                         break;
 284                 default:
 285                         hpd.hpd = RADEON_HPD_NONE;
 286                         break;
 287                 }
 288         } else
 289                 hpd.hpd = RADEON_HPD_NONE;
 290         return hpd;
 291 }
 292
 293 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 294                                      uint32_t supported_device,
 295                                      int *connector_type,
 296                                      struct radeon_i2c_bus_rec *i2c_bus,
 297                                      uint16_t *line_mux,
 298                                      struct radeon_hpd *hpd)
 299 {
 300         struct radeon_device *rdev = dev->dev_private;
 301
 302         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 303         if ((dev->pdev->device == 0x791e) &&
 304             (dev->pdev->subsystem_vendor == 0x1043) &&
 305             (dev->pdev->subsystem_device == 0x826d)) {
 306                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 307                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 308                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 309         }
 310
 311         /* Asrock RS600 board lists the DVI port as HDMI */
 312         if ((dev->pdev->device == 0x7941) &&
 313             (dev->pdev->subsystem_vendor == 0x1849) &&
 314             (dev->pdev->subsystem_device == 0x7941)) {
 315                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 316                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 317                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 318         }
 319
 320         /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
 321         if ((dev->pdev->device == 0x796e) &&
 322             (dev->pdev->subsystem_vendor == 0x1462) &&
 323             (dev->pdev->subsystem_device == 0x7302)) {
 324                 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 325                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 326                         return false;
 327         }
 328
 329         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 330         if ((dev->pdev->device == 0x7941) &&
 331             (dev->pdev->subsystem_vendor == 0x147b) &&
 332             (dev->pdev->subsystem_device == 0x2412)) {
 333                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 334                         return false;
 335         }
 336
 337         /* Falcon NW laptop lists vga ddc line for LVDS */
 338         if ((dev->pdev->device == 0x5653) &&
 339             (dev->pdev->subsystem_vendor == 0x1462) &&
 340             (dev->pdev->subsystem_device == 0x0291)) {
 341                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 342                         i2c_bus->valid = false;
 343                         *line_mux = 53;
 344                 }
 345         }
 346
 347         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 348         if ((dev->pdev->device == 0x7146) &&
 349             (dev->pdev->subsystem_vendor == 0x17af) &&
 350             (dev->pdev->subsystem_device == 0x2058)) {
 351                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 352                         return false;
 353         }
 354
 355         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 356         if ((dev->pdev->device == 0x7142) &&
 357             (dev->pdev->subsystem_vendor == 0x1458) &&
 358             (dev->pdev->subsystem_device == 0x2134)) {
 359                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 360                         return false;
 361         }
 362
 363
 364         /* Funky macbooks */
 365         if ((dev->pdev->device == 0x71C5) &&
 366             (dev->pdev->subsystem_vendor == 0x106b) &&
 367             (dev->pdev->subsystem_device == 0x0080)) {
 368                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 369                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 370                         return false;
 371                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 372                         *line_mux = 0x90;
 373         }
 374
 375         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 376         if ((dev->pdev->device == 0x9598) &&
 377             (dev->pdev->subsystem_vendor == 0x1043) &&
 378             (dev->pdev->subsystem_device == 0x01da)) {
 379                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 380                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 381                 }
 382         }
 383
 384         /* ASUS HD 3600 board lists the DVI port as HDMI */
 385         if ((dev->pdev->device == 0x9598) &&
 386             (dev->pdev->subsystem_vendor == 0x1043) &&
 387             (dev->pdev->subsystem_device == 0x01e4)) {
 388                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 389                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 390                 }
 391         }
 392
 393         /* ASUS HD 3450 board lists the DVI port as HDMI */
 394         if ((dev->pdev->device == 0x95C5) &&
 395             (dev->pdev->subsystem_vendor == 0x1043) &&
 396             (dev->pdev->subsystem_device == 0x01e2)) {
 397                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 398                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 399                 }
 400         }
 401
 402         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 403          * HDMI + VGA reporting as HDMI
 404          */
 405         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 406                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 407                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 408                         *line_mux = 0;
 409                 }
 410         }
 411
 412         /* Acer laptop reports DVI-D as DVI-I and hpd pins reversed */
 413         if ((dev->pdev->device == 0x95c4) &&
 414             (dev->pdev->subsystem_vendor == 0x1025) &&
 415             (dev->pdev->subsystem_device == 0x013c)) {
 416                 struct radeon_gpio_rec gpio;
 417
 418                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 419                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 420                         gpio = radeon_lookup_gpio(rdev, 6);
 421                         *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 422                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 423                 } else if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 424                            (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 425                         gpio = radeon_lookup_gpio(rdev, 7);
 426                         *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 427                 }
 428         }
 429
 430         /* XFX Pine Group device rv730 reports no VGA DDC lines
 431          * even though they are wired up to record 0x93
 432          */
 433         if ((dev->pdev->device == 0x9498) &&
 434             (dev->pdev->subsystem_vendor == 0x1682) &&
 435             (dev->pdev->subsystem_device == 0x2452)) {
 436                 struct radeon_device *rdev = dev->dev_private;
 437                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 438         }
 439         return true;
 440 }
 441
 442 const int supported_devices_connector_convert[] = {
 443         DRM_MODE_CONNECTOR_Unknown,
 444         DRM_MODE_CONNECTOR_VGA,
 445         DRM_MODE_CONNECTOR_DVII,
 446         DRM_MODE_CONNECTOR_DVID,
 447         DRM_MODE_CONNECTOR_DVIA,
 448         DRM_MODE_CONNECTOR_SVIDEO,
 449         DRM_MODE_CONNECTOR_Composite,
 450         DRM_MODE_CONNECTOR_LVDS,
 451         DRM_MODE_CONNECTOR_Unknown,
 452         DRM_MODE_CONNECTOR_Unknown,
 453         DRM_MODE_CONNECTOR_HDMIA,
 454         DRM_MODE_CONNECTOR_HDMIB,
 455         DRM_MODE_CONNECTOR_Unknown,
 456         DRM_MODE_CONNECTOR_Unknown,
 457         DRM_MODE_CONNECTOR_9PinDIN,
 458         DRM_MODE_CONNECTOR_DisplayPort
 459 };
 460
 461 const uint16_t supported_devices_connector_object_id_convert[] = {
 462         CONNECTOR_OBJECT_ID_NONE,
 463         CONNECTOR_OBJECT_ID_VGA,
 464         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 465         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 466         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 467         CONNECTOR_OBJECT_ID_COMPOSITE,
 468         CONNECTOR_OBJECT_ID_SVIDEO,
 469         CONNECTOR_OBJECT_ID_LVDS,
 470         CONNECTOR_OBJECT_ID_9PIN_DIN,
 471         CONNECTOR_OBJECT_ID_9PIN_DIN,
 472         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 473         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 474         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 475         CONNECTOR_OBJECT_ID_SVIDEO
 476 };
 477
 478 const int object_connector_convert[] = {
 479         DRM_MODE_CONNECTOR_Unknown,
 480         DRM_MODE_CONNECTOR_DVII,
 481         DRM_MODE_CONNECTOR_DVII,
 482         DRM_MODE_CONNECTOR_DVID,
 483         DRM_MODE_CONNECTOR_DVID,
 484         DRM_MODE_CONNECTOR_VGA,
 485         DRM_MODE_CONNECTOR_Composite,
 486         DRM_MODE_CONNECTOR_SVIDEO,
 487         DRM_MODE_CONNECTOR_Unknown,
 488         DRM_MODE_CONNECTOR_Unknown,
 489         DRM_MODE_CONNECTOR_9PinDIN,
 490         DRM_MODE_CONNECTOR_Unknown,
 491         DRM_MODE_CONNECTOR_HDMIA,
 492         DRM_MODE_CONNECTOR_HDMIB,
 493         DRM_MODE_CONNECTOR_LVDS,
 494         DRM_MODE_CONNECTOR_9PinDIN,
 495         DRM_MODE_CONNECTOR_Unknown,
 496         DRM_MODE_CONNECTOR_Unknown,
 497         DRM_MODE_CONNECTOR_Unknown,
 498         DRM_MODE_CONNECTOR_DisplayPort,
 499         DRM_MODE_CONNECTOR_eDP,
 500         DRM_MODE_CONNECTOR_Unknown
 501 };
 502
 503 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 504 {
 505         struct radeon_device *rdev = dev->dev_private;
 506         struct radeon_mode_info *mode_info = &rdev->mode_info;
 507         struct atom_context *ctx = mode_info->atom_context;
 508         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 509         u16 size, data_offset;
 510         u8 frev, crev;
 511         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 512         ATOM_OBJECT_TABLE *router_obj;
 513         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 514         ATOM_OBJECT_HEADER *obj_header;
 515         int i, j, k, path_size, device_support;
 516         int connector_type;
 517         u16 igp_lane_info, conn_id, connector_object_id;
 518         struct radeon_i2c_bus_rec ddc_bus;
 519         struct radeon_router router;
 520         struct radeon_gpio_rec gpio;
 521         struct radeon_hpd hpd;
 522
 523         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 524                 return false;
 525
 526         if (crev < 2)
 527                 return false;
 528
 529         router.valid = false;
 530
 531         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 532         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 533             (ctx->bios + data_offset +
 534              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 535         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 536             (ctx->bios + data_offset +
 537              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 538         router_obj = (ATOM_OBJECT_TABLE *)
 539                 (ctx->bios + data_offset +
 540                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 541         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 542
 543         path_size = 0;
 544         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 545                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 546                 ATOM_DISPLAY_OBJECT_PATH *path;
 547                 addr += path_size;
 548                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 549                 path_size += le16_to_cpu(path->usSize);
 550
 551                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 552                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 553
 554                         con_obj_id =
 555                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 556                             >> OBJECT_ID_SHIFT;
 557                         con_obj_num =
 558                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 559                             >> ENUM_ID_SHIFT;
 560                         con_obj_type =
 561                             (le16_to_cpu(path->usConnObjectId) &
 562                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 563
 564                         /* TODO CV support */
 565                         if (le16_to_cpu(path->usDeviceTag) ==
 566                                 ATOM_DEVICE_CV_SUPPORT)
 567                                 continue;
 568
 569                         /* IGP chips */
 570                         if ((rdev->flags & RADEON_IS_IGP) &&
 571                             (con_obj_id ==
 572                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 573                                 uint16_t igp_offset = 0;
 574                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 575
 576                                 index =
 577                                     GetIndexIntoMasterTable(DATA,
 578                                                             IntegratedSystemInfo);
 579
 580                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 581                                                            &crev, &igp_offset)) {
 582
 583                                         if (crev >= 2) {
 584                                                 igp_obj =
 585                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 586                                                          *) (ctx->bios + igp_offset);
 587
 588                                                 if (igp_obj) {
 589                                                         uint32_t slot_config, ct;
 590
 591                                                         if (con_obj_num == 1)
 592                                                                 slot_config =
 593                                                                         igp_obj->
 594                                                                         ulDDISlot1Config;
 595                                                         else
 596                                                                 slot_config =
 597                                                                         igp_obj->
 598                                                                         ulDDISlot2Config;
 599
 600                                                         ct = (slot_config >> 16) & 0xff;
 601                                                         connector_type =
 602                                                                 object_connector_convert
 603                                                                 [ct];
 604                                                         connector_object_id = ct;
 605                                                         igp_lane_info =
 606                                                                 slot_config & 0xffff;
 607                                                 } else
 608                                                         continue;
 609                                         } else
 610                                                 continue;
 611                                 } else {
 612                                         igp_lane_info = 0;
 613                                         connector_type =
 614                                                 object_connector_convert[con_obj_id];
 615                                         connector_object_id = con_obj_id;
 616                                 }
 617                         } else {
 618                                 igp_lane_info = 0;
 619                                 connector_type =
 620                                     object_connector_convert[con_obj_id];
 621                                 connector_object_id = con_obj_id;
 622                         }
 623
 624                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 625                                 continue;
 626
 627                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 628                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 629
 630                                 grph_obj_id =
 631                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 632                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 633                                 grph_obj_num =
 634                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 635                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 636                                 grph_obj_type =
 637                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 638                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 639
 640                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 641                                         u16 encoder_obj = le16_to_cpu(path->usGraphicObjIds[j]);
 642
 643                                         radeon_add_atom_encoder(dev,
 644                                                                 encoder_obj,
 645                                                                 le16_to_cpu
 646                                                                 (path->
 647                                                                  usDeviceTag));
 648
 649                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 650                                         router.valid = false;
 651                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 652                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[j].usObjectID);
 653                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 654                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 655                                                                 (ctx->bios + data_offset +
 656                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 657                                                         ATOM_I2C_RECORD *i2c_record;
 658                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 659                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 660                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 661                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 662                                                                 (ctx->bios + data_offset +
 663                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 664                                                         int enum_id;
 665
 666                                                         router.router_id = router_obj_id;
 667                                                         for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
 668                                                              enum_id++) {
 669                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 670                                                                     le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
 671                                                                         break;
 672                                                         }
 673
 674                                                         while (record->ucRecordType > 0 &&
 675                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 676                                                                 switch (record->ucRecordType) {
 677                                                                 case ATOM_I2C_RECORD_TYPE:
 678                                                                         i2c_record =
 679                                                                                 (ATOM_I2C_RECORD *)
 680                                                                                 record;
 681                                                                         i2c_config =
 682                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 683                                                                                 &i2c_record->sucI2cId;
 684                                                                         router.i2c_info =
 685                                                                                 radeon_lookup_i2c_gpio(rdev,
 686                                                                                                        i2c_config->
 687                                                                                                        ucAccess);
 688                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 689                                                                         break;
 690                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 691                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 692                                                                                 record;
 693                                                                         router.valid = true;
 694                                                                         router.mux_type = ddc_path->ucMuxType;
 695                                                                         router.mux_control_pin = ddc_path->ucMuxControlPin;
 696                                                                         router.mux_state = ddc_path->ucMuxState[enum_id];
 697                                                                         break;
 698                                                                 }
 699                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 700                                                                         ((char *)record + record->ucRecordSize);
 701                                                         }
 702                                                 }
 703                                         }
 704                                 }
 705                         }
 706
 707                         /* look up gpio for ddc, hpd */
 708                         ddc_bus.valid = false;
 709                         hpd.hpd = RADEON_HPD_NONE;
 710                         if ((le16_to_cpu(path->usDeviceTag) &
 711                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 712                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 713                                         if (le16_to_cpu(path->usConnObjectId) ==
 714                                             le16_to_cpu(con_obj->asObjects[j].
 715                                                         usObjectID)) {
 716                                                 ATOM_COMMON_RECORD_HEADER
 717                                                     *record =
 718                                                     (ATOM_COMMON_RECORD_HEADER
 719                                                      *)
 720                                                     (ctx->bios + data_offset +
 721                                                      le16_to_cpu(con_obj->
 722                                                                  asObjects[j].
 723                                                                  usRecordOffset));
 724                                                 ATOM_I2C_RECORD *i2c_record;
 725                                                 ATOM_HPD_INT_RECORD *hpd_record;
 726                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 727
 728                                                 while (record->ucRecordType > 0
 729                                                        && record->
 730                                                        ucRecordType <=
 731                                                        ATOM_MAX_OBJECT_RECORD_NUMBER) {
 732                                                         switch (record->ucRecordType) {
 733                                                         case ATOM_I2C_RECORD_TYPE:
 734                                                                 i2c_record =
 735                                                                     (ATOM_I2C_RECORD *)
 736                                                                         record;
 737                                                                 i2c_config =
 738                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 739                                                                         &i2c_record->sucI2cId;
 740                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 741                                                                                                  i2c_config->
 742                                                                                                  ucAccess);
 743                                                                 break;
 744                                                         case ATOM_HPD_INT_RECORD_TYPE:
 745                                                                 hpd_record =
 746                                                                         (ATOM_HPD_INT_RECORD *)
 747                                                                         record;
 748                                                                 gpio = radeon_lookup_gpio(rdev,
 749                                                                                           hpd_record->ucHPDIntGPIOID);
 750                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 751                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 752                                                                 break;
 753                                                         }
 754                                                         record =
 755                                                             (ATOM_COMMON_RECORD_HEADER
 756                                                              *) ((char *)record
 757                                                                  +
 758                                                                  record->
 759                                                                  ucRecordSize);
 760                                                 }
 761                                                 break;
 762                                         }
 763                                 }
 764                         }
 765
 766                         /* needed for aux chan transactions */
 767                         ddc_bus.hpd = hpd.hpd;
 768
 769                         conn_id = le16_to_cpu(path->usConnObjectId);
 770
 771                         if (!radeon_atom_apply_quirks
 772                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 773                              &ddc_bus, &conn_id, &hpd))
 774                                 continue;
 775
 776                         radeon_add_atom_connector(dev,
 777                                                   conn_id,
 778                                                   le16_to_cpu(path->
 779                                                               usDeviceTag),
 780                                                   connector_type, &ddc_bus,
 781                                                   igp_lane_info,
 782                                                   connector_object_id,
 783                                                   &hpd,
 784                                                   &router);
 785
 786                 }
 787         }
 788
 789         radeon_link_encoder_connector(dev);
 790
 791         return true;
 792 }
 793
 794 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 795                                                  int connector_type,
 796                                                  uint16_t devices)
 797 {
 798         struct radeon_device *rdev = dev->dev_private;
 799
 800         if (rdev->flags & RADEON_IS_IGP) {
 801                 return supported_devices_connector_object_id_convert
 802                         [connector_type];
 803         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 804                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 805                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 806                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 807                 struct atom_context *ctx = mode_info->atom_context;
 808                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 809                 uint16_t size, data_offset;
 810                 uint8_t frev, crev;
 811                 ATOM_XTMDS_INFO *xtmds;
 812
 813                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 814                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 815
 816                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 817                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 818                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 819                                 else
 820                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 821                         } else {
 822                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 823                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 824                                 else
 825                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 826                         }
 827                 } else
 828                         return supported_devices_connector_object_id_convert
 829                                 [connector_type];
 830         } else {
 831                 return supported_devices_connector_object_id_convert
 832                         [connector_type];
 833         }
 834 }
 835
 836 struct bios_connector {
 837         bool valid;
 838         uint16_t line_mux;
 839         uint16_t devices;
 840         int connector_type;
 841         struct radeon_i2c_bus_rec ddc_bus;
 842         struct radeon_hpd hpd;
 843 };
 844
 845 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 846                                                                  drm_device
 847                                                                  *dev)
 848 {
 849         struct radeon_device *rdev = dev->dev_private;
 850         struct radeon_mode_info *mode_info = &rdev->mode_info;
 851         struct atom_context *ctx = mode_info->atom_context;
 852         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 853         uint16_t size, data_offset;
 854         uint8_t frev, crev;
 855         uint16_t device_support;
 856         uint8_t dac;
 857         union atom_supported_devices *supported_devices;
 858         int i, j, max_device;
 859         struct bios_connector *bios_connectors;
 860         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 861         struct radeon_router router;
 862
 863         router.valid = false;
 864
 865         bios_connectors = kzalloc(bc_size, GFP_KERNEL);
 866         if (!bios_connectors)
 867                 return false;
 868
 869         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 870                                     &data_offset)) {
 871                 kfree(bios_connectors);
 872                 return false;
 873         }
 874
 875         supported_devices =
 876             (union atom_supported_devices *)(ctx->bios + data_offset);
 877
 878         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 879
 880         if (frev > 1)
 881                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 882         else
 883                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 884
 885         for (i = 0; i < max_device; i++) {
 886                 ATOM_CONNECTOR_INFO_I2C ci =
 887                     supported_devices->info.asConnInfo[i];
 888
 889                 bios_connectors[i].valid = false;
 890
 891                 if (!(device_support & (1 << i))) {
 892                         continue;
 893                 }
 894
 895                 if (i == ATOM_DEVICE_CV_INDEX) {
 896                         DRM_DEBUG_KMS("Skipping Component Video\n");
 897                         continue;
 898                 }
 899
 900                 bios_connectors[i].connector_type =
 901                     supported_devices_connector_convert[ci.sucConnectorInfo.
 902                                                         sbfAccess.
 903                                                         bfConnectorType];
 904
 905                 if (bios_connectors[i].connector_type ==
 906                     DRM_MODE_CONNECTOR_Unknown)
 907                         continue;
 908
 909                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 910
 911                 bios_connectors[i].line_mux =
 912                         ci.sucI2cId.ucAccess;
 913
 914                 /* give tv unique connector ids */
 915                 if (i == ATOM_DEVICE_TV1_INDEX) {
 916                         bios_connectors[i].ddc_bus.valid = false;
 917                         bios_connectors[i].line_mux = 50;
 918                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 919                         bios_connectors[i].ddc_bus.valid = false;
 920                         bios_connectors[i].line_mux = 51;
 921                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 922                         bios_connectors[i].ddc_bus.valid = false;
 923                         bios_connectors[i].line_mux = 52;
 924                 } else
 925                         bios_connectors[i].ddc_bus =
 926                             radeon_lookup_i2c_gpio(rdev,
 927                                                    bios_connectors[i].line_mux);
 928
 929                 if ((crev > 1) && (frev > 1)) {
 930                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 931                         switch (isb) {
 932                         case 0x4:
 933                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 934                                 break;
 935                         case 0xa:
 936                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 937                                 break;
 938                         default:
 939                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 940                                 break;
 941                         }
 942                 } else {
 943                         if (i == ATOM_DEVICE_DFP1_INDEX)
 944                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 945                         else if (i == ATOM_DEVICE_DFP2_INDEX)
 946                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 947                         else
 948                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 949                 }
 950
 951                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 952                  * shared with a DVI port, we'll pick up the DVI connector when we
 953                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 954                  */
 955                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 956                         bios_connectors[i].connector_type =
 957                             DRM_MODE_CONNECTOR_VGA;
 958
 959                 if (!radeon_atom_apply_quirks
 960                     (dev, (1 << i), &bios_connectors[i].connector_type,
 961                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
 962                      &bios_connectors[i].hpd))
 963                         continue;
 964
 965                 bios_connectors[i].valid = true;
 966                 bios_connectors[i].devices = (1 << i);
 967
 968                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
 969                         radeon_add_atom_encoder(dev,
 970                                                 radeon_get_encoder_enum(dev,
 971                                                                       (1 << i),
 972                                                                       dac),
 973                                                 (1 << i));
 974                 else
 975                         radeon_add_legacy_encoder(dev,
 976                                                   radeon_get_encoder_enum(dev,
 977                                                                         (1 << i),
 978                                                                         dac),
 979                                                   (1 << i));
 980         }
 981
 982         /* combine shared connectors */
 983         for (i = 0; i < max_device; i++) {
 984                 if (bios_connectors[i].valid) {
 985                         for (j = 0; j < max_device; j++) {
 986                                 if (bios_connectors[j].valid && (i != j)) {
 987                                         if (bios_connectors[i].line_mux ==
 988                                             bios_connectors[j].line_mux) {
 989                                                 /* make sure not to combine LVDS */
 990                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 991                                                         bios_connectors[i].line_mux = 53;
 992                                                         bios_connectors[i].ddc_bus.valid = false;
 993                                                         continue;
 994                                                 }
 995                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 996                                                         bios_connectors[j].line_mux = 53;
 997                                                         bios_connectors[j].ddc_bus.valid = false;
 998                                                         continue;
 999                                                 }
1000                                                 /* combine analog and digital for DVI-I */
1001                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1002                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1003                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1004                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1005                                                         bios_connectors[i].devices |=
1006                                                                 bios_connectors[j].devices;
1007                                                         bios_connectors[i].connector_type =
1008                                                                 DRM_MODE_CONNECTOR_DVII;
1009                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1010                                                                 bios_connectors[i].hpd =
1011                                                                         bios_connectors[j].hpd;
1012                                                         bios_connectors[j].valid = false;
1013                                                 }
1014                                         }
1015                                 }
1016                         }
1017                 }
1018         }
1019
1020         /* add the connectors */
1021         for (i = 0; i < max_device; i++) {
1022                 if (bios_connectors[i].valid) {
1023                         uint16_t connector_object_id =
1024                                 atombios_get_connector_object_id(dev,
1025                                                       bios_connectors[i].connector_type,
1026                                                       bios_connectors[i].devices);
1027                         radeon_add_atom_connector(dev,
1028                                                   bios_connectors[i].line_mux,
1029                                                   bios_connectors[i].devices,
1030                                                   bios_connectors[i].
1031                                                   connector_type,
1032                                                   &bios_connectors[i].ddc_bus,
1033                                                   0,
1034                                                   connector_object_id,
1035                                                   &bios_connectors[i].hpd,
1036                                                   &router);
1037                 }
1038         }
1039
1040         radeon_link_encoder_connector(dev);
1041
1042         kfree(bios_connectors);
1043         return true;
1044 }
1045
1046 union firmware_info {
1047         ATOM_FIRMWARE_INFO info;
1048         ATOM_FIRMWARE_INFO_V1_2 info_12;
1049         ATOM_FIRMWARE_INFO_V1_3 info_13;
1050         ATOM_FIRMWARE_INFO_V1_4 info_14;
1051         ATOM_FIRMWARE_INFO_V2_1 info_21;
1052 };
1053
1054 bool radeon_atom_get_clock_info(struct drm_device *dev)
1055 {
1056         struct radeon_device *rdev = dev->dev_private;
1057         struct radeon_mode_info *mode_info = &rdev->mode_info;
1058         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1059         union firmware_info *firmware_info;
1060         uint8_t frev, crev;
1061         struct radeon_pll *p1pll = &rdev->clock.p1pll;
1062         struct radeon_pll *p2pll = &rdev->clock.p2pll;
1063         struct radeon_pll *dcpll = &rdev->clock.dcpll;
1064         struct radeon_pll *spll = &rdev->clock.spll;
1065         struct radeon_pll *mpll = &rdev->clock.mpll;
1066         uint16_t data_offset;
1067
1068         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1069                                    &frev, &crev, &data_offset)) {
1070                 firmware_info =
1071                         (union firmware_info *)(mode_info->atom_context->bios +
1072                                                 data_offset);
1073                 /* pixel clocks */
1074                 p1pll->reference_freq =
1075                     le16_to_cpu(firmware_info->info.usReferenceClock);
1076                 p1pll->reference_div = 0;
1077
1078                 if (crev < 2)
1079                         p1pll->pll_out_min =
1080                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1081                 else
1082                         p1pll->pll_out_min =
1083                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1084                 p1pll->pll_out_max =
1085                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1086
1087                 if (crev >= 4) {
1088                         p1pll->lcd_pll_out_min =
1089                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1090                         if (p1pll->lcd_pll_out_min == 0)
1091                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1092                         p1pll->lcd_pll_out_max =
1093                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1094                         if (p1pll->lcd_pll_out_max == 0)
1095                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1096                 } else {
1097                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1098                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1099                 }
1100
1101                 if (p1pll->pll_out_min == 0) {
1102                         if (ASIC_IS_AVIVO(rdev))
1103                                 p1pll->pll_out_min = 64800;
1104                         else
1105                                 p1pll->pll_out_min = 20000;
1106                 } else if (p1pll->pll_out_min > 64800) {
1107                         /* Limiting the pll output range is a good thing generally as
1108                          * it limits the number of possible pll combinations for a given
1109                          * frequency presumably to the ones that work best on each card.
1110                          * However, certain duallink DVI monitors seem to like
1111                          * pll combinations that would be limited by this at least on
1112                          * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per
1113                          * family.
1114                          */
1115                         p1pll->pll_out_min = 64800;
1116                 }
1117
1118                 p1pll->pll_in_min =
1119                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1120                 p1pll->pll_in_max =
1121                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1122
1123                 *p2pll = *p1pll;
1124
1125                 /* system clock */
1126                 spll->reference_freq =
1127                     le16_to_cpu(firmware_info->info.usReferenceClock);
1128                 spll->reference_div = 0;
1129
1130                 spll->pll_out_min =
1131                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1132                 spll->pll_out_max =
1133                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1134
1135                 /* ??? */
1136                 if (spll->pll_out_min == 0) {
1137                         if (ASIC_IS_AVIVO(rdev))
1138                                 spll->pll_out_min = 64800;
1139                         else
1140                                 spll->pll_out_min = 20000;
1141                 }
1142
1143                 spll->pll_in_min =
1144                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1145                 spll->pll_in_max =
1146                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1147
1148                 /* memory clock */
1149                 mpll->reference_freq =
1150                     le16_to_cpu(firmware_info->info.usReferenceClock);
1151                 mpll->reference_div = 0;
1152
1153                 mpll->pll_out_min =
1154                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1155                 mpll->pll_out_max =
1156                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1157
1158                 /* ??? */
1159                 if (mpll->pll_out_min == 0) {
1160                         if (ASIC_IS_AVIVO(rdev))
1161                                 mpll->pll_out_min = 64800;
1162                         else
1163                                 mpll->pll_out_min = 20000;
1164                 }
1165
1166                 mpll->pll_in_min =
1167                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1168                 mpll->pll_in_max =
1169                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1170
1171                 rdev->clock.default_sclk =
1172                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1173                 rdev->clock.default_mclk =
1174                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1175
1176                 if (ASIC_IS_DCE4(rdev)) {
1177                         rdev->clock.default_dispclk =
1178                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1179                         if (rdev->clock.default_dispclk == 0)
1180                                 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1181                         rdev->clock.dp_extclk =
1182                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1183                 }
1184                 *dcpll = *p1pll;
1185
1186                 return true;
1187         }
1188
1189         return false;
1190 }
1191
1192 union igp_info {
1193         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1194         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1195 };
1196
1197 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1198 {
1199         struct radeon_mode_info *mode_info = &rdev->mode_info;
1200         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1201         union igp_info *igp_info;
1202         u8 frev, crev;
1203         u16 data_offset;
1204
1205         /* sideport is AMD only */
1206         if (rdev->family == CHIP_RS600)
1207                 return false;
1208
1209         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1210                                    &frev, &crev, &data_offset)) {
1211                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1212                                       data_offset);
1213                 switch (crev) {
1214                 case 1:
1215                         if (igp_info->info.ulBootUpMemoryClock)
1216                                 return true;
1217                         break;
1218                 case 2:
1219                         if (igp_info->info_2.ulBootUpSidePortClock)
1220                                 return true;
1221                         break;
1222                 default:
1223                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1224                         break;
1225                 }
1226         }
1227         return false;
1228 }
1229
1230 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1231                                    struct radeon_encoder_int_tmds *tmds)
1232 {
1233         struct drm_device *dev = encoder->base.dev;
1234         struct radeon_device *rdev = dev->dev_private;
1235         struct radeon_mode_info *mode_info = &rdev->mode_info;
1236         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1237         uint16_t data_offset;
1238         struct _ATOM_TMDS_INFO *tmds_info;
1239         uint8_t frev, crev;
1240         uint16_t maxfreq;
1241         int i;
1242
1243         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1244                                    &frev, &crev, &data_offset)) {
1245                 tmds_info =
1246                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1247                                                    data_offset);
1248
1249                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1250                 for (i = 0; i < 4; i++) {
1251                         tmds->tmds_pll[i].freq =
1252                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1253                         tmds->tmds_pll[i].value =
1254                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1255                         tmds->tmds_pll[i].value |=
1256                             (tmds_info->asMiscInfo[i].
1257                              ucPLL_VCO_Gain & 0x3f) << 6;
1258                         tmds->tmds_pll[i].value |=
1259                             (tmds_info->asMiscInfo[i].
1260                              ucPLL_DutyCycle & 0xf) << 12;
1261                         tmds->tmds_pll[i].value |=
1262                             (tmds_info->asMiscInfo[i].
1263                              ucPLL_VoltageSwing & 0xf) << 16;
1264
1265                         DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1266                                   tmds->tmds_pll[i].freq,
1267                                   tmds->tmds_pll[i].value);
1268
1269                         if (maxfreq == tmds->tmds_pll[i].freq) {
1270                                 tmds->tmds_pll[i].freq = 0xffffffff;
1271                                 break;
1272                         }
1273                 }
1274                 return true;
1275         }
1276         return false;
1277 }
1278
1279 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1280                                       struct radeon_atom_ss *ss,
1281                                       int id)
1282 {
1283         struct radeon_mode_info *mode_info = &rdev->mode_info;
1284         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1285         uint16_t data_offset, size;
1286         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1287         uint8_t frev, crev;
1288         int i, num_indices;
1289
1290         memset(ss, 0, sizeof(struct radeon_atom_ss));
1291         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1292                                    &frev, &crev, &data_offset)) {
1293                 ss_info =
1294                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1295
1296                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1297                         sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1298
1299                 for (i = 0; i < num_indices; i++) {
1300                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1301                                 ss->percentage =
1302                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1303                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1304                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1305                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1306                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1307                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1308                                 return true;
1309                         }
1310                 }
1311         }
1312         return false;
1313 }
1314
1315 union asic_ss_info {
1316         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1317         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1318         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1319 };
1320
1321 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1322                                       struct radeon_atom_ss *ss,
1323                                       int id, u32 clock)
1324 {
1325         struct radeon_mode_info *mode_info = &rdev->mode_info;
1326         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1327         uint16_t data_offset, size;
1328         union asic_ss_info *ss_info;
1329         uint8_t frev, crev;
1330         int i, num_indices;
1331
1332         memset(ss, 0, sizeof(struct radeon_atom_ss));
1333         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1334                                    &frev, &crev, &data_offset)) {
1335
1336                 ss_info =
1337                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1338
1339                 switch (frev) {
1340                 case 1:
1341                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1342                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1343
1344                         for (i = 0; i < num_indices; i++) {
1345                                 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1346                                     (clock <= ss_info->info.asSpreadSpectrum[i].ulTargetClockRange)) {
1347                                         ss->percentage =
1348                                                 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1349                                         ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1350                                         ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1351                                         return true;
1352                                 }
1353                         }
1354                         break;
1355                 case 2:
1356                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1357                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1358                         for (i = 0; i < num_indices; i++) {
1359                                 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1360                                     (clock <= ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange)) {
1361                                         ss->percentage =
1362                                                 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1363                                         ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1364                                         ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1365                                         return true;
1366                                 }
1367                         }
1368                         break;
1369                 case 3:
1370                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1371                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1372                         for (i = 0; i < num_indices; i++) {
1373                                 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1374                                     (clock <= ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange)) {
1375                                         ss->percentage =
1376                                                 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1377                                         ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1378                                         ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1379                                         return true;
1380                                 }
1381                         }
1382                         break;
1383                 default:
1384                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1385                         break;
1386                 }
1387
1388         }
1389         return false;
1390 }
1391
1392 union lvds_info {
1393         struct _ATOM_LVDS_INFO info;
1394         struct _ATOM_LVDS_INFO_V12 info_12;
1395 };
1396
1397 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1398                                                               radeon_encoder
1399                                                               *encoder)
1400 {
1401         struct drm_device *dev = encoder->base.dev;
1402         struct radeon_device *rdev = dev->dev_private;
1403         struct radeon_mode_info *mode_info = &rdev->mode_info;
1404         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1405         uint16_t data_offset, misc;
1406         union lvds_info *lvds_info;
1407         uint8_t frev, crev;
1408         struct radeon_encoder_atom_dig *lvds = NULL;
1409         int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1410
1411         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1412                                    &frev, &crev, &data_offset)) {
1413                 lvds_info =
1414                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1415                 lvds =
1416                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1417
1418                 if (!lvds)
1419                         return NULL;
1420
1421                 lvds->native_mode.clock =
1422                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1423                 lvds->native_mode.hdisplay =
1424                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1425                 lvds->native_mode.vdisplay =
1426                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1427                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1428                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1429                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1430                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1431                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1432                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1433                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1434                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1435                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1436                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1437                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1438                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1439                 lvds->panel_pwr_delay =
1440                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1441                 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1442
1443                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1444                 if (misc & ATOM_VSYNC_POLARITY)
1445                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1446                 if (misc & ATOM_HSYNC_POLARITY)
1447                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1448                 if (misc & ATOM_COMPOSITESYNC)
1449                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1450                 if (misc & ATOM_INTERLACE)
1451                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1452                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1453                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1454
1455                 /* set crtc values */
1456                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1457
1458                 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1459
1460                 encoder->native_mode = lvds->native_mode;
1461
1462                 if (encoder_enum == 2)
1463                         lvds->linkb = true;
1464                 else
1465                         lvds->linkb = false;
1466
1467         }
1468         return lvds;
1469 }
1470
1471 struct radeon_encoder_primary_dac *
1472 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1473 {
1474         struct drm_device *dev = encoder->base.dev;
1475         struct radeon_device *rdev = dev->dev_private;
1476         struct radeon_mode_info *mode_info = &rdev->mode_info;
1477         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1478         uint16_t data_offset;
1479         struct _COMPASSIONATE_DATA *dac_info;
1480         uint8_t frev, crev;
1481         uint8_t bg, dac;
1482         struct radeon_encoder_primary_dac *p_dac = NULL;
1483
1484         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1485                                    &frev, &crev, &data_offset)) {
1486                 dac_info = (struct _COMPASSIONATE_DATA *)
1487                         (mode_info->atom_context->bios + data_offset);
1488
1489                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1490
1491                 if (!p_dac)
1492                         return NULL;
1493
1494                 bg = dac_info->ucDAC1_BG_Adjustment;
1495                 dac = dac_info->ucDAC1_DAC_Adjustment;
1496                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1497
1498         }
1499         return p_dac;
1500 }
1501
1502 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1503                                 struct drm_display_mode *mode)
1504 {
1505         struct radeon_mode_info *mode_info = &rdev->mode_info;
1506         ATOM_ANALOG_TV_INFO *tv_info;
1507         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1508         ATOM_DTD_FORMAT *dtd_timings;
1509         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1510         u8 frev, crev;
1511         u16 data_offset, misc;
1512
1513         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1514                                     &frev, &crev, &data_offset))
1515                 return false;
1516
1517         switch (crev) {
1518         case 1:
1519                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1520                 if (index >= MAX_SUPPORTED_TV_TIMING)
1521                         return false;
1522
1523                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1524                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1525                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1526                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1527                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1528
1529                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1530                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1531                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1532                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1533                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1534
1535                 mode->flags = 0;
1536                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1537                 if (misc & ATOM_VSYNC_POLARITY)
1538                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1539                 if (misc & ATOM_HSYNC_POLARITY)
1540                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1541                 if (misc & ATOM_COMPOSITESYNC)
1542                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1543                 if (misc & ATOM_INTERLACE)
1544                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1545                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1546                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1547
1548                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1549
1550                 if (index == 1) {
1551                         /* PAL timings appear to have wrong values for totals */
1552                         mode->crtc_htotal -= 1;
1553                         mode->crtc_vtotal -= 1;
1554                 }
1555                 break;
1556         case 2:
1557                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1558                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1559                         return false;
1560
1561                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1562                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1563                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1564                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1565                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1566                         le16_to_cpu(dtd_timings->usHSyncOffset);
1567                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1568                         le16_to_cpu(dtd_timings->usHSyncWidth);
1569
1570                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1571                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1572                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1573                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1574                         le16_to_cpu(dtd_timings->usVSyncOffset);
1575                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1576                         le16_to_cpu(dtd_timings->usVSyncWidth);
1577
1578                 mode->flags = 0;
1579                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1580                 if (misc & ATOM_VSYNC_POLARITY)
1581                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1582                 if (misc & ATOM_HSYNC_POLARITY)
1583                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1584                 if (misc & ATOM_COMPOSITESYNC)
1585                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1586                 if (misc & ATOM_INTERLACE)
1587                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1588                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1589                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1590
1591                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1592                 break;
1593         }
1594         return true;
1595 }
1596
1597 enum radeon_tv_std
1598 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1599 {
1600         struct radeon_mode_info *mode_info = &rdev->mode_info;
1601         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1602         uint16_t data_offset;
1603         uint8_t frev, crev;
1604         struct _ATOM_ANALOG_TV_INFO *tv_info;
1605         enum radeon_tv_std tv_std = TV_STD_NTSC;
1606
1607         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1608                                    &frev, &crev, &data_offset)) {
1609
1610                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1611                         (mode_info->atom_context->bios + data_offset);
1612
1613                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1614                 case ATOM_TV_NTSC:
1615                         tv_std = TV_STD_NTSC;
1616                         DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1617                         break;
1618                 case ATOM_TV_NTSCJ:
1619                         tv_std = TV_STD_NTSC_J;
1620                         DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1621                         break;
1622                 case ATOM_TV_PAL:
1623                         tv_std = TV_STD_PAL;
1624                         DRM_DEBUG_KMS("Default TV standard: PAL\n");
1625                         break;
1626                 case ATOM_TV_PALM:
1627                         tv_std = TV_STD_PAL_M;
1628                         DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1629                         break;
1630                 case ATOM_TV_PALN:
1631                         tv_std = TV_STD_PAL_N;
1632                         DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1633                         break;
1634                 case ATOM_TV_PALCN:
1635                         tv_std = TV_STD_PAL_CN;
1636                         DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1637                         break;
1638                 case ATOM_TV_PAL60:
1639                         tv_std = TV_STD_PAL_60;
1640                         DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1641                         break;
1642                 case ATOM_TV_SECAM:
1643                         tv_std = TV_STD_SECAM;
1644                         DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1645                         break;
1646                 default:
1647                         tv_std = TV_STD_NTSC;
1648                         DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1649                         break;
1650                 }
1651         }
1652         return tv_std;
1653 }
1654
1655 struct radeon_encoder_tv_dac *
1656 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1657 {
1658         struct drm_device *dev = encoder->base.dev;
1659         struct radeon_device *rdev = dev->dev_private;
1660         struct radeon_mode_info *mode_info = &rdev->mode_info;
1661         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1662         uint16_t data_offset;
1663         struct _COMPASSIONATE_DATA *dac_info;
1664         uint8_t frev, crev;
1665         uint8_t bg, dac;
1666         struct radeon_encoder_tv_dac *tv_dac = NULL;
1667
1668         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1669                                    &frev, &crev, &data_offset)) {
1670
1671                 dac_info = (struct _COMPASSIONATE_DATA *)
1672                         (mode_info->atom_context->bios + data_offset);
1673
1674                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1675
1676                 if (!tv_dac)
1677                         return NULL;
1678
1679                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1680                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1681                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1682
1683                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1684                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1685                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1686
1687                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1688                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1689                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1690
1691                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1692         }
1693         return tv_dac;
1694 }
1695
1696 static const char *thermal_controller_names[] = {
1697         "NONE",
1698         "lm63",
1699         "adm1032",
1700         "adm1030",
1701         "max6649",
1702         "lm64",
1703         "f75375",
1704         "asc7xxx",
1705 };
1706
1707 static const char *pp_lib_thermal_controller_names[] = {
1708         "NONE",
1709         "lm63",
1710         "adm1032",
1711         "adm1030",
1712         "max6649",
1713         "lm64",
1714         "f75375",
1715         "RV6xx",
1716         "RV770",
1717         "adt7473",
1718         "External GPIO",
1719         "Evergreen",
1720         "adt7473 with internal",
1721
1722 };
1723
1724 union power_info {
1725         struct _ATOM_POWERPLAY_INFO info;
1726         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1727         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1728         struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1729 };
1730
1731 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1732 {
1733         struct radeon_mode_info *mode_info = &rdev->mode_info;
1734         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1735         u16 data_offset;
1736         u8 frev, crev;
1737         u32 misc, misc2 = 0, sclk, mclk;
1738         union power_info *power_info;
1739         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1740         struct _ATOM_PPLIB_STATE *power_state;
1741         int num_modes = 0, i, j;
1742         int state_index = 0, mode_index = 0;
1743         struct radeon_i2c_bus_rec i2c_bus;
1744
1745         rdev->pm.default_power_state_index = -1;
1746
1747         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1748                                    &frev, &crev, &data_offset)) {
1749                 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1750                 if (frev < 4) {
1751                         /* add the i2c bus for thermal/fan chip */
1752                         if (power_info->info.ucOverdriveThermalController > 0) {
1753                                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1754                                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
1755                                          power_info->info.ucOverdriveControllerAddress >> 1);
1756                                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1757                                 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1758                                 if (rdev->pm.i2c_bus) {
1759                                         struct i2c_board_info info = { };
1760                                         const char *name = thermal_controller_names[power_info->info.
1761                                                                                     ucOverdriveThermalController];
1762                                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1763                                         strlcpy(info.type, name, sizeof(info.type));
1764                                         i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1765                                 }
1766                         }
1767                         num_modes = power_info->info.ucNumOfPowerModeEntries;
1768                         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1769                                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1770                         /* last mode is usually default, array is low to high */
1771                         for (i = 0; i < num_modes; i++) {
1772                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1773                                 switch (frev) {
1774                                 case 1:
1775                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1776                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1777                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1778                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1779                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1780                                         /* skip invalid modes */
1781                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1782                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1783                                                 continue;
1784                                         rdev->pm.power_state[state_index].pcie_lanes =
1785                                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1786                                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1787                                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1788                                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1789                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1790                                                         VOLTAGE_GPIO;
1791                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1792                                                         radeon_lookup_gpio(rdev,
1793                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1794                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1795                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1796                                                                 true;
1797                                                 else
1798                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1799                                                                 false;
1800                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1801                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1802                                                         VOLTAGE_VDDC;
1803                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1804                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1805                                         }
1806                                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1807                                         rdev->pm.power_state[state_index].misc = misc;
1808                                         /* order matters! */
1809                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1810                                                 rdev->pm.power_state[state_index].type =
1811                                                         POWER_STATE_TYPE_POWERSAVE;
1812                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1813                                                 rdev->pm.power_state[state_index].type =
1814                                                         POWER_STATE_TYPE_BATTERY;
1815                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1816                                                 rdev->pm.power_state[state_index].type =
1817                                                         POWER_STATE_TYPE_BATTERY;
1818                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1819                                                 rdev->pm.power_state[state_index].type =
1820                                                         POWER_STATE_TYPE_BALANCED;
1821                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1822                                                 rdev->pm.power_state[state_index].type =
1823                                                         POWER_STATE_TYPE_PERFORMANCE;
1824                                                 rdev->pm.power_state[state_index].flags &=
1825                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1826                                         }
1827                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1828                                                 rdev->pm.power_state[state_index].type =
1829                                                         POWER_STATE_TYPE_DEFAULT;
1830                                                 rdev->pm.default_power_state_index = state_index;
1831                                                 rdev->pm.power_state[state_index].default_clock_mode =
1832                                                         &rdev->pm.power_state[state_index].clock_info[0];
1833                                                 rdev->pm.power_state[state_index].flags &=
1834                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1835                                         } else if (state_index == 0) {
1836                                                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1837                                                         RADEON_PM_MODE_NO_DISPLAY;
1838                                         }
1839                                         state_index++;
1840                                         break;
1841                                 case 2:
1842                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1843                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1844                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1845                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1846                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1847                                         /* skip invalid modes */
1848                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1849                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1850                                                 continue;
1851                                         rdev->pm.power_state[state_index].pcie_lanes =
1852                                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1853                                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1854                                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1855                                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1856                                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1857                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1858                                                         VOLTAGE_GPIO;
1859                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1860                                                         radeon_lookup_gpio(rdev,
1861                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1862                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1863                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1864                                                                 true;
1865                                                 else
1866                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1867                                                                 false;
1868                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1869                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1870                                                         VOLTAGE_VDDC;
1871                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1872                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1873                                         }
1874                                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1875                                         rdev->pm.power_state[state_index].misc = misc;
1876                                         rdev->pm.power_state[state_index].misc2 = misc2;
1877                                         /* order matters! */
1878                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1879                                                 rdev->pm.power_state[state_index].type =
1880                                                         POWER_STATE_TYPE_POWERSAVE;
1881                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1882                                                 rdev->pm.power_state[state_index].type =
1883                                                         POWER_STATE_TYPE_BATTERY;
1884                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1885                                                 rdev->pm.power_state[state_index].type =
1886                                                         POWER_STATE_TYPE_BATTERY;
1887                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1888                                                 rdev->pm.power_state[state_index].type =
1889                                                         POWER_STATE_TYPE_BALANCED;
1890                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1891                                                 rdev->pm.power_state[state_index].type =
1892                                                         POWER_STATE_TYPE_PERFORMANCE;
1893                                                 rdev->pm.power_state[state_index].flags &=
1894                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1895                                         }
1896                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1897                                                 rdev->pm.power_state[state_index].type =
1898                                                         POWER_STATE_TYPE_BALANCED;
1899                                         if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1900                                                 rdev->pm.power_state[state_index].flags &=
1901                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1902                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1903                                                 rdev->pm.power_state[state_index].type =
1904                                                         POWER_STATE_TYPE_DEFAULT;
1905                                                 rdev->pm.default_power_state_index = state_index;
1906                                                 rdev->pm.power_state[state_index].default_clock_mode =
1907                                                         &rdev->pm.power_state[state_index].clock_info[0];
1908                                                 rdev->pm.power_state[state_index].flags &=
1909                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1910                                         } else if (state_index == 0) {
1911                                                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1912                                                         RADEON_PM_MODE_NO_DISPLAY;
1913                                         }
1914                                         state_index++;
1915                                         break;
1916                                 case 3:
1917                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1918                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1919                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1920                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1921                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1922                                         /* skip invalid modes */
1923                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1924                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1925                                                 continue;
1926                                         rdev->pm.power_state[state_index].pcie_lanes =
1927                                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1928                                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1929                                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1930                                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1931                                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1932                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1933                                                         VOLTAGE_GPIO;
1934                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1935                                                         radeon_lookup_gpio(rdev,
1936                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1937                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1938                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1939                                                                 true;
1940                                                 else
1941                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1942                                                                 false;
1943                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1944                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1945                                                         VOLTAGE_VDDC;
1946                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1947                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1948                                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1949                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1950                                                                 true;
1951                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1952                                                         power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1953                                                 }
1954                                         }
1955                                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1956                                         rdev->pm.power_state[state_index].misc = misc;
1957                                         rdev->pm.power_state[state_index].misc2 = misc2;
1958                                         /* order matters! */
1959                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1960                                                 rdev->pm.power_state[state_index].type =
1961                                                         POWER_STATE_TYPE_POWERSAVE;
1962                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1963                                                 rdev->pm.power_state[state_index].type =
1964                                                         POWER_STATE_TYPE_BATTERY;
1965                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1966                                                 rdev->pm.power_state[state_index].type =
1967                                                         POWER_STATE_TYPE_BATTERY;
1968                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1969                                                 rdev->pm.power_state[state_index].type =
1970                                                         POWER_STATE_TYPE_BALANCED;
1971                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1972                                                 rdev->pm.power_state[state_index].type =
1973                                                         POWER_STATE_TYPE_PERFORMANCE;
1974                                                 rdev->pm.power_state[state_index].flags &=
1975                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1976                                         }
1977                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1978                                                 rdev->pm.power_state[state_index].type =
1979                                                         POWER_STATE_TYPE_BALANCED;
1980                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1981                                                 rdev->pm.power_state[state_index].type =
1982                                                         POWER_STATE_TYPE_DEFAULT;
1983                                                 rdev->pm.default_power_state_index = state_index;
1984                                                 rdev->pm.power_state[state_index].default_clock_mode =
1985                                                         &rdev->pm.power_state[state_index].clock_info[0];
1986                                         } else if (state_index == 0) {
1987                                                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1988                                                         RADEON_PM_MODE_NO_DISPLAY;
1989                                         }
1990                                         state_index++;
1991                                         break;
1992                                 }
1993                         }
1994                         /* last mode is usually default */
1995                         if (rdev->pm.default_power_state_index == -1) {
1996                                 rdev->pm.power_state[state_index - 1].type =
1997                                         POWER_STATE_TYPE_DEFAULT;
1998                                 rdev->pm.default_power_state_index = state_index - 1;
1999                                 rdev->pm.power_state[state_index - 1].default_clock_mode =
2000                                         &rdev->pm.power_state[state_index - 1].clock_info[0];
2001                                 rdev->pm.power_state[state_index].flags &=
2002                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2003                                 rdev->pm.power_state[state_index].misc = 0;
2004                                 rdev->pm.power_state[state_index].misc2 = 0;
2005                         }
2006                 } else {
2007                         int fw_index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2008                         uint8_t fw_frev, fw_crev;
2009                         uint16_t fw_data_offset, vddc = 0;
2010                         union firmware_info *firmware_info;
2011                         ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController;
2012
2013                         if (atom_parse_data_header(mode_info->atom_context, fw_index, NULL,
2014                                                    &fw_frev, &fw_crev, &fw_data_offset)) {
2015                                 firmware_info =
2016                                         (union firmware_info *)(mode_info->atom_context->bios +
2017                                                                 fw_data_offset);
2018                                 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
2019                         }
2020
2021                         /* add the i2c bus for thermal/fan chip */
2022                         if (controller->ucType > 0) {
2023                                 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2024                                         DRM_INFO("Internal thermal controller %s fan control\n",
2025                                                  (controller->ucFanParameters &
2026                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2027                                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2028                                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2029                                         DRM_INFO("Internal thermal controller %s fan control\n",
2030                                                  (controller->ucFanParameters &
2031                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2032                                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2033                                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2034                                         DRM_INFO("Internal thermal controller %s fan control\n",
2035                                                  (controller->ucFanParameters &
2036                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2037                                         rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2038                                 } else if ((controller->ucType ==
2039                                             ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2040                                            (controller->ucType ==
2041                                             ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
2042                                         DRM_INFO("Special thermal controller config\n");
2043                                 } else {
2044                                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2045                                                  pp_lib_thermal_controller_names[controller->ucType],
2046                                                  controller->ucI2cAddress >> 1,
2047                                                  (controller->ucFanParameters &
2048                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2049                                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2050                                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2051                                         if (rdev->pm.i2c_bus) {
2052                                                 struct i2c_board_info info = { };
2053                                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2054                                                 info.addr = controller->ucI2cAddress >> 1;
2055                                                 strlcpy(info.type, name, sizeof(info.type));
2056                                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2057                                         }
2058
2059                                 }
2060                         }
2061                         /* first mode is usually default, followed by low to high */
2062                         for (i = 0; i < power_info->info_4.ucNumStates; i++) {
2063                                 mode_index = 0;
2064                                 power_state = (struct _ATOM_PPLIB_STATE *)
2065                                         (mode_info->atom_context->bios +
2066                                          data_offset +
2067                                          le16_to_cpu(power_info->info_4.usStateArrayOffset) +
2068                                          i * power_info->info_4.ucStateEntrySize);
2069                                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2070                                         (mode_info->atom_context->bios +
2071                                          data_offset +
2072                                          le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
2073                                          (power_state->ucNonClockStateIndex *
2074                                           power_info->info_4.ucNonClockSize));
2075                                 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
2076                                         if (rdev->flags & RADEON_IS_IGP) {
2077                                                 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
2078                                                         (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
2079                                                         (mode_info->atom_context->bios +
2080                                                          data_offset +
2081                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2082                                                          (power_state->ucClockStateIndices[j] *
2083                                                           power_info->info_4.ucClockInfoSize));
2084                                                 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
2085                                                 sclk |= clock_info->ucLowEngineClockHigh << 16;
2086                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2087                                                 /* skip invalid modes */
2088                                                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2089                                                         continue;
2090                                                 /* voltage works differently on IGPs */
2091                                                 mode_index++;
2092                                         } else if (ASIC_IS_DCE4(rdev)) {
2093                                                 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
2094                                                         (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
2095                                                         (mode_info->atom_context->bios +
2096                                                          data_offset +
2097                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2098                                                          (power_state->ucClockStateIndices[j] *
2099                                                           power_info->info_4.ucClockInfoSize));
2100                                                 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2101                                                 sclk |= clock_info->ucEngineClockHigh << 16;
2102                                                 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2103                                                 mclk |= clock_info->ucMemoryClockHigh << 16;
2104                                                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2105                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2106                                                 /* skip invalid modes */
2107                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2108                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2109                                                         continue;
2110                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2111                                                         VOLTAGE_SW;
2112                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2113                                                         clock_info->usVDDC;
2114                                                 /* XXX usVDDCI */
2115                                                 mode_index++;
2116                                         } else {
2117                                                 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
2118                                                         (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
2119                                                         (mode_info->atom_context->bios +
2120                                                          data_offset +
2121                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2122                                                          (power_state->ucClockStateIndices[j] *
2123                                                           power_info->info_4.ucClockInfoSize));
2124                                                 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2125                                                 sclk |= clock_info->ucEngineClockHigh << 16;
2126                                                 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2127                                                 mclk |= clock_info->ucMemoryClockHigh << 16;
2128                                                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2129                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2130                                                 /* skip invalid modes */
2131                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2132                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2133                                                         continue;
2134                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2135                                                         VOLTAGE_SW;
2136                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2137                                                         clock_info->usVDDC;
2138                                                 mode_index++;
2139                                         }
2140                                 }
2141                                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2142                                 if (mode_index) {
2143                                         misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2144                                         misc2 = le16_to_cpu(non_clock_info->usClassification);
2145                                         rdev->pm.power_state[state_index].misc = misc;
2146                                         rdev->pm.power_state[state_index].misc2 = misc2;
2147                                         rdev->pm.power_state[state_index].pcie_lanes =
2148                                                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2149                                                 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2150                                         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2151                                         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2152                                                 rdev->pm.power_state[state_index].type =
2153                                                         POWER_STATE_TYPE_BATTERY;
2154                                                 break;
2155                                         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2156                                                 rdev->pm.power_state[state_index].type =
2157                                                         POWER_STATE_TYPE_BALANCED;
2158                                                 break;
2159                                         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2160                                                 rdev->pm.power_state[state_index].type =
2161                                                         POWER_STATE_TYPE_PERFORMANCE;
2162                                                 break;
2163                                         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2164                                                 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2165                                                         rdev->pm.power_state[state_index].type =
2166                                                                 POWER_STATE_TYPE_PERFORMANCE;
2167                                                 break;
2168                                         }
2169                                         rdev->pm.power_state[state_index].flags = 0;
2170                                         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2171                                                 rdev->pm.power_state[state_index].flags |=
2172                                                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2173                                         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2174                                                 rdev->pm.power_state[state_index].type =
2175                                                         POWER_STATE_TYPE_DEFAULT;
2176                                                 rdev->pm.default_power_state_index = state_index;
2177                                                 rdev->pm.power_state[state_index].default_clock_mode =
2178                                                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2179                                                 /* patch the table values with the default slck/mclk from firmware info */
2180                                                 for (j = 0; j < mode_index; j++) {
2181                                                         rdev->pm.power_state[state_index].clock_info[j].mclk =
2182                                                                 rdev->clock.default_mclk;
2183                                                         rdev->pm.power_state[state_index].clock_info[j].sclk =
2184                                                                 rdev->clock.default_sclk;
2185                                                         if (vddc)
2186                                                                 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2187                                                                         vddc;
2188                                                 }
2189                                         }
2190                                         state_index++;
2191                                 }
2192                         }
2193                         /* if multiple clock modes, mark the lowest as no display */
2194                         for (i = 0; i < state_index; i++) {
2195                                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2196                                         rdev->pm.power_state[i].clock_info[0].flags |=
2197                                                 RADEON_PM_MODE_NO_DISPLAY;
2198                         }
2199                         /* first mode is usually default */
2200                         if (rdev->pm.default_power_state_index == -1) {
2201                                 rdev->pm.power_state[0].type =
2202                                         POWER_STATE_TYPE_DEFAULT;
2203                                 rdev->pm.default_power_state_index = 0;
2204                                 rdev->pm.power_state[0].default_clock_mode =
2205                                         &rdev->pm.power_state[0].clock_info[0];
2206                         }
2207                 }
2208         } else {
2209                 /* add the default mode */
2210                 rdev->pm.power_state[state_index].type =
2211                         POWER_STATE_TYPE_DEFAULT;
2212                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2213                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2214                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2215                 rdev->pm.power_state[state_index].default_clock_mode =
2216                         &rdev->pm.power_state[state_index].clock_info[0];
2217                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2218                 rdev->pm.power_state[state_index].pcie_lanes = 16;
2219                 rdev->pm.default_power_state_index = state_index;
2220                 rdev->pm.power_state[state_index].flags = 0;
2221                 state_index++;
2222         }
2223
2224         rdev->pm.num_power_states = state_index;
2225
2226         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2227         rdev->pm.current_clock_mode_index = 0;
2228         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2229 }
2230
2231 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2232 {
2233         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2234         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2235
2236         args.ucEnable = enable;
2237
2238         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2239 }
2240
2241 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2242 {
2243         GET_ENGINE_CLOCK_PS_ALLOCATION args;
2244         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2245
2246         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2247         return args.ulReturnEngineClock;
2248 }
2249
2250 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2251 {
2252         GET_MEMORY_CLOCK_PS_ALLOCATION args;
2253         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2254
2255         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2256         return args.ulReturnMemoryClock;
2257 }
2258
2259 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2260                                   uint32_t eng_clock)
2261 {
2262         SET_ENGINE_CLOCK_PS_ALLOCATION args;
2263         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2264
2265         args.ulTargetEngineClock = eng_clock;   /* 10 khz */
2266
2267         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2268 }
2269
2270 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2271                                   uint32_t mem_clock)
2272 {
2273         SET_MEMORY_CLOCK_PS_ALLOCATION args;
2274         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2275
2276         if (rdev->flags & RADEON_IS_IGP)
2277                 return;
2278
2279         args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
2280
2281         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2282 }
2283
2284 union set_voltage {
2285         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2286         struct _SET_VOLTAGE_PARAMETERS v1;
2287         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2288 };
2289
2290 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2291 {
2292         union set_voltage args;
2293         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2294         u8 frev, crev, volt_index = level;
2295
2296         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2297                 return;
2298
2299         switch (crev) {
2300         case 1:
2301                 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2302                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2303                 args.v1.ucVoltageIndex = volt_index;
2304                 break;
2305         case 2:
2306                 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2307                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2308                 args.v2.usVoltageLevel = cpu_to_le16(level);
2309                 break;
2310         default:
2311                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2312                 return;
2313         }
2314
2315         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2316 }
2317
2318
2319
2320 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2321 {
2322         struct radeon_device *rdev = dev->dev_private;
2323         uint32_t bios_2_scratch, bios_6_scratch;
2324
2325         if (rdev->family >= CHIP_R600) {
2326                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2327                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2328         } else {
2329                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2330                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2331         }
2332
2333         /* let the bios control the backlight */
2334         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2335
2336         /* tell the bios not to handle mode switching */
2337         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2338
2339         if (rdev->family >= CHIP_R600) {
2340                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2341                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2342         } else {
2343                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2344                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2345         }
2346
2347 }
2348
2349 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2350 {
2351         uint32_t scratch_reg;
2352         int i;
2353
2354         if (rdev->family >= CHIP_R600)
2355                 scratch_reg = R600_BIOS_0_SCRATCH;
2356         else
2357                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2358
2359         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2360                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2361 }
2362
2363 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2364 {
2365         uint32_t scratch_reg;
2366         int i;
2367
2368         if (rdev->family >= CHIP_R600)
2369                 scratch_reg = R600_BIOS_0_SCRATCH;
2370         else
2371                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2372
2373         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2374                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2375 }
2376
2377 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2378 {
2379         struct drm_device *dev = encoder->dev;
2380         struct radeon_device *rdev = dev->dev_private;
2381         uint32_t bios_6_scratch;
2382
2383         if (rdev->family >= CHIP_R600)
2384                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2385         else
2386                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2387
2388         if (lock)
2389                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2390         else
2391                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2392
2393         if (rdev->family >= CHIP_R600)
2394                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2395         else
2396                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2397 }
2398
2399 /* at some point we may want to break this out into individual functions */
2400 void
2401 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2402                                        struct drm_encoder *encoder,
2403                                        bool connected)
2404 {
2405         struct drm_device *dev = connector->dev;
2406         struct radeon_device *rdev = dev->dev_private;
2407         struct radeon_connector *radeon_connector =
2408             to_radeon_connector(connector);
2409         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2410         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2411
2412         if (rdev->family >= CHIP_R600) {
2413                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2414                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2415                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2416         } else {
2417                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2418                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2419                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2420         }
2421
2422         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2423             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2424                 if (connected) {
2425                         DRM_DEBUG_KMS("TV1 connected\n");
2426                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2427                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2428                 } else {
2429                         DRM_DEBUG_KMS("TV1 disconnected\n");
2430                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2431                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2432                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2433                 }
2434         }
2435         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2436             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2437                 if (connected) {
2438                         DRM_DEBUG_KMS("CV connected\n");
2439                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2440                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2441                 } else {
2442                         DRM_DEBUG_KMS("CV disconnected\n");
2443                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
2444                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2445                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2446                 }
2447         }
2448         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2449             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2450                 if (connected) {
2451                         DRM_DEBUG_KMS("LCD1 connected\n");
2452                         bios_0_scratch |= ATOM_S0_LCD1;
2453                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2454                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2455                 } else {
2456                         DRM_DEBUG_KMS("LCD1 disconnected\n");
2457                         bios_0_scratch &= ~ATOM_S0_LCD1;
2458                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2459                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2460                 }
2461         }
2462         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2463             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2464                 if (connected) {
2465                         DRM_DEBUG_KMS("CRT1 connected\n");
2466                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2467                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2468                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2469                 } else {
2470                         DRM_DEBUG_KMS("CRT1 disconnected\n");
2471                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2472                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2473                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2474                 }
2475         }
2476         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2477             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2478                 if (connected) {
2479                         DRM_DEBUG_KMS("CRT2 connected\n");
2480                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2481                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2482                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2483                 } else {
2484                         DRM_DEBUG_KMS("CRT2 disconnected\n");
2485                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2486                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2487                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2488                 }
2489         }
2490         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2491             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2492                 if (connected) {
2493                         DRM_DEBUG_KMS("DFP1 connected\n");
2494                         bios_0_scratch |= ATOM_S0_DFP1;
2495                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2496                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2497                 } else {
2498                         DRM_DEBUG_KMS("DFP1 disconnected\n");
2499                         bios_0_scratch &= ~ATOM_S0_DFP1;
2500                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2501                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2502                 }
2503         }
2504         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2505             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2506                 if (connected) {
2507                         DRM_DEBUG_KMS("DFP2 connected\n");
2508                         bios_0_scratch |= ATOM_S0_DFP2;
2509                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2510                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2511                 } else {
2512                         DRM_DEBUG_KMS("DFP2 disconnected\n");
2513                         bios_0_scratch &= ~ATOM_S0_DFP2;
2514                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2515                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2516                 }
2517         }
2518         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2519             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2520                 if (connected) {
2521                         DRM_DEBUG_KMS("DFP3 connected\n");
2522                         bios_0_scratch |= ATOM_S0_DFP3;
2523                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2524                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2525                 } else {
2526                         DRM_DEBUG_KMS("DFP3 disconnected\n");
2527                         bios_0_scratch &= ~ATOM_S0_DFP3;
2528                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2529                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2530                 }
2531         }
2532         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2533             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2534                 if (connected) {
2535                         DRM_DEBUG_KMS("DFP4 connected\n");
2536                         bios_0_scratch |= ATOM_S0_DFP4;
2537                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2538                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2539                 } else {
2540                         DRM_DEBUG_KMS("DFP4 disconnected\n");
2541                         bios_0_scratch &= ~ATOM_S0_DFP4;
2542                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2543                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2544                 }
2545         }
2546         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2547             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2548                 if (connected) {
2549                         DRM_DEBUG_KMS("DFP5 connected\n");
2550                         bios_0_scratch |= ATOM_S0_DFP5;
2551                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2552                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2553                 } else {
2554                         DRM_DEBUG_KMS("DFP5 disconnected\n");
2555                         bios_0_scratch &= ~ATOM_S0_DFP5;
2556                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2557                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2558                 }
2559         }
2560
2561         if (rdev->family >= CHIP_R600) {
2562                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2563                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2564                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2565         } else {
2566                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2567                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2568                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2569         }
2570 }
2571
2572 void
2573 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2574 {
2575         struct drm_device *dev = encoder->dev;
2576         struct radeon_device *rdev = dev->dev_private;
2577         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2578         uint32_t bios_3_scratch;
2579
2580         if (rdev->family >= CHIP_R600)
2581                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2582         else
2583                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2584
2585         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2586                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2587                 bios_3_scratch |= (crtc << 18);
2588         }
2589         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2590                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2591                 bios_3_scratch |= (crtc << 24);
2592         }
2593         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2594                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2595                 bios_3_scratch |= (crtc << 16);
2596         }
2597         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2598                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2599                 bios_3_scratch |= (crtc << 20);
2600         }
2601         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2602                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2603                 bios_3_scratch |= (crtc << 17);
2604         }
2605         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2606                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2607                 bios_3_scratch |= (crtc << 19);
2608         }
2609         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2610                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2611                 bios_3_scratch |= (crtc << 23);
2612         }
2613         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2614                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2615                 bios_3_scratch |= (crtc << 25);
2616         }
2617
2618         if (rdev->family >= CHIP_R600)
2619                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2620         else
2621                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2622 }
2623
2624 void
2625 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2626 {
2627         struct drm_device *dev = encoder->dev;
2628         struct radeon_device *rdev = dev->dev_private;
2629         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2630         uint32_t bios_2_scratch;
2631
2632         if (rdev->family >= CHIP_R600)
2633                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2634         else
2635                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2636
2637         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2638                 if (on)
2639                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2640                 else
2641                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2642         }
2643         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2644                 if (on)
2645                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2646                 else
2647                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2648         }
2649         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2650                 if (on)
2651                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2652                 else
2653                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2654         }
2655         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2656                 if (on)
2657                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2658                 else
2659                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2660         }
2661         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2662                 if (on)
2663                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2664                 else
2665                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2666         }
2667         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2668                 if (on)
2669                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2670                 else
2671                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2672         }
2673         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2674                 if (on)
2675                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2676                 else
2677                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2678         }
2679         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2680                 if (on)
2681                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2682                 else
2683                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2684         }
2685         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2686                 if (on)
2687                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2688                 else
2689                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2690         }
2691         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2692                 if (on)
2693                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2694                 else
2695                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2696         }
2697
2698         if (rdev->family >= CHIP_R600)
2699                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2700         else
2701                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2702 }