drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/module.h>
  33 #include "drmP.h"
  34 #include "radeon_drm.h"
  35 #include "radeon.h"
  36 #include "radeon_asic.h"
  37 #include "radeon_mode.h"
  38 #include "r600d.h"
  39 #include "atom.h"
  40 #include "avivod.h"
  41
  42 #define PFP_UCODE_SIZE 576
  43 #define PM4_UCODE_SIZE 1792
  44 #define RLC_UCODE_SIZE 768
  45 #define R700_PFP_UCODE_SIZE 848
  46 #define R700_PM4_UCODE_SIZE 1360
  47 #define R700_RLC_UCODE_SIZE 1024
  48 #define EVERGREEN_PFP_UCODE_SIZE 1120
  49 #define EVERGREEN_PM4_UCODE_SIZE 1376
  50 #define EVERGREEN_RLC_UCODE_SIZE 768
  51 #define CAYMAN_RLC_UCODE_SIZE 1024
  52
  53 /* Firmware Names */
  54 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  55 MODULE_FIRMWARE("radeon/R600_me.bin");
  56 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  57 MODULE_FIRMWARE("radeon/RV610_me.bin");
  58 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  59 MODULE_FIRMWARE("radeon/RV630_me.bin");
  60 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RV620_me.bin");
  62 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  63 MODULE_FIRMWARE("radeon/RV635_me.bin");
  64 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RV670_me.bin");
  66 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  67 MODULE_FIRMWARE("radeon/RS780_me.bin");
  68 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  69 MODULE_FIRMWARE("radeon/RV770_me.bin");
  70 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  71 MODULE_FIRMWARE("radeon/RV730_me.bin");
  72 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  73 MODULE_FIRMWARE("radeon/RV710_me.bin");
  74 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  75 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  76 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  77 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  78 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  79 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  80 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  81 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  82 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  83 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  84 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  85 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  86 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  87 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  88 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
  89 MODULE_FIRMWARE("radeon/PALM_me.bin");
  90 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
  91 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
  92 MODULE_FIRMWARE("radeon/SUMO_me.bin");
  93 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
  94 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
  95
  96 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  97
  98 /* r600,rv610,rv630,rv620,rv635,rv670 */
  99 int r600_mc_wait_for_idle(struct radeon_device *rdev);
 100 void r600_gpu_init(struct radeon_device *rdev);
 101 void r600_fini(struct radeon_device *rdev);
 102 void r600_irq_disable(struct radeon_device *rdev);
 103 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
 104
 105 /* get temperature in millidegrees */
 106 int rv6xx_get_temp(struct radeon_device *rdev)
 107 {
 108         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 109                 ASIC_T_SHIFT;
 110         int actual_temp = temp & 0xff;
 111
 112         if (temp & 0x100)
 113                 actual_temp -= 256;
 114
 115         return actual_temp * 1000;
 116 }
 117
 118 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 119 {
 120         int i;
 121
 122         rdev->pm.dynpm_can_upclock = true;
 123         rdev->pm.dynpm_can_downclock = true;
 124
 125         /* power state array is low to high, default is first */
 126         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 127                 int min_power_state_index = 0;
 128
 129                 if (rdev->pm.num_power_states > 2)
 130                         min_power_state_index = 1;
 131
 132                 switch (rdev->pm.dynpm_planned_action) {
 133                 case DYNPM_ACTION_MINIMUM:
 134                         rdev->pm.requested_power_state_index = min_power_state_index;
 135                         rdev->pm.requested_clock_mode_index = 0;
 136                         rdev->pm.dynpm_can_downclock = false;
 137                         break;
 138                 case DYNPM_ACTION_DOWNCLOCK:
 139                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 140                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 141                                 rdev->pm.dynpm_can_downclock = false;
 142                         } else {
 143                                 if (rdev->pm.active_crtc_count > 1) {
 144                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 145                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 146                                                         continue;
 147                                                 else if (i >= rdev->pm.current_power_state_index) {
 148                                                         rdev->pm.requested_power_state_index =
 149                                                                 rdev->pm.current_power_state_index;
 150                                                         break;
 151                                                 } else {
 152                                                         rdev->pm.requested_power_state_index = i;
 153                                                         break;
 154                                                 }
 155                                         }
 156                                 } else {
 157                                         if (rdev->pm.current_power_state_index == 0)
 158                                                 rdev->pm.requested_power_state_index =
 159                                                         rdev->pm.num_power_states - 1;
 160                                         else
 161                                                 rdev->pm.requested_power_state_index =
 162                                                         rdev->pm.current_power_state_index - 1;
 163                                 }
 164                         }
 165                         rdev->pm.requested_clock_mode_index = 0;
 166                         /* don't use the power state if crtcs are active and no display flag is set */
 167                         if ((rdev->pm.active_crtc_count > 0) &&
 168                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 169                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 170                              RADEON_PM_MODE_NO_DISPLAY)) {
 171                                 rdev->pm.requested_power_state_index++;
 172                         }
 173                         break;
 174                 case DYNPM_ACTION_UPCLOCK:
 175                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 176                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 177                                 rdev->pm.dynpm_can_upclock = false;
 178                         } else {
 179                                 if (rdev->pm.active_crtc_count > 1) {
 180                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 181                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 182                                                         continue;
 183                                                 else if (i <= rdev->pm.current_power_state_index) {
 184                                                         rdev->pm.requested_power_state_index =
 185                                                                 rdev->pm.current_power_state_index;
 186                                                         break;
 187                                                 } else {
 188                                                         rdev->pm.requested_power_state_index = i;
 189                                                         break;
 190                                                 }
 191                                         }
 192                                 } else
 193                                         rdev->pm.requested_power_state_index =
 194                                                 rdev->pm.current_power_state_index + 1;
 195                         }
 196                         rdev->pm.requested_clock_mode_index = 0;
 197                         break;
 198                 case DYNPM_ACTION_DEFAULT:
 199                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 200                         rdev->pm.requested_clock_mode_index = 0;
 201                         rdev->pm.dynpm_can_upclock = false;
 202                         break;
 203                 case DYNPM_ACTION_NONE:
 204                 default:
 205                         DRM_ERROR("Requested mode for not defined action\n");
 206                         return;
 207                 }
 208         } else {
 209                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 210                 /* for now just select the first power state and switch between clock modes */
 211                 /* power state array is low to high, default is first (0) */
 212                 if (rdev->pm.active_crtc_count > 1) {
 213                         rdev->pm.requested_power_state_index = -1;
 214                         /* start at 1 as we don't want the default mode */
 215                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 216                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 217                                         continue;
 218                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 219                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 220                                         rdev->pm.requested_power_state_index = i;
 221                                         break;
 222                                 }
 223                         }
 224                         /* if nothing selected, grab the default state. */
 225                         if (rdev->pm.requested_power_state_index == -1)
 226                                 rdev->pm.requested_power_state_index = 0;
 227                 } else
 228                         rdev->pm.requested_power_state_index = 1;
 229
 230                 switch (rdev->pm.dynpm_planned_action) {
 231                 case DYNPM_ACTION_MINIMUM:
 232                         rdev->pm.requested_clock_mode_index = 0;
 233                         rdev->pm.dynpm_can_downclock = false;
 234                         break;
 235                 case DYNPM_ACTION_DOWNCLOCK:
 236                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 237                                 if (rdev->pm.current_clock_mode_index == 0) {
 238                                         rdev->pm.requested_clock_mode_index = 0;
 239                                         rdev->pm.dynpm_can_downclock = false;
 240                                 } else
 241                                         rdev->pm.requested_clock_mode_index =
 242                                                 rdev->pm.current_clock_mode_index - 1;
 243                         } else {
 244                                 rdev->pm.requested_clock_mode_index = 0;
 245                                 rdev->pm.dynpm_can_downclock = false;
 246                         }
 247                         /* don't use the power state if crtcs are active and no display flag is set */
 248                         if ((rdev->pm.active_crtc_count > 0) &&
 249                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 250                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 251                              RADEON_PM_MODE_NO_DISPLAY)) {
 252                                 rdev->pm.requested_clock_mode_index++;
 253                         }
 254                         break;
 255                 case DYNPM_ACTION_UPCLOCK:
 256                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 257                                 if (rdev->pm.current_clock_mode_index ==
 258                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 259                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 260                                         rdev->pm.dynpm_can_upclock = false;
 261                                 } else
 262                                         rdev->pm.requested_clock_mode_index =
 263                                                 rdev->pm.current_clock_mode_index + 1;
 264                         } else {
 265                                 rdev->pm.requested_clock_mode_index =
 266                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 267                                 rdev->pm.dynpm_can_upclock = false;
 268                         }
 269                         break;
 270                 case DYNPM_ACTION_DEFAULT:
 271                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 272                         rdev->pm.requested_clock_mode_index = 0;
 273                         rdev->pm.dynpm_can_upclock = false;
 274                         break;
 275                 case DYNPM_ACTION_NONE:
 276                 default:
 277                         DRM_ERROR("Requested mode for not defined action\n");
 278                         return;
 279                 }
 280         }
 281
 282         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 283                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 284                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 285                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 286                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 287                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 288                   pcie_lanes);
 289 }
 290
 291 void rs780_pm_init_profile(struct radeon_device *rdev)
 292 {
 293         if (rdev->pm.num_power_states == 2) {
 294                 /* default */
 295                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 296                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 297                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 298                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 299                 /* low sh */
 300                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 301                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 302                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 303                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 304                 /* mid sh */
 305                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 306                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 307                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 308                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 309                 /* high sh */
 310                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 311                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 312                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 313                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 314                 /* low mh */
 315                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 316                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 317                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 318                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 319                 /* mid mh */
 320                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 321                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 322                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 323                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 324                 /* high mh */
 325                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 326                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 327                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 328                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 329         } else if (rdev->pm.num_power_states == 3) {
 330                 /* default */
 331                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 332                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 333                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 334                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 335                 /* low sh */
 336                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 337                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 338                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 339                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 340                 /* mid sh */
 341                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 342                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 343                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 344                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 345                 /* high sh */
 346                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 347                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 348                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 349                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 350                 /* low mh */
 351                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 352                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 353                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 354                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 355                 /* mid mh */
 356                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 357                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 358                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 359                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 360                 /* high mh */
 361                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 362                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 363                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 364                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 365         } else {
 366                 /* default */
 367                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 368                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 369                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 370                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 371                 /* low sh */
 372                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 373                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 374                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 375                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 376                 /* mid sh */
 377                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 378                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 379                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 380                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 381                 /* high sh */
 382                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 383                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 384                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 385                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 386                 /* low mh */
 387                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 388                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 389                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 390                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 391                 /* mid mh */
 392                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 393                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 394                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 395                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 396                 /* high mh */
 397                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 398                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 399                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 400                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 401         }
 402 }
 403
 404 void r600_pm_init_profile(struct radeon_device *rdev)
 405 {
 406         if (rdev->family == CHIP_R600) {
 407                 /* XXX */
 408                 /* default */
 409                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 410                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 411                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 412                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 413                 /* low sh */
 414                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 415                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 416                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 417                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 418                 /* mid sh */
 419                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 420                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 421                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 422                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 423                 /* high sh */
 424                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 425                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 426                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 427                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 428                 /* low mh */
 429                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 430                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 431                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 432                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 433                 /* mid mh */
 434                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 435                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 436                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 437                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 438                 /* high mh */
 439                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 440                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 441                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 442                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 443         } else {
 444                 if (rdev->pm.num_power_states < 4) {
 445                         /* default */
 446                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 447                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 448                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 449                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 450                         /* low sh */
 451                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 452                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 453                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 454                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 455                         /* mid sh */
 456                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 457                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 458                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 459                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 460                         /* high sh */
 461                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 462                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 463                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 464                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 465                         /* low mh */
 466                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 467                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 468                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 469                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 470                         /* low mh */
 471                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 472                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 473                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 474                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 475                         /* high mh */
 476                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 477                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 478                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 479                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 480                 } else {
 481                         /* default */
 482                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 483                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 484                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 485                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 486                         /* low sh */
 487                         if (rdev->flags & RADEON_IS_MOBILITY) {
 488                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 489                                         radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 490                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 491                                         radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 492                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 493                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 494                         } else {
 495                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 496                                         radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 497                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 498                                         radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 499                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 500                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 501                         }
 502                         /* mid sh */
 503                         if (rdev->flags & RADEON_IS_MOBILITY) {
 504                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 505                                         radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 506                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 507                                         radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 508                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 509                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 510                         } else {
 511                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 512                                         radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 513                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 514                                         radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 515                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 516                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 517                         }
 518                         /* high sh */
 519                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
 520                                 radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 521                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
 522                                 radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 523                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 524                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 525                         /* low mh */
 526                         if (rdev->flags & RADEON_IS_MOBILITY) {
 527                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 528                                         radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 529                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 530                                         radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 531                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 532                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 533                         } else {
 534                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 535                                         radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 536                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 537                                         radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 538                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 539                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 540                         }
 541                         /* mid mh */
 542                         if (rdev->flags & RADEON_IS_MOBILITY) {
 543                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 544                                         radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 545                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 546                                         radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 547                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 548                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 549                         } else {
 550                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 551                                         radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 552                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 553                                         radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 554                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 555                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 556                         }
 557                         /* high mh */
 558                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
 559                                 radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 560                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
 561                                 radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 562                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 563                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 564                 }
 565         }
 566 }
 567
 568 void r600_pm_misc(struct radeon_device *rdev)
 569 {
 570         int req_ps_idx = rdev->pm.requested_power_state_index;
 571         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 572         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 573         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 574
 575         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 576                 /* 0xff01 is a flag rather then an actual voltage */
 577                 if (voltage->voltage == 0xff01)
 578                         return;
 579                 if (voltage->voltage != rdev->pm.current_vddc) {
 580                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 581                         rdev->pm.current_vddc = voltage->voltage;
 582                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 583                 }
 584         }
 585 }
 586
 587 bool r600_gui_idle(struct radeon_device *rdev)
 588 {
 589         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 590                 return false;
 591         else
 592                 return true;
 593 }
 594
 595 /* hpd for digital panel detect/disconnect */
 596 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 597 {
 598         bool connected = false;
 599
 600         if (ASIC_IS_DCE3(rdev)) {
 601                 switch (hpd) {
 602                 case RADEON_HPD_1:
 603                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 604                                 connected = true;
 605                         break;
 606                 case RADEON_HPD_2:
 607                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 608                                 connected = true;
 609                         break;
 610                 case RADEON_HPD_3:
 611                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 612                                 connected = true;
 613                         break;
 614                 case RADEON_HPD_4:
 615                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 616                                 connected = true;
 617                         break;
 618                         /* DCE 3.2 */
 619                 case RADEON_HPD_5:
 620                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 621                                 connected = true;
 622                         break;
 623                 case RADEON_HPD_6:
 624                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 625                                 connected = true;
 626                         break;
 627                 default:
 628                         break;
 629                 }
 630         } else {
 631                 switch (hpd) {
 632                 case RADEON_HPD_1:
 633                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 634                                 connected = true;
 635                         break;
 636                 case RADEON_HPD_2:
 637                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 638                                 connected = true;
 639                         break;
 640                 case RADEON_HPD_3:
 641                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 642                                 connected = true;
 643                         break;
 644                 default:
 645                         break;
 646                 }
 647         }
 648         return connected;
 649 }
 650
 651 void r600_hpd_set_polarity(struct radeon_device *rdev,
 652                            enum radeon_hpd_id hpd)
 653 {
 654         u32 tmp;
 655         bool connected = r600_hpd_sense(rdev, hpd);
 656
 657         if (ASIC_IS_DCE3(rdev)) {
 658                 switch (hpd) {
 659                 case RADEON_HPD_1:
 660                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 661                         if (connected)
 662                                 tmp &= ~DC_HPDx_INT_POLARITY;
 663                         else
 664                                 tmp |= DC_HPDx_INT_POLARITY;
 665                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 666                         break;
 667                 case RADEON_HPD_2:
 668                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 669                         if (connected)
 670                                 tmp &= ~DC_HPDx_INT_POLARITY;
 671                         else
 672                                 tmp |= DC_HPDx_INT_POLARITY;
 673                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 674                         break;
 675                 case RADEON_HPD_3:
 676                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 677                         if (connected)
 678                                 tmp &= ~DC_HPDx_INT_POLARITY;
 679                         else
 680                                 tmp |= DC_HPDx_INT_POLARITY;
 681                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 682                         break;
 683                 case RADEON_HPD_4:
 684                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 685                         if (connected)
 686                                 tmp &= ~DC_HPDx_INT_POLARITY;
 687                         else
 688                                 tmp |= DC_HPDx_INT_POLARITY;
 689                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 690                         break;
 691                 case RADEON_HPD_5:
 692                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 693                         if (connected)
 694                                 tmp &= ~DC_HPDx_INT_POLARITY;
 695                         else
 696                                 tmp |= DC_HPDx_INT_POLARITY;
 697                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 698                         break;
 699                         /* DCE 3.2 */
 700                 case RADEON_HPD_6:
 701                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 702                         if (connected)
 703                                 tmp &= ~DC_HPDx_INT_POLARITY;
 704                         else
 705                                 tmp |= DC_HPDx_INT_POLARITY;
 706                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 707                         break;
 708                 default:
 709                         break;
 710                 }
 711         } else {
 712                 switch (hpd) {
 713                 case RADEON_HPD_1:
 714                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 715                         if (connected)
 716                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 717                         else
 718                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 719                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 720                         break;
 721                 case RADEON_HPD_2:
 722                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 723                         if (connected)
 724                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 725                         else
 726                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 727                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 728                         break;
 729                 case RADEON_HPD_3:
 730                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 731                         if (connected)
 732                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 733                         else
 734                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 735                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 736                         break;
 737                 default:
 738                         break;
 739                 }
 740         }
 741 }
 742
 743 void r600_hpd_init(struct radeon_device *rdev)
 744 {
 745         struct drm_device *dev = rdev->ddev;
 746         struct drm_connector *connector;
 747
 748         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 749                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 750
 751                 if (ASIC_IS_DCE3(rdev)) {
 752                         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 753                         if (ASIC_IS_DCE32(rdev))
 754                                 tmp |= DC_HPDx_EN;
 755
 756                         switch (radeon_connector->hpd.hpd) {
 757                         case RADEON_HPD_1:
 758                                 WREG32(DC_HPD1_CONTROL, tmp);
 759                                 rdev->irq.hpd[0] = true;
 760                                 break;
 761                         case RADEON_HPD_2:
 762                                 WREG32(DC_HPD2_CONTROL, tmp);
 763                                 rdev->irq.hpd[1] = true;
 764                                 break;
 765                         case RADEON_HPD_3:
 766                                 WREG32(DC_HPD3_CONTROL, tmp);
 767                                 rdev->irq.hpd[2] = true;
 768                                 break;
 769                         case RADEON_HPD_4:
 770                                 WREG32(DC_HPD4_CONTROL, tmp);
 771                                 rdev->irq.hpd[3] = true;
 772                                 break;
 773                                 /* DCE 3.2 */
 774                         case RADEON_HPD_5:
 775                                 WREG32(DC_HPD5_CONTROL, tmp);
 776                                 rdev->irq.hpd[4] = true;
 777                                 break;
 778                         case RADEON_HPD_6:
 779                                 WREG32(DC_HPD6_CONTROL, tmp);
 780                                 rdev->irq.hpd[5] = true;
 781                                 break;
 782                         default:
 783                                 break;
 784                         }
 785                 } else {
 786                         switch (radeon_connector->hpd.hpd) {
 787                         case RADEON_HPD_1:
 788                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 789                                 rdev->irq.hpd[0] = true;
 790                                 break;
 791                         case RADEON_HPD_2:
 792                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 793                                 rdev->irq.hpd[1] = true;
 794                                 break;
 795                         case RADEON_HPD_3:
 796                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 797                                 rdev->irq.hpd[2] = true;
 798                                 break;
 799                         default:
 800                                 break;
 801                         }
 802                 }
 803                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 804         }
 805         if (rdev->irq.installed)
 806                 r600_irq_set(rdev);
 807 }
 808
 809 void r600_hpd_fini(struct radeon_device *rdev)
 810 {
 811         struct drm_device *dev = rdev->ddev;
 812         struct drm_connector *connector;
 813
 814         if (ASIC_IS_DCE3(rdev)) {
 815                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 816                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 817                         switch (radeon_connector->hpd.hpd) {
 818                         case RADEON_HPD_1:
 819                                 WREG32(DC_HPD1_CONTROL, 0);
 820                                 rdev->irq.hpd[0] = false;
 821                                 break;
 822                         case RADEON_HPD_2:
 823                                 WREG32(DC_HPD2_CONTROL, 0);
 824                                 rdev->irq.hpd[1] = false;
 825                                 break;
 826                         case RADEON_HPD_3:
 827                                 WREG32(DC_HPD3_CONTROL, 0);
 828                                 rdev->irq.hpd[2] = false;
 829                                 break;
 830                         case RADEON_HPD_4:
 831                                 WREG32(DC_HPD4_CONTROL, 0);
 832                                 rdev->irq.hpd[3] = false;
 833                                 break;
 834                                 /* DCE 3.2 */
 835                         case RADEON_HPD_5:
 836                                 WREG32(DC_HPD5_CONTROL, 0);
 837                                 rdev->irq.hpd[4] = false;
 838                                 break;
 839                         case RADEON_HPD_6:
 840                                 WREG32(DC_HPD6_CONTROL, 0);
 841                                 rdev->irq.hpd[5] = false;
 842                                 break;
 843                         default:
 844                                 break;
 845                         }
 846                 }
 847         } else {
 848                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 849                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 850                         switch (radeon_connector->hpd.hpd) {
 851                         case RADEON_HPD_1:
 852                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 853                                 rdev->irq.hpd[0] = false;
 854                                 break;
 855                         case RADEON_HPD_2:
 856                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 857                                 rdev->irq.hpd[1] = false;
 858                                 break;
 859                         case RADEON_HPD_3:
 860                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 861                                 rdev->irq.hpd[2] = false;
 862                                 break;
 863                         default:
 864                                 break;
 865                         }
 866                 }
 867         }
 868 }
 869
 870 /*
 871  * R600 PCIE GART
 872  */
 873 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 874 {
 875         unsigned i;
 876         u32 tmp;
 877
 878         /* flush hdp cache so updates hit vram */
 879         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
 880             !(rdev->flags & RADEON_IS_AGP)) {
 881                 void __iomem *ptr = (void *)rdev->gart.ptr;
 882                 u32 tmp;
 883
 884                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 885                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
 886                  * This seems to cause problems on some AGP cards. Just use the old
 887                  * method for them.
 888                  */
 889                 WREG32(HDP_DEBUG1, 0);
 890                 tmp = readl((void __iomem *)ptr);
 891         } else
 892                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 893
 894         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 895         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 896         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 897         for (i = 0; i < rdev->usec_timeout; i++) {
 898                 /* read MC_STATUS */
 899                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 900                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 901                 if (tmp == 2) {
 902                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 903                         return;
 904                 }
 905                 if (tmp) {
 906                         return;
 907                 }
 908                 udelay(1);
 909         }
 910 }
 911
 912 int r600_pcie_gart_init(struct radeon_device *rdev)
 913 {
 914         int r;
 915
 916         if (rdev->gart.robj) {
 917                 WARN(1, "R600 PCIE GART already initialized\n");
 918                 return 0;
 919         }
 920         /* Initialize common gart structure */
 921         r = radeon_gart_init(rdev);
 922         if (r)
 923                 return r;
 924         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 925         return radeon_gart_table_vram_alloc(rdev);
 926 }
 927
 928 int r600_pcie_gart_enable(struct radeon_device *rdev)
 929 {
 930         u32 tmp;
 931         int r, i;
 932
 933         if (rdev->gart.robj == NULL) {
 934                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 935                 return -EINVAL;
 936         }
 937         r = radeon_gart_table_vram_pin(rdev);
 938         if (r)
 939                 return r;
 940         radeon_gart_restore(rdev);
 941
 942         /* Setup L2 cache */
 943         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 944                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 945                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 946         WREG32(VM_L2_CNTL2, 0);
 947         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 948         /* Setup TLB control */
 949         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 950                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 951                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 952                 ENABLE_WAIT_L2_QUERY;
 953         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 954         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 955         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 956         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 957         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 958         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 959         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 960         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 961         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 962         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 963         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 964         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 965         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 966         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 967         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 968         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 969         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 970         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 971                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 972         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 973                         (u32)(rdev->dummy_page.addr >> 12));
 974         for (i = 1; i < 7; i++)
 975                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 976
 977         r600_pcie_gart_tlb_flush(rdev);
 978         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 979                  (unsigned)(rdev->mc.gtt_size >> 20),
 980                  (unsigned long long)rdev->gart.table_addr);
 981         rdev->gart.ready = true;
 982         return 0;
 983 }
 984
 985 void r600_pcie_gart_disable(struct radeon_device *rdev)
 986 {
 987         u32 tmp;
 988         int i;
 989
 990         /* Disable all tables */
 991         for (i = 0; i < 7; i++)
 992                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 993
 994         /* Disable L2 cache */
 995         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 996                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 997         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 998         /* Setup L1 TLB control */
 999         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1000                 ENABLE_WAIT_L2_QUERY;
1001         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1002         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1003         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1004         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1005         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1006         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1007         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1008         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1009         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1010         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1011         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1012         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1013         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1014         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1015         radeon_gart_table_vram_unpin(rdev);
1016 }
1017
1018 void r600_pcie_gart_fini(struct radeon_device *rdev)
1019 {
1020         radeon_gart_fini(rdev);
1021         r600_pcie_gart_disable(rdev);
1022         radeon_gart_table_vram_free(rdev);
1023 }
1024
1025 void r600_agp_enable(struct radeon_device *rdev)
1026 {
1027         u32 tmp;
1028         int i;
1029
1030         /* Setup L2 cache */
1031         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1032                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1033                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1034         WREG32(VM_L2_CNTL2, 0);
1035         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1036         /* Setup TLB control */
1037         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1038                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1039                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1040                 ENABLE_WAIT_L2_QUERY;
1041         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1042         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1043         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1044         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1045         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1046         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1047         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1048         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1049         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1050         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1051         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1052         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1053         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1054         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1055         for (i = 0; i < 7; i++)
1056                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1057 }
1058
1059 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1060 {
1061         unsigned i;
1062         u32 tmp;
1063
1064         for (i = 0; i < rdev->usec_timeout; i++) {
1065                 /* read MC_STATUS */
1066                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1067                 if (!tmp)
1068                         return 0;
1069                 udelay(1);
1070         }
1071         return -1;
1072 }
1073
1074 static void r600_mc_program(struct radeon_device *rdev)
1075 {
1076         struct rv515_mc_save save;
1077         u32 tmp;
1078         int i, j;
1079
1080         /* Initialize HDP */
1081         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1082                 WREG32((0x2c14 + j), 0x00000000);
1083                 WREG32((0x2c18 + j), 0x00000000);
1084                 WREG32((0x2c1c + j), 0x00000000);
1085                 WREG32((0x2c20 + j), 0x00000000);
1086                 WREG32((0x2c24 + j), 0x00000000);
1087         }
1088         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1089
1090         rv515_mc_stop(rdev, &save);
1091         if (r600_mc_wait_for_idle(rdev)) {
1092                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1093         }
1094         /* Lockout access through VGA aperture (doesn't exist before R600) */
1095         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1096         /* Update configuration */
1097         if (rdev->flags & RADEON_IS_AGP) {
1098                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1099                         /* VRAM before AGP */
1100                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1101                                 rdev->mc.vram_start >> 12);
1102                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1103                                 rdev->mc.gtt_end >> 12);
1104                 } else {
1105                         /* VRAM after AGP */
1106                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1107                                 rdev->mc.gtt_start >> 12);
1108                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1109                                 rdev->mc.vram_end >> 12);
1110                 }
1111         } else {
1112                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1113                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1114         }
1115         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1116         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1117         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1118         WREG32(MC_VM_FB_LOCATION, tmp);
1119         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1120         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1121         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1122         if (rdev->flags & RADEON_IS_AGP) {
1123                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1124                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1125                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1126         } else {
1127                 WREG32(MC_VM_AGP_BASE, 0);
1128                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1129                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1130         }
1131         if (r600_mc_wait_for_idle(rdev)) {
1132                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1133         }
1134         rv515_mc_resume(rdev, &save);
1135         /* we need to own VRAM, so turn off the VGA renderer here
1136          * to stop it overwriting our objects */
1137         rv515_vga_render_disable(rdev);
1138 }
1139
1140 /**
1141  * r600_vram_gtt_location - try to find VRAM & GTT location
1142  * @rdev: radeon device structure holding all necessary informations
1143  * @mc: memory controller structure holding memory informations
1144  *
1145  * Function will place try to place VRAM at same place as in CPU (PCI)
1146  * address space as some GPU seems to have issue when we reprogram at
1147  * different address space.
1148  *
1149  * If there is not enough space to fit the unvisible VRAM after the
1150  * aperture then we limit the VRAM size to the aperture.
1151  *
1152  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1153  * them to be in one from GPU point of view so that we can program GPU to
1154  * catch access outside them (weird GPU policy see ??).
1155  *
1156  * This function will never fails, worst case are limiting VRAM or GTT.
1157  *
1158  * Note: GTT start, end, size should be initialized before calling this
1159  * function on AGP platform.
1160  */
1161 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1162 {
1163         u64 size_bf, size_af;
1164
1165         if (mc->mc_vram_size > 0xE0000000) {
1166                 /* leave room for at least 512M GTT */
1167                 dev_warn(rdev->dev, "limiting VRAM\n");
1168                 mc->real_vram_size = 0xE0000000;
1169                 mc->mc_vram_size = 0xE0000000;
1170         }
1171         if (rdev->flags & RADEON_IS_AGP) {
1172                 size_bf = mc->gtt_start;
1173                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1174                 if (size_bf > size_af) {
1175                         if (mc->mc_vram_size > size_bf) {
1176                                 dev_warn(rdev->dev, "limiting VRAM\n");
1177                                 mc->real_vram_size = size_bf;
1178                                 mc->mc_vram_size = size_bf;
1179                         }
1180                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1181                 } else {
1182                         if (mc->mc_vram_size > size_af) {
1183                                 dev_warn(rdev->dev, "limiting VRAM\n");
1184                                 mc->real_vram_size = size_af;
1185                                 mc->mc_vram_size = size_af;
1186                         }
1187                         mc->vram_start = mc->gtt_end;
1188                 }
1189                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1190                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1191                                 mc->mc_vram_size >> 20, mc->vram_start,
1192                                 mc->vram_end, mc->real_vram_size >> 20);
1193         } else {
1194                 u64 base = 0;
1195                 if (rdev->flags & RADEON_IS_IGP) {
1196                         base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1197                         base <<= 24;
1198                 }
1199                 radeon_vram_location(rdev, &rdev->mc, base);
1200                 rdev->mc.gtt_base_align = 0;
1201                 radeon_gtt_location(rdev, mc);
1202         }
1203 }
1204
1205 int r600_mc_init(struct radeon_device *rdev)
1206 {
1207         u32 tmp;
1208         int chansize, numchan;
1209
1210         /* Get VRAM informations */
1211         rdev->mc.vram_is_ddr = true;
1212         tmp = RREG32(RAMCFG);
1213         if (tmp & CHANSIZE_OVERRIDE) {
1214                 chansize = 16;
1215         } else if (tmp & CHANSIZE_MASK) {
1216                 chansize = 64;
1217         } else {
1218                 chansize = 32;
1219         }
1220         tmp = RREG32(CHMAP);
1221         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1222         case 0:
1223         default:
1224                 numchan = 1;
1225                 break;
1226         case 1:
1227                 numchan = 2;
1228                 break;
1229         case 2:
1230                 numchan = 4;
1231                 break;
1232         case 3:
1233                 numchan = 8;
1234                 break;
1235         }
1236         rdev->mc.vram_width = numchan * chansize;
1237         /* Could aper size report 0 ? */
1238         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1239         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1240         /* Setup GPU memory space */
1241         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1242         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1243         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1244         r600_vram_gtt_location(rdev, &rdev->mc);
1245
1246         if (rdev->flags & RADEON_IS_IGP) {
1247                 rs690_pm_info(rdev);
1248                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1249         }
1250         radeon_update_bandwidth_info(rdev);
1251         return 0;
1252 }
1253
1254 int r600_vram_scratch_init(struct radeon_device *rdev)
1255 {
1256         int r;
1257
1258         if (rdev->vram_scratch.robj == NULL) {
1259                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1260                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1261                                      &rdev->vram_scratch.robj);
1262                 if (r) {
1263                         return r;
1264                 }
1265         }
1266
1267         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1268         if (unlikely(r != 0))
1269                 return r;
1270         r = radeon_bo_pin(rdev->vram_scratch.robj,
1271                           RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1272         if (r) {
1273                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1274                 return r;
1275         }
1276         r = radeon_bo_kmap(rdev->vram_scratch.robj,
1277                                 (void **)&rdev->vram_scratch.ptr);
1278         if (r)
1279                 radeon_bo_unpin(rdev->vram_scratch.robj);
1280         radeon_bo_unreserve(rdev->vram_scratch.robj);
1281
1282         return r;
1283 }
1284
1285 void r600_vram_scratch_fini(struct radeon_device *rdev)
1286 {
1287         int r;
1288
1289         if (rdev->vram_scratch.robj == NULL) {
1290                 return;
1291         }
1292         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1293         if (likely(r == 0)) {
1294                 radeon_bo_kunmap(rdev->vram_scratch.robj);
1295                 radeon_bo_unpin(rdev->vram_scratch.robj);
1296                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1297         }
1298         radeon_bo_unref(&rdev->vram_scratch.robj);
1299 }
1300
1301 /* We doesn't check that the GPU really needs a reset we simply do the
1302  * reset, it's up to the caller to determine if the GPU needs one. We
1303  * might add an helper function to check that.
1304  */
1305 int r600_gpu_soft_reset(struct radeon_device *rdev)
1306 {
1307         struct rv515_mc_save save;
1308         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1309                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1310                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1311                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1312                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1313                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1314                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1315                                 S_008010_GUI_ACTIVE(1);
1316         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1317                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1318                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1319                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1320                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1321                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1322                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1323                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1324         u32 tmp;
1325
1326         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1327                 return 0;
1328
1329         dev_info(rdev->dev, "GPU softreset \n");
1330         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1331                 RREG32(R_008010_GRBM_STATUS));
1332         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1333                 RREG32(R_008014_GRBM_STATUS2));
1334         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1335                 RREG32(R_000E50_SRBM_STATUS));
1336         rv515_mc_stop(rdev, &save);
1337         if (r600_mc_wait_for_idle(rdev)) {
1338                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1339         }
1340         /* Disable CP parsing/prefetching */
1341         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1342         /* Check if any of the rendering block is busy and reset it */
1343         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1344             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1345                 tmp = S_008020_SOFT_RESET_CR(1) |
1346                         S_008020_SOFT_RESET_DB(1) |
1347                         S_008020_SOFT_RESET_CB(1) |
1348                         S_008020_SOFT_RESET_PA(1) |
1349                         S_008020_SOFT_RESET_SC(1) |
1350                         S_008020_SOFT_RESET_SMX(1) |
1351                         S_008020_SOFT_RESET_SPI(1) |
1352                         S_008020_SOFT_RESET_SX(1) |
1353                         S_008020_SOFT_RESET_SH(1) |
1354                         S_008020_SOFT_RESET_TC(1) |
1355                         S_008020_SOFT_RESET_TA(1) |
1356                         S_008020_SOFT_RESET_VC(1) |
1357                         S_008020_SOFT_RESET_VGT(1);
1358                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1359                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1360                 RREG32(R_008020_GRBM_SOFT_RESET);
1361                 mdelay(15);
1362                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1363         }
1364         /* Reset CP (we always reset CP) */
1365         tmp = S_008020_SOFT_RESET_CP(1);
1366         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1367         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1368         RREG32(R_008020_GRBM_SOFT_RESET);
1369         mdelay(15);
1370         WREG32(R_008020_GRBM_SOFT_RESET, 0);
1371         /* Wait a little for things to settle down */
1372         mdelay(1);
1373         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1374                 RREG32(R_008010_GRBM_STATUS));
1375         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1376                 RREG32(R_008014_GRBM_STATUS2));
1377         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1378                 RREG32(R_000E50_SRBM_STATUS));
1379         rv515_mc_resume(rdev, &save);
1380         return 0;
1381 }
1382
1383 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1384 {
1385         u32 srbm_status;
1386         u32 grbm_status;
1387         u32 grbm_status2;
1388         struct r100_gpu_lockup *lockup;
1389         int r;
1390
1391         if (rdev->family >= CHIP_RV770)
1392                 lockup = &rdev->config.rv770.lockup;
1393         else
1394                 lockup = &rdev->config.r600.lockup;
1395
1396         srbm_status = RREG32(R_000E50_SRBM_STATUS);
1397         grbm_status = RREG32(R_008010_GRBM_STATUS);
1398         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1399         if (!G_008010_GUI_ACTIVE(grbm_status)) {
1400                 r100_gpu_lockup_update(lockup, &rdev->cp);
1401                 return false;
1402         }
1403         /* force CP activities */
1404         r = radeon_ring_lock(rdev, 2);
1405         if (!r) {
1406                 /* PACKET2 NOP */
1407                 radeon_ring_write(rdev, 0x80000000);
1408                 radeon_ring_write(rdev, 0x80000000);
1409                 radeon_ring_unlock_commit(rdev);
1410         }
1411         rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1412         return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
1413 }
1414
1415 int r600_asic_reset(struct radeon_device *rdev)
1416 {
1417         return r600_gpu_soft_reset(rdev);
1418 }
1419
1420 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1421                                              u32 num_backends,
1422                                              u32 backend_disable_mask)
1423 {
1424         u32 backend_map = 0;
1425         u32 enabled_backends_mask;
1426         u32 enabled_backends_count;
1427         u32 cur_pipe;
1428         u32 swizzle_pipe[R6XX_MAX_PIPES];
1429         u32 cur_backend;
1430         u32 i;
1431
1432         if (num_tile_pipes > R6XX_MAX_PIPES)
1433                 num_tile_pipes = R6XX_MAX_PIPES;
1434         if (num_tile_pipes < 1)
1435                 num_tile_pipes = 1;
1436         if (num_backends > R6XX_MAX_BACKENDS)
1437                 num_backends = R6XX_MAX_BACKENDS;
1438         if (num_backends < 1)
1439                 num_backends = 1;
1440
1441         enabled_backends_mask = 0;
1442         enabled_backends_count = 0;
1443         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1444                 if (((backend_disable_mask >> i) & 1) == 0) {
1445                         enabled_backends_mask |= (1 << i);
1446                         ++enabled_backends_count;
1447                 }
1448                 if (enabled_backends_count == num_backends)
1449                         break;
1450         }
1451
1452         if (enabled_backends_count == 0) {
1453                 enabled_backends_mask = 1;
1454                 enabled_backends_count = 1;
1455         }
1456
1457         if (enabled_backends_count != num_backends)
1458                 num_backends = enabled_backends_count;
1459
1460         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1461         switch (num_tile_pipes) {
1462         case 1:
1463                 swizzle_pipe[0] = 0;
1464                 break;
1465         case 2:
1466                 swizzle_pipe[0] = 0;
1467                 swizzle_pipe[1] = 1;
1468                 break;
1469         case 3:
1470                 swizzle_pipe[0] = 0;
1471                 swizzle_pipe[1] = 1;
1472                 swizzle_pipe[2] = 2;
1473                 break;
1474         case 4:
1475                 swizzle_pipe[0] = 0;
1476                 swizzle_pipe[1] = 1;
1477                 swizzle_pipe[2] = 2;
1478                 swizzle_pipe[3] = 3;
1479                 break;
1480         case 5:
1481                 swizzle_pipe[0] = 0;
1482                 swizzle_pipe[1] = 1;
1483                 swizzle_pipe[2] = 2;
1484                 swizzle_pipe[3] = 3;
1485                 swizzle_pipe[4] = 4;
1486                 break;
1487         case 6:
1488                 swizzle_pipe[0] = 0;
1489                 swizzle_pipe[1] = 2;
1490                 swizzle_pipe[2] = 4;
1491                 swizzle_pipe[3] = 5;
1492                 swizzle_pipe[4] = 1;
1493                 swizzle_pipe[5] = 3;
1494                 break;
1495         case 7:
1496                 swizzle_pipe[0] = 0;
1497                 swizzle_pipe[1] = 2;
1498                 swizzle_pipe[2] = 4;
1499                 swizzle_pipe[3] = 6;
1500                 swizzle_pipe[4] = 1;
1501                 swizzle_pipe[5] = 3;
1502                 swizzle_pipe[6] = 5;
1503                 break;
1504         case 8:
1505                 swizzle_pipe[0] = 0;
1506                 swizzle_pipe[1] = 2;
1507                 swizzle_pipe[2] = 4;
1508                 swizzle_pipe[3] = 6;
1509                 swizzle_pipe[4] = 1;
1510                 swizzle_pipe[5] = 3;
1511                 swizzle_pipe[6] = 5;
1512                 swizzle_pipe[7] = 7;
1513                 break;
1514         }
1515
1516         cur_backend = 0;
1517         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1518                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1519                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1520
1521                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1522
1523                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1524         }
1525
1526         return backend_map;
1527 }
1528
1529 int r600_count_pipe_bits(uint32_t val)
1530 {
1531         int i, ret = 0;
1532
1533         for (i = 0; i < 32; i++) {
1534                 ret += val & 1;
1535                 val >>= 1;
1536         }
1537         return ret;
1538 }
1539
1540 void r600_gpu_init(struct radeon_device *rdev)
1541 {
1542         u32 tiling_config;
1543         u32 ramcfg;
1544         u32 backend_map;
1545         u32 cc_rb_backend_disable;
1546         u32 cc_gc_shader_pipe_config;
1547         u32 tmp;
1548         int i, j;
1549         u32 sq_config;
1550         u32 sq_gpr_resource_mgmt_1 = 0;
1551         u32 sq_gpr_resource_mgmt_2 = 0;
1552         u32 sq_thread_resource_mgmt = 0;
1553         u32 sq_stack_resource_mgmt_1 = 0;
1554         u32 sq_stack_resource_mgmt_2 = 0;
1555
1556         /* FIXME: implement */
1557         switch (rdev->family) {
1558         case CHIP_R600:
1559                 rdev->config.r600.max_pipes = 4;
1560                 rdev->config.r600.max_tile_pipes = 8;
1561                 rdev->config.r600.max_simds = 4;
1562                 rdev->config.r600.max_backends = 4;
1563                 rdev->config.r600.max_gprs = 256;
1564                 rdev->config.r600.max_threads = 192;
1565                 rdev->config.r600.max_stack_entries = 256;
1566                 rdev->config.r600.max_hw_contexts = 8;
1567                 rdev->config.r600.max_gs_threads = 16;
1568                 rdev->config.r600.sx_max_export_size = 128;
1569                 rdev->config.r600.sx_max_export_pos_size = 16;
1570                 rdev->config.r600.sx_max_export_smx_size = 128;
1571                 rdev->config.r600.sq_num_cf_insts = 2;
1572                 break;
1573         case CHIP_RV630:
1574         case CHIP_RV635:
1575                 rdev->config.r600.max_pipes = 2;
1576                 rdev->config.r600.max_tile_pipes = 2;
1577                 rdev->config.r600.max_simds = 3;
1578                 rdev->config.r600.max_backends = 1;
1579                 rdev->config.r600.max_gprs = 128;
1580                 rdev->config.r600.max_threads = 192;
1581                 rdev->config.r600.max_stack_entries = 128;
1582                 rdev->config.r600.max_hw_contexts = 8;
1583                 rdev->config.r600.max_gs_threads = 4;
1584                 rdev->config.r600.sx_max_export_size = 128;
1585                 rdev->config.r600.sx_max_export_pos_size = 16;
1586                 rdev->config.r600.sx_max_export_smx_size = 128;
1587                 rdev->config.r600.sq_num_cf_insts = 2;
1588                 break;
1589         case CHIP_RV610:
1590         case CHIP_RV620:
1591         case CHIP_RS780:
1592         case CHIP_RS880:
1593                 rdev->config.r600.max_pipes = 1;
1594                 rdev->config.r600.max_tile_pipes = 1;
1595                 rdev->config.r600.max_simds = 2;
1596                 rdev->config.r600.max_backends = 1;
1597                 rdev->config.r600.max_gprs = 128;
1598                 rdev->config.r600.max_threads = 192;
1599                 rdev->config.r600.max_stack_entries = 128;
1600                 rdev->config.r600.max_hw_contexts = 4;
1601                 rdev->config.r600.max_gs_threads = 4;
1602                 rdev->config.r600.sx_max_export_size = 128;
1603                 rdev->config.r600.sx_max_export_pos_size = 16;
1604                 rdev->config.r600.sx_max_export_smx_size = 128;
1605                 rdev->config.r600.sq_num_cf_insts = 1;
1606                 break;
1607         case CHIP_RV670:
1608                 rdev->config.r600.max_pipes = 4;
1609                 rdev->config.r600.max_tile_pipes = 4;
1610                 rdev->config.r600.max_simds = 4;
1611                 rdev->config.r600.max_backends = 4;
1612                 rdev->config.r600.max_gprs = 192;
1613                 rdev->config.r600.max_threads = 192;
1614                 rdev->config.r600.max_stack_entries = 256;
1615                 rdev->config.r600.max_hw_contexts = 8;
1616                 rdev->config.r600.max_gs_threads = 16;
1617                 rdev->config.r600.sx_max_export_size = 128;
1618                 rdev->config.r600.sx_max_export_pos_size = 16;
1619                 rdev->config.r600.sx_max_export_smx_size = 128;
1620                 rdev->config.r600.sq_num_cf_insts = 2;
1621                 break;
1622         default:
1623                 break;
1624         }
1625
1626         /* Initialize HDP */
1627         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1628                 WREG32((0x2c14 + j), 0x00000000);
1629                 WREG32((0x2c18 + j), 0x00000000);
1630                 WREG32((0x2c1c + j), 0x00000000);
1631                 WREG32((0x2c20 + j), 0x00000000);
1632                 WREG32((0x2c24 + j), 0x00000000);
1633         }
1634
1635         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1636
1637         /* Setup tiling */
1638         tiling_config = 0;
1639         ramcfg = RREG32(RAMCFG);
1640         switch (rdev->config.r600.max_tile_pipes) {
1641         case 1:
1642                 tiling_config |= PIPE_TILING(0);
1643                 break;
1644         case 2:
1645                 tiling_config |= PIPE_TILING(1);
1646                 break;
1647         case 4:
1648                 tiling_config |= PIPE_TILING(2);
1649                 break;
1650         case 8:
1651                 tiling_config |= PIPE_TILING(3);
1652                 break;
1653         default:
1654                 break;
1655         }
1656         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1657         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1658         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1659         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1660         if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
1661                 rdev->config.r600.tiling_group_size = 512;
1662         else
1663                 rdev->config.r600.tiling_group_size = 256;
1664         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1665         if (tmp > 3) {
1666                 tiling_config |= ROW_TILING(3);
1667                 tiling_config |= SAMPLE_SPLIT(3);
1668         } else {
1669                 tiling_config |= ROW_TILING(tmp);
1670                 tiling_config |= SAMPLE_SPLIT(tmp);
1671         }
1672         tiling_config |= BANK_SWAPS(1);
1673
1674         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1675         cc_rb_backend_disable |=
1676                 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1677
1678         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1679         cc_gc_shader_pipe_config |=
1680                 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1681         cc_gc_shader_pipe_config |=
1682                 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1683
1684         backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1685                                                         (R6XX_MAX_BACKENDS -
1686                                                          r600_count_pipe_bits((cc_rb_backend_disable &
1687                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
1688                                                         (cc_rb_backend_disable >> 16));
1689         rdev->config.r600.tile_config = tiling_config;
1690         rdev->config.r600.backend_map = backend_map;
1691         tiling_config |= BACKEND_MAP(backend_map);
1692         WREG32(GB_TILING_CONFIG, tiling_config);
1693         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1694         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1695
1696         /* Setup pipes */
1697         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1698         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1699         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1700
1701         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1702         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1703         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1704
1705         /* Setup some CP states */
1706         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1707         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1708
1709         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1710                              SYNC_WALKER | SYNC_ALIGNER));
1711         /* Setup various GPU states */
1712         if (rdev->family == CHIP_RV670)
1713                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1714
1715         tmp = RREG32(SX_DEBUG_1);
1716         tmp |= SMX_EVENT_RELEASE;
1717         if ((rdev->family > CHIP_R600))
1718                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1719         WREG32(SX_DEBUG_1, tmp);
1720
1721         if (((rdev->family) == CHIP_R600) ||
1722             ((rdev->family) == CHIP_RV630) ||
1723             ((rdev->family) == CHIP_RV610) ||
1724             ((rdev->family) == CHIP_RV620) ||
1725             ((rdev->family) == CHIP_RS780) ||
1726             ((rdev->family) == CHIP_RS880)) {
1727                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1728         } else {
1729                 WREG32(DB_DEBUG, 0);
1730         }
1731         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1732                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1733
1734         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1735         WREG32(VGT_NUM_INSTANCES, 0);
1736
1737         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1738         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1739
1740         tmp = RREG32(SQ_MS_FIFO_SIZES);
1741         if (((rdev->family) == CHIP_RV610) ||
1742             ((rdev->family) == CHIP_RV620) ||
1743             ((rdev->family) == CHIP_RS780) ||
1744             ((rdev->family) == CHIP_RS880)) {
1745                 tmp = (CACHE_FIFO_SIZE(0xa) |
1746                        FETCH_FIFO_HIWATER(0xa) |
1747                        DONE_FIFO_HIWATER(0xe0) |
1748                        ALU_UPDATE_FIFO_HIWATER(0x8));
1749         } else if (((rdev->family) == CHIP_R600) ||
1750                    ((rdev->family) == CHIP_RV630)) {
1751                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1752                 tmp |= DONE_FIFO_HIWATER(0x4);
1753         }
1754         WREG32(SQ_MS_FIFO_SIZES, tmp);
1755
1756         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1757          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1758          */
1759         sq_config = RREG32(SQ_CONFIG);
1760         sq_config &= ~(PS_PRIO(3) |
1761                        VS_PRIO(3) |
1762                        GS_PRIO(3) |
1763                        ES_PRIO(3));
1764         sq_config |= (DX9_CONSTS |
1765                       VC_ENABLE |
1766                       PS_PRIO(0) |
1767                       VS_PRIO(1) |
1768                       GS_PRIO(2) |
1769                       ES_PRIO(3));
1770
1771         if ((rdev->family) == CHIP_R600) {
1772                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1773                                           NUM_VS_GPRS(124) |
1774                                           NUM_CLAUSE_TEMP_GPRS(4));
1775                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1776                                           NUM_ES_GPRS(0));
1777                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1778                                            NUM_VS_THREADS(48) |
1779                                            NUM_GS_THREADS(4) |
1780                                            NUM_ES_THREADS(4));
1781                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1782                                             NUM_VS_STACK_ENTRIES(128));
1783                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1784                                             NUM_ES_STACK_ENTRIES(0));
1785         } else if (((rdev->family) == CHIP_RV610) ||
1786                    ((rdev->family) == CHIP_RV620) ||
1787                    ((rdev->family) == CHIP_RS780) ||
1788                    ((rdev->family) == CHIP_RS880)) {
1789                 /* no vertex cache */
1790                 sq_config &= ~VC_ENABLE;
1791
1792                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1793                                           NUM_VS_GPRS(44) |
1794                                           NUM_CLAUSE_TEMP_GPRS(2));
1795                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1796                                           NUM_ES_GPRS(17));
1797                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1798                                            NUM_VS_THREADS(78) |
1799                                            NUM_GS_THREADS(4) |
1800                                            NUM_ES_THREADS(31));
1801                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1802                                             NUM_VS_STACK_ENTRIES(40));
1803                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1804                                             NUM_ES_STACK_ENTRIES(16));
1805         } else if (((rdev->family) == CHIP_RV630) ||
1806                    ((rdev->family) == CHIP_RV635)) {
1807                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1808                                           NUM_VS_GPRS(44) |
1809                                           NUM_CLAUSE_TEMP_GPRS(2));
1810                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1811                                           NUM_ES_GPRS(18));
1812                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1813                                            NUM_VS_THREADS(78) |
1814                                            NUM_GS_THREADS(4) |
1815                                            NUM_ES_THREADS(31));
1816                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1817                                             NUM_VS_STACK_ENTRIES(40));
1818                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1819                                             NUM_ES_STACK_ENTRIES(16));
1820         } else if ((rdev->family) == CHIP_RV670) {
1821                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1822                                           NUM_VS_GPRS(44) |
1823                                           NUM_CLAUSE_TEMP_GPRS(2));
1824                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1825                                           NUM_ES_GPRS(17));
1826                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1827                                            NUM_VS_THREADS(78) |
1828                                            NUM_GS_THREADS(4) |
1829                                            NUM_ES_THREADS(31));
1830                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1831                                             NUM_VS_STACK_ENTRIES(64));
1832                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1833                                             NUM_ES_STACK_ENTRIES(64));
1834         }
1835
1836         WREG32(SQ_CONFIG, sq_config);
1837         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1838         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1839         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1840         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1841         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1842
1843         if (((rdev->family) == CHIP_RV610) ||
1844             ((rdev->family) == CHIP_RV620) ||
1845             ((rdev->family) == CHIP_RS780) ||
1846             ((rdev->family) == CHIP_RS880)) {
1847                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1848         } else {
1849                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1850         }
1851
1852         /* More default values. 2D/3D driver should adjust as needed */
1853         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1854                                          S1_X(0x4) | S1_Y(0xc)));
1855         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1856                                          S1_X(0x2) | S1_Y(0x2) |
1857                                          S2_X(0xa) | S2_Y(0x6) |
1858                                          S3_X(0x6) | S3_Y(0xa)));
1859         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1860                                              S1_X(0x4) | S1_Y(0xc) |
1861                                              S2_X(0x1) | S2_Y(0x6) |
1862                                              S3_X(0xa) | S3_Y(0xe)));
1863         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1864                                              S5_X(0x0) | S5_Y(0x0) |
1865                                              S6_X(0xb) | S6_Y(0x4) |
1866                                              S7_X(0x7) | S7_Y(0x8)));
1867
1868         WREG32(VGT_STRMOUT_EN, 0);
1869         tmp = rdev->config.r600.max_pipes * 16;
1870         switch (rdev->family) {
1871         case CHIP_RV610:
1872         case CHIP_RV620:
1873         case CHIP_RS780:
1874         case CHIP_RS880:
1875                 tmp += 32;
1876                 break;
1877         case CHIP_RV670:
1878                 tmp += 128;
1879                 break;
1880         default:
1881                 break;
1882         }
1883         if (tmp > 256) {
1884                 tmp = 256;
1885         }
1886         WREG32(VGT_ES_PER_GS, 128);
1887         WREG32(VGT_GS_PER_ES, tmp);
1888         WREG32(VGT_GS_PER_VS, 2);
1889         WREG32(VGT_GS_VERTEX_REUSE, 16);
1890
1891         /* more default values. 2D/3D driver should adjust as needed */
1892         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1893         WREG32(VGT_STRMOUT_EN, 0);
1894         WREG32(SX_MISC, 0);
1895         WREG32(PA_SC_MODE_CNTL, 0);
1896         WREG32(PA_SC_AA_CONFIG, 0);
1897         WREG32(PA_SC_LINE_STIPPLE, 0);
1898         WREG32(SPI_INPUT_Z, 0);
1899         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1900         WREG32(CB_COLOR7_FRAG, 0);
1901
1902         /* Clear render buffer base addresses */
1903         WREG32(CB_COLOR0_BASE, 0);
1904         WREG32(CB_COLOR1_BASE, 0);
1905         WREG32(CB_COLOR2_BASE, 0);
1906         WREG32(CB_COLOR3_BASE, 0);
1907         WREG32(CB_COLOR4_BASE, 0);
1908         WREG32(CB_COLOR5_BASE, 0);
1909         WREG32(CB_COLOR6_BASE, 0);
1910         WREG32(CB_COLOR7_BASE, 0);
1911         WREG32(CB_COLOR7_FRAG, 0);
1912
1913         switch (rdev->family) {
1914         case CHIP_RV610:
1915         case CHIP_RV620:
1916         case CHIP_RS780:
1917         case CHIP_RS880:
1918                 tmp = TC_L2_SIZE(8);
1919                 break;
1920         case CHIP_RV630:
1921         case CHIP_RV635:
1922                 tmp = TC_L2_SIZE(4);
1923                 break;
1924         case CHIP_R600:
1925                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1926                 break;
1927         default:
1928                 tmp = TC_L2_SIZE(0);
1929                 break;
1930         }
1931         WREG32(TC_CNTL, tmp);
1932
1933         tmp = RREG32(HDP_HOST_PATH_CNTL);
1934         WREG32(HDP_HOST_PATH_CNTL, tmp);
1935
1936         tmp = RREG32(ARB_POP);
1937         tmp |= ENABLE_TC128;
1938         WREG32(ARB_POP, tmp);
1939
1940         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1941         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1942                                NUM_CLIP_SEQ(3)));
1943         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1944 }
1945
1946
1947 /*
1948  * Indirect registers accessor
1949  */
1950 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1951 {
1952         u32 r;
1953
1954         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1955         (void)RREG32(PCIE_PORT_INDEX);
1956         r = RREG32(PCIE_PORT_DATA);
1957         return r;
1958 }
1959
1960 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1961 {
1962         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1963         (void)RREG32(PCIE_PORT_INDEX);
1964         WREG32(PCIE_PORT_DATA, (v));
1965         (void)RREG32(PCIE_PORT_DATA);
1966 }
1967
1968 /*
1969  * CP & Ring
1970  */
1971 void r600_cp_stop(struct radeon_device *rdev)
1972 {
1973         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1974         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1975         WREG32(SCRATCH_UMSK, 0);
1976 }
1977
1978 int r600_init_microcode(struct radeon_device *rdev)
1979 {
1980         struct platform_device *pdev;
1981         const char *chip_name;
1982         const char *rlc_chip_name;
1983         size_t pfp_req_size, me_req_size, rlc_req_size;
1984         char fw_name[30];
1985         int err;
1986
1987         DRM_DEBUG("\n");
1988
1989         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1990         err = IS_ERR(pdev);
1991         if (err) {
1992                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1993                 return -EINVAL;
1994         }
1995
1996         switch (rdev->family) {
1997         case CHIP_R600:
1998                 chip_name = "R600";
1999                 rlc_chip_name = "R600";
2000                 break;
2001         case CHIP_RV610:
2002                 chip_name = "RV610";
2003                 rlc_chip_name = "R600";
2004                 break;
2005         case CHIP_RV630:
2006                 chip_name = "RV630";
2007                 rlc_chip_name = "R600";
2008                 break;
2009         case CHIP_RV620:
2010                 chip_name = "RV620";
2011                 rlc_chip_name = "R600";
2012                 break;
2013         case CHIP_RV635:
2014                 chip_name = "RV635";
2015                 rlc_chip_name = "R600";
2016                 break;
2017         case CHIP_RV670:
2018                 chip_name = "RV670";
2019                 rlc_chip_name = "R600";
2020                 break;
2021         case CHIP_RS780:
2022         case CHIP_RS880:
2023                 chip_name = "RS780";
2024                 rlc_chip_name = "R600";
2025                 break;
2026         case CHIP_RV770:
2027                 chip_name = "RV770";
2028                 rlc_chip_name = "R700";
2029                 break;
2030         case CHIP_RV730:
2031         case CHIP_RV740:
2032                 chip_name = "RV730";
2033                 rlc_chip_name = "R700";
2034                 break;
2035         case CHIP_RV710:
2036                 chip_name = "RV710";
2037                 rlc_chip_name = "R700";
2038                 break;
2039         case CHIP_CEDAR:
2040                 chip_name = "CEDAR";
2041                 rlc_chip_name = "CEDAR";
2042                 break;
2043         case CHIP_REDWOOD:
2044                 chip_name = "REDWOOD";
2045                 rlc_chip_name = "REDWOOD";
2046                 break;
2047         case CHIP_JUNIPER:
2048                 chip_name = "JUNIPER";
2049                 rlc_chip_name = "JUNIPER";
2050                 break;
2051         case CHIP_CYPRESS:
2052         case CHIP_HEMLOCK:
2053                 chip_name = "CYPRESS";
2054                 rlc_chip_name = "CYPRESS";
2055                 break;
2056         case CHIP_PALM:
2057                 chip_name = "PALM";
2058                 rlc_chip_name = "SUMO";
2059                 break;
2060         case CHIP_SUMO:
2061                 chip_name = "SUMO";
2062                 rlc_chip_name = "SUMO";
2063                 break;
2064         case CHIP_SUMO2:
2065                 chip_name = "SUMO2";
2066                 rlc_chip_name = "SUMO";
2067                 break;
2068         default: BUG();
2069         }
2070
2071         if (rdev->family >= CHIP_CEDAR) {
2072                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2073                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2074                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2075         } else if (rdev->family >= CHIP_RV770) {
2076                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2077                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2078                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2079         } else {
2080                 pfp_req_size = PFP_UCODE_SIZE * 4;
2081                 me_req_size = PM4_UCODE_SIZE * 12;
2082                 rlc_req_size = RLC_UCODE_SIZE * 4;
2083         }
2084
2085         DRM_INFO("Loading %s Microcode\n", chip_name);
2086
2087         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2088         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2089         if (err)
2090                 goto out;
2091         if (rdev->pfp_fw->size != pfp_req_size) {
2092                 printk(KERN_ERR
2093                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2094                        rdev->pfp_fw->size, fw_name);
2095                 err = -EINVAL;
2096                 goto out;
2097         }
2098
2099         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2100         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2101         if (err)
2102                 goto out;
2103         if (rdev->me_fw->size != me_req_size) {
2104                 printk(KERN_ERR
2105                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2106                        rdev->me_fw->size, fw_name);
2107                 err = -EINVAL;
2108         }
2109
2110         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2111         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2112         if (err)
2113                 goto out;
2114         if (rdev->rlc_fw->size != rlc_req_size) {
2115                 printk(KERN_ERR
2116                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2117                        rdev->rlc_fw->size, fw_name);
2118                 err = -EINVAL;
2119         }
2120
2121 out:
2122         platform_device_unregister(pdev);
2123
2124         if (err) {
2125                 if (err != -EINVAL)
2126                         printk(KERN_ERR
2127                                "r600_cp: Failed to load firmware \"%s\"\n",
2128                                fw_name);
2129                 release_firmware(rdev->pfp_fw);
2130                 rdev->pfp_fw = NULL;
2131                 release_firmware(rdev->me_fw);
2132                 rdev->me_fw = NULL;
2133                 release_firmware(rdev->rlc_fw);
2134                 rdev->rlc_fw = NULL;
2135         }
2136         return err;
2137 }
2138
2139 static int r600_cp_load_microcode(struct radeon_device *rdev)
2140 {
2141         const __be32 *fw_data;
2142         int i;
2143
2144         if (!rdev->me_fw || !rdev->pfp_fw)
2145                 return -EINVAL;
2146
2147         r600_cp_stop(rdev);
2148
2149         WREG32(CP_RB_CNTL,
2150 #ifdef __BIG_ENDIAN
2151                BUF_SWAP_32BIT |
2152 #endif
2153                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2154
2155         /* Reset cp */
2156         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2157         RREG32(GRBM_SOFT_RESET);
2158         mdelay(15);
2159         WREG32(GRBM_SOFT_RESET, 0);
2160
2161         WREG32(CP_ME_RAM_WADDR, 0);
2162
2163         fw_data = (const __be32 *)rdev->me_fw->data;
2164         WREG32(CP_ME_RAM_WADDR, 0);
2165         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2166                 WREG32(CP_ME_RAM_DATA,
2167                        be32_to_cpup(fw_data++));
2168
2169         fw_data = (const __be32 *)rdev->pfp_fw->data;
2170         WREG32(CP_PFP_UCODE_ADDR, 0);
2171         for (i = 0; i < PFP_UCODE_SIZE; i++)
2172                 WREG32(CP_PFP_UCODE_DATA,
2173                        be32_to_cpup(fw_data++));
2174
2175         WREG32(CP_PFP_UCODE_ADDR, 0);
2176         WREG32(CP_ME_RAM_WADDR, 0);
2177         WREG32(CP_ME_RAM_RADDR, 0);
2178         return 0;
2179 }
2180
2181 int r600_cp_start(struct radeon_device *rdev)
2182 {
2183         int r;
2184         uint32_t cp_me;
2185
2186         r = radeon_ring_lock(rdev, 7);
2187         if (r) {
2188                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2189                 return r;
2190         }
2191         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2192         radeon_ring_write(rdev, 0x1);
2193         if (rdev->family >= CHIP_RV770) {
2194                 radeon_ring_write(rdev, 0x0);
2195                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2196         } else {
2197                 radeon_ring_write(rdev, 0x3);
2198                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
2199         }
2200         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2201         radeon_ring_write(rdev, 0);
2202         radeon_ring_write(rdev, 0);
2203         radeon_ring_unlock_commit(rdev);
2204
2205         cp_me = 0xff;
2206         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2207         return 0;
2208 }
2209
2210 int r600_cp_resume(struct radeon_device *rdev)
2211 {
2212         u32 tmp;
2213         u32 rb_bufsz;
2214         int r;
2215
2216         /* Reset cp */
2217         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2218         RREG32(GRBM_SOFT_RESET);
2219         mdelay(15);
2220         WREG32(GRBM_SOFT_RESET, 0);
2221
2222         /* Set ring buffer size */
2223         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
2224         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2225 #ifdef __BIG_ENDIAN
2226         tmp |= BUF_SWAP_32BIT;
2227 #endif
2228         WREG32(CP_RB_CNTL, tmp);
2229         WREG32(CP_SEM_WAIT_TIMER, 0x4);
2230
2231         /* Set the write pointer delay */
2232         WREG32(CP_RB_WPTR_DELAY, 0);
2233
2234         /* Initialize the ring buffer's read and write pointers */
2235         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2236         WREG32(CP_RB_RPTR_WR, 0);
2237         rdev->cp.wptr = 0;
2238         WREG32(CP_RB_WPTR, rdev->cp.wptr);
2239
2240         /* set the wb address whether it's enabled or not */
2241         WREG32(CP_RB_RPTR_ADDR,
2242                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2243         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2244         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2245
2246         if (rdev->wb.enabled)
2247                 WREG32(SCRATCH_UMSK, 0xff);
2248         else {
2249                 tmp |= RB_NO_UPDATE;
2250                 WREG32(SCRATCH_UMSK, 0);
2251         }
2252
2253         mdelay(1);
2254         WREG32(CP_RB_CNTL, tmp);
2255
2256         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2257         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2258
2259         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2260
2261         r600_cp_start(rdev);
2262         rdev->cp.ready = true;
2263         r = radeon_ring_test(rdev);
2264         if (r) {
2265                 rdev->cp.ready = false;
2266                 return r;
2267         }
2268         return 0;
2269 }
2270
2271 void r600_cp_commit(struct radeon_device *rdev)
2272 {
2273         WREG32(CP_RB_WPTR, rdev->cp.wptr);
2274         (void)RREG32(CP_RB_WPTR);
2275 }
2276
2277 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2278 {
2279         u32 rb_bufsz;
2280
2281         /* Align ring size */
2282         rb_bufsz = drm_order(ring_size / 8);
2283         ring_size = (1 << (rb_bufsz + 1)) * 4;
2284         rdev->cp.ring_size = ring_size;
2285         rdev->cp.align_mask = 16 - 1;
2286 }
2287
2288 void r600_cp_fini(struct radeon_device *rdev)
2289 {
2290         r600_cp_stop(rdev);
2291         radeon_ring_fini(rdev);
2292 }
2293
2294
2295 /*
2296  * GPU scratch registers helpers function.
2297  */
2298 void r600_scratch_init(struct radeon_device *rdev)
2299 {
2300         int i;
2301
2302         rdev->scratch.num_reg = 7;
2303         rdev->scratch.reg_base = SCRATCH_REG0;
2304         for (i = 0; i < rdev->scratch.num_reg; i++) {
2305                 rdev->scratch.free[i] = true;
2306                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2307         }
2308 }
2309
2310 int r600_ring_test(struct radeon_device *rdev)
2311 {
2312         uint32_t scratch;
2313         uint32_t tmp = 0;
2314         unsigned i;
2315         int r;
2316
2317         r = radeon_scratch_get(rdev, &scratch);
2318         if (r) {
2319                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2320                 return r;
2321         }
2322         WREG32(scratch, 0xCAFEDEAD);
2323         r = radeon_ring_lock(rdev, 3);
2324         if (r) {
2325                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2326                 radeon_scratch_free(rdev, scratch);
2327                 return r;
2328         }
2329         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2330         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2331         radeon_ring_write(rdev, 0xDEADBEEF);
2332         radeon_ring_unlock_commit(rdev);
2333         for (i = 0; i < rdev->usec_timeout; i++) {
2334                 tmp = RREG32(scratch);
2335                 if (tmp == 0xDEADBEEF)
2336                         break;
2337                 DRM_UDELAY(1);
2338         }
2339         if (i < rdev->usec_timeout) {
2340                 DRM_INFO("ring test succeeded in %d usecs\n", i);
2341         } else {
2342                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2343                           scratch, tmp);
2344                 r = -EINVAL;
2345         }
2346         radeon_scratch_free(rdev, scratch);
2347         return r;
2348 }
2349
2350 void r600_fence_ring_emit(struct radeon_device *rdev,
2351                           struct radeon_fence *fence)
2352 {
2353         if (rdev->wb.use_event) {
2354                 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
2355                         (u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base);
2356                 /* flush read cache over gart */
2357                 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
2358                 radeon_ring_write(rdev, PACKET3_TC_ACTION_ENA |
2359                                         PACKET3_VC_ACTION_ENA |
2360                                         PACKET3_SH_ACTION_ENA);
2361                 radeon_ring_write(rdev, 0xFFFFFFFF);
2362                 radeon_ring_write(rdev, 0);
2363                 radeon_ring_write(rdev, 10); /* poll interval */
2364                 /* EVENT_WRITE_EOP - flush caches, send int */
2365                 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2366                 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2367                 radeon_ring_write(rdev, addr & 0xffffffff);
2368                 radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2369                 radeon_ring_write(rdev, fence->seq);
2370                 radeon_ring_write(rdev, 0);
2371         } else {
2372                 /* flush read cache over gart */
2373                 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
2374                 radeon_ring_write(rdev, PACKET3_TC_ACTION_ENA |
2375                                         PACKET3_VC_ACTION_ENA |
2376                                         PACKET3_SH_ACTION_ENA);
2377                 radeon_ring_write(rdev, 0xFFFFFFFF);
2378                 radeon_ring_write(rdev, 0);
2379                 radeon_ring_write(rdev, 10); /* poll interval */
2380                 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2381                 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2382                 /* wait for 3D idle clean */
2383                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2384                 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2385                 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2386                 /* Emit fence sequence & fire IRQ */
2387                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2388                 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2389                 radeon_ring_write(rdev, fence->seq);
2390                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2391                 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2392                 radeon_ring_write(rdev, RB_INT_STAT);
2393         }
2394 }
2395
2396 int r600_copy_blit(struct radeon_device *rdev,
2397                    uint64_t src_offset,
2398                    uint64_t dst_offset,
2399                    unsigned num_gpu_pages,
2400                    struct radeon_fence *fence)
2401 {
2402         int r;
2403
2404         mutex_lock(&rdev->r600_blit.mutex);
2405         rdev->r600_blit.vb_ib = NULL;
2406         r = r600_blit_prepare_copy(rdev, num_gpu_pages);
2407         if (r) {
2408                 if (rdev->r600_blit.vb_ib)
2409                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2410                 mutex_unlock(&rdev->r600_blit.mutex);
2411                 return r;
2412         }
2413         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages);
2414         r600_blit_done_copy(rdev, fence);
2415         mutex_unlock(&rdev->r600_blit.mutex);
2416         return 0;
2417 }
2418
2419 void r600_blit_suspend(struct radeon_device *rdev)
2420 {
2421         int r;
2422
2423         /* unpin shaders bo */
2424         if (rdev->r600_blit.shader_obj) {
2425                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2426                 if (!r) {
2427                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
2428                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2429                 }
2430         }
2431 }
2432
2433 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2434                          uint32_t tiling_flags, uint32_t pitch,
2435                          uint32_t offset, uint32_t obj_size)
2436 {
2437         /* FIXME: implement */
2438         return 0;
2439 }
2440
2441 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2442 {
2443         /* FIXME: implement */
2444 }
2445
2446 int r600_startup(struct radeon_device *rdev)
2447 {
2448         int r;
2449
2450         /* enable pcie gen2 link */
2451         r600_pcie_gen2_enable(rdev);
2452
2453         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2454                 r = r600_init_microcode(rdev);
2455                 if (r) {
2456                         DRM_ERROR("Failed to load firmware!\n");
2457                         return r;
2458                 }
2459         }
2460
2461         r = r600_vram_scratch_init(rdev);
2462         if (r)
2463                 return r;
2464
2465         r600_mc_program(rdev);
2466         if (rdev->flags & RADEON_IS_AGP) {
2467                 r600_agp_enable(rdev);
2468         } else {
2469                 r = r600_pcie_gart_enable(rdev);
2470                 if (r)
2471                         return r;
2472         }
2473         r600_gpu_init(rdev);
2474         r = r600_blit_init(rdev);
2475         if (r) {
2476                 r600_blit_fini(rdev);
2477                 rdev->asic->copy = NULL;
2478                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2479         }
2480
2481         /* allocate wb buffer */
2482         r = radeon_wb_init(rdev);
2483         if (r)
2484                 return r;
2485
2486         /* Enable IRQ */
2487         r = r600_irq_init(rdev);
2488         if (r) {
2489                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2490                 radeon_irq_kms_fini(rdev);
2491                 return r;
2492         }
2493         r600_irq_set(rdev);
2494
2495         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2496         if (r)
2497                 return r;
2498         r = r600_cp_load_microcode(rdev);
2499         if (r)
2500                 return r;
2501         r = r600_cp_resume(rdev);
2502         if (r)
2503                 return r;
2504
2505         return 0;
2506 }
2507
2508 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2509 {
2510         uint32_t temp;
2511
2512         temp = RREG32(CONFIG_CNTL);
2513         if (state == false) {
2514                 temp &= ~(1<<0);
2515                 temp |= (1<<1);
2516         } else {
2517                 temp &= ~(1<<1);
2518         }
2519         WREG32(CONFIG_CNTL, temp);
2520 }
2521
2522 int r600_resume(struct radeon_device *rdev)
2523 {
2524         int r;
2525
2526         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2527          * posting will perform necessary task to bring back GPU into good
2528          * shape.
2529          */
2530         /* post card */
2531         atom_asic_init(rdev->mode_info.atom_context);
2532
2533         r = r600_startup(rdev);
2534         if (r) {
2535                 DRM_ERROR("r600 startup failed on resume\n");
2536                 return r;
2537         }
2538
2539         r = r600_ib_test(rdev);
2540         if (r) {
2541                 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2542                 return r;
2543         }
2544
2545         r = r600_audio_init(rdev);
2546         if (r) {
2547                 DRM_ERROR("radeon: audio resume failed\n");
2548                 return r;
2549         }
2550
2551         return r;
2552 }
2553
2554 int r600_suspend(struct radeon_device *rdev)
2555 {
2556         r600_audio_fini(rdev);
2557         /* FIXME: we should wait for ring to be empty */
2558         r600_cp_stop(rdev);
2559         rdev->cp.ready = false;
2560         r600_irq_suspend(rdev);
2561         radeon_wb_disable(rdev);
2562         r600_pcie_gart_disable(rdev);
2563         r600_blit_suspend(rdev);
2564
2565         return 0;
2566 }
2567
2568 /* Plan is to move initialization in that function and use
2569  * helper function so that radeon_device_init pretty much
2570  * do nothing more than calling asic specific function. This
2571  * should also allow to remove a bunch of callback function
2572  * like vram_info.
2573  */
2574 int r600_init(struct radeon_device *rdev)
2575 {
2576         int r;
2577
2578         if (r600_debugfs_mc_info_init(rdev)) {
2579                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2580         }
2581         /* This don't do much */
2582         r = radeon_gem_init(rdev);
2583         if (r)
2584                 return r;
2585         /* Read BIOS */
2586         if (!radeon_get_bios(rdev)) {
2587                 if (ASIC_IS_AVIVO(rdev))
2588                         return -EINVAL;
2589         }
2590         /* Must be an ATOMBIOS */
2591         if (!rdev->is_atom_bios) {
2592                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2593                 return -EINVAL;
2594         }
2595         r = radeon_atombios_init(rdev);
2596         if (r)
2597                 return r;
2598         /* Post card if necessary */
2599         if (!radeon_card_posted(rdev)) {
2600                 if (!rdev->bios) {
2601                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2602                         return -EINVAL;
2603                 }
2604                 DRM_INFO("GPU not posted. posting now...\n");
2605                 atom_asic_init(rdev->mode_info.atom_context);
2606         }
2607         /* Initialize scratch registers */
2608         r600_scratch_init(rdev);
2609         /* Initialize surface registers */
2610         radeon_surface_init(rdev);
2611         /* Initialize clocks */
2612         radeon_get_clock_info(rdev->ddev);
2613         /* Fence driver */
2614         r = radeon_fence_driver_init(rdev);
2615         if (r)
2616                 return r;
2617         if (rdev->flags & RADEON_IS_AGP) {
2618                 r = radeon_agp_init(rdev);
2619                 if (r)
2620                         radeon_agp_disable(rdev);
2621         }
2622         r = r600_mc_init(rdev);
2623         if (r)
2624                 return r;
2625         /* Memory manager */
2626         r = radeon_bo_init(rdev);
2627         if (r)
2628                 return r;
2629
2630         r = radeon_irq_kms_init(rdev);
2631         if (r)
2632                 return r;
2633
2634         rdev->cp.ring_obj = NULL;
2635         r600_ring_init(rdev, 1024 * 1024);
2636
2637         rdev->ih.ring_obj = NULL;
2638         r600_ih_ring_init(rdev, 64 * 1024);
2639
2640         r = r600_pcie_gart_init(rdev);
2641         if (r)
2642                 return r;
2643
2644         rdev->accel_working = true;
2645         r = r600_startup(rdev);
2646         if (r) {
2647                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2648                 r600_cp_fini(rdev);
2649                 r600_irq_fini(rdev);
2650                 radeon_wb_fini(rdev);
2651                 radeon_irq_kms_fini(rdev);
2652                 r600_pcie_gart_fini(rdev);
2653                 rdev->accel_working = false;
2654         }
2655         if (rdev->accel_working) {
2656                 r = radeon_ib_pool_init(rdev);
2657                 if (r) {
2658                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2659                         rdev->accel_working = false;
2660                 } else {
2661                         r = r600_ib_test(rdev);
2662                         if (r) {
2663                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2664                                 rdev->accel_working = false;
2665                         }
2666                 }
2667         }
2668
2669         r = r600_audio_init(rdev);
2670         if (r)
2671                 return r; /* TODO error handling */
2672         return 0;
2673 }
2674
2675 void r600_fini(struct radeon_device *rdev)
2676 {
2677         r600_audio_fini(rdev);
2678         r600_blit_fini(rdev);
2679         r600_cp_fini(rdev);
2680         r600_irq_fini(rdev);
2681         radeon_wb_fini(rdev);
2682         radeon_ib_pool_fini(rdev);
2683         radeon_irq_kms_fini(rdev);
2684         r600_pcie_gart_fini(rdev);
2685         r600_vram_scratch_fini(rdev);
2686         radeon_agp_fini(rdev);
2687         radeon_gem_fini(rdev);
2688         radeon_fence_driver_fini(rdev);
2689         radeon_bo_fini(rdev);
2690         radeon_atombios_fini(rdev);
2691         kfree(rdev->bios);
2692         rdev->bios = NULL;
2693 }
2694
2695
2696 /*
2697  * CS stuff
2698  */
2699 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2700 {
2701         /* FIXME: implement */
2702         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2703         radeon_ring_write(rdev,
2704 #ifdef __BIG_ENDIAN
2705                           (2 << 0) |
2706 #endif
2707                           (ib->gpu_addr & 0xFFFFFFFC));
2708         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2709         radeon_ring_write(rdev, ib->length_dw);
2710 }
2711
2712 int r600_ib_test(struct radeon_device *rdev)
2713 {
2714         struct radeon_ib *ib;
2715         uint32_t scratch;
2716         uint32_t tmp = 0;
2717         unsigned i;
2718         int r;
2719
2720         r = radeon_scratch_get(rdev, &scratch);
2721         if (r) {
2722                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2723                 return r;
2724         }
2725         WREG32(scratch, 0xCAFEDEAD);
2726         r = radeon_ib_get(rdev, &ib);
2727         if (r) {
2728                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2729                 return r;
2730         }
2731         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2732         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2733         ib->ptr[2] = 0xDEADBEEF;
2734         ib->ptr[3] = PACKET2(0);
2735         ib->ptr[4] = PACKET2(0);
2736         ib->ptr[5] = PACKET2(0);
2737         ib->ptr[6] = PACKET2(0);
2738         ib->ptr[7] = PACKET2(0);
2739         ib->ptr[8] = PACKET2(0);
2740         ib->ptr[9] = PACKET2(0);
2741         ib->ptr[10] = PACKET2(0);
2742         ib->ptr[11] = PACKET2(0);
2743         ib->ptr[12] = PACKET2(0);
2744         ib->ptr[13] = PACKET2(0);
2745         ib->ptr[14] = PACKET2(0);
2746         ib->ptr[15] = PACKET2(0);
2747         ib->length_dw = 16;
2748         r = radeon_ib_schedule(rdev, ib);
2749         if (r) {
2750                 radeon_scratch_free(rdev, scratch);
2751                 radeon_ib_free(rdev, &ib);
2752                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2753                 return r;
2754         }
2755         r = radeon_fence_wait(ib->fence, false);
2756         if (r) {
2757                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2758                 return r;
2759         }
2760         for (i = 0; i < rdev->usec_timeout; i++) {
2761                 tmp = RREG32(scratch);
2762                 if (tmp == 0xDEADBEEF)
2763                         break;
2764                 DRM_UDELAY(1);
2765         }
2766         if (i < rdev->usec_timeout) {
2767                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2768         } else {
2769                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2770                           scratch, tmp);
2771                 r = -EINVAL;
2772         }
2773         radeon_scratch_free(rdev, scratch);
2774         radeon_ib_free(rdev, &ib);
2775         return r;
2776 }
2777
2778 /*
2779  * Interrupts
2780  *
2781  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2782  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2783  * writing to the ring and the GPU consuming, the GPU writes to the ring
2784  * and host consumes.  As the host irq handler processes interrupts, it
2785  * increments the rptr.  When the rptr catches up with the wptr, all the
2786  * current interrupts have been processed.
2787  */
2788
2789 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2790 {
2791         u32 rb_bufsz;
2792
2793         /* Align ring size */
2794         rb_bufsz = drm_order(ring_size / 4);
2795         ring_size = (1 << rb_bufsz) * 4;
2796         rdev->ih.ring_size = ring_size;
2797         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2798         rdev->ih.rptr = 0;
2799 }
2800
2801 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2802 {
2803         int r;
2804
2805         /* Allocate ring buffer */
2806         if (rdev->ih.ring_obj == NULL) {
2807                 r = radeon_bo_create(rdev, rdev->ih.ring_size,
2808                                      PAGE_SIZE, true,
2809                                      RADEON_GEM_DOMAIN_GTT,
2810                                      &rdev->ih.ring_obj);
2811                 if (r) {
2812                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2813                         return r;
2814                 }
2815                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2816                 if (unlikely(r != 0))
2817                         return r;
2818                 r = radeon_bo_pin(rdev->ih.ring_obj,
2819                                   RADEON_GEM_DOMAIN_GTT,
2820                                   &rdev->ih.gpu_addr);
2821                 if (r) {
2822                         radeon_bo_unreserve(rdev->ih.ring_obj);
2823                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2824                         return r;
2825                 }
2826                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2827                                    (void **)&rdev->ih.ring);
2828                 radeon_bo_unreserve(rdev->ih.ring_obj);
2829                 if (r) {
2830                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2831                         return r;
2832                 }
2833         }
2834         return 0;
2835 }
2836
2837 static void r600_ih_ring_fini(struct radeon_device *rdev)
2838 {
2839         int r;
2840         if (rdev->ih.ring_obj) {
2841                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2842                 if (likely(r == 0)) {
2843                         radeon_bo_kunmap(rdev->ih.ring_obj);
2844                         radeon_bo_unpin(rdev->ih.ring_obj);
2845                         radeon_bo_unreserve(rdev->ih.ring_obj);
2846                 }
2847                 radeon_bo_unref(&rdev->ih.ring_obj);
2848                 rdev->ih.ring = NULL;
2849                 rdev->ih.ring_obj = NULL;
2850         }
2851 }
2852
2853 void r600_rlc_stop(struct radeon_device *rdev)
2854 {
2855
2856         if ((rdev->family >= CHIP_RV770) &&
2857             (rdev->family <= CHIP_RV740)) {
2858                 /* r7xx asics need to soft reset RLC before halting */
2859                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2860                 RREG32(SRBM_SOFT_RESET);
2861                 udelay(15000);
2862                 WREG32(SRBM_SOFT_RESET, 0);
2863                 RREG32(SRBM_SOFT_RESET);
2864         }
2865
2866         WREG32(RLC_CNTL, 0);
2867 }
2868
2869 static void r600_rlc_start(struct radeon_device *rdev)
2870 {
2871         WREG32(RLC_CNTL, RLC_ENABLE);
2872 }
2873
2874 static int r600_rlc_init(struct radeon_device *rdev)
2875 {
2876         u32 i;
2877         const __be32 *fw_data;
2878
2879         if (!rdev->rlc_fw)
2880                 return -EINVAL;
2881
2882         r600_rlc_stop(rdev);
2883
2884         WREG32(RLC_HB_BASE, 0);
2885         WREG32(RLC_HB_CNTL, 0);
2886         WREG32(RLC_HB_RPTR, 0);
2887         WREG32(RLC_HB_WPTR, 0);
2888         if (rdev->family <= CHIP_CAICOS) {
2889                 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2890                 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2891         }
2892         WREG32(RLC_MC_CNTL, 0);
2893         WREG32(RLC_UCODE_CNTL, 0);
2894
2895         fw_data = (const __be32 *)rdev->rlc_fw->data;
2896         if (rdev->family >= CHIP_CAYMAN) {
2897                 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
2898                         WREG32(RLC_UCODE_ADDR, i);
2899                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2900                 }
2901         } else if (rdev->family >= CHIP_CEDAR) {
2902                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2903                         WREG32(RLC_UCODE_ADDR, i);
2904                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2905                 }
2906         } else if (rdev->family >= CHIP_RV770) {
2907                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2908                         WREG32(RLC_UCODE_ADDR, i);
2909                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2910                 }
2911         } else {
2912                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2913                         WREG32(RLC_UCODE_ADDR, i);
2914                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2915                 }
2916         }
2917         WREG32(RLC_UCODE_ADDR, 0);
2918
2919         r600_rlc_start(rdev);
2920
2921         return 0;
2922 }
2923
2924 static void r600_enable_interrupts(struct radeon_device *rdev)
2925 {
2926         u32 ih_cntl = RREG32(IH_CNTL);
2927         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2928
2929         ih_cntl |= ENABLE_INTR;
2930         ih_rb_cntl |= IH_RB_ENABLE;
2931         WREG32(IH_CNTL, ih_cntl);
2932         WREG32(IH_RB_CNTL, ih_rb_cntl);
2933         rdev->ih.enabled = true;
2934 }
2935
2936 void r600_disable_interrupts(struct radeon_device *rdev)
2937 {
2938         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2939         u32 ih_cntl = RREG32(IH_CNTL);
2940
2941         ih_rb_cntl &= ~IH_RB_ENABLE;
2942         ih_cntl &= ~ENABLE_INTR;
2943         WREG32(IH_RB_CNTL, ih_rb_cntl);
2944         WREG32(IH_CNTL, ih_cntl);
2945         /* set rptr, wptr to 0 */
2946         WREG32(IH_RB_RPTR, 0);
2947         WREG32(IH_RB_WPTR, 0);
2948         rdev->ih.enabled = false;
2949         rdev->ih.wptr = 0;
2950         rdev->ih.rptr = 0;
2951 }
2952
2953 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2954 {
2955         u32 tmp;
2956
2957         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2958         WREG32(GRBM_INT_CNTL, 0);
2959         WREG32(DxMODE_INT_MASK, 0);
2960         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
2961         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
2962         if (ASIC_IS_DCE3(rdev)) {
2963                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2964                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2965                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2966                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2967                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2968                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2969                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2970                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2971                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2972                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2973                 if (ASIC_IS_DCE32(rdev)) {
2974                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2975                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2976                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2977                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2978                 }
2979         } else {
2980                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2981                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2982                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2983                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2984                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2985                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2986                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2987                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2988         }
2989 }
2990
2991 int r600_irq_init(struct radeon_device *rdev)
2992 {
2993         int ret = 0;
2994         int rb_bufsz;
2995         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2996
2997         /* allocate ring */
2998         ret = r600_ih_ring_alloc(rdev);
2999         if (ret)
3000                 return ret;
3001
3002         /* disable irqs */
3003         r600_disable_interrupts(rdev);
3004
3005         /* init rlc */
3006         ret = r600_rlc_init(rdev);
3007         if (ret) {
3008                 r600_ih_ring_fini(rdev);
3009                 return ret;
3010         }
3011
3012         /* setup interrupt control */
3013         /* set dummy read address to ring address */
3014         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3015         interrupt_cntl = RREG32(INTERRUPT_CNTL);
3016         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3017          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3018          */
3019         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3020         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3021         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3022         WREG32(INTERRUPT_CNTL, interrupt_cntl);
3023
3024         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3025         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3026
3027         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3028                       IH_WPTR_OVERFLOW_CLEAR |
3029                       (rb_bufsz << 1));
3030
3031         if (rdev->wb.enabled)
3032                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3033
3034         /* set the writeback address whether it's enabled or not */
3035         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3036         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3037
3038         WREG32(IH_RB_CNTL, ih_rb_cntl);
3039
3040         /* set rptr, wptr to 0 */
3041         WREG32(IH_RB_RPTR, 0);
3042         WREG32(IH_RB_WPTR, 0);
3043
3044         /* Default settings for IH_CNTL (disabled at first) */
3045         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3046         /* RPTR_REARM only works if msi's are enabled */
3047         if (rdev->msi_enabled)
3048                 ih_cntl |= RPTR_REARM;
3049         WREG32(IH_CNTL, ih_cntl);
3050
3051         /* force the active interrupt state to all disabled */
3052         if (rdev->family >= CHIP_CEDAR)
3053                 evergreen_disable_interrupt_state(rdev);
3054         else
3055                 r600_disable_interrupt_state(rdev);
3056
3057         /* enable irqs */
3058         r600_enable_interrupts(rdev);
3059
3060         return ret;
3061 }
3062
3063 void r600_irq_suspend(struct radeon_device *rdev)
3064 {
3065         r600_irq_disable(rdev);
3066         r600_rlc_stop(rdev);
3067 }
3068
3069 void r600_irq_fini(struct radeon_device *rdev)
3070 {
3071         r600_irq_suspend(rdev);
3072         r600_ih_ring_fini(rdev);
3073 }
3074
3075 int r600_irq_set(struct radeon_device *rdev)
3076 {
3077         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3078         u32 mode_int = 0;
3079         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3080         u32 grbm_int_cntl = 0;
3081         u32 hdmi1, hdmi2;
3082         u32 d1grph = 0, d2grph = 0;
3083
3084         if (!rdev->irq.installed) {
3085                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3086                 return -EINVAL;
3087         }
3088         /* don't enable anything if the ih is disabled */
3089         if (!rdev->ih.enabled) {
3090                 r600_disable_interrupts(rdev);
3091                 /* force the active interrupt state to all disabled */
3092                 r600_disable_interrupt_state(rdev);
3093                 return 0;
3094         }
3095
3096         hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3097         if (ASIC_IS_DCE3(rdev)) {
3098                 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3099                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3100                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3101                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3102                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3103                 if (ASIC_IS_DCE32(rdev)) {
3104                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3105                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3106                 }
3107         } else {
3108                 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3109                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3110                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3111                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3112         }
3113
3114         if (rdev->irq.sw_int) {
3115                 DRM_DEBUG("r600_irq_set: sw int\n");
3116                 cp_int_cntl |= RB_INT_ENABLE;
3117                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3118         }
3119         if (rdev->irq.crtc_vblank_int[0] ||
3120             rdev->irq.pflip[0]) {
3121                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3122                 mode_int |= D1MODE_VBLANK_INT_MASK;
3123         }
3124         if (rdev->irq.crtc_vblank_int[1] ||
3125             rdev->irq.pflip[1]) {
3126                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3127                 mode_int |= D2MODE_VBLANK_INT_MASK;
3128         }
3129         if (rdev->irq.hpd[0]) {
3130                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3131                 hpd1 |= DC_HPDx_INT_EN;
3132         }
3133         if (rdev->irq.hpd[1]) {
3134                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3135                 hpd2 |= DC_HPDx_INT_EN;
3136         }
3137         if (rdev->irq.hpd[2]) {
3138                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3139                 hpd3 |= DC_HPDx_INT_EN;
3140         }
3141         if (rdev->irq.hpd[3]) {
3142                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3143                 hpd4 |= DC_HPDx_INT_EN;
3144         }
3145         if (rdev->irq.hpd[4]) {
3146                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3147                 hpd5 |= DC_HPDx_INT_EN;
3148         }
3149         if (rdev->irq.hpd[5]) {
3150                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3151                 hpd6 |= DC_HPDx_INT_EN;
3152         }
3153         if (rdev->irq.hdmi[0]) {
3154                 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3155                 hdmi1 |= R600_HDMI_INT_EN;
3156         }
3157         if (rdev->irq.hdmi[1]) {
3158                 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3159                 hdmi2 |= R600_HDMI_INT_EN;
3160         }
3161         if (rdev->irq.gui_idle) {
3162                 DRM_DEBUG("gui idle\n");
3163                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3164         }
3165
3166         WREG32(CP_INT_CNTL, cp_int_cntl);
3167         WREG32(DxMODE_INT_MASK, mode_int);
3168         WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3169         WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3170         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3171         WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
3172         if (ASIC_IS_DCE3(rdev)) {
3173                 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
3174                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3175                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3176                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3177                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3178                 if (ASIC_IS_DCE32(rdev)) {
3179                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3180                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3181                 }
3182         } else {
3183                 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
3184                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3185                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3186                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3187         }
3188
3189         return 0;
3190 }
3191
3192 static void r600_irq_ack(struct radeon_device *rdev)
3193 {
3194         u32 tmp;
3195
3196         if (ASIC_IS_DCE3(rdev)) {
3197                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3198                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3199                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3200         } else {
3201                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3202                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3203                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3204         }
3205         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3206         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3207
3208         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3209                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3210         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3211                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3212         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3213                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3214         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3215                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3216         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3217                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3218         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3219                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3220         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3221                 if (ASIC_IS_DCE3(rdev)) {
3222                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3223                         tmp |= DC_HPDx_INT_ACK;
3224                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3225                 } else {
3226                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3227                         tmp |= DC_HPDx_INT_ACK;
3228                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3229                 }
3230         }
3231         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3232                 if (ASIC_IS_DCE3(rdev)) {
3233                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3234                         tmp |= DC_HPDx_INT_ACK;
3235                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3236                 } else {
3237                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3238                         tmp |= DC_HPDx_INT_ACK;
3239                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3240                 }
3241         }
3242         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3243                 if (ASIC_IS_DCE3(rdev)) {
3244                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3245                         tmp |= DC_HPDx_INT_ACK;
3246                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3247                 } else {
3248                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3249                         tmp |= DC_HPDx_INT_ACK;
3250                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3251                 }
3252         }
3253         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3254                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3255                 tmp |= DC_HPDx_INT_ACK;
3256                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3257         }
3258         if (ASIC_IS_DCE32(rdev)) {
3259                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3260                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3261                         tmp |= DC_HPDx_INT_ACK;
3262                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3263                 }
3264                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3265                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3266                         tmp |= DC_HPDx_INT_ACK;
3267                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3268                 }
3269         }
3270         if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3271                 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3272         }
3273         if (ASIC_IS_DCE3(rdev)) {
3274                 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3275                         WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3276                 }
3277         } else {
3278                 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3279                         WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3280                 }
3281         }
3282 }
3283
3284 void r600_irq_disable(struct radeon_device *rdev)
3285 {
3286         r600_disable_interrupts(rdev);
3287         /* Wait and acknowledge irq */
3288         mdelay(1);
3289         r600_irq_ack(rdev);
3290         r600_disable_interrupt_state(rdev);
3291 }
3292
3293 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
3294 {
3295         u32 wptr, tmp;
3296
3297         if (rdev->wb.enabled)
3298                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3299         else
3300                 wptr = RREG32(IH_RB_WPTR);
3301
3302         if (wptr & RB_OVERFLOW) {
3303                 /* When a ring buffer overflow happen start parsing interrupt
3304                  * from the last not overwritten vector (wptr + 16). Hopefully
3305                  * this should allow us to catchup.
3306                  */
3307                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3308                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3309                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3310                 tmp = RREG32(IH_RB_CNTL);
3311                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3312                 WREG32(IH_RB_CNTL, tmp);
3313         }
3314         return (wptr & rdev->ih.ptr_mask);
3315 }
3316
3317 /*        r600 IV Ring
3318  * Each IV ring entry is 128 bits:
3319  * [7:0]    - interrupt source id
3320  * [31:8]   - reserved
3321  * [59:32]  - interrupt source data
3322  * [127:60]  - reserved
3323  *
3324  * The basic interrupt vector entries
3325  * are decoded as follows:
3326  * src_id  src_data  description
3327  *      1         0  D1 Vblank
3328  *      1         1  D1 Vline
3329  *      5         0  D2 Vblank
3330  *      5         1  D2 Vline
3331  *     19         0  FP Hot plug detection A
3332  *     19         1  FP Hot plug detection B
3333  *     19         2  DAC A auto-detection
3334  *     19         3  DAC B auto-detection
3335  *     21         4  HDMI block A
3336  *     21         5  HDMI block B
3337  *    176         -  CP_INT RB
3338  *    177         -  CP_INT IB1
3339  *    178         -  CP_INT IB2
3340  *    181         -  EOP Interrupt
3341  *    233         -  GUI Idle
3342  *
3343  * Note, these are based on r600 and may need to be
3344  * adjusted or added to on newer asics
3345  */
3346
3347 int r600_irq_process(struct radeon_device *rdev)
3348 {
3349         u32 wptr;
3350         u32 rptr;
3351         u32 src_id, src_data;
3352         u32 ring_index;
3353         unsigned long flags;
3354         bool queue_hotplug = false;
3355
3356         if (!rdev->ih.enabled || rdev->shutdown)
3357                 return IRQ_NONE;
3358
3359         /* No MSIs, need a dummy read to flush PCI DMAs */
3360         if (!rdev->msi_enabled)
3361                 RREG32(IH_RB_WPTR);
3362
3363         wptr = r600_get_ih_wptr(rdev);
3364         rptr = rdev->ih.rptr;
3365         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3366
3367         spin_lock_irqsave(&rdev->ih.lock, flags);
3368
3369         if (rptr == wptr) {
3370                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3371                 return IRQ_NONE;
3372         }
3373
3374 restart_ih:
3375         /* Order reading of wptr vs. reading of IH ring data */
3376         rmb();
3377
3378         /* display interrupts */
3379         r600_irq_ack(rdev);
3380
3381         rdev->ih.wptr = wptr;
3382         while (rptr != wptr) {
3383                 /* wptr/rptr are in bytes! */
3384                 ring_index = rptr / 4;
3385                 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3386                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3387
3388                 switch (src_id) {
3389                 case 1: /* D1 vblank/vline */
3390                         switch (src_data) {
3391                         case 0: /* D1 vblank */
3392                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3393                                         if (rdev->irq.crtc_vblank_int[0]) {
3394                                                 drm_handle_vblank(rdev->ddev, 0);
3395                                                 rdev->pm.vblank_sync = true;
3396                                                 wake_up(&rdev->irq.vblank_queue);
3397                                         }
3398                                         if (rdev->irq.pflip[0])
3399                                                 radeon_crtc_handle_flip(rdev, 0);
3400                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3401                                         DRM_DEBUG("IH: D1 vblank\n");
3402                                 }
3403                                 break;
3404                         case 1: /* D1 vline */
3405                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3406                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3407                                         DRM_DEBUG("IH: D1 vline\n");
3408                                 }
3409                                 break;
3410                         default:
3411                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3412                                 break;
3413                         }
3414                         break;
3415                 case 5: /* D2 vblank/vline */
3416                         switch (src_data) {
3417                         case 0: /* D2 vblank */
3418                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3419                                         if (rdev->irq.crtc_vblank_int[1]) {
3420                                                 drm_handle_vblank(rdev->ddev, 1);
3421                                                 rdev->pm.vblank_sync = true;
3422                                                 wake_up(&rdev->irq.vblank_queue);
3423                                         }
3424                                         if (rdev->irq.pflip[1])
3425                                                 radeon_crtc_handle_flip(rdev, 1);
3426                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3427                                         DRM_DEBUG("IH: D2 vblank\n");
3428                                 }
3429                                 break;
3430                         case 1: /* D1 vline */
3431                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3432                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3433                                         DRM_DEBUG("IH: D2 vline\n");
3434                                 }
3435                                 break;
3436                         default:
3437                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3438                                 break;
3439                         }
3440                         break;
3441                 case 19: /* HPD/DAC hotplug */
3442                         switch (src_data) {
3443                         case 0:
3444                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3445                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3446                                         queue_hotplug = true;
3447                                         DRM_DEBUG("IH: HPD1\n");
3448                                 }
3449                                 break;
3450                         case 1:
3451                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3452                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3453                                         queue_hotplug = true;
3454                                         DRM_DEBUG("IH: HPD2\n");
3455                                 }
3456                                 break;
3457                         case 4:
3458                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3459                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3460                                         queue_hotplug = true;
3461                                         DRM_DEBUG("IH: HPD3\n");
3462                                 }
3463                                 break;
3464                         case 5:
3465                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3466                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3467                                         queue_hotplug = true;
3468                                         DRM_DEBUG("IH: HPD4\n");
3469                                 }
3470                                 break;
3471                         case 10:
3472                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3473                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3474                                         queue_hotplug = true;
3475                                         DRM_DEBUG("IH: HPD5\n");
3476                                 }
3477                                 break;
3478                         case 12:
3479                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3480                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3481                                         queue_hotplug = true;
3482                                         DRM_DEBUG("IH: HPD6\n");
3483                                 }
3484                                 break;
3485                         default:
3486                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3487                                 break;
3488                         }
3489                         break;
3490                 case 21: /* HDMI */
3491                         DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3492                         r600_audio_schedule_polling(rdev);
3493                         break;
3494                 case 176: /* CP_INT in ring buffer */
3495                 case 177: /* CP_INT in IB1 */
3496                 case 178: /* CP_INT in IB2 */
3497                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3498                         radeon_fence_process(rdev);
3499                         break;
3500                 case 181: /* CP EOP event */
3501                         DRM_DEBUG("IH: CP EOP\n");
3502                         radeon_fence_process(rdev);
3503                         break;
3504                 case 233: /* GUI IDLE */
3505                         DRM_DEBUG("IH: GUI idle\n");
3506                         rdev->pm.gui_idle = true;
3507                         wake_up(&rdev->irq.idle_queue);
3508                         break;
3509                 default:
3510                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3511                         break;
3512                 }
3513
3514                 /* wptr/rptr are in bytes! */
3515                 rptr += 16;
3516                 rptr &= rdev->ih.ptr_mask;
3517         }
3518         /* make sure wptr hasn't changed while processing */
3519         wptr = r600_get_ih_wptr(rdev);
3520         if (wptr != rdev->ih.wptr)
3521                 goto restart_ih;
3522         if (queue_hotplug)
3523                 schedule_work(&rdev->hotplug_work);
3524         rdev->ih.rptr = rptr;
3525         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3526         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3527         return IRQ_HANDLED;
3528 }
3529
3530 /*
3531  * Debugfs info
3532  */
3533 #if defined(CONFIG_DEBUG_FS)
3534
3535 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3536 {
3537         struct drm_info_node *node = (struct drm_info_node *) m->private;
3538         struct drm_device *dev = node->minor->dev;
3539         struct radeon_device *rdev = dev->dev_private;
3540         unsigned count, i, j;
3541
3542         radeon_ring_free_size(rdev);
3543         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3544         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3545         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3546         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3547         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3548         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3549         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3550         seq_printf(m, "%u dwords in ring\n", count);
3551         i = rdev->cp.rptr;
3552         for (j = 0; j <= count; j++) {
3553                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3554                 i = (i + 1) & rdev->cp.ptr_mask;
3555         }
3556         return 0;
3557 }
3558
3559 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3560 {
3561         struct drm_info_node *node = (struct drm_info_node *) m->private;
3562         struct drm_device *dev = node->minor->dev;
3563         struct radeon_device *rdev = dev->dev_private;
3564
3565         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3566         DREG32_SYS(m, rdev, VM_L2_STATUS);
3567         return 0;
3568 }
3569
3570 static struct drm_info_list r600_mc_info_list[] = {
3571         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3572         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3573 };
3574 #endif
3575
3576 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3577 {
3578 #if defined(CONFIG_DEBUG_FS)
3579         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3580 #else
3581         return 0;
3582 #endif
3583 }
3584
3585 /**
3586  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3587  * rdev: radeon device structure
3588  * bo: buffer object struct which userspace is waiting for idle
3589  *
3590  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3591  * through ring buffer, this leads to corruption in rendering, see
3592  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3593  * directly perform HDP flush by writing register through MMIO.
3594  */
3595 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3596 {
3597         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
3598          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3599          * This seems to cause problems on some AGP cards. Just use the old
3600          * method for them.
3601          */
3602         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3603             rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
3604                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3605                 u32 tmp;
3606
3607                 WREG32(HDP_DEBUG1, 0);
3608                 tmp = readl((void __iomem *)ptr);
3609         } else
3610                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3611 }
3612
3613 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
3614 {
3615         u32 link_width_cntl, mask, target_reg;
3616
3617         if (rdev->flags & RADEON_IS_IGP)
3618                 return;
3619
3620         if (!(rdev->flags & RADEON_IS_PCIE))
3621                 return;
3622
3623         /* x2 cards have a special sequence */
3624         if (ASIC_IS_X2(rdev))
3625                 return;
3626
3627         /* FIXME wait for idle */
3628
3629         switch (lanes) {
3630         case 0:
3631                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
3632                 break;
3633         case 1:
3634                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
3635                 break;
3636         case 2:
3637                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
3638                 break;
3639         case 4:
3640                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
3641                 break;
3642         case 8:
3643                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
3644                 break;
3645         case 12:
3646                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
3647                 break;
3648         case 16:
3649         default:
3650                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
3651                 break;
3652         }
3653
3654         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3655
3656         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
3657             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
3658                 return;
3659
3660         if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
3661                 return;
3662
3663         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
3664                              RADEON_PCIE_LC_RECONFIG_NOW |
3665                              R600_PCIE_LC_RENEGOTIATE_EN |
3666                              R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3667         link_width_cntl |= mask;
3668
3669         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3670
3671         /* some northbridges can renegotiate the link rather than requiring
3672          * a complete re-config.
3673          * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3674          */
3675         if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
3676                 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
3677         else
3678                 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
3679
3680         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
3681                                                        RADEON_PCIE_LC_RECONFIG_NOW));
3682
3683         if (rdev->family >= CHIP_RV770)
3684                 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
3685         else
3686                 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
3687
3688         /* wait for lane set to complete */
3689         link_width_cntl = RREG32(target_reg);
3690         while (link_width_cntl == 0xffffffff)
3691                 link_width_cntl = RREG32(target_reg);
3692
3693 }
3694
3695 int r600_get_pcie_lanes(struct radeon_device *rdev)
3696 {
3697         u32 link_width_cntl;
3698
3699         if (rdev->flags & RADEON_IS_IGP)
3700                 return 0;
3701
3702         if (!(rdev->flags & RADEON_IS_PCIE))
3703                 return 0;
3704
3705         /* x2 cards have a special sequence */
3706         if (ASIC_IS_X2(rdev))
3707                 return 0;
3708
3709         /* FIXME wait for idle */
3710
3711         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3712
3713         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3714         case RADEON_PCIE_LC_LINK_WIDTH_X0:
3715                 return 0;
3716         case RADEON_PCIE_LC_LINK_WIDTH_X1:
3717                 return 1;
3718         case RADEON_PCIE_LC_LINK_WIDTH_X2:
3719                 return 2;
3720         case RADEON_PCIE_LC_LINK_WIDTH_X4:
3721                 return 4;
3722         case RADEON_PCIE_LC_LINK_WIDTH_X8:
3723                 return 8;
3724         case RADEON_PCIE_LC_LINK_WIDTH_X16:
3725         default:
3726                 return 16;
3727         }
3728 }
3729
3730 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
3731 {
3732         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
3733         u16 link_cntl2;
3734
3735         if (radeon_pcie_gen2 == 0)
3736                 return;
3737
3738         if (rdev->flags & RADEON_IS_IGP)
3739                 return;
3740
3741         if (!(rdev->flags & RADEON_IS_PCIE))
3742                 return;
3743
3744         /* x2 cards have a special sequence */
3745         if (ASIC_IS_X2(rdev))
3746                 return;
3747
3748         /* only RV6xx+ chips are supported */
3749         if (rdev->family <= CHIP_R600)
3750                 return;
3751
3752         /* 55 nm r6xx asics */
3753         if ((rdev->family == CHIP_RV670) ||
3754             (rdev->family == CHIP_RV620) ||
3755             (rdev->family == CHIP_RV635)) {
3756                 /* advertise upconfig capability */
3757                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3758                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3759                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3760                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3761                 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
3762                         lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
3763                         link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
3764                                              LC_RECONFIG_ARC_MISSING_ESCAPE);
3765                         link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
3766                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3767                 } else {
3768                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3769                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3770                 }
3771         }
3772
3773         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3774         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3775             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3776
3777                 /* 55 nm r6xx asics */
3778                 if ((rdev->family == CHIP_RV670) ||
3779                     (rdev->family == CHIP_RV620) ||
3780                     (rdev->family == CHIP_RV635)) {
3781                         WREG32(MM_CFGREGS_CNTL, 0x8);
3782                         link_cntl2 = RREG32(0x4088);
3783                         WREG32(MM_CFGREGS_CNTL, 0);
3784                         /* not supported yet */
3785                         if (link_cntl2 & SELECTABLE_DEEMPHASIS)
3786                                 return;
3787                 }
3788
3789                 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
3790                 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
3791                 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
3792                 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
3793                 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
3794                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3795
3796                 tmp = RREG32(0x541c);
3797                 WREG32(0x541c, tmp | 0x8);
3798                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
3799                 link_cntl2 = RREG16(0x4088);
3800                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
3801                 link_cntl2 |= 0x2;
3802                 WREG16(0x4088, link_cntl2);
3803                 WREG32(MM_CFGREGS_CNTL, 0);
3804
3805                 if ((rdev->family == CHIP_RV670) ||
3806                     (rdev->family == CHIP_RV620) ||
3807                     (rdev->family == CHIP_RV635)) {
3808                         training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
3809                         training_cntl &= ~LC_POINT_7_PLUS_EN;
3810                         WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
3811                 } else {
3812                         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3813                         speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3814                         WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3815                 }
3816
3817                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3818                 speed_cntl |= LC_GEN2_EN_STRAP;
3819                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3820
3821         } else {
3822                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3823                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3824                 if (1)
3825                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3826                 else
3827                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3828                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3829         }
3830 }