drivers/gpu/drm/radeon/r300.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_drm.h"
  37 #include "r100_track.h"
  38 #include "r300d.h"
  39 #include "rv350d.h"
  40 #include "r300_reg_safe.h"
  41
  42 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
  43  *
  44  * GPU Errata:
  45  * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
  46  *   using MMIO to flush host path read cache, this lead to HARDLOCKUP.
  47  *   However, scheduling such write to the ring seems harmless, i suspect
  48  *   the CP read collide with the flush somehow, or maybe the MC, hard to
  49  *   tell. (Jerome Glisse)
  50  */
  51
  52 /*
  53  * rv370,rv380 PCIE GART
  54  */
  55 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
  56
  57 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
  58 {
  59         uint32_t tmp;
  60         int i;
  61
  62         /* Workaround HW bug do flush 2 times */
  63         for (i = 0; i < 2; i++) {
  64                 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  65                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
  66                 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  67                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
  68         }
  69         mb();
  70 }
  71
  72 #define R300_PTE_WRITEABLE (1 << 2)
  73 #define R300_PTE_READABLE  (1 << 3)
  74
  75 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
  76 {
  77         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
  78
  79         if (i < 0 || i > rdev->gart.num_gpu_pages) {
  80                 return -EINVAL;
  81         }
  82         addr = (lower_32_bits(addr) >> 8) |
  83                ((upper_32_bits(addr) & 0xff) << 24) |
  84                R300_PTE_WRITEABLE | R300_PTE_READABLE;
  85         /* on x86 we want this to be CPU endian, on powerpc
  86          * on powerpc without HW swappers, it'll get swapped on way
  87          * into VRAM - so no need for cpu_to_le32 on VRAM tables */
  88         writel(addr, ((void __iomem *)ptr) + (i * 4));
  89         return 0;
  90 }
  91
  92 int rv370_pcie_gart_init(struct radeon_device *rdev)
  93 {
  94         int r;
  95
  96         if (rdev->gart.table.vram.robj) {
  97                 WARN(1, "RV370 PCIE GART already initialized\n");
  98                 return 0;
  99         }
 100         /* Initialize common gart structure */
 101         r = radeon_gart_init(rdev);
 102         if (r)
 103                 return r;
 104         r = rv370_debugfs_pcie_gart_info_init(rdev);
 105         if (r)
 106                 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
 107         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 108         rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
 109         rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 110         return radeon_gart_table_vram_alloc(rdev);
 111 }
 112
 113 int rv370_pcie_gart_enable(struct radeon_device *rdev)
 114 {
 115         uint32_t table_addr;
 116         uint32_t tmp;
 117         int r;
 118
 119         if (rdev->gart.table.vram.robj == NULL) {
 120                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 121                 return -EINVAL;
 122         }
 123         r = radeon_gart_table_vram_pin(rdev);
 124         if (r)
 125                 return r;
 126         radeon_gart_restore(rdev);
 127         /* discard memory request outside of configured range */
 128         tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 129         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 130         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
 131         tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
 132         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
 133         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
 134         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
 135         table_addr = rdev->gart.table_addr;
 136         WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
 137         /* FIXME: setup default page */
 138         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
 139         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
 140         /* Clear error */
 141         WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);
 142         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 143         tmp |= RADEON_PCIE_TX_GART_EN;
 144         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 145         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 146         rv370_pcie_gart_tlb_flush(rdev);
 147         DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
 148                  (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
 149         rdev->gart.ready = true;
 150         return 0;
 151 }
 152
 153 void rv370_pcie_gart_disable(struct radeon_device *rdev)
 154 {
 155         u32 tmp;
 156         int r;
 157
 158         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
 159         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
 160         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
 161         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
 162         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 163         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 164         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
 165         if (rdev->gart.table.vram.robj) {
 166                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 167                 if (likely(r == 0)) {
 168                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 169                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 170                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 171                 }
 172         }
 173 }
 174
 175 void rv370_pcie_gart_fini(struct radeon_device *rdev)
 176 {
 177         radeon_gart_fini(rdev);
 178         rv370_pcie_gart_disable(rdev);
 179         radeon_gart_table_vram_free(rdev);
 180 }
 181
 182 void r300_fence_ring_emit(struct radeon_device *rdev,
 183                           struct radeon_fence *fence)
 184 {
 185         /* Who ever call radeon_fence_emit should call ring_lock and ask
 186          * for enough space (today caller are ib schedule and buffer move) */
 187         /* Write SC register so SC & US assert idle */
 188         radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
 189         radeon_ring_write(rdev, 0);
 190         radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
 191         radeon_ring_write(rdev, 0);
 192         /* Flush 3D cache */
 193         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 194         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
 195         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 196         radeon_ring_write(rdev, R300_ZC_FLUSH);
 197         /* Wait until IDLE & CLEAN */
 198         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 199         radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN |
 200                                  RADEON_WAIT_2D_IDLECLEAN |
 201                                  RADEON_WAIT_DMA_GUI_IDLE));
 202         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 203         radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
 204                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 205         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 206         radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
 207         /* Emit fence sequence & fire IRQ */
 208         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 209         radeon_ring_write(rdev, fence->seq);
 210         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 211         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 212 }
 213
 214 void r300_ring_start(struct radeon_device *rdev)
 215 {
 216         unsigned gb_tile_config;
 217         int r;
 218
 219         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
 220         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 221         switch(rdev->num_gb_pipes) {
 222         case 2:
 223                 gb_tile_config |= R300_PIPE_COUNT_R300;
 224                 break;
 225         case 3:
 226                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 227                 break;
 228         case 4:
 229                 gb_tile_config |= R300_PIPE_COUNT_R420;
 230                 break;
 231         case 1:
 232         default:
 233                 gb_tile_config |= R300_PIPE_COUNT_RV350;
 234                 break;
 235         }
 236
 237         r = radeon_ring_lock(rdev, 64);
 238         if (r) {
 239                 return;
 240         }
 241         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 242         radeon_ring_write(rdev,
 243                           RADEON_ISYNC_ANY2D_IDLE3D |
 244                           RADEON_ISYNC_ANY3D_IDLE2D |
 245                           RADEON_ISYNC_WAIT_IDLEGUI |
 246                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 247         radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
 248         radeon_ring_write(rdev, gb_tile_config);
 249         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 250         radeon_ring_write(rdev,
 251                           RADEON_WAIT_2D_IDLECLEAN |
 252                           RADEON_WAIT_3D_IDLECLEAN);
 253         radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
 254         radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
 255         radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
 256         radeon_ring_write(rdev, 0);
 257         radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
 258         radeon_ring_write(rdev, 0);
 259         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 260         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 261         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 262         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
 263         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 264         radeon_ring_write(rdev,
 265                           RADEON_WAIT_2D_IDLECLEAN |
 266                           RADEON_WAIT_3D_IDLECLEAN);
 267         radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
 268         radeon_ring_write(rdev, 0);
 269         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 270         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 271         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 272         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
 273         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
 274         radeon_ring_write(rdev,
 275                           ((6 << R300_MS_X0_SHIFT) |
 276                            (6 << R300_MS_Y0_SHIFT) |
 277                            (6 << R300_MS_X1_SHIFT) |
 278                            (6 << R300_MS_Y1_SHIFT) |
 279                            (6 << R300_MS_X2_SHIFT) |
 280                            (6 << R300_MS_Y2_SHIFT) |
 281                            (6 << R300_MSBD0_Y_SHIFT) |
 282                            (6 << R300_MSBD0_X_SHIFT)));
 283         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
 284         radeon_ring_write(rdev,
 285                           ((6 << R300_MS_X3_SHIFT) |
 286                            (6 << R300_MS_Y3_SHIFT) |
 287                            (6 << R300_MS_X4_SHIFT) |
 288                            (6 << R300_MS_Y4_SHIFT) |
 289                            (6 << R300_MS_X5_SHIFT) |
 290                            (6 << R300_MS_Y5_SHIFT) |
 291                            (6 << R300_MSBD1_SHIFT)));
 292         radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
 293         radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
 294         radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
 295         radeon_ring_write(rdev,
 296                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
 297         radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
 298         radeon_ring_write(rdev,
 299                           R300_GEOMETRY_ROUND_NEAREST |
 300                           R300_COLOR_ROUND_NEAREST);
 301         radeon_ring_unlock_commit(rdev);
 302 }
 303
 304 void r300_errata(struct radeon_device *rdev)
 305 {
 306         rdev->pll_errata = 0;
 307
 308         if (rdev->family == CHIP_R300 &&
 309             (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
 310                 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
 311         }
 312 }
 313
 314 int r300_mc_wait_for_idle(struct radeon_device *rdev)
 315 {
 316         unsigned i;
 317         uint32_t tmp;
 318
 319         for (i = 0; i < rdev->usec_timeout; i++) {
 320                 /* read MC_STATUS */
 321                 tmp = RREG32(RADEON_MC_STATUS);
 322                 if (tmp & R300_MC_IDLE) {
 323                         return 0;
 324                 }
 325                 DRM_UDELAY(1);
 326         }
 327         return -1;
 328 }
 329
 330 void r300_gpu_init(struct radeon_device *rdev)
 331 {
 332         uint32_t gb_tile_config, tmp;
 333
 334         if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
 335             (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
 336                 /* r300,r350 */
 337                 rdev->num_gb_pipes = 2;
 338         } else {
 339                 /* rv350,rv370,rv380,r300 AD, r350 AH */
 340                 rdev->num_gb_pipes = 1;
 341         }
 342         rdev->num_z_pipes = 1;
 343         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 344         switch (rdev->num_gb_pipes) {
 345         case 2:
 346                 gb_tile_config |= R300_PIPE_COUNT_R300;
 347                 break;
 348         case 3:
 349                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 350                 break;
 351         case 4:
 352                 gb_tile_config |= R300_PIPE_COUNT_R420;
 353                 break;
 354         default:
 355         case 1:
 356                 gb_tile_config |= R300_PIPE_COUNT_RV350;
 357                 break;
 358         }
 359         WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
 360
 361         if (r100_gui_wait_for_idle(rdev)) {
 362                 printk(KERN_WARNING "Failed to wait GUI idle while "
 363                        "programming pipes. Bad things might happen.\n");
 364         }
 365
 366         tmp = RREG32(R300_DST_PIPE_CONFIG);
 367         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
 368
 369         WREG32(R300_RB2D_DSTCACHE_MODE,
 370                R300_DC_AUTOFLUSH_ENABLE |
 371                R300_DC_DC_DISABLE_IGNORE_PE);
 372
 373         if (r100_gui_wait_for_idle(rdev)) {
 374                 printk(KERN_WARNING "Failed to wait GUI idle while "
 375                        "programming pipes. Bad things might happen.\n");
 376         }
 377         if (r300_mc_wait_for_idle(rdev)) {
 378                 printk(KERN_WARNING "Failed to wait MC idle while "
 379                        "programming pipes. Bad things might happen.\n");
 380         }
 381         DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
 382                  rdev->num_gb_pipes, rdev->num_z_pipes);
 383 }
 384
 385 bool r300_gpu_is_lockup(struct radeon_device *rdev)
 386 {
 387         u32 rbbm_status;
 388         int r;
 389
 390         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
 391         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
 392                 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
 393                 return false;
 394         }
 395         /* force CP activities */
 396         r = radeon_ring_lock(rdev, 2);
 397         if (!r) {
 398                 /* PACKET2 NOP */
 399                 radeon_ring_write(rdev, 0x80000000);
 400                 radeon_ring_write(rdev, 0x80000000);
 401                 radeon_ring_unlock_commit(rdev);
 402         }
 403         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
 404         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
 405 }
 406
 407 int r300_asic_reset(struct radeon_device *rdev)
 408 {
 409         struct r100_mc_save save;
 410         u32 status, tmp;
 411         int ret = 0;
 412
 413         status = RREG32(R_000E40_RBBM_STATUS);
 414         if (!G_000E40_GUI_ACTIVE(status)) {
 415                 return 0;
 416         }
 417         r100_mc_stop(rdev, &save);
 418         status = RREG32(R_000E40_RBBM_STATUS);
 419         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 420         /* stop CP */
 421         WREG32(RADEON_CP_CSQ_CNTL, 0);
 422         tmp = RREG32(RADEON_CP_RB_CNTL);
 423         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 424         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 425         WREG32(RADEON_CP_RB_WPTR, 0);
 426         WREG32(RADEON_CP_RB_CNTL, tmp);
 427         /* save PCI state */
 428         pci_save_state(rdev->pdev);
 429         /* disable bus mastering */
 430         r100_bm_disable(rdev);
 431         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
 432                                         S_0000F0_SOFT_RESET_GA(1));
 433         RREG32(R_0000F0_RBBM_SOFT_RESET);
 434         mdelay(500);
 435         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 436         mdelay(1);
 437         status = RREG32(R_000E40_RBBM_STATUS);
 438         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 439         /* resetting the CP seems to be problematic sometimes it end up
 440          * hard locking the computer, but it's necessary for successfull
 441          * reset more test & playing is needed on R3XX/R4XX to find a
 442          * reliable (if any solution)
 443          */
 444         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
 445         RREG32(R_0000F0_RBBM_SOFT_RESET);
 446         mdelay(500);
 447         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 448         mdelay(1);
 449         status = RREG32(R_000E40_RBBM_STATUS);
 450         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 451         /* restore PCI & busmastering */
 452         pci_restore_state(rdev->pdev);
 453         r100_enable_bm(rdev);
 454         /* Check if GPU is idle */
 455         if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
 456                 dev_err(rdev->dev, "failed to reset GPU\n");
 457                 rdev->gpu_lockup = true;
 458                 ret = -1;
 459         } else
 460                 dev_info(rdev->dev, "GPU reset succeed\n");
 461         r100_mc_resume(rdev, &save);
 462         return ret;
 463 }
 464
 465 /*
 466  * r300,r350,rv350,rv380 VRAM info
 467  */
 468 void r300_mc_init(struct radeon_device *rdev)
 469 {
 470         u64 base;
 471         u32 tmp;
 472
 473         /* DDR for all card after R300 & IGP */
 474         rdev->mc.vram_is_ddr = true;
 475         tmp = RREG32(RADEON_MEM_CNTL);
 476         tmp &= R300_MEM_NUM_CHANNELS_MASK;
 477         switch (tmp) {
 478         case 0: rdev->mc.vram_width = 64; break;
 479         case 1: rdev->mc.vram_width = 128; break;
 480         case 2: rdev->mc.vram_width = 256; break;
 481         default:  rdev->mc.vram_width = 128; break;
 482         }
 483         r100_vram_init_sizes(rdev);
 484         base = rdev->mc.aper_base;
 485         if (rdev->flags & RADEON_IS_IGP)
 486                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
 487         radeon_vram_location(rdev, &rdev->mc, base);
 488         rdev->mc.gtt_base_align = 0;
 489         if (!(rdev->flags & RADEON_IS_AGP))
 490                 radeon_gtt_location(rdev, &rdev->mc);
 491         radeon_update_bandwidth_info(rdev);
 492 }
 493
 494 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
 495 {
 496         uint32_t link_width_cntl, mask;
 497
 498         if (rdev->flags & RADEON_IS_IGP)
 499                 return;
 500
 501         if (!(rdev->flags & RADEON_IS_PCIE))
 502                 return;
 503
 504         /* FIXME wait for idle */
 505
 506         switch (lanes) {
 507         case 0:
 508                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
 509                 break;
 510         case 1:
 511                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
 512                 break;
 513         case 2:
 514                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
 515                 break;
 516         case 4:
 517                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
 518                 break;
 519         case 8:
 520                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
 521                 break;
 522         case 12:
 523                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
 524                 break;
 525         case 16:
 526         default:
 527                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
 528                 break;
 529         }
 530
 531         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 532
 533         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
 534             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
 535                 return;
 536
 537         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
 538                              RADEON_PCIE_LC_RECONFIG_NOW |
 539                              RADEON_PCIE_LC_RECONFIG_LATER |
 540                              RADEON_PCIE_LC_SHORT_RECONFIG_EN);
 541         link_width_cntl |= mask;
 542         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
 543         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
 544                                                      RADEON_PCIE_LC_RECONFIG_NOW));
 545
 546         /* wait for lane set to complete */
 547         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 548         while (link_width_cntl == 0xffffffff)
 549                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 550
 551 }
 552
 553 int rv370_get_pcie_lanes(struct radeon_device *rdev)
 554 {
 555         u32 link_width_cntl;
 556
 557         if (rdev->flags & RADEON_IS_IGP)
 558                 return 0;
 559
 560         if (!(rdev->flags & RADEON_IS_PCIE))
 561                 return 0;
 562
 563         /* FIXME wait for idle */
 564
 565         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 566
 567         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
 568         case RADEON_PCIE_LC_LINK_WIDTH_X0:
 569                 return 0;
 570         case RADEON_PCIE_LC_LINK_WIDTH_X1:
 571                 return 1;
 572         case RADEON_PCIE_LC_LINK_WIDTH_X2:
 573                 return 2;
 574         case RADEON_PCIE_LC_LINK_WIDTH_X4:
 575                 return 4;
 576         case RADEON_PCIE_LC_LINK_WIDTH_X8:
 577                 return 8;
 578         case RADEON_PCIE_LC_LINK_WIDTH_X16:
 579         default:
 580                 return 16;
 581         }
 582 }
 583
 584 #if defined(CONFIG_DEBUG_FS)
 585 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
 586 {
 587         struct drm_info_node *node = (struct drm_info_node *) m->private;
 588         struct drm_device *dev = node->minor->dev;
 589         struct radeon_device *rdev = dev->dev_private;
 590         uint32_t tmp;
 591
 592         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 593         seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
 594         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
 595         seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
 596         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
 597         seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
 598         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
 599         seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
 600         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
 601         seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
 602         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
 603         seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
 604         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
 605         seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
 606         return 0;
 607 }
 608
 609 static struct drm_info_list rv370_pcie_gart_info_list[] = {
 610         {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
 611 };
 612 #endif
 613
 614 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
 615 {
 616 #if defined(CONFIG_DEBUG_FS)
 617         return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
 618 #else
 619         return 0;
 620 #endif
 621 }
 622
 623 static int r300_packet0_check(struct radeon_cs_parser *p,
 624                 struct radeon_cs_packet *pkt,
 625                 unsigned idx, unsigned reg)
 626 {
 627         struct radeon_cs_reloc *reloc;
 628         struct r100_cs_track *track;
 629         volatile uint32_t *ib;
 630         uint32_t tmp, tile_flags = 0;
 631         unsigned i;
 632         int r;
 633         u32 idx_value;
 634
 635         ib = p->ib->ptr;
 636         track = (struct r100_cs_track *)p->track;
 637         idx_value = radeon_get_ib_value(p, idx);
 638
 639         switch(reg) {
 640         case AVIVO_D1MODE_VLINE_START_END:
 641         case RADEON_CRTC_GUI_TRIG_VLINE:
 642                 r = r100_cs_packet_parse_vline(p);
 643                 if (r) {
 644                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 645                                         idx, reg);
 646                         r100_cs_dump_packet(p, pkt);
 647                         return r;
 648                 }
 649                 break;
 650         case RADEON_DST_PITCH_OFFSET:
 651         case RADEON_SRC_PITCH_OFFSET:
 652                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
 653                 if (r)
 654                         return r;
 655                 break;
 656         case R300_RB3D_COLOROFFSET0:
 657         case R300_RB3D_COLOROFFSET1:
 658         case R300_RB3D_COLOROFFSET2:
 659         case R300_RB3D_COLOROFFSET3:
 660                 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
 661                 r = r100_cs_packet_next_reloc(p, &reloc);
 662                 if (r) {
 663                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 664                                         idx, reg);
 665                         r100_cs_dump_packet(p, pkt);
 666                         return r;
 667                 }
 668                 track->cb[i].robj = reloc->robj;
 669                 track->cb[i].offset = idx_value;
 670                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 671                 break;
 672         case R300_ZB_DEPTHOFFSET:
 673                 r = r100_cs_packet_next_reloc(p, &reloc);
 674                 if (r) {
 675                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 676                                         idx, reg);
 677                         r100_cs_dump_packet(p, pkt);
 678                         return r;
 679                 }
 680                 track->zb.robj = reloc->robj;
 681                 track->zb.offset = idx_value;
 682                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 683                 break;
 684         case R300_TX_OFFSET_0:
 685         case R300_TX_OFFSET_0+4:
 686         case R300_TX_OFFSET_0+8:
 687         case R300_TX_OFFSET_0+12:
 688         case R300_TX_OFFSET_0+16:
 689         case R300_TX_OFFSET_0+20:
 690         case R300_TX_OFFSET_0+24:
 691         case R300_TX_OFFSET_0+28:
 692         case R300_TX_OFFSET_0+32:
 693         case R300_TX_OFFSET_0+36:
 694         case R300_TX_OFFSET_0+40:
 695         case R300_TX_OFFSET_0+44:
 696         case R300_TX_OFFSET_0+48:
 697         case R300_TX_OFFSET_0+52:
 698         case R300_TX_OFFSET_0+56:
 699         case R300_TX_OFFSET_0+60:
 700                 i = (reg - R300_TX_OFFSET_0) >> 2;
 701                 r = r100_cs_packet_next_reloc(p, &reloc);
 702                 if (r) {
 703                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 704                                         idx, reg);
 705                         r100_cs_dump_packet(p, pkt);
 706                         return r;
 707                 }
 708
 709                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 710                         tile_flags |= R300_TXO_MACRO_TILE;
 711                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 712                         tile_flags |= R300_TXO_MICRO_TILE;
 713                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
 714                         tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
 715
 716                 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
 717                 tmp |= tile_flags;
 718                 ib[idx] = tmp;
 719                 track->textures[i].robj = reloc->robj;
 720                 break;
 721         /* Tracked registers */
 722         case 0x2084:
 723                 /* VAP_VF_CNTL */
 724                 track->vap_vf_cntl = idx_value;
 725                 break;
 726         case 0x20B4:
 727                 /* VAP_VTX_SIZE */
 728                 track->vtx_size = idx_value & 0x7F;
 729                 break;
 730         case 0x2134:
 731                 /* VAP_VF_MAX_VTX_INDX */
 732                 track->max_indx = idx_value & 0x00FFFFFFUL;
 733                 break;
 734         case 0x2088:
 735                 /* VAP_ALT_NUM_VERTICES - only valid on r500 */
 736                 if (p->rdev->family < CHIP_RV515)
 737                         goto fail;
 738                 track->vap_alt_nverts = idx_value & 0xFFFFFF;
 739                 break;
 740         case 0x43E4:
 741                 /* SC_SCISSOR1 */
 742                 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
 743                 if (p->rdev->family < CHIP_RV515) {
 744                         track->maxy -= 1440;
 745                 }
 746                 break;
 747         case 0x4E00:
 748                 /* RB3D_CCTL */
 749                 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */
 750                     p->rdev->cmask_filp != p->filp) {
 751                         DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n");
 752                         return -EINVAL;
 753                 }
 754                 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
 755                 break;
 756         case 0x4E38:
 757         case 0x4E3C:
 758         case 0x4E40:
 759         case 0x4E44:
 760                 /* RB3D_COLORPITCH0 */
 761                 /* RB3D_COLORPITCH1 */
 762                 /* RB3D_COLORPITCH2 */
 763                 /* RB3D_COLORPITCH3 */
 764                 r = r100_cs_packet_next_reloc(p, &reloc);
 765                 if (r) {
 766                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 767                                   idx, reg);
 768                         r100_cs_dump_packet(p, pkt);
 769                         return r;
 770                 }
 771
 772                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 773                         tile_flags |= R300_COLOR_TILE_ENABLE;
 774                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 775                         tile_flags |= R300_COLOR_MICROTILE_ENABLE;
 776                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
 777                         tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
 778
 779                 tmp = idx_value & ~(0x7 << 16);
 780                 tmp |= tile_flags;
 781                 ib[idx] = tmp;
 782                 i = (reg - 0x4E38) >> 2;
 783                 track->cb[i].pitch = idx_value & 0x3FFE;
 784                 switch (((idx_value >> 21) & 0xF)) {
 785                 case 9:
 786                 case 11:
 787                 case 12:
 788                         track->cb[i].cpp = 1;
 789                         break;
 790                 case 3:
 791                 case 4:
 792                 case 13:
 793                 case 15:
 794                         track->cb[i].cpp = 2;
 795                         break;
 796                 case 5:
 797                         if (p->rdev->family < CHIP_RV515) {
 798                                 DRM_ERROR("Invalid color buffer format (%d)!\n",
 799                                           ((idx_value >> 21) & 0xF));
 800                                 return -EINVAL;
 801                         }
 802                         /* Pass through. */
 803                 case 6:
 804                         track->cb[i].cpp = 4;
 805                         break;
 806                 case 10:
 807                         track->cb[i].cpp = 8;
 808                         break;
 809                 case 7:
 810                         track->cb[i].cpp = 16;
 811                         break;
 812                 default:
 813                         DRM_ERROR("Invalid color buffer format (%d) !\n",
 814                                   ((idx_value >> 21) & 0xF));
 815                         return -EINVAL;
 816                 }
 817                 break;
 818         case 0x4F00:
 819                 /* ZB_CNTL */
 820                 if (idx_value & 2) {
 821                         track->z_enabled = true;
 822                 } else {
 823                         track->z_enabled = false;
 824                 }
 825                 break;
 826         case 0x4F10:
 827                 /* ZB_FORMAT */
 828                 switch ((idx_value & 0xF)) {
 829                 case 0:
 830                 case 1:
 831                         track->zb.cpp = 2;
 832                         break;
 833                 case 2:
 834                         track->zb.cpp = 4;
 835                         break;
 836                 default:
 837                         DRM_ERROR("Invalid z buffer format (%d) !\n",
 838                                   (idx_value & 0xF));
 839                         return -EINVAL;
 840                 }
 841                 break;
 842         case 0x4F24:
 843                 /* ZB_DEPTHPITCH */
 844                 r = r100_cs_packet_next_reloc(p, &reloc);
 845                 if (r) {
 846                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 847                                   idx, reg);
 848                         r100_cs_dump_packet(p, pkt);
 849                         return r;
 850                 }
 851
 852                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 853                         tile_flags |= R300_DEPTHMACROTILE_ENABLE;
 854                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 855                         tile_flags |= R300_DEPTHMICROTILE_TILED;
 856                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
 857                         tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
 858
 859                 tmp = idx_value & ~(0x7 << 16);
 860                 tmp |= tile_flags;
 861                 ib[idx] = tmp;
 862
 863                 track->zb.pitch = idx_value & 0x3FFC;
 864                 break;
 865         case 0x4104:
 866                 for (i = 0; i < 16; i++) {
 867                         bool enabled;
 868
 869                         enabled = !!(idx_value & (1 << i));
 870                         track->textures[i].enabled = enabled;
 871                 }
 872                 break;
 873         case 0x44C0:
 874         case 0x44C4:
 875         case 0x44C8:
 876         case 0x44CC:
 877         case 0x44D0:
 878         case 0x44D4:
 879         case 0x44D8:
 880         case 0x44DC:
 881         case 0x44E0:
 882         case 0x44E4:
 883         case 0x44E8:
 884         case 0x44EC:
 885         case 0x44F0:
 886         case 0x44F4:
 887         case 0x44F8:
 888         case 0x44FC:
 889                 /* TX_FORMAT1_[0-15] */
 890                 i = (reg - 0x44C0) >> 2;
 891                 tmp = (idx_value >> 25) & 0x3;
 892                 track->textures[i].tex_coord_type = tmp;
 893                 switch ((idx_value & 0x1F)) {
 894                 case R300_TX_FORMAT_X8:
 895                 case R300_TX_FORMAT_Y4X4:
 896                 case R300_TX_FORMAT_Z3Y3X2:
 897                         track->textures[i].cpp = 1;
 898                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 899                         break;
 900                 case R300_TX_FORMAT_X16:
 901                 case R300_TX_FORMAT_Y8X8:
 902                 case R300_TX_FORMAT_Z5Y6X5:
 903                 case R300_TX_FORMAT_Z6Y5X5:
 904                 case R300_TX_FORMAT_W4Z4Y4X4:
 905                 case R300_TX_FORMAT_W1Z5Y5X5:
 906                 case R300_TX_FORMAT_D3DMFT_CxV8U8:
 907                 case R300_TX_FORMAT_B8G8_B8G8:
 908                 case R300_TX_FORMAT_G8R8_G8B8:
 909                         track->textures[i].cpp = 2;
 910                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 911                         break;
 912                 case R300_TX_FORMAT_Y16X16:
 913                 case R300_TX_FORMAT_Z11Y11X10:
 914                 case R300_TX_FORMAT_Z10Y11X11:
 915                 case R300_TX_FORMAT_W8Z8Y8X8:
 916                 case R300_TX_FORMAT_W2Z10Y10X10:
 917                 case 0x17:
 918                 case R300_TX_FORMAT_FL_I32:
 919                 case 0x1e:
 920                         track->textures[i].cpp = 4;
 921                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 922                         break;
 923                 case R300_TX_FORMAT_W16Z16Y16X16:
 924                 case R300_TX_FORMAT_FL_R16G16B16A16:
 925                 case R300_TX_FORMAT_FL_I32A32:
 926                         track->textures[i].cpp = 8;
 927                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 928                         break;
 929                 case R300_TX_FORMAT_FL_R32G32B32A32:
 930                         track->textures[i].cpp = 16;
 931                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 932                         break;
 933                 case R300_TX_FORMAT_DXT1:
 934                         track->textures[i].cpp = 1;
 935                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
 936                         break;
 937                 case R300_TX_FORMAT_ATI2N:
 938                         if (p->rdev->family < CHIP_R420) {
 939                                 DRM_ERROR("Invalid texture format %u\n",
 940                                           (idx_value & 0x1F));
 941                                 return -EINVAL;
 942                         }
 943                         /* The same rules apply as for DXT3/5. */
 944                         /* Pass through. */
 945                 case R300_TX_FORMAT_DXT3:
 946                 case R300_TX_FORMAT_DXT5:
 947                         track->textures[i].cpp = 1;
 948                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
 949                         break;
 950                 default:
 951                         DRM_ERROR("Invalid texture format %u\n",
 952                                   (idx_value & 0x1F));
 953                         return -EINVAL;
 954                         break;
 955                 }
 956                 break;
 957         case 0x4400:
 958         case 0x4404:
 959         case 0x4408:
 960         case 0x440C:
 961         case 0x4410:
 962         case 0x4414:
 963         case 0x4418:
 964         case 0x441C:
 965         case 0x4420:
 966         case 0x4424:
 967         case 0x4428:
 968         case 0x442C:
 969         case 0x4430:
 970         case 0x4434:
 971         case 0x4438:
 972         case 0x443C:
 973                 /* TX_FILTER0_[0-15] */
 974                 i = (reg - 0x4400) >> 2;
 975                 tmp = idx_value & 0x7;
 976                 if (tmp == 2 || tmp == 4 || tmp == 6) {
 977                         track->textures[i].roundup_w = false;
 978                 }
 979                 tmp = (idx_value >> 3) & 0x7;
 980                 if (tmp == 2 || tmp == 4 || tmp == 6) {
 981                         track->textures[i].roundup_h = false;
 982                 }
 983                 break;
 984         case 0x4500:
 985         case 0x4504:
 986         case 0x4508:
 987         case 0x450C:
 988         case 0x4510:
 989         case 0x4514:
 990         case 0x4518:
 991         case 0x451C:
 992         case 0x4520:
 993         case 0x4524:
 994         case 0x4528:
 995         case 0x452C:
 996         case 0x4530:
 997         case 0x4534:
 998         case 0x4538:
 999         case 0x453C:
1000                 /* TX_FORMAT2_[0-15] */
1001                 i = (reg - 0x4500) >> 2;
1002                 tmp = idx_value & 0x3FFF;
1003                 track->textures[i].pitch = tmp + 1;
1004                 if (p->rdev->family >= CHIP_RV515) {
1005                         tmp = ((idx_value >> 15) & 1) << 11;
1006                         track->textures[i].width_11 = tmp;
1007                         tmp = ((idx_value >> 16) & 1) << 11;
1008                         track->textures[i].height_11 = tmp;
1009
1010                         /* ATI1N */
1011                         if (idx_value & (1 << 14)) {
1012                                 /* The same rules apply as for DXT1. */
1013                                 track->textures[i].compress_format =
1014                                         R100_TRACK_COMP_DXT1;
1015                         }
1016                 } else if (idx_value & (1 << 14)) {
1017                         DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
1018                         return -EINVAL;
1019                 }
1020                 break;
1021         case 0x4480:
1022         case 0x4484:
1023         case 0x4488:
1024         case 0x448C:
1025         case 0x4490:
1026         case 0x4494:
1027         case 0x4498:
1028         case 0x449C:
1029         case 0x44A0:
1030         case 0x44A4:
1031         case 0x44A8:
1032         case 0x44AC:
1033         case 0x44B0:
1034         case 0x44B4:
1035         case 0x44B8:
1036         case 0x44BC:
1037                 /* TX_FORMAT0_[0-15] */
1038                 i = (reg - 0x4480) >> 2;
1039                 tmp = idx_value & 0x7FF;
1040                 track->textures[i].width = tmp + 1;
1041                 tmp = (idx_value >> 11) & 0x7FF;
1042                 track->textures[i].height = tmp + 1;
1043                 tmp = (idx_value >> 26) & 0xF;
1044                 track->textures[i].num_levels = tmp;
1045                 tmp = idx_value & (1 << 31);
1046                 track->textures[i].use_pitch = !!tmp;
1047                 tmp = (idx_value >> 22) & 0xF;
1048                 track->textures[i].txdepth = tmp;
1049                 break;
1050         case R300_ZB_ZPASS_ADDR:
1051                 r = r100_cs_packet_next_reloc(p, &reloc);
1052                 if (r) {
1053                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1054                                         idx, reg);
1055                         r100_cs_dump_packet(p, pkt);
1056                         return r;
1057                 }
1058                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1059                 break;
1060         case 0x4e0c:
1061                 /* RB3D_COLOR_CHANNEL_MASK */
1062                 track->color_channel_mask = idx_value;
1063                 break;
1064         case 0x43a4:
1065                 /* SC_HYPERZ_EN */
1066                 /* r300c emits this register - we need to disable hyperz for it
1067                  * without complaining */
1068                 if (p->rdev->hyperz_filp != p->filp) {
1069                         if (idx_value & 0x1)
1070                                 ib[idx] = idx_value & ~1;
1071                 }
1072                 break;
1073         case 0x4f1c:
1074                 /* ZB_BW_CNTL */
1075                 track->zb_cb_clear = !!(idx_value & (1 << 5));
1076                 if (p->rdev->hyperz_filp != p->filp) {
1077                         if (idx_value & (R300_HIZ_ENABLE |
1078                                          R300_RD_COMP_ENABLE |
1079                                          R300_WR_COMP_ENABLE |
1080                                          R300_FAST_FILL_ENABLE))
1081                                 goto fail;
1082                 }
1083                 break;
1084         case 0x4e04:
1085                 /* RB3D_BLENDCNTL */
1086                 track->blend_read_enable = !!(idx_value & (1 << 2));
1087                 break;
1088         case 0x4f28: /* ZB_DEPTHCLEARVALUE */
1089                 break;
1090         case 0x4f30: /* ZB_MASK_OFFSET */
1091         case 0x4f34: /* ZB_ZMASK_PITCH */
1092         case 0x4f44: /* ZB_HIZ_OFFSET */
1093         case 0x4f54: /* ZB_HIZ_PITCH */
1094                 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1095                         goto fail;
1096                 break;
1097         case 0x4028:
1098                 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1099                         goto fail;
1100                 /* GB_Z_PEQ_CONFIG */
1101                 if (p->rdev->family >= CHIP_RV350)
1102                         break;
1103                 goto fail;
1104                 break;
1105         case 0x4be8:
1106                 /* valid register only on RV530 */
1107                 if (p->rdev->family == CHIP_RV530)
1108                         break;
1109                 /* fallthrough do not move */
1110         default:
1111                 goto fail;
1112         }
1113         return 0;
1114 fail:
1115         printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n",
1116                reg, idx, idx_value);
1117         return -EINVAL;
1118 }
1119
1120 static int r300_packet3_check(struct radeon_cs_parser *p,
1121                               struct radeon_cs_packet *pkt)
1122 {
1123         struct radeon_cs_reloc *reloc;
1124         struct r100_cs_track *track;
1125         volatile uint32_t *ib;
1126         unsigned idx;
1127         int r;
1128
1129         ib = p->ib->ptr;
1130         idx = pkt->idx + 1;
1131         track = (struct r100_cs_track *)p->track;
1132         switch(pkt->opcode) {
1133         case PACKET3_3D_LOAD_VBPNTR:
1134                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1135                 if (r)
1136                         return r;
1137                 break;
1138         case PACKET3_INDX_BUFFER:
1139                 r = r100_cs_packet_next_reloc(p, &reloc);
1140                 if (r) {
1141                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1142                         r100_cs_dump_packet(p, pkt);
1143                         return r;
1144                 }
1145                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1146                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1147                 if (r) {
1148                         return r;
1149                 }
1150                 break;
1151         /* Draw packet */
1152         case PACKET3_3D_DRAW_IMMD:
1153                 /* Number of dwords is vtx_size * (num_vertices - 1)
1154                  * PRIM_WALK must be equal to 3 vertex data in embedded
1155                  * in cmd stream */
1156                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1157                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1158                         return -EINVAL;
1159                 }
1160                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1161                 track->immd_dwords = pkt->count - 1;
1162                 r = r100_cs_track_check(p->rdev, track);
1163                 if (r) {
1164                         return r;
1165                 }
1166                 break;
1167         case PACKET3_3D_DRAW_IMMD_2:
1168                 /* Number of dwords is vtx_size * (num_vertices - 1)
1169                  * PRIM_WALK must be equal to 3 vertex data in embedded
1170                  * in cmd stream */
1171                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1172                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1173                         return -EINVAL;
1174                 }
1175                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1176                 track->immd_dwords = pkt->count;
1177                 r = r100_cs_track_check(p->rdev, track);
1178                 if (r) {
1179                         return r;
1180                 }
1181                 break;
1182         case PACKET3_3D_DRAW_VBUF:
1183                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1184                 r = r100_cs_track_check(p->rdev, track);
1185                 if (r) {
1186                         return r;
1187                 }
1188                 break;
1189         case PACKET3_3D_DRAW_VBUF_2:
1190                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1191                 r = r100_cs_track_check(p->rdev, track);
1192                 if (r) {
1193                         return r;
1194                 }
1195                 break;
1196         case PACKET3_3D_DRAW_INDX:
1197                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1198                 r = r100_cs_track_check(p->rdev, track);
1199                 if (r) {
1200                         return r;
1201                 }
1202                 break;
1203         case PACKET3_3D_DRAW_INDX_2:
1204                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1205                 r = r100_cs_track_check(p->rdev, track);
1206                 if (r) {
1207                         return r;
1208                 }
1209                 break;
1210         case PACKET3_3D_CLEAR_HIZ:
1211         case PACKET3_3D_CLEAR_ZMASK:
1212                 if (p->rdev->hyperz_filp != p->filp)
1213                         return -EINVAL;
1214                 break;
1215         case PACKET3_3D_CLEAR_CMASK:
1216                 if (p->rdev->cmask_filp != p->filp)
1217                         return -EINVAL;
1218                 break;
1219         case PACKET3_NOP:
1220                 break;
1221         default:
1222                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1223                 return -EINVAL;
1224         }
1225         return 0;
1226 }
1227
1228 int r300_cs_parse(struct radeon_cs_parser *p)
1229 {
1230         struct radeon_cs_packet pkt;
1231         struct r100_cs_track *track;
1232         int r;
1233
1234         track = kzalloc(sizeof(*track), GFP_KERNEL);
1235         if (track == NULL)
1236                 return -ENOMEM;
1237         r100_cs_track_clear(p->rdev, track);
1238         p->track = track;
1239         do {
1240                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1241                 if (r) {
1242                         return r;
1243                 }
1244                 p->idx += pkt.count + 2;
1245                 switch (pkt.type) {
1246                 case PACKET_TYPE0:
1247                         r = r100_cs_parse_packet0(p, &pkt,
1248                                                   p->rdev->config.r300.reg_safe_bm,
1249                                                   p->rdev->config.r300.reg_safe_bm_size,
1250                                                   &r300_packet0_check);
1251                         break;
1252                 case PACKET_TYPE2:
1253                         break;
1254                 case PACKET_TYPE3:
1255                         r = r300_packet3_check(p, &pkt);
1256                         break;
1257                 default:
1258                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1259                         return -EINVAL;
1260                 }
1261                 if (r) {
1262                         return r;
1263                 }
1264         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1265         return 0;
1266 }
1267
1268 void r300_set_reg_safe(struct radeon_device *rdev)
1269 {
1270         rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1271         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1272 }
1273
1274 void r300_mc_program(struct radeon_device *rdev)
1275 {
1276         struct r100_mc_save save;
1277         int r;
1278
1279         r = r100_debugfs_mc_info_init(rdev);
1280         if (r) {
1281                 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1282         }
1283
1284         /* Stops all mc clients */
1285         r100_mc_stop(rdev, &save);
1286         if (rdev->flags & RADEON_IS_AGP) {
1287                 WREG32(R_00014C_MC_AGP_LOCATION,
1288                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1289                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1290                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1291                 WREG32(R_00015C_AGP_BASE_2,
1292                         upper_32_bits(rdev->mc.agp_base) & 0xff);
1293         } else {
1294                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1295                 WREG32(R_000170_AGP_BASE, 0);
1296                 WREG32(R_00015C_AGP_BASE_2, 0);
1297         }
1298         /* Wait for mc idle */
1299         if (r300_mc_wait_for_idle(rdev))
1300                 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1301         /* Program MC, should be a 32bits limited address space */
1302         WREG32(R_000148_MC_FB_LOCATION,
1303                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1304                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1305         r100_mc_resume(rdev, &save);
1306 }
1307
1308 void r300_clock_startup(struct radeon_device *rdev)
1309 {
1310         u32 tmp;
1311
1312         if (radeon_dynclks != -1 && radeon_dynclks)
1313                 radeon_legacy_set_clock_gating(rdev, 1);
1314         /* We need to force on some of the block */
1315         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1316         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1317         if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1318                 tmp |= S_00000D_FORCE_VAP(1);
1319         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1320 }
1321
1322 static int r300_startup(struct radeon_device *rdev)
1323 {
1324         int r;
1325
1326         /* set common regs */
1327         r100_set_common_regs(rdev);
1328         /* program mc */
1329         r300_mc_program(rdev);
1330         /* Resume clock */
1331         r300_clock_startup(rdev);
1332         /* Initialize GPU configuration (# pipes, ...) */
1333         r300_gpu_init(rdev);
1334         /* Initialize GART (initialize after TTM so we can allocate
1335          * memory through TTM but finalize after TTM) */
1336         if (rdev->flags & RADEON_IS_PCIE) {
1337                 r = rv370_pcie_gart_enable(rdev);
1338                 if (r)
1339                         return r;
1340         }
1341
1342         if (rdev->family == CHIP_R300 ||
1343             rdev->family == CHIP_R350 ||
1344             rdev->family == CHIP_RV350)
1345                 r100_enable_bm(rdev);
1346
1347         if (rdev->flags & RADEON_IS_PCI) {
1348                 r = r100_pci_gart_enable(rdev);
1349                 if (r)
1350                         return r;
1351         }
1352
1353         /* allocate wb buffer */
1354         r = radeon_wb_init(rdev);
1355         if (r)
1356                 return r;
1357
1358         /* Enable IRQ */
1359         r100_irq_set(rdev);
1360         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1361         /* 1M ring buffer */
1362         r = r100_cp_init(rdev, 1024 * 1024);
1363         if (r) {
1364                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
1365                 return r;
1366         }
1367         r = r100_ib_init(rdev);
1368         if (r) {
1369                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
1370                 return r;
1371         }
1372         return 0;
1373 }
1374
1375 int r300_resume(struct radeon_device *rdev)
1376 {
1377         /* Make sur GART are not working */
1378         if (rdev->flags & RADEON_IS_PCIE)
1379                 rv370_pcie_gart_disable(rdev);
1380         if (rdev->flags & RADEON_IS_PCI)
1381                 r100_pci_gart_disable(rdev);
1382         /* Resume clock before doing reset */
1383         r300_clock_startup(rdev);
1384         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1385         if (radeon_asic_reset(rdev)) {
1386                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1387                         RREG32(R_000E40_RBBM_STATUS),
1388                         RREG32(R_0007C0_CP_STAT));
1389         }
1390         /* post */
1391         radeon_combios_asic_init(rdev->ddev);
1392         /* Resume clock after posting */
1393         r300_clock_startup(rdev);
1394         /* Initialize surface registers */
1395         radeon_surface_init(rdev);
1396         return r300_startup(rdev);
1397 }
1398
1399 int r300_suspend(struct radeon_device *rdev)
1400 {
1401         r100_cp_disable(rdev);
1402         radeon_wb_disable(rdev);
1403         r100_irq_disable(rdev);
1404         if (rdev->flags & RADEON_IS_PCIE)
1405                 rv370_pcie_gart_disable(rdev);
1406         if (rdev->flags & RADEON_IS_PCI)
1407                 r100_pci_gart_disable(rdev);
1408         return 0;
1409 }
1410
1411 void r300_fini(struct radeon_device *rdev)
1412 {
1413         r100_cp_fini(rdev);
1414         radeon_wb_fini(rdev);
1415         r100_ib_fini(rdev);
1416         radeon_gem_fini(rdev);
1417         if (rdev->flags & RADEON_IS_PCIE)
1418                 rv370_pcie_gart_fini(rdev);
1419         if (rdev->flags & RADEON_IS_PCI)
1420                 r100_pci_gart_fini(rdev);
1421         radeon_agp_fini(rdev);
1422         radeon_irq_kms_fini(rdev);
1423         radeon_fence_driver_fini(rdev);
1424         radeon_bo_fini(rdev);
1425         radeon_atombios_fini(rdev);
1426         kfree(rdev->bios);
1427         rdev->bios = NULL;
1428 }
1429
1430 int r300_init(struct radeon_device *rdev)
1431 {
1432         int r;
1433
1434         /* Disable VGA */
1435         r100_vga_render_disable(rdev);
1436         /* Initialize scratch registers */
1437         radeon_scratch_init(rdev);
1438         /* Initialize surface registers */
1439         radeon_surface_init(rdev);
1440         /* TODO: disable VGA need to use VGA request */
1441         /* restore some register to sane defaults */
1442         r100_restore_sanity(rdev);
1443         /* BIOS*/
1444         if (!radeon_get_bios(rdev)) {
1445                 if (ASIC_IS_AVIVO(rdev))
1446                         return -EINVAL;
1447         }
1448         if (rdev->is_atom_bios) {
1449                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1450                 return -EINVAL;
1451         } else {
1452                 r = radeon_combios_init(rdev);
1453                 if (r)
1454                         return r;
1455         }
1456         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1457         if (radeon_asic_reset(rdev)) {
1458                 dev_warn(rdev->dev,
1459                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1460                         RREG32(R_000E40_RBBM_STATUS),
1461                         RREG32(R_0007C0_CP_STAT));
1462         }
1463         /* check if cards are posted or not */
1464         if (radeon_boot_test_post_card(rdev) == false)
1465                 return -EINVAL;
1466         /* Set asic errata */
1467         r300_errata(rdev);
1468         /* Initialize clocks */
1469         radeon_get_clock_info(rdev->ddev);
1470         /* initialize AGP */
1471         if (rdev->flags & RADEON_IS_AGP) {
1472                 r = radeon_agp_init(rdev);
1473                 if (r) {
1474                         radeon_agp_disable(rdev);
1475                 }
1476         }
1477         /* initialize memory controller */
1478         r300_mc_init(rdev);
1479         /* Fence driver */
1480         r = radeon_fence_driver_init(rdev);
1481         if (r)
1482                 return r;
1483         r = radeon_irq_kms_init(rdev);
1484         if (r)
1485                 return r;
1486         /* Memory manager */
1487         r = radeon_bo_init(rdev);
1488         if (r)
1489                 return r;
1490         if (rdev->flags & RADEON_IS_PCIE) {
1491                 r = rv370_pcie_gart_init(rdev);
1492                 if (r)
1493                         return r;
1494         }
1495         if (rdev->flags & RADEON_IS_PCI) {
1496                 r = r100_pci_gart_init(rdev);
1497                 if (r)
1498                         return r;
1499         }
1500         r300_set_reg_safe(rdev);
1501         rdev->accel_working = true;
1502         r = r300_startup(rdev);
1503         if (r) {
1504                 /* Somethings want wront with the accel init stop accel */
1505                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1506                 r100_cp_fini(rdev);
1507                 radeon_wb_fini(rdev);
1508                 r100_ib_fini(rdev);
1509                 radeon_irq_kms_fini(rdev);
1510                 if (rdev->flags & RADEON_IS_PCIE)
1511                         rv370_pcie_gart_fini(rdev);
1512                 if (rdev->flags & RADEON_IS_PCI)
1513                         r100_pci_gart_fini(rdev);
1514                 radeon_agp_fini(rdev);
1515                 rdev->accel_working = false;
1516         }
1517         return 0;
1518 }