drivers/gpu/drm/radeon/r300.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "radeon_reg.h"
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34 #include "radeon_drm.h"
  35 #include "r100_track.h"
  36 #include "r300d.h"
  37 #include "rv350d.h"
  38 #include "r300_reg_safe.h"
  39
  40 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
  41  *
  42  * GPU Errata:
  43  * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
  44  *   using MMIO to flush host path read cache, this lead to HARDLOCKUP.
  45  *   However, scheduling such write to the ring seems harmless, i suspect
  46  *   the CP read collide with the flush somehow, or maybe the MC, hard to
  47  *   tell. (Jerome Glisse)
  48  */
  49
  50 /*
  51  * rv370,rv380 PCIE GART
  52  */
  53 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
  54
  55 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
  56 {
  57         uint32_t tmp;
  58         int i;
  59
  60         /* Workaround HW bug do flush 2 times */
  61         for (i = 0; i < 2; i++) {
  62                 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  63                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
  64                 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  65                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
  66         }
  67         mb();
  68 }
  69
  70 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
  71 {
  72         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
  73
  74         if (i < 0 || i > rdev->gart.num_gpu_pages) {
  75                 return -EINVAL;
  76         }
  77         addr = (lower_32_bits(addr) >> 8) |
  78                ((upper_32_bits(addr) & 0xff) << 24) |
  79                0xc;
  80         /* on x86 we want this to be CPU endian, on powerpc
  81          * on powerpc without HW swappers, it'll get swapped on way
  82          * into VRAM - so no need for cpu_to_le32 on VRAM tables */
  83         writel(addr, ((void __iomem *)ptr) + (i * 4));
  84         return 0;
  85 }
  86
  87 int rv370_pcie_gart_init(struct radeon_device *rdev)
  88 {
  89         int r;
  90
  91         if (rdev->gart.table.vram.robj) {
  92                 WARN(1, "RV370 PCIE GART already initialized.\n");
  93                 return 0;
  94         }
  95         /* Initialize common gart structure */
  96         r = radeon_gart_init(rdev);
  97         if (r)
  98                 return r;
  99         r = rv370_debugfs_pcie_gart_info_init(rdev);
 100         if (r)
 101                 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
 102         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 103         rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
 104         rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 105         return radeon_gart_table_vram_alloc(rdev);
 106 }
 107
 108 int rv370_pcie_gart_enable(struct radeon_device *rdev)
 109 {
 110         uint32_t table_addr;
 111         uint32_t tmp;
 112         int r;
 113
 114         if (rdev->gart.table.vram.robj == NULL) {
 115                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 116                 return -EINVAL;
 117         }
 118         r = radeon_gart_table_vram_pin(rdev);
 119         if (r)
 120                 return r;
 121         radeon_gart_restore(rdev);
 122         /* discard memory request outside of configured range */
 123         tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 124         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 125         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
 126         tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
 127         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
 128         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
 129         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
 130         table_addr = rdev->gart.table_addr;
 131         WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
 132         /* FIXME: setup default page */
 133         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
 134         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
 135         /* Clear error */
 136         WREG32_PCIE(0x18, 0);
 137         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 138         tmp |= RADEON_PCIE_TX_GART_EN;
 139         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 140         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 141         rv370_pcie_gart_tlb_flush(rdev);
 142         DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
 143                  (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
 144         rdev->gart.ready = true;
 145         return 0;
 146 }
 147
 148 void rv370_pcie_gart_disable(struct radeon_device *rdev)
 149 {
 150         u32 tmp;
 151         int r;
 152
 153         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 154         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 155         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
 156         if (rdev->gart.table.vram.robj) {
 157                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 158                 if (likely(r == 0)) {
 159                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 160                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 161                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 162                 }
 163         }
 164 }
 165
 166 void rv370_pcie_gart_fini(struct radeon_device *rdev)
 167 {
 168         radeon_gart_fini(rdev);
 169         rv370_pcie_gart_disable(rdev);
 170         radeon_gart_table_vram_free(rdev);
 171 }
 172
 173 void r300_fence_ring_emit(struct radeon_device *rdev,
 174                           struct radeon_fence *fence)
 175 {
 176         /* Who ever call radeon_fence_emit should call ring_lock and ask
 177          * for enough space (today caller are ib schedule and buffer move) */
 178         /* Write SC register so SC & US assert idle */
 179         radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
 180         radeon_ring_write(rdev, 0);
 181         radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
 182         radeon_ring_write(rdev, 0);
 183         /* Flush 3D cache */
 184         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 185         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
 186         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 187         radeon_ring_write(rdev, R300_ZC_FLUSH);
 188         /* Wait until IDLE & CLEAN */
 189         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 190         radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN |
 191                                  RADEON_WAIT_2D_IDLECLEAN |
 192                                  RADEON_WAIT_DMA_GUI_IDLE));
 193         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 194         radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
 195                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 196         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 197         radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
 198         /* Emit fence sequence & fire IRQ */
 199         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 200         radeon_ring_write(rdev, fence->seq);
 201         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 202         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 203 }
 204
 205 void r300_ring_start(struct radeon_device *rdev)
 206 {
 207         unsigned gb_tile_config;
 208         int r;
 209
 210         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
 211         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 212         switch(rdev->num_gb_pipes) {
 213         case 2:
 214                 gb_tile_config |= R300_PIPE_COUNT_R300;
 215                 break;
 216         case 3:
 217                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 218                 break;
 219         case 4:
 220                 gb_tile_config |= R300_PIPE_COUNT_R420;
 221                 break;
 222         case 1:
 223         default:
 224                 gb_tile_config |= R300_PIPE_COUNT_RV350;
 225                 break;
 226         }
 227
 228         r = radeon_ring_lock(rdev, 64);
 229         if (r) {
 230                 return;
 231         }
 232         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 233         radeon_ring_write(rdev,
 234                           RADEON_ISYNC_ANY2D_IDLE3D |
 235                           RADEON_ISYNC_ANY3D_IDLE2D |
 236                           RADEON_ISYNC_WAIT_IDLEGUI |
 237                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 238         radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
 239         radeon_ring_write(rdev, gb_tile_config);
 240         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 241         radeon_ring_write(rdev,
 242                           RADEON_WAIT_2D_IDLECLEAN |
 243                           RADEON_WAIT_3D_IDLECLEAN);
 244         radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
 245         radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
 246         radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
 247         radeon_ring_write(rdev, 0);
 248         radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
 249         radeon_ring_write(rdev, 0);
 250         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 251         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 252         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 253         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
 254         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 255         radeon_ring_write(rdev,
 256                           RADEON_WAIT_2D_IDLECLEAN |
 257                           RADEON_WAIT_3D_IDLECLEAN);
 258         radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
 259         radeon_ring_write(rdev, 0);
 260         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 261         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 262         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 263         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
 264         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
 265         radeon_ring_write(rdev,
 266                           ((6 << R300_MS_X0_SHIFT) |
 267                            (6 << R300_MS_Y0_SHIFT) |
 268                            (6 << R300_MS_X1_SHIFT) |
 269                            (6 << R300_MS_Y1_SHIFT) |
 270                            (6 << R300_MS_X2_SHIFT) |
 271                            (6 << R300_MS_Y2_SHIFT) |
 272                            (6 << R300_MSBD0_Y_SHIFT) |
 273                            (6 << R300_MSBD0_X_SHIFT)));
 274         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
 275         radeon_ring_write(rdev,
 276                           ((6 << R300_MS_X3_SHIFT) |
 277                            (6 << R300_MS_Y3_SHIFT) |
 278                            (6 << R300_MS_X4_SHIFT) |
 279                            (6 << R300_MS_Y4_SHIFT) |
 280                            (6 << R300_MS_X5_SHIFT) |
 281                            (6 << R300_MS_Y5_SHIFT) |
 282                            (6 << R300_MSBD1_SHIFT)));
 283         radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
 284         radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
 285         radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
 286         radeon_ring_write(rdev,
 287                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
 288         radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
 289         radeon_ring_write(rdev,
 290                           R300_GEOMETRY_ROUND_NEAREST |
 291                           R300_COLOR_ROUND_NEAREST);
 292         radeon_ring_unlock_commit(rdev);
 293 }
 294
 295 void r300_errata(struct radeon_device *rdev)
 296 {
 297         rdev->pll_errata = 0;
 298
 299         if (rdev->family == CHIP_R300 &&
 300             (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
 301                 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
 302         }
 303 }
 304
 305 int r300_mc_wait_for_idle(struct radeon_device *rdev)
 306 {
 307         unsigned i;
 308         uint32_t tmp;
 309
 310         for (i = 0; i < rdev->usec_timeout; i++) {
 311                 /* read MC_STATUS */
 312                 tmp = RREG32(RADEON_MC_STATUS);
 313                 if (tmp & R300_MC_IDLE) {
 314                         return 0;
 315                 }
 316                 DRM_UDELAY(1);
 317         }
 318         return -1;
 319 }
 320
 321 void r300_gpu_init(struct radeon_device *rdev)
 322 {
 323         uint32_t gb_tile_config, tmp;
 324
 325         r100_hdp_reset(rdev);
 326         if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
 327             (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
 328                 /* r300,r350 */
 329                 rdev->num_gb_pipes = 2;
 330         } else {
 331                 /* rv350,rv370,rv380,r300 AD, r350 AH */
 332                 rdev->num_gb_pipes = 1;
 333         }
 334         rdev->num_z_pipes = 1;
 335         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 336         switch (rdev->num_gb_pipes) {
 337         case 2:
 338                 gb_tile_config |= R300_PIPE_COUNT_R300;
 339                 break;
 340         case 3:
 341                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 342                 break;
 343         case 4:
 344                 gb_tile_config |= R300_PIPE_COUNT_R420;
 345                 break;
 346         default:
 347         case 1:
 348                 gb_tile_config |= R300_PIPE_COUNT_RV350;
 349                 break;
 350         }
 351         WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
 352
 353         if (r100_gui_wait_for_idle(rdev)) {
 354                 printk(KERN_WARNING "Failed to wait GUI idle while "
 355                        "programming pipes. Bad things might happen.\n");
 356         }
 357
 358         tmp = RREG32(R300_DST_PIPE_CONFIG);
 359         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
 360
 361         WREG32(R300_RB2D_DSTCACHE_MODE,
 362                R300_DC_AUTOFLUSH_ENABLE |
 363                R300_DC_DC_DISABLE_IGNORE_PE);
 364
 365         if (r100_gui_wait_for_idle(rdev)) {
 366                 printk(KERN_WARNING "Failed to wait GUI idle while "
 367                        "programming pipes. Bad things might happen.\n");
 368         }
 369         if (r300_mc_wait_for_idle(rdev)) {
 370                 printk(KERN_WARNING "Failed to wait MC idle while "
 371                        "programming pipes. Bad things might happen.\n");
 372         }
 373         DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
 374                  rdev->num_gb_pipes, rdev->num_z_pipes);
 375 }
 376
 377 int r300_ga_reset(struct radeon_device *rdev)
 378 {
 379         uint32_t tmp;
 380         bool reinit_cp;
 381         int i;
 382
 383         reinit_cp = rdev->cp.ready;
 384         rdev->cp.ready = false;
 385         for (i = 0; i < rdev->usec_timeout; i++) {
 386                 WREG32(RADEON_CP_CSQ_MODE, 0);
 387                 WREG32(RADEON_CP_CSQ_CNTL, 0);
 388                 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
 389                 (void)RREG32(RADEON_RBBM_SOFT_RESET);
 390                 udelay(200);
 391                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
 392                 /* Wait to prevent race in RBBM_STATUS */
 393                 mdelay(1);
 394                 tmp = RREG32(RADEON_RBBM_STATUS);
 395                 if (tmp & ((1 << 20) | (1 << 26))) {
 396                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
 397                         /* GA still busy soft reset it */
 398                         WREG32(0x429C, 0x200);
 399                         WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 400                         WREG32(R300_RE_SCISSORS_TL, 0);
 401                         WREG32(R300_RE_SCISSORS_BR, 0);
 402                         WREG32(0x24AC, 0);
 403                 }
 404                 /* Wait to prevent race in RBBM_STATUS */
 405                 mdelay(1);
 406                 tmp = RREG32(RADEON_RBBM_STATUS);
 407                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
 408                         break;
 409                 }
 410         }
 411         for (i = 0; i < rdev->usec_timeout; i++) {
 412                 tmp = RREG32(RADEON_RBBM_STATUS);
 413                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
 414                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
 415                                  tmp);
 416                         if (reinit_cp) {
 417                                 return r100_cp_init(rdev, rdev->cp.ring_size);
 418                         }
 419                         return 0;
 420                 }
 421                 DRM_UDELAY(1);
 422         }
 423         tmp = RREG32(RADEON_RBBM_STATUS);
 424         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
 425         return -1;
 426 }
 427
 428 int r300_gpu_reset(struct radeon_device *rdev)
 429 {
 430         uint32_t status;
 431
 432         /* reset order likely matter */
 433         status = RREG32(RADEON_RBBM_STATUS);
 434         /* reset HDP */
 435         r100_hdp_reset(rdev);
 436         /* reset rb2d */
 437         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
 438                 r100_rb2d_reset(rdev);
 439         }
 440         /* reset GA */
 441         if (status & ((1 << 20) | (1 << 26))) {
 442                 r300_ga_reset(rdev);
 443         }
 444         /* reset CP */
 445         status = RREG32(RADEON_RBBM_STATUS);
 446         if (status & (1 << 16)) {
 447                 r100_cp_reset(rdev);
 448         }
 449         /* Check if GPU is idle */
 450         status = RREG32(RADEON_RBBM_STATUS);
 451         if (status & RADEON_RBBM_ACTIVE) {
 452                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
 453                 return -1;
 454         }
 455         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
 456         return 0;
 457 }
 458
 459
 460 /*
 461  * r300,r350,rv350,rv380 VRAM info
 462  */
 463 void r300_mc_init(struct radeon_device *rdev)
 464 {
 465         u64 base;
 466         u32 tmp;
 467
 468         /* DDR for all card after R300 & IGP */
 469         rdev->mc.vram_is_ddr = true;
 470         tmp = RREG32(RADEON_MEM_CNTL);
 471         tmp &= R300_MEM_NUM_CHANNELS_MASK;
 472         switch (tmp) {
 473         case 0: rdev->mc.vram_width = 64; break;
 474         case 1: rdev->mc.vram_width = 128; break;
 475         case 2: rdev->mc.vram_width = 256; break;
 476         default:  rdev->mc.vram_width = 128; break;
 477         }
 478         r100_vram_init_sizes(rdev);
 479         base = rdev->mc.aper_base;
 480         if (rdev->flags & RADEON_IS_IGP)
 481                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
 482         radeon_vram_location(rdev, &rdev->mc, base);
 483         if (!(rdev->flags & RADEON_IS_AGP))
 484                 radeon_gtt_location(rdev, &rdev->mc);
 485         radeon_update_bandwidth_info(rdev);
 486 }
 487
 488 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
 489 {
 490         uint32_t link_width_cntl, mask;
 491
 492         if (rdev->flags & RADEON_IS_IGP)
 493                 return;
 494
 495         if (!(rdev->flags & RADEON_IS_PCIE))
 496                 return;
 497
 498         /* FIXME wait for idle */
 499
 500         switch (lanes) {
 501         case 0:
 502                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
 503                 break;
 504         case 1:
 505                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
 506                 break;
 507         case 2:
 508                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
 509                 break;
 510         case 4:
 511                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
 512                 break;
 513         case 8:
 514                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
 515                 break;
 516         case 12:
 517                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
 518                 break;
 519         case 16:
 520         default:
 521                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
 522                 break;
 523         }
 524
 525         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 526
 527         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
 528             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
 529                 return;
 530
 531         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
 532                              RADEON_PCIE_LC_RECONFIG_NOW |
 533                              RADEON_PCIE_LC_RECONFIG_LATER |
 534                              RADEON_PCIE_LC_SHORT_RECONFIG_EN);
 535         link_width_cntl |= mask;
 536         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
 537         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
 538                                                      RADEON_PCIE_LC_RECONFIG_NOW));
 539
 540         /* wait for lane set to complete */
 541         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 542         while (link_width_cntl == 0xffffffff)
 543                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 544
 545 }
 546
 547 int rv370_get_pcie_lanes(struct radeon_device *rdev)
 548 {
 549         u32 link_width_cntl;
 550
 551         if (rdev->flags & RADEON_IS_IGP)
 552                 return 0;
 553
 554         if (!(rdev->flags & RADEON_IS_PCIE))
 555                 return 0;
 556
 557         /* FIXME wait for idle */
 558
 559         if (rdev->family < CHIP_R600)
 560                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 561         else
 562                 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 563
 564         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
 565         case RADEON_PCIE_LC_LINK_WIDTH_X0:
 566                 return 0;
 567         case RADEON_PCIE_LC_LINK_WIDTH_X1:
 568                 return 1;
 569         case RADEON_PCIE_LC_LINK_WIDTH_X2:
 570                 return 2;
 571         case RADEON_PCIE_LC_LINK_WIDTH_X4:
 572                 return 4;
 573         case RADEON_PCIE_LC_LINK_WIDTH_X8:
 574                 return 8;
 575         case RADEON_PCIE_LC_LINK_WIDTH_X16:
 576         default:
 577                 return 16;
 578         }
 579 }
 580
 581 #if defined(CONFIG_DEBUG_FS)
 582 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
 583 {
 584         struct drm_info_node *node = (struct drm_info_node *) m->private;
 585         struct drm_device *dev = node->minor->dev;
 586         struct radeon_device *rdev = dev->dev_private;
 587         uint32_t tmp;
 588
 589         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 590         seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
 591         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
 592         seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
 593         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
 594         seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
 595         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
 596         seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
 597         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
 598         seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
 599         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
 600         seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
 601         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
 602         seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
 603         return 0;
 604 }
 605
 606 static struct drm_info_list rv370_pcie_gart_info_list[] = {
 607         {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
 608 };
 609 #endif
 610
 611 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
 612 {
 613 #if defined(CONFIG_DEBUG_FS)
 614         return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
 615 #else
 616         return 0;
 617 #endif
 618 }
 619
 620 static int r300_packet0_check(struct radeon_cs_parser *p,
 621                 struct radeon_cs_packet *pkt,
 622                 unsigned idx, unsigned reg)
 623 {
 624         struct radeon_cs_reloc *reloc;
 625         struct r100_cs_track *track;
 626         volatile uint32_t *ib;
 627         uint32_t tmp, tile_flags = 0;
 628         unsigned i;
 629         int r;
 630         u32 idx_value;
 631
 632         ib = p->ib->ptr;
 633         track = (struct r100_cs_track *)p->track;
 634         idx_value = radeon_get_ib_value(p, idx);
 635
 636         switch(reg) {
 637         case AVIVO_D1MODE_VLINE_START_END:
 638         case RADEON_CRTC_GUI_TRIG_VLINE:
 639                 r = r100_cs_packet_parse_vline(p);
 640                 if (r) {
 641                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 642                                         idx, reg);
 643                         r100_cs_dump_packet(p, pkt);
 644                         return r;
 645                 }
 646                 break;
 647         case RADEON_DST_PITCH_OFFSET:
 648         case RADEON_SRC_PITCH_OFFSET:
 649                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
 650                 if (r)
 651                         return r;
 652                 break;
 653         case R300_RB3D_COLOROFFSET0:
 654         case R300_RB3D_COLOROFFSET1:
 655         case R300_RB3D_COLOROFFSET2:
 656         case R300_RB3D_COLOROFFSET3:
 657                 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
 658                 r = r100_cs_packet_next_reloc(p, &reloc);
 659                 if (r) {
 660                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 661                                         idx, reg);
 662                         r100_cs_dump_packet(p, pkt);
 663                         return r;
 664                 }
 665                 track->cb[i].robj = reloc->robj;
 666                 track->cb[i].offset = idx_value;
 667                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 668                 break;
 669         case R300_ZB_DEPTHOFFSET:
 670                 r = r100_cs_packet_next_reloc(p, &reloc);
 671                 if (r) {
 672                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 673                                         idx, reg);
 674                         r100_cs_dump_packet(p, pkt);
 675                         return r;
 676                 }
 677                 track->zb.robj = reloc->robj;
 678                 track->zb.offset = idx_value;
 679                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 680                 break;
 681         case R300_TX_OFFSET_0:
 682         case R300_TX_OFFSET_0+4:
 683         case R300_TX_OFFSET_0+8:
 684         case R300_TX_OFFSET_0+12:
 685         case R300_TX_OFFSET_0+16:
 686         case R300_TX_OFFSET_0+20:
 687         case R300_TX_OFFSET_0+24:
 688         case R300_TX_OFFSET_0+28:
 689         case R300_TX_OFFSET_0+32:
 690         case R300_TX_OFFSET_0+36:
 691         case R300_TX_OFFSET_0+40:
 692         case R300_TX_OFFSET_0+44:
 693         case R300_TX_OFFSET_0+48:
 694         case R300_TX_OFFSET_0+52:
 695         case R300_TX_OFFSET_0+56:
 696         case R300_TX_OFFSET_0+60:
 697                 i = (reg - R300_TX_OFFSET_0) >> 2;
 698                 r = r100_cs_packet_next_reloc(p, &reloc);
 699                 if (r) {
 700                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 701                                         idx, reg);
 702                         r100_cs_dump_packet(p, pkt);
 703                         return r;
 704                 }
 705
 706                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 707                         tile_flags |= R300_TXO_MACRO_TILE;
 708                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 709                         tile_flags |= R300_TXO_MICRO_TILE;
 710                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
 711                         tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
 712
 713                 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
 714                 tmp |= tile_flags;
 715                 ib[idx] = tmp;
 716                 track->textures[i].robj = reloc->robj;
 717                 break;
 718         /* Tracked registers */
 719         case 0x2084:
 720                 /* VAP_VF_CNTL */
 721                 track->vap_vf_cntl = idx_value;
 722                 break;
 723         case 0x20B4:
 724                 /* VAP_VTX_SIZE */
 725                 track->vtx_size = idx_value & 0x7F;
 726                 break;
 727         case 0x2134:
 728                 /* VAP_VF_MAX_VTX_INDX */
 729                 track->max_indx = idx_value & 0x00FFFFFFUL;
 730                 break;
 731         case 0x2088:
 732                 /* VAP_ALT_NUM_VERTICES - only valid on r500 */
 733                 if (p->rdev->family < CHIP_RV515)
 734                         goto fail;
 735                 track->vap_alt_nverts = idx_value & 0xFFFFFF;
 736                 break;
 737         case 0x43E4:
 738                 /* SC_SCISSOR1 */
 739                 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
 740                 if (p->rdev->family < CHIP_RV515) {
 741                         track->maxy -= 1440;
 742                 }
 743                 break;
 744         case 0x4E00:
 745                 /* RB3D_CCTL */
 746                 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
 747                 break;
 748         case 0x4E38:
 749         case 0x4E3C:
 750         case 0x4E40:
 751         case 0x4E44:
 752                 /* RB3D_COLORPITCH0 */
 753                 /* RB3D_COLORPITCH1 */
 754                 /* RB3D_COLORPITCH2 */
 755                 /* RB3D_COLORPITCH3 */
 756                 r = r100_cs_packet_next_reloc(p, &reloc);
 757                 if (r) {
 758                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 759                                   idx, reg);
 760                         r100_cs_dump_packet(p, pkt);
 761                         return r;
 762                 }
 763
 764                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 765                         tile_flags |= R300_COLOR_TILE_ENABLE;
 766                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 767                         tile_flags |= R300_COLOR_MICROTILE_ENABLE;
 768                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
 769                         tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
 770
 771                 tmp = idx_value & ~(0x7 << 16);
 772                 tmp |= tile_flags;
 773                 ib[idx] = tmp;
 774                 i = (reg - 0x4E38) >> 2;
 775                 track->cb[i].pitch = idx_value & 0x3FFE;
 776                 switch (((idx_value >> 21) & 0xF)) {
 777                 case 9:
 778                 case 11:
 779                 case 12:
 780                         track->cb[i].cpp = 1;
 781                         break;
 782                 case 3:
 783                 case 4:
 784                 case 13:
 785                 case 15:
 786                         track->cb[i].cpp = 2;
 787                         break;
 788                 case 6:
 789                         track->cb[i].cpp = 4;
 790                         break;
 791                 case 10:
 792                         track->cb[i].cpp = 8;
 793                         break;
 794                 case 7:
 795                         track->cb[i].cpp = 16;
 796                         break;
 797                 default:
 798                         DRM_ERROR("Invalid color buffer format (%d) !\n",
 799                                   ((idx_value >> 21) & 0xF));
 800                         return -EINVAL;
 801                 }
 802                 break;
 803         case 0x4F00:
 804                 /* ZB_CNTL */
 805                 if (idx_value & 2) {
 806                         track->z_enabled = true;
 807                 } else {
 808                         track->z_enabled = false;
 809                 }
 810                 break;
 811         case 0x4F10:
 812                 /* ZB_FORMAT */
 813                 switch ((idx_value & 0xF)) {
 814                 case 0:
 815                 case 1:
 816                         track->zb.cpp = 2;
 817                         break;
 818                 case 2:
 819                         track->zb.cpp = 4;
 820                         break;
 821                 default:
 822                         DRM_ERROR("Invalid z buffer format (%d) !\n",
 823                                   (idx_value & 0xF));
 824                         return -EINVAL;
 825                 }
 826                 break;
 827         case 0x4F24:
 828                 /* ZB_DEPTHPITCH */
 829                 r = r100_cs_packet_next_reloc(p, &reloc);
 830                 if (r) {
 831                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 832                                   idx, reg);
 833                         r100_cs_dump_packet(p, pkt);
 834                         return r;
 835                 }
 836
 837                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 838                         tile_flags |= R300_DEPTHMACROTILE_ENABLE;
 839                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 840                         tile_flags |= R300_DEPTHMICROTILE_TILED;
 841                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
 842                         tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
 843
 844                 tmp = idx_value & ~(0x7 << 16);
 845                 tmp |= tile_flags;
 846                 ib[idx] = tmp;
 847
 848                 track->zb.pitch = idx_value & 0x3FFC;
 849                 break;
 850         case 0x4104:
 851                 for (i = 0; i < 16; i++) {
 852                         bool enabled;
 853
 854                         enabled = !!(idx_value & (1 << i));
 855                         track->textures[i].enabled = enabled;
 856                 }
 857                 break;
 858         case 0x44C0:
 859         case 0x44C4:
 860         case 0x44C8:
 861         case 0x44CC:
 862         case 0x44D0:
 863         case 0x44D4:
 864         case 0x44D8:
 865         case 0x44DC:
 866         case 0x44E0:
 867         case 0x44E4:
 868         case 0x44E8:
 869         case 0x44EC:
 870         case 0x44F0:
 871         case 0x44F4:
 872         case 0x44F8:
 873         case 0x44FC:
 874                 /* TX_FORMAT1_[0-15] */
 875                 i = (reg - 0x44C0) >> 2;
 876                 tmp = (idx_value >> 25) & 0x3;
 877                 track->textures[i].tex_coord_type = tmp;
 878                 switch ((idx_value & 0x1F)) {
 879                 case R300_TX_FORMAT_X8:
 880                 case R300_TX_FORMAT_Y4X4:
 881                 case R300_TX_FORMAT_Z3Y3X2:
 882                         track->textures[i].cpp = 1;
 883                         break;
 884                 case R300_TX_FORMAT_X16:
 885                 case R300_TX_FORMAT_Y8X8:
 886                 case R300_TX_FORMAT_Z5Y6X5:
 887                 case R300_TX_FORMAT_Z6Y5X5:
 888                 case R300_TX_FORMAT_W4Z4Y4X4:
 889                 case R300_TX_FORMAT_W1Z5Y5X5:
 890                 case R300_TX_FORMAT_D3DMFT_CxV8U8:
 891                 case R300_TX_FORMAT_B8G8_B8G8:
 892                 case R300_TX_FORMAT_G8R8_G8B8:
 893                         track->textures[i].cpp = 2;
 894                         break;
 895                 case R300_TX_FORMAT_Y16X16:
 896                 case R300_TX_FORMAT_Z11Y11X10:
 897                 case R300_TX_FORMAT_Z10Y11X11:
 898                 case R300_TX_FORMAT_W8Z8Y8X8:
 899                 case R300_TX_FORMAT_W2Z10Y10X10:
 900                 case 0x17:
 901                 case R300_TX_FORMAT_FL_I32:
 902                 case 0x1e:
 903                         track->textures[i].cpp = 4;
 904                         break;
 905                 case R300_TX_FORMAT_W16Z16Y16X16:
 906                 case R300_TX_FORMAT_FL_R16G16B16A16:
 907                 case R300_TX_FORMAT_FL_I32A32:
 908                         track->textures[i].cpp = 8;
 909                         break;
 910                 case R300_TX_FORMAT_FL_R32G32B32A32:
 911                         track->textures[i].cpp = 16;
 912                         break;
 913                 case R300_TX_FORMAT_DXT1:
 914                         track->textures[i].cpp = 1;
 915                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
 916                         break;
 917                 case R300_TX_FORMAT_ATI2N:
 918                         if (p->rdev->family < CHIP_R420) {
 919                                 DRM_ERROR("Invalid texture format %u\n",
 920                                           (idx_value & 0x1F));
 921                                 return -EINVAL;
 922                         }
 923                         /* The same rules apply as for DXT3/5. */
 924                         /* Pass through. */
 925                 case R300_TX_FORMAT_DXT3:
 926                 case R300_TX_FORMAT_DXT5:
 927                         track->textures[i].cpp = 1;
 928                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
 929                         break;
 930                 default:
 931                         DRM_ERROR("Invalid texture format %u\n",
 932                                   (idx_value & 0x1F));
 933                         return -EINVAL;
 934                         break;
 935                 }
 936                 break;
 937         case 0x4400:
 938         case 0x4404:
 939         case 0x4408:
 940         case 0x440C:
 941         case 0x4410:
 942         case 0x4414:
 943         case 0x4418:
 944         case 0x441C:
 945         case 0x4420:
 946         case 0x4424:
 947         case 0x4428:
 948         case 0x442C:
 949         case 0x4430:
 950         case 0x4434:
 951         case 0x4438:
 952         case 0x443C:
 953                 /* TX_FILTER0_[0-15] */
 954                 i = (reg - 0x4400) >> 2;
 955                 tmp = idx_value & 0x7;
 956                 if (tmp == 2 || tmp == 4 || tmp == 6) {
 957                         track->textures[i].roundup_w = false;
 958                 }
 959                 tmp = (idx_value >> 3) & 0x7;
 960                 if (tmp == 2 || tmp == 4 || tmp == 6) {
 961                         track->textures[i].roundup_h = false;
 962                 }
 963                 break;
 964         case 0x4500:
 965         case 0x4504:
 966         case 0x4508:
 967         case 0x450C:
 968         case 0x4510:
 969         case 0x4514:
 970         case 0x4518:
 971         case 0x451C:
 972         case 0x4520:
 973         case 0x4524:
 974         case 0x4528:
 975         case 0x452C:
 976         case 0x4530:
 977         case 0x4534:
 978         case 0x4538:
 979         case 0x453C:
 980                 /* TX_FORMAT2_[0-15] */
 981                 i = (reg - 0x4500) >> 2;
 982                 tmp = idx_value & 0x3FFF;
 983                 track->textures[i].pitch = tmp + 1;
 984                 if (p->rdev->family >= CHIP_RV515) {
 985                         tmp = ((idx_value >> 15) & 1) << 11;
 986                         track->textures[i].width_11 = tmp;
 987                         tmp = ((idx_value >> 16) & 1) << 11;
 988                         track->textures[i].height_11 = tmp;
 989
 990                         /* ATI1N */
 991                         if (idx_value & (1 << 14)) {
 992                                 /* The same rules apply as for DXT1. */
 993                                 track->textures[i].compress_format =
 994                                         R100_TRACK_COMP_DXT1;
 995                         }
 996                 } else if (idx_value & (1 << 14)) {
 997                         DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
 998                         return -EINVAL;
 999                 }
1000                 break;
1001         case 0x4480:
1002         case 0x4484:
1003         case 0x4488:
1004         case 0x448C:
1005         case 0x4490:
1006         case 0x4494:
1007         case 0x4498:
1008         case 0x449C:
1009         case 0x44A0:
1010         case 0x44A4:
1011         case 0x44A8:
1012         case 0x44AC:
1013         case 0x44B0:
1014         case 0x44B4:
1015         case 0x44B8:
1016         case 0x44BC:
1017                 /* TX_FORMAT0_[0-15] */
1018                 i = (reg - 0x4480) >> 2;
1019                 tmp = idx_value & 0x7FF;
1020                 track->textures[i].width = tmp + 1;
1021                 tmp = (idx_value >> 11) & 0x7FF;
1022                 track->textures[i].height = tmp + 1;
1023                 tmp = (idx_value >> 26) & 0xF;
1024                 track->textures[i].num_levels = tmp;
1025                 tmp = idx_value & (1 << 31);
1026                 track->textures[i].use_pitch = !!tmp;
1027                 tmp = (idx_value >> 22) & 0xF;
1028                 track->textures[i].txdepth = tmp;
1029                 break;
1030         case R300_ZB_ZPASS_ADDR:
1031                 r = r100_cs_packet_next_reloc(p, &reloc);
1032                 if (r) {
1033                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1034                                         idx, reg);
1035                         r100_cs_dump_packet(p, pkt);
1036                         return r;
1037                 }
1038                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1039                 break;
1040         case 0x4e0c:
1041                 /* RB3D_COLOR_CHANNEL_MASK */
1042                 track->color_channel_mask = idx_value;
1043                 break;
1044         case 0x4d1c:
1045                 /* ZB_BW_CNTL */
1046                 track->fastfill = !!(idx_value & (1 << 2));
1047                 break;
1048         case 0x4e04:
1049                 /* RB3D_BLENDCNTL */
1050                 track->blend_read_enable = !!(idx_value & (1 << 2));
1051                 break;
1052         case 0x4be8:
1053                 /* valid register only on RV530 */
1054                 if (p->rdev->family == CHIP_RV530)
1055                         break;
1056                 /* fallthrough do not move */
1057         default:
1058                 goto fail;
1059         }
1060         return 0;
1061 fail:
1062         printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1063                reg, idx);
1064         return -EINVAL;
1065 }
1066
1067 static int r300_packet3_check(struct radeon_cs_parser *p,
1068                               struct radeon_cs_packet *pkt)
1069 {
1070         struct radeon_cs_reloc *reloc;
1071         struct r100_cs_track *track;
1072         volatile uint32_t *ib;
1073         unsigned idx;
1074         int r;
1075
1076         ib = p->ib->ptr;
1077         idx = pkt->idx + 1;
1078         track = (struct r100_cs_track *)p->track;
1079         switch(pkt->opcode) {
1080         case PACKET3_3D_LOAD_VBPNTR:
1081                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1082                 if (r)
1083                         return r;
1084                 break;
1085         case PACKET3_INDX_BUFFER:
1086                 r = r100_cs_packet_next_reloc(p, &reloc);
1087                 if (r) {
1088                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1089                         r100_cs_dump_packet(p, pkt);
1090                         return r;
1091                 }
1092                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1093                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1094                 if (r) {
1095                         return r;
1096                 }
1097                 break;
1098         /* Draw packet */
1099         case PACKET3_3D_DRAW_IMMD:
1100                 /* Number of dwords is vtx_size * (num_vertices - 1)
1101                  * PRIM_WALK must be equal to 3 vertex data in embedded
1102                  * in cmd stream */
1103                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1104                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1105                         return -EINVAL;
1106                 }
1107                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1108                 track->immd_dwords = pkt->count - 1;
1109                 r = r100_cs_track_check(p->rdev, track);
1110                 if (r) {
1111                         return r;
1112                 }
1113                 break;
1114         case PACKET3_3D_DRAW_IMMD_2:
1115                 /* Number of dwords is vtx_size * (num_vertices - 1)
1116                  * PRIM_WALK must be equal to 3 vertex data in embedded
1117                  * in cmd stream */
1118                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1119                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1120                         return -EINVAL;
1121                 }
1122                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1123                 track->immd_dwords = pkt->count;
1124                 r = r100_cs_track_check(p->rdev, track);
1125                 if (r) {
1126                         return r;
1127                 }
1128                 break;
1129         case PACKET3_3D_DRAW_VBUF:
1130                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1131                 r = r100_cs_track_check(p->rdev, track);
1132                 if (r) {
1133                         return r;
1134                 }
1135                 break;
1136         case PACKET3_3D_DRAW_VBUF_2:
1137                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1138                 r = r100_cs_track_check(p->rdev, track);
1139                 if (r) {
1140                         return r;
1141                 }
1142                 break;
1143         case PACKET3_3D_DRAW_INDX:
1144                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1145                 r = r100_cs_track_check(p->rdev, track);
1146                 if (r) {
1147                         return r;
1148                 }
1149                 break;
1150         case PACKET3_3D_DRAW_INDX_2:
1151                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1152                 r = r100_cs_track_check(p->rdev, track);
1153                 if (r) {
1154                         return r;
1155                 }
1156                 break;
1157         case PACKET3_NOP:
1158                 break;
1159         default:
1160                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1161                 return -EINVAL;
1162         }
1163         return 0;
1164 }
1165
1166 int r300_cs_parse(struct radeon_cs_parser *p)
1167 {
1168         struct radeon_cs_packet pkt;
1169         struct r100_cs_track *track;
1170         int r;
1171
1172         track = kzalloc(sizeof(*track), GFP_KERNEL);
1173         r100_cs_track_clear(p->rdev, track);
1174         p->track = track;
1175         do {
1176                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1177                 if (r) {
1178                         return r;
1179                 }
1180                 p->idx += pkt.count + 2;
1181                 switch (pkt.type) {
1182                 case PACKET_TYPE0:
1183                         r = r100_cs_parse_packet0(p, &pkt,
1184                                                   p->rdev->config.r300.reg_safe_bm,
1185                                                   p->rdev->config.r300.reg_safe_bm_size,
1186                                                   &r300_packet0_check);
1187                         break;
1188                 case PACKET_TYPE2:
1189                         break;
1190                 case PACKET_TYPE3:
1191                         r = r300_packet3_check(p, &pkt);
1192                         break;
1193                 default:
1194                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1195                         return -EINVAL;
1196                 }
1197                 if (r) {
1198                         return r;
1199                 }
1200         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1201         return 0;
1202 }
1203
1204 void r300_set_reg_safe(struct radeon_device *rdev)
1205 {
1206         rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1207         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1208 }
1209
1210 void r300_mc_program(struct radeon_device *rdev)
1211 {
1212         struct r100_mc_save save;
1213         int r;
1214
1215         r = r100_debugfs_mc_info_init(rdev);
1216         if (r) {
1217                 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1218         }
1219
1220         /* Stops all mc clients */
1221         r100_mc_stop(rdev, &save);
1222         if (rdev->flags & RADEON_IS_AGP) {
1223                 WREG32(R_00014C_MC_AGP_LOCATION,
1224                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1225                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1226                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1227                 WREG32(R_00015C_AGP_BASE_2,
1228                         upper_32_bits(rdev->mc.agp_base) & 0xff);
1229         } else {
1230                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1231                 WREG32(R_000170_AGP_BASE, 0);
1232                 WREG32(R_00015C_AGP_BASE_2, 0);
1233         }
1234         /* Wait for mc idle */
1235         if (r300_mc_wait_for_idle(rdev))
1236                 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1237         /* Program MC, should be a 32bits limited address space */
1238         WREG32(R_000148_MC_FB_LOCATION,
1239                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1240                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1241         r100_mc_resume(rdev, &save);
1242 }
1243
1244 void r300_clock_startup(struct radeon_device *rdev)
1245 {
1246         u32 tmp;
1247
1248         if (radeon_dynclks != -1 && radeon_dynclks)
1249                 radeon_legacy_set_clock_gating(rdev, 1);
1250         /* We need to force on some of the block */
1251         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1252         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1253         if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1254                 tmp |= S_00000D_FORCE_VAP(1);
1255         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1256 }
1257
1258 static int r300_startup(struct radeon_device *rdev)
1259 {
1260         int r;
1261
1262         /* set common regs */
1263         r100_set_common_regs(rdev);
1264         /* program mc */
1265         r300_mc_program(rdev);
1266         /* Resume clock */
1267         r300_clock_startup(rdev);
1268         /* Initialize GPU configuration (# pipes, ...) */
1269         r300_gpu_init(rdev);
1270         /* Initialize GART (initialize after TTM so we can allocate
1271          * memory through TTM but finalize after TTM) */
1272         if (rdev->flags & RADEON_IS_PCIE) {
1273                 r = rv370_pcie_gart_enable(rdev);
1274                 if (r)
1275                         return r;
1276         }
1277
1278         if (rdev->family == CHIP_R300 ||
1279             rdev->family == CHIP_R350 ||
1280             rdev->family == CHIP_RV350)
1281                 r100_enable_bm(rdev);
1282
1283         if (rdev->flags & RADEON_IS_PCI) {
1284                 r = r100_pci_gart_enable(rdev);
1285                 if (r)
1286                         return r;
1287         }
1288         /* Enable IRQ */
1289         r100_irq_set(rdev);
1290         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1291         /* 1M ring buffer */
1292         r = r100_cp_init(rdev, 1024 * 1024);
1293         if (r) {
1294                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
1295                 return r;
1296         }
1297         r = r100_wb_init(rdev);
1298         if (r)
1299                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
1300         r = r100_ib_init(rdev);
1301         if (r) {
1302                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
1303                 return r;
1304         }
1305         return 0;
1306 }
1307
1308 int r300_resume(struct radeon_device *rdev)
1309 {
1310         /* Make sur GART are not working */
1311         if (rdev->flags & RADEON_IS_PCIE)
1312                 rv370_pcie_gart_disable(rdev);
1313         if (rdev->flags & RADEON_IS_PCI)
1314                 r100_pci_gart_disable(rdev);
1315         /* Resume clock before doing reset */
1316         r300_clock_startup(rdev);
1317         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1318         if (radeon_gpu_reset(rdev)) {
1319                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1320                         RREG32(R_000E40_RBBM_STATUS),
1321                         RREG32(R_0007C0_CP_STAT));
1322         }
1323         /* post */
1324         radeon_combios_asic_init(rdev->ddev);
1325         /* Resume clock after posting */
1326         r300_clock_startup(rdev);
1327         /* Initialize surface registers */
1328         radeon_surface_init(rdev);
1329         return r300_startup(rdev);
1330 }
1331
1332 int r300_suspend(struct radeon_device *rdev)
1333 {
1334         r100_cp_disable(rdev);
1335         r100_wb_disable(rdev);
1336         r100_irq_disable(rdev);
1337         if (rdev->flags & RADEON_IS_PCIE)
1338                 rv370_pcie_gart_disable(rdev);
1339         if (rdev->flags & RADEON_IS_PCI)
1340                 r100_pci_gart_disable(rdev);
1341         return 0;
1342 }
1343
1344 void r300_fini(struct radeon_device *rdev)
1345 {
1346         radeon_pm_fini(rdev);
1347         r100_cp_fini(rdev);
1348         r100_wb_fini(rdev);
1349         r100_ib_fini(rdev);
1350         radeon_gem_fini(rdev);
1351         if (rdev->flags & RADEON_IS_PCIE)
1352                 rv370_pcie_gart_fini(rdev);
1353         if (rdev->flags & RADEON_IS_PCI)
1354                 r100_pci_gart_fini(rdev);
1355         radeon_agp_fini(rdev);
1356         radeon_irq_kms_fini(rdev);
1357         radeon_fence_driver_fini(rdev);
1358         radeon_bo_fini(rdev);
1359         radeon_atombios_fini(rdev);
1360         kfree(rdev->bios);
1361         rdev->bios = NULL;
1362 }
1363
1364 int r300_init(struct radeon_device *rdev)
1365 {
1366         int r;
1367
1368         /* Disable VGA */
1369         r100_vga_render_disable(rdev);
1370         /* Initialize scratch registers */
1371         radeon_scratch_init(rdev);
1372         /* Initialize surface registers */
1373         radeon_surface_init(rdev);
1374         /* TODO: disable VGA need to use VGA request */
1375         /* BIOS*/
1376         if (!radeon_get_bios(rdev)) {
1377                 if (ASIC_IS_AVIVO(rdev))
1378                         return -EINVAL;
1379         }
1380         if (rdev->is_atom_bios) {
1381                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1382                 return -EINVAL;
1383         } else {
1384                 r = radeon_combios_init(rdev);
1385                 if (r)
1386                         return r;
1387         }
1388         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1389         if (radeon_gpu_reset(rdev)) {
1390                 dev_warn(rdev->dev,
1391                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1392                         RREG32(R_000E40_RBBM_STATUS),
1393                         RREG32(R_0007C0_CP_STAT));
1394         }
1395         /* check if cards are posted or not */
1396         if (radeon_boot_test_post_card(rdev) == false)
1397                 return -EINVAL;
1398         /* Set asic errata */
1399         r300_errata(rdev);
1400         /* Initialize clocks */
1401         radeon_get_clock_info(rdev->ddev);
1402         /* Initialize power management */
1403         radeon_pm_init(rdev);
1404         /* initialize AGP */
1405         if (rdev->flags & RADEON_IS_AGP) {
1406                 r = radeon_agp_init(rdev);
1407                 if (r) {
1408                         radeon_agp_disable(rdev);
1409                 }
1410         }
1411         /* initialize memory controller */
1412         r300_mc_init(rdev);
1413         /* Fence driver */
1414         r = radeon_fence_driver_init(rdev);
1415         if (r)
1416                 return r;
1417         r = radeon_irq_kms_init(rdev);
1418         if (r)
1419                 return r;
1420         /* Memory manager */
1421         r = radeon_bo_init(rdev);
1422         if (r)
1423                 return r;
1424         if (rdev->flags & RADEON_IS_PCIE) {
1425                 r = rv370_pcie_gart_init(rdev);
1426                 if (r)
1427                         return r;
1428         }
1429         if (rdev->flags & RADEON_IS_PCI) {
1430                 r = r100_pci_gart_init(rdev);
1431                 if (r)
1432                         return r;
1433         }
1434         r300_set_reg_safe(rdev);
1435         rdev->accel_working = true;
1436         r = r300_startup(rdev);
1437         if (r) {
1438                 /* Somethings want wront with the accel init stop accel */
1439                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1440                 r100_cp_fini(rdev);
1441                 r100_wb_fini(rdev);
1442                 r100_ib_fini(rdev);
1443                 radeon_irq_kms_fini(rdev);
1444                 if (rdev->flags & RADEON_IS_PCIE)
1445                         rv370_pcie_gart_fini(rdev);
1446                 if (rdev->flags & RADEON_IS_PCI)
1447                         r100_pci_gart_fini(rdev);
1448                 radeon_agp_fini(rdev);
1449                 rdev->accel_working = false;
1450         }
1451         return 0;
1452 }