drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "radeon_drm.h"
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "r100d.h"
  37 #include "rs100d.h"
  38 #include "rv200d.h"
  39 #include "rv250d.h"
  40 #include "atom.h"
  41
  42 #include <linux/firmware.h>
  43 #include <linux/platform_device.h>
  44
  45 #include "r100_reg_safe.h"
  46 #include "rn50_reg_safe.h"
  47
  48 /* Firmware Names */
  49 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  50 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  51 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  52 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  53 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  54 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  55 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  56
  57 MODULE_FIRMWARE(FIRMWARE_R100);
  58 MODULE_FIRMWARE(FIRMWARE_R200);
  59 MODULE_FIRMWARE(FIRMWARE_R300);
  60 MODULE_FIRMWARE(FIRMWARE_R420);
  61 MODULE_FIRMWARE(FIRMWARE_RS690);
  62 MODULE_FIRMWARE(FIRMWARE_RS600);
  63 MODULE_FIRMWARE(FIRMWARE_R520);
  64
  65 #include "r100_track.h"
  66
  67 /* This files gather functions specifics to:
  68  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  69  */
  70
  71 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
  72 {
  73         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
  74         u32 tmp;
  75
  76         /* make sure flip is at vb rather than hb */
  77         tmp = RREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset);
  78         tmp &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
  79         /* make sure pending bit is asserted */
  80         tmp |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
  81         WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, tmp);
  82
  83         /* set pageflip to happen as late as possible in the vblank interval.
  84          * same field for crtc1/2
  85          */
  86         tmp = RREG32(RADEON_CRTC_GEN_CNTL);
  87         tmp &= ~RADEON_CRTC_VSTAT_MODE_MASK;
  88         WREG32(RADEON_CRTC_GEN_CNTL, tmp);
  89
  90         /* enable the pflip int */
  91         radeon_irq_kms_pflip_irq_get(rdev, crtc);
  92 }
  93
  94 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
  95 {
  96         /* disable the pflip int */
  97         radeon_irq_kms_pflip_irq_put(rdev, crtc);
  98 }
  99
 100 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 101 {
 102         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 103         u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
 104
 105         /* Lock the graphics update lock */
 106         /* update the scanout addresses */
 107         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 108
 109         /* Wait for update_pending to go high. */
 110         while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET));
 111         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 112
 113         /* Unlock the lock, so double-buffering can take place inside vblank */
 114         tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
 115         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 116
 117         /* Return current update_pending status: */
 118         return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
 119 }
 120
 121 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
 122 {
 123         int i;
 124         rdev->pm.dynpm_can_upclock = true;
 125         rdev->pm.dynpm_can_downclock = true;
 126
 127         switch (rdev->pm.dynpm_planned_action) {
 128         case DYNPM_ACTION_MINIMUM:
 129                 rdev->pm.requested_power_state_index = 0;
 130                 rdev->pm.dynpm_can_downclock = false;
 131                 break;
 132         case DYNPM_ACTION_DOWNCLOCK:
 133                 if (rdev->pm.current_power_state_index == 0) {
 134                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 135                         rdev->pm.dynpm_can_downclock = false;
 136                 } else {
 137                         if (rdev->pm.active_crtc_count > 1) {
 138                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
 139                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 140                                                 continue;
 141                                         else if (i >= rdev->pm.current_power_state_index) {
 142                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 143                                                 break;
 144                                         } else {
 145                                                 rdev->pm.requested_power_state_index = i;
 146                                                 break;
 147                                         }
 148                                 }
 149                         } else
 150                                 rdev->pm.requested_power_state_index =
 151                                         rdev->pm.current_power_state_index - 1;
 152                 }
 153                 /* don't use the power state if crtcs are active and no display flag is set */
 154                 if ((rdev->pm.active_crtc_count > 0) &&
 155                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
 156                      RADEON_PM_MODE_NO_DISPLAY)) {
 157                         rdev->pm.requested_power_state_index++;
 158                 }
 159                 break;
 160         case DYNPM_ACTION_UPCLOCK:
 161                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 162                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 163                         rdev->pm.dynpm_can_upclock = false;
 164                 } else {
 165                         if (rdev->pm.active_crtc_count > 1) {
 166                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 167                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 168                                                 continue;
 169                                         else if (i <= rdev->pm.current_power_state_index) {
 170                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 171                                                 break;
 172                                         } else {
 173                                                 rdev->pm.requested_power_state_index = i;
 174                                                 break;
 175                                         }
 176                                 }
 177                         } else
 178                                 rdev->pm.requested_power_state_index =
 179                                         rdev->pm.current_power_state_index + 1;
 180                 }
 181                 break;
 182         case DYNPM_ACTION_DEFAULT:
 183                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 184                 rdev->pm.dynpm_can_upclock = false;
 185                 break;
 186         case DYNPM_ACTION_NONE:
 187         default:
 188                 DRM_ERROR("Requested mode for not defined action\n");
 189                 return;
 190         }
 191         /* only one clock mode per power state */
 192         rdev->pm.requested_clock_mode_index = 0;
 193
 194         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 195                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 196                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 197                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 198                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 199                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 200                   pcie_lanes);
 201 }
 202
 203 void r100_pm_init_profile(struct radeon_device *rdev)
 204 {
 205         /* default */
 206         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 207         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 208         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 209         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 210         /* low sh */
 211         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 212         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 213         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 214         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 215         /* mid sh */
 216         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 217         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 218         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 219         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 220         /* high sh */
 221         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 222         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 223         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 224         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 225         /* low mh */
 226         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 227         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 228         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 229         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 230         /* mid mh */
 231         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 232         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 233         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 234         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 235         /* high mh */
 236         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 237         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 238         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 239         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 240 }
 241
 242 void r100_pm_misc(struct radeon_device *rdev)
 243 {
 244         int requested_index = rdev->pm.requested_power_state_index;
 245         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 246         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 247         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 248
 249         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 250                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 251                         tmp = RREG32(voltage->gpio.reg);
 252                         if (voltage->active_high)
 253                                 tmp |= voltage->gpio.mask;
 254                         else
 255                                 tmp &= ~(voltage->gpio.mask);
 256                         WREG32(voltage->gpio.reg, tmp);
 257                         if (voltage->delay)
 258                                 udelay(voltage->delay);
 259                 } else {
 260                         tmp = RREG32(voltage->gpio.reg);
 261                         if (voltage->active_high)
 262                                 tmp &= ~voltage->gpio.mask;
 263                         else
 264                                 tmp |= voltage->gpio.mask;
 265                         WREG32(voltage->gpio.reg, tmp);
 266                         if (voltage->delay)
 267                                 udelay(voltage->delay);
 268                 }
 269         }
 270
 271         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 272         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 273         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 274         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 275         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 276         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 277                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 278                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 279                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 280                 else
 281                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 282                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 283                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 284                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 285                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 286         } else
 287                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 288
 289         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 290                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 291                 if (voltage->delay) {
 292                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 293                         switch (voltage->delay) {
 294                         case 33:
 295                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 296                                 break;
 297                         case 66:
 298                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 299                                 break;
 300                         case 99:
 301                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 302                                 break;
 303                         case 132:
 304                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 305                                 break;
 306                         }
 307                 } else
 308                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 309         } else
 310                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 311
 312         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 313                 sclk_cntl &= ~FORCE_HDP;
 314         else
 315                 sclk_cntl |= FORCE_HDP;
 316
 317         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 318         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 319         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 320
 321         /* set pcie lanes */
 322         if ((rdev->flags & RADEON_IS_PCIE) &&
 323             !(rdev->flags & RADEON_IS_IGP) &&
 324             rdev->asic->set_pcie_lanes &&
 325             (ps->pcie_lanes !=
 326              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 327                 radeon_set_pcie_lanes(rdev,
 328                                       ps->pcie_lanes);
 329                 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
 330         }
 331 }
 332
 333 void r100_pm_prepare(struct radeon_device *rdev)
 334 {
 335         struct drm_device *ddev = rdev->ddev;
 336         struct drm_crtc *crtc;
 337         struct radeon_crtc *radeon_crtc;
 338         u32 tmp;
 339
 340         /* disable any active CRTCs */
 341         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 342                 radeon_crtc = to_radeon_crtc(crtc);
 343                 if (radeon_crtc->enabled) {
 344                         if (radeon_crtc->crtc_id) {
 345                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 346                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 347                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 348                         } else {
 349                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 350                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 351                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 352                         }
 353                 }
 354         }
 355 }
 356
 357 void r100_pm_finish(struct radeon_device *rdev)
 358 {
 359         struct drm_device *ddev = rdev->ddev;
 360         struct drm_crtc *crtc;
 361         struct radeon_crtc *radeon_crtc;
 362         u32 tmp;
 363
 364         /* enable any active CRTCs */
 365         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 366                 radeon_crtc = to_radeon_crtc(crtc);
 367                 if (radeon_crtc->enabled) {
 368                         if (radeon_crtc->crtc_id) {
 369                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 370                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 371                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 372                         } else {
 373                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 374                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 375                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 376                         }
 377                 }
 378         }
 379 }
 380
 381 bool r100_gui_idle(struct radeon_device *rdev)
 382 {
 383         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 384                 return false;
 385         else
 386                 return true;
 387 }
 388
 389 /* hpd for digital panel detect/disconnect */
 390 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 391 {
 392         bool connected = false;
 393
 394         switch (hpd) {
 395         case RADEON_HPD_1:
 396                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 397                         connected = true;
 398                 break;
 399         case RADEON_HPD_2:
 400                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 401                         connected = true;
 402                 break;
 403         default:
 404                 break;
 405         }
 406         return connected;
 407 }
 408
 409 void r100_hpd_set_polarity(struct radeon_device *rdev,
 410                            enum radeon_hpd_id hpd)
 411 {
 412         u32 tmp;
 413         bool connected = r100_hpd_sense(rdev, hpd);
 414
 415         switch (hpd) {
 416         case RADEON_HPD_1:
 417                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 418                 if (connected)
 419                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 420                 else
 421                         tmp |= RADEON_FP_DETECT_INT_POL;
 422                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 423                 break;
 424         case RADEON_HPD_2:
 425                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 426                 if (connected)
 427                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 428                 else
 429                         tmp |= RADEON_FP2_DETECT_INT_POL;
 430                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 431                 break;
 432         default:
 433                 break;
 434         }
 435 }
 436
 437 void r100_hpd_init(struct radeon_device *rdev)
 438 {
 439         struct drm_device *dev = rdev->ddev;
 440         struct drm_connector *connector;
 441
 442         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 443                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 444                 switch (radeon_connector->hpd.hpd) {
 445                 case RADEON_HPD_1:
 446                         rdev->irq.hpd[0] = true;
 447                         break;
 448                 case RADEON_HPD_2:
 449                         rdev->irq.hpd[1] = true;
 450                         break;
 451                 default:
 452                         break;
 453                 }
 454         }
 455         if (rdev->irq.installed)
 456                 r100_irq_set(rdev);
 457 }
 458
 459 void r100_hpd_fini(struct radeon_device *rdev)
 460 {
 461         struct drm_device *dev = rdev->ddev;
 462         struct drm_connector *connector;
 463
 464         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 465                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 466                 switch (radeon_connector->hpd.hpd) {
 467                 case RADEON_HPD_1:
 468                         rdev->irq.hpd[0] = false;
 469                         break;
 470                 case RADEON_HPD_2:
 471                         rdev->irq.hpd[1] = false;
 472                         break;
 473                 default:
 474                         break;
 475                 }
 476         }
 477 }
 478
 479 /*
 480  * PCI GART
 481  */
 482 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 483 {
 484         /* TODO: can we do somethings here ? */
 485         /* It seems hw only cache one entry so we should discard this
 486          * entry otherwise if first GPU GART read hit this entry it
 487          * could end up in wrong address. */
 488 }
 489
 490 int r100_pci_gart_init(struct radeon_device *rdev)
 491 {
 492         int r;
 493
 494         if (rdev->gart.table.ram.ptr) {
 495                 WARN(1, "R100 PCI GART already initialized\n");
 496                 return 0;
 497         }
 498         /* Initialize common gart structure */
 499         r = radeon_gart_init(rdev);
 500         if (r)
 501                 return r;
 502         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 503         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 504         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 505         return radeon_gart_table_ram_alloc(rdev);
 506 }
 507
 508 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 509 void r100_enable_bm(struct radeon_device *rdev)
 510 {
 511         uint32_t tmp;
 512         /* Enable bus mastering */
 513         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 514         WREG32(RADEON_BUS_CNTL, tmp);
 515 }
 516
 517 int r100_pci_gart_enable(struct radeon_device *rdev)
 518 {
 519         uint32_t tmp;
 520
 521         radeon_gart_restore(rdev);
 522         /* discard memory request outside of configured range */
 523         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 524         WREG32(RADEON_AIC_CNTL, tmp);
 525         /* set address range for PCI address translate */
 526         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 527         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 528         /* set PCI GART page-table base address */
 529         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 530         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 531         WREG32(RADEON_AIC_CNTL, tmp);
 532         r100_pci_gart_tlb_flush(rdev);
 533         rdev->gart.ready = true;
 534         return 0;
 535 }
 536
 537 void r100_pci_gart_disable(struct radeon_device *rdev)
 538 {
 539         uint32_t tmp;
 540
 541         /* discard memory request outside of configured range */
 542         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 543         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 544         WREG32(RADEON_AIC_LO_ADDR, 0);
 545         WREG32(RADEON_AIC_HI_ADDR, 0);
 546 }
 547
 548 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 549 {
 550         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 551                 return -EINVAL;
 552         }
 553         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
 554         return 0;
 555 }
 556
 557 void r100_pci_gart_fini(struct radeon_device *rdev)
 558 {
 559         radeon_gart_fini(rdev);
 560         r100_pci_gart_disable(rdev);
 561         radeon_gart_table_ram_free(rdev);
 562 }
 563
 564 int r100_irq_set(struct radeon_device *rdev)
 565 {
 566         uint32_t tmp = 0;
 567
 568         if (!rdev->irq.installed) {
 569                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 570                 WREG32(R_000040_GEN_INT_CNTL, 0);
 571                 return -EINVAL;
 572         }
 573         if (rdev->irq.sw_int) {
 574                 tmp |= RADEON_SW_INT_ENABLE;
 575         }
 576         if (rdev->irq.gui_idle) {
 577                 tmp |= RADEON_GUI_IDLE_MASK;
 578         }
 579         if (rdev->irq.crtc_vblank_int[0] ||
 580             rdev->irq.pflip[0]) {
 581                 tmp |= RADEON_CRTC_VBLANK_MASK;
 582         }
 583         if (rdev->irq.crtc_vblank_int[1] ||
 584             rdev->irq.pflip[1]) {
 585                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 586         }
 587         if (rdev->irq.hpd[0]) {
 588                 tmp |= RADEON_FP_DETECT_MASK;
 589         }
 590         if (rdev->irq.hpd[1]) {
 591                 tmp |= RADEON_FP2_DETECT_MASK;
 592         }
 593         WREG32(RADEON_GEN_INT_CNTL, tmp);
 594         return 0;
 595 }
 596
 597 void r100_irq_disable(struct radeon_device *rdev)
 598 {
 599         u32 tmp;
 600
 601         WREG32(R_000040_GEN_INT_CNTL, 0);
 602         /* Wait and acknowledge irq */
 603         mdelay(1);
 604         tmp = RREG32(R_000044_GEN_INT_STATUS);
 605         WREG32(R_000044_GEN_INT_STATUS, tmp);
 606 }
 607
 608 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
 609 {
 610         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 611         uint32_t irq_mask = RADEON_SW_INT_TEST |
 612                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 613                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 614
 615         /* the interrupt works, but the status bit is permanently asserted */
 616         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
 617                 if (!rdev->irq.gui_idle_acked)
 618                         irq_mask |= RADEON_GUI_IDLE_STAT;
 619         }
 620
 621         if (irqs) {
 622                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 623         }
 624         return irqs & irq_mask;
 625 }
 626
 627 int r100_irq_process(struct radeon_device *rdev)
 628 {
 629         uint32_t status, msi_rearm;
 630         bool queue_hotplug = false;
 631
 632         /* reset gui idle ack.  the status bit is broken */
 633         rdev->irq.gui_idle_acked = false;
 634
 635         status = r100_irq_ack(rdev);
 636         if (!status) {
 637                 return IRQ_NONE;
 638         }
 639         if (rdev->shutdown) {
 640                 return IRQ_NONE;
 641         }
 642         while (status) {
 643                 /* SW interrupt */
 644                 if (status & RADEON_SW_INT_TEST) {
 645                         radeon_fence_process(rdev);
 646                 }
 647                 /* gui idle interrupt */
 648                 if (status & RADEON_GUI_IDLE_STAT) {
 649                         rdev->irq.gui_idle_acked = true;
 650                         rdev->pm.gui_idle = true;
 651                         wake_up(&rdev->irq.idle_queue);
 652                 }
 653                 /* Vertical blank interrupts */
 654                 if (status & RADEON_CRTC_VBLANK_STAT) {
 655                         if (rdev->irq.crtc_vblank_int[0]) {
 656                                 drm_handle_vblank(rdev->ddev, 0);
 657                                 rdev->pm.vblank_sync = true;
 658                                 wake_up(&rdev->irq.vblank_queue);
 659                         }
 660                         if (rdev->irq.pflip[0])
 661                                 radeon_crtc_handle_flip(rdev, 0);
 662                 }
 663                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 664                         if (rdev->irq.crtc_vblank_int[1]) {
 665                                 drm_handle_vblank(rdev->ddev, 1);
 666                                 rdev->pm.vblank_sync = true;
 667                                 wake_up(&rdev->irq.vblank_queue);
 668                         }
 669                         if (rdev->irq.pflip[1])
 670                                 radeon_crtc_handle_flip(rdev, 1);
 671                 }
 672                 if (status & RADEON_FP_DETECT_STAT) {
 673                         queue_hotplug = true;
 674                         DRM_DEBUG("HPD1\n");
 675                 }
 676                 if (status & RADEON_FP2_DETECT_STAT) {
 677                         queue_hotplug = true;
 678                         DRM_DEBUG("HPD2\n");
 679                 }
 680                 status = r100_irq_ack(rdev);
 681         }
 682         /* reset gui idle ack.  the status bit is broken */
 683         rdev->irq.gui_idle_acked = false;
 684         if (queue_hotplug)
 685                 schedule_work(&rdev->hotplug_work);
 686         if (rdev->msi_enabled) {
 687                 switch (rdev->family) {
 688                 case CHIP_RS400:
 689                 case CHIP_RS480:
 690                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 691                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 692                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 693                         break;
 694                 default:
 695                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 696                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 697                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 698                         break;
 699                 }
 700         }
 701         return IRQ_HANDLED;
 702 }
 703
 704 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 705 {
 706         if (crtc == 0)
 707                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 708         else
 709                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 710 }
 711
 712 /* Who ever call radeon_fence_emit should call ring_lock and ask
 713  * for enough space (today caller are ib schedule and buffer move) */
 714 void r100_fence_ring_emit(struct radeon_device *rdev,
 715                           struct radeon_fence *fence)
 716 {
 717         /* We have to make sure that caches are flushed before
 718          * CPU might read something from VRAM. */
 719         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 720         radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
 721         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 722         radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
 723         /* Wait until IDLE & CLEAN */
 724         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 725         radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 726         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 727         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
 728                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 729         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 730         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
 731         /* Emit fence sequence & fire IRQ */
 732         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 733         radeon_ring_write(rdev, fence->seq);
 734         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 735         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 736 }
 737
 738 int r100_copy_blit(struct radeon_device *rdev,
 739                    uint64_t src_offset,
 740                    uint64_t dst_offset,
 741                    unsigned num_pages,
 742                    struct radeon_fence *fence)
 743 {
 744         uint32_t cur_pages;
 745         uint32_t stride_bytes = PAGE_SIZE;
 746         uint32_t pitch;
 747         uint32_t stride_pixels;
 748         unsigned ndw;
 749         int num_loops;
 750         int r = 0;
 751
 752         /* radeon limited to 16k stride */
 753         stride_bytes &= 0x3fff;
 754         /* radeon pitch is /64 */
 755         pitch = stride_bytes / 64;
 756         stride_pixels = stride_bytes / 4;
 757         num_loops = DIV_ROUND_UP(num_pages, 8191);
 758
 759         /* Ask for enough room for blit + flush + fence */
 760         ndw = 64 + (10 * num_loops);
 761         r = radeon_ring_lock(rdev, ndw);
 762         if (r) {
 763                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 764                 return -EINVAL;
 765         }
 766         while (num_pages > 0) {
 767                 cur_pages = num_pages;
 768                 if (cur_pages > 8191) {
 769                         cur_pages = 8191;
 770                 }
 771                 num_pages -= cur_pages;
 772
 773                 /* pages are in Y direction - height
 774                    page width in X direction - width */
 775                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 776                 radeon_ring_write(rdev,
 777                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 778                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 779                                   RADEON_GMC_SRC_CLIPPING |
 780                                   RADEON_GMC_DST_CLIPPING |
 781                                   RADEON_GMC_BRUSH_NONE |
 782                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 783                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 784                                   RADEON_ROP3_S |
 785                                   RADEON_DP_SRC_SOURCE_MEMORY |
 786                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 787                                   RADEON_GMC_WR_MSK_DIS);
 788                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 789                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 790                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 791                 radeon_ring_write(rdev, 0);
 792                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 793                 radeon_ring_write(rdev, num_pages);
 794                 radeon_ring_write(rdev, num_pages);
 795                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 796         }
 797         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 798         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 799         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 800         radeon_ring_write(rdev,
 801                           RADEON_WAIT_2D_IDLECLEAN |
 802                           RADEON_WAIT_HOST_IDLECLEAN |
 803                           RADEON_WAIT_DMA_GUI_IDLE);
 804         if (fence) {
 805                 r = radeon_fence_emit(rdev, fence);
 806         }
 807         radeon_ring_unlock_commit(rdev);
 808         return r;
 809 }
 810
 811 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 812 {
 813         unsigned i;
 814         u32 tmp;
 815
 816         for (i = 0; i < rdev->usec_timeout; i++) {
 817                 tmp = RREG32(R_000E40_RBBM_STATUS);
 818                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 819                         return 0;
 820                 }
 821                 udelay(1);
 822         }
 823         return -1;
 824 }
 825
 826 void r100_ring_start(struct radeon_device *rdev)
 827 {
 828         int r;
 829
 830         r = radeon_ring_lock(rdev, 2);
 831         if (r) {
 832                 return;
 833         }
 834         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 835         radeon_ring_write(rdev,
 836                           RADEON_ISYNC_ANY2D_IDLE3D |
 837                           RADEON_ISYNC_ANY3D_IDLE2D |
 838                           RADEON_ISYNC_WAIT_IDLEGUI |
 839                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 840         radeon_ring_unlock_commit(rdev);
 841 }
 842
 843
 844 /* Load the microcode for the CP */
 845 static int r100_cp_init_microcode(struct radeon_device *rdev)
 846 {
 847         struct platform_device *pdev;
 848         const char *fw_name = NULL;
 849         int err;
 850
 851         DRM_DEBUG_KMS("\n");
 852
 853         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 854         err = IS_ERR(pdev);
 855         if (err) {
 856                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 857                 return -EINVAL;
 858         }
 859         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 860             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 861             (rdev->family == CHIP_RS200)) {
 862                 DRM_INFO("Loading R100 Microcode\n");
 863                 fw_name = FIRMWARE_R100;
 864         } else if ((rdev->family == CHIP_R200) ||
 865                    (rdev->family == CHIP_RV250) ||
 866                    (rdev->family == CHIP_RV280) ||
 867                    (rdev->family == CHIP_RS300)) {
 868                 DRM_INFO("Loading R200 Microcode\n");
 869                 fw_name = FIRMWARE_R200;
 870         } else if ((rdev->family == CHIP_R300) ||
 871                    (rdev->family == CHIP_R350) ||
 872                    (rdev->family == CHIP_RV350) ||
 873                    (rdev->family == CHIP_RV380) ||
 874                    (rdev->family == CHIP_RS400) ||
 875                    (rdev->family == CHIP_RS480)) {
 876                 DRM_INFO("Loading R300 Microcode\n");
 877                 fw_name = FIRMWARE_R300;
 878         } else if ((rdev->family == CHIP_R420) ||
 879                    (rdev->family == CHIP_R423) ||
 880                    (rdev->family == CHIP_RV410)) {
 881                 DRM_INFO("Loading R400 Microcode\n");
 882                 fw_name = FIRMWARE_R420;
 883         } else if ((rdev->family == CHIP_RS690) ||
 884                    (rdev->family == CHIP_RS740)) {
 885                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 886                 fw_name = FIRMWARE_RS690;
 887         } else if (rdev->family == CHIP_RS600) {
 888                 DRM_INFO("Loading RS600 Microcode\n");
 889                 fw_name = FIRMWARE_RS600;
 890         } else if ((rdev->family == CHIP_RV515) ||
 891                    (rdev->family == CHIP_R520) ||
 892                    (rdev->family == CHIP_RV530) ||
 893                    (rdev->family == CHIP_R580) ||
 894                    (rdev->family == CHIP_RV560) ||
 895                    (rdev->family == CHIP_RV570)) {
 896                 DRM_INFO("Loading R500 Microcode\n");
 897                 fw_name = FIRMWARE_R520;
 898         }
 899
 900         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 901         platform_device_unregister(pdev);
 902         if (err) {
 903                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 904                        fw_name);
 905         } else if (rdev->me_fw->size % 8) {
 906                 printk(KERN_ERR
 907                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 908                        rdev->me_fw->size, fw_name);
 909                 err = -EINVAL;
 910                 release_firmware(rdev->me_fw);
 911                 rdev->me_fw = NULL;
 912         }
 913         return err;
 914 }
 915
 916 static void r100_cp_load_microcode(struct radeon_device *rdev)
 917 {
 918         const __be32 *fw_data;
 919         int i, size;
 920
 921         if (r100_gui_wait_for_idle(rdev)) {
 922                 printk(KERN_WARNING "Failed to wait GUI idle while "
 923                        "programming pipes. Bad things might happen.\n");
 924         }
 925
 926         if (rdev->me_fw) {
 927                 size = rdev->me_fw->size / 4;
 928                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
 929                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 930                 for (i = 0; i < size; i += 2) {
 931                         WREG32(RADEON_CP_ME_RAM_DATAH,
 932                                be32_to_cpup(&fw_data[i]));
 933                         WREG32(RADEON_CP_ME_RAM_DATAL,
 934                                be32_to_cpup(&fw_data[i + 1]));
 935                 }
 936         }
 937 }
 938
 939 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 940 {
 941         unsigned rb_bufsz;
 942         unsigned rb_blksz;
 943         unsigned max_fetch;
 944         unsigned pre_write_timer;
 945         unsigned pre_write_limit;
 946         unsigned indirect2_start;
 947         unsigned indirect1_start;
 948         uint32_t tmp;
 949         int r;
 950
 951         if (r100_debugfs_cp_init(rdev)) {
 952                 DRM_ERROR("Failed to register debugfs file for CP !\n");
 953         }
 954         if (!rdev->me_fw) {
 955                 r = r100_cp_init_microcode(rdev);
 956                 if (r) {
 957                         DRM_ERROR("Failed to load firmware!\n");
 958                         return r;
 959                 }
 960         }
 961
 962         /* Align ring size */
 963         rb_bufsz = drm_order(ring_size / 8);
 964         ring_size = (1 << (rb_bufsz + 1)) * 4;
 965         r100_cp_load_microcode(rdev);
 966         r = radeon_ring_init(rdev, ring_size);
 967         if (r) {
 968                 return r;
 969         }
 970         /* Each time the cp read 1024 bytes (16 dword/quadword) update
 971          * the rptr copy in system ram */
 972         rb_blksz = 9;
 973         /* cp will read 128bytes at a time (4 dwords) */
 974         max_fetch = 1;
 975         rdev->cp.align_mask = 16 - 1;
 976         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
 977         pre_write_timer = 64;
 978         /* Force CP_RB_WPTR write if written more than one time before the
 979          * delay expire
 980          */
 981         pre_write_limit = 0;
 982         /* Setup the cp cache like this (cache size is 96 dwords) :
 983          *      RING            0  to 15
 984          *      INDIRECT1       16 to 79
 985          *      INDIRECT2       80 to 95
 986          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 987          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
 988          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 989          * Idea being that most of the gpu cmd will be through indirect1 buffer
 990          * so it gets the bigger cache.
 991          */
 992         indirect2_start = 80;
 993         indirect1_start = 16;
 994         /* cp setup */
 995         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
 996         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
 997                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
 998                REG_SET(RADEON_MAX_FETCH, max_fetch));
 999 #ifdef __BIG_ENDIAN
1000         tmp |= RADEON_BUF_SWAP_32BIT;
1001 #endif
1002         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1003
1004         /* Set ring address */
1005         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
1006         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
1007         /* Force read & write ptr to 0 */
1008         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1009         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1010         WREG32(RADEON_CP_RB_WPTR, 0);
1011
1012         /* set the wb address whether it's enabled or not */
1013         WREG32(R_00070C_CP_RB_RPTR_ADDR,
1014                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1015         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1016
1017         if (rdev->wb.enabled)
1018                 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1019         else {
1020                 tmp |= RADEON_RB_NO_UPDATE;
1021                 WREG32(R_000770_SCRATCH_UMSK, 0);
1022         }
1023
1024         WREG32(RADEON_CP_RB_CNTL, tmp);
1025         udelay(10);
1026         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1027         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
1028         /* protect against crazy HW on resume */
1029         rdev->cp.wptr &= rdev->cp.ptr_mask;
1030         /* Set cp mode to bus mastering & enable cp*/
1031         WREG32(RADEON_CP_CSQ_MODE,
1032                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1033                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1034         WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1035         WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1036         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1037         radeon_ring_start(rdev);
1038         r = radeon_ring_test(rdev);
1039         if (r) {
1040                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1041                 return r;
1042         }
1043         rdev->cp.ready = true;
1044         rdev->mc.active_vram_size = rdev->mc.real_vram_size;
1045         return 0;
1046 }
1047
1048 void r100_cp_fini(struct radeon_device *rdev)
1049 {
1050         if (r100_cp_wait_for_idle(rdev)) {
1051                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1052         }
1053         /* Disable ring */
1054         r100_cp_disable(rdev);
1055         radeon_ring_fini(rdev);
1056         DRM_INFO("radeon: cp finalized\n");
1057 }
1058
1059 void r100_cp_disable(struct radeon_device *rdev)
1060 {
1061         /* Disable ring */
1062         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1063         rdev->cp.ready = false;
1064         WREG32(RADEON_CP_CSQ_MODE, 0);
1065         WREG32(RADEON_CP_CSQ_CNTL, 0);
1066         WREG32(R_000770_SCRATCH_UMSK, 0);
1067         if (r100_gui_wait_for_idle(rdev)) {
1068                 printk(KERN_WARNING "Failed to wait GUI idle while "
1069                        "programming pipes. Bad things might happen.\n");
1070         }
1071 }
1072
1073 void r100_cp_commit(struct radeon_device *rdev)
1074 {
1075         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1076         (void)RREG32(RADEON_CP_RB_WPTR);
1077 }
1078
1079
1080 /*
1081  * CS functions
1082  */
1083 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1084                           struct radeon_cs_packet *pkt,
1085                           const unsigned *auth, unsigned n,
1086                           radeon_packet0_check_t check)
1087 {
1088         unsigned reg;
1089         unsigned i, j, m;
1090         unsigned idx;
1091         int r;
1092
1093         idx = pkt->idx + 1;
1094         reg = pkt->reg;
1095         /* Check that register fall into register range
1096          * determined by the number of entry (n) in the
1097          * safe register bitmap.
1098          */
1099         if (pkt->one_reg_wr) {
1100                 if ((reg >> 7) > n) {
1101                         return -EINVAL;
1102                 }
1103         } else {
1104                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1105                         return -EINVAL;
1106                 }
1107         }
1108         for (i = 0; i <= pkt->count; i++, idx++) {
1109                 j = (reg >> 7);
1110                 m = 1 << ((reg >> 2) & 31);
1111                 if (auth[j] & m) {
1112                         r = check(p, pkt, idx, reg);
1113                         if (r) {
1114                                 return r;
1115                         }
1116                 }
1117                 if (pkt->one_reg_wr) {
1118                         if (!(auth[j] & m)) {
1119                                 break;
1120                         }
1121                 } else {
1122                         reg += 4;
1123                 }
1124         }
1125         return 0;
1126 }
1127
1128 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1129                          struct radeon_cs_packet *pkt)
1130 {
1131         volatile uint32_t *ib;
1132         unsigned i;
1133         unsigned idx;
1134
1135         ib = p->ib->ptr;
1136         idx = pkt->idx;
1137         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1138                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1139         }
1140 }
1141
1142 /**
1143  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1144  * @parser:     parser structure holding parsing context.
1145  * @pkt:        where to store packet informations
1146  *
1147  * Assume that chunk_ib_index is properly set. Will return -EINVAL
1148  * if packet is bigger than remaining ib size. or if packets is unknown.
1149  **/
1150 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1151                          struct radeon_cs_packet *pkt,
1152                          unsigned idx)
1153 {
1154         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1155         uint32_t header;
1156
1157         if (idx >= ib_chunk->length_dw) {
1158                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1159                           idx, ib_chunk->length_dw);
1160                 return -EINVAL;
1161         }
1162         header = radeon_get_ib_value(p, idx);
1163         pkt->idx = idx;
1164         pkt->type = CP_PACKET_GET_TYPE(header);
1165         pkt->count = CP_PACKET_GET_COUNT(header);
1166         switch (pkt->type) {
1167         case PACKET_TYPE0:
1168                 pkt->reg = CP_PACKET0_GET_REG(header);
1169                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1170                 break;
1171         case PACKET_TYPE3:
1172                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1173                 break;
1174         case PACKET_TYPE2:
1175                 pkt->count = -1;
1176                 break;
1177         default:
1178                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1179                 return -EINVAL;
1180         }
1181         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1182                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1183                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1184                 return -EINVAL;
1185         }
1186         return 0;
1187 }
1188
1189 /**
1190  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1191  * @parser:             parser structure holding parsing context.
1192  *
1193  * Userspace sends a special sequence for VLINE waits.
1194  * PACKET0 - VLINE_START_END + value
1195  * PACKET0 - WAIT_UNTIL +_value
1196  * RELOC (P3) - crtc_id in reloc.
1197  *
1198  * This function parses this and relocates the VLINE START END
1199  * and WAIT UNTIL packets to the correct crtc.
1200  * It also detects a switched off crtc and nulls out the
1201  * wait in that case.
1202  */
1203 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1204 {
1205         struct drm_mode_object *obj;
1206         struct drm_crtc *crtc;
1207         struct radeon_crtc *radeon_crtc;
1208         struct radeon_cs_packet p3reloc, waitreloc;
1209         int crtc_id;
1210         int r;
1211         uint32_t header, h_idx, reg;
1212         volatile uint32_t *ib;
1213
1214         ib = p->ib->ptr;
1215
1216         /* parse the wait until */
1217         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1218         if (r)
1219                 return r;
1220
1221         /* check its a wait until and only 1 count */
1222         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1223             waitreloc.count != 0) {
1224                 DRM_ERROR("vline wait had illegal wait until segment\n");
1225                 r = -EINVAL;
1226                 return r;
1227         }
1228
1229         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1230                 DRM_ERROR("vline wait had illegal wait until\n");
1231                 r = -EINVAL;
1232                 return r;
1233         }
1234
1235         /* jump over the NOP */
1236         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1237         if (r)
1238                 return r;
1239
1240         h_idx = p->idx - 2;
1241         p->idx += waitreloc.count + 2;
1242         p->idx += p3reloc.count + 2;
1243
1244         header = radeon_get_ib_value(p, h_idx);
1245         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1246         reg = CP_PACKET0_GET_REG(header);
1247         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1248         if (!obj) {
1249                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1250                 r = -EINVAL;
1251                 goto out;
1252         }
1253         crtc = obj_to_crtc(obj);
1254         radeon_crtc = to_radeon_crtc(crtc);
1255         crtc_id = radeon_crtc->crtc_id;
1256
1257         if (!crtc->enabled) {
1258                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1259                 ib[h_idx + 2] = PACKET2(0);
1260                 ib[h_idx + 3] = PACKET2(0);
1261         } else if (crtc_id == 1) {
1262                 switch (reg) {
1263                 case AVIVO_D1MODE_VLINE_START_END:
1264                         header &= ~R300_CP_PACKET0_REG_MASK;
1265                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1266                         break;
1267                 case RADEON_CRTC_GUI_TRIG_VLINE:
1268                         header &= ~R300_CP_PACKET0_REG_MASK;
1269                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1270                         break;
1271                 default:
1272                         DRM_ERROR("unknown crtc reloc\n");
1273                         r = -EINVAL;
1274                         goto out;
1275                 }
1276                 ib[h_idx] = header;
1277                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1278         }
1279 out:
1280         return r;
1281 }
1282
1283 /**
1284  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1285  * @parser:             parser structure holding parsing context.
1286  * @data:               pointer to relocation data
1287  * @offset_start:       starting offset
1288  * @offset_mask:        offset mask (to align start offset on)
1289  * @reloc:              reloc informations
1290  *
1291  * Check next packet is relocation packet3, do bo validation and compute
1292  * GPU offset using the provided start.
1293  **/
1294 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1295                               struct radeon_cs_reloc **cs_reloc)
1296 {
1297         struct radeon_cs_chunk *relocs_chunk;
1298         struct radeon_cs_packet p3reloc;
1299         unsigned idx;
1300         int r;
1301
1302         if (p->chunk_relocs_idx == -1) {
1303                 DRM_ERROR("No relocation chunk !\n");
1304                 return -EINVAL;
1305         }
1306         *cs_reloc = NULL;
1307         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1308         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1309         if (r) {
1310                 return r;
1311         }
1312         p->idx += p3reloc.count + 2;
1313         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1314                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1315                           p3reloc.idx);
1316                 r100_cs_dump_packet(p, &p3reloc);
1317                 return -EINVAL;
1318         }
1319         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1320         if (idx >= relocs_chunk->length_dw) {
1321                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1322                           idx, relocs_chunk->length_dw);
1323                 r100_cs_dump_packet(p, &p3reloc);
1324                 return -EINVAL;
1325         }
1326         /* FIXME: we assume reloc size is 4 dwords */
1327         *cs_reloc = p->relocs_ptr[(idx / 4)];
1328         return 0;
1329 }
1330
1331 static int r100_get_vtx_size(uint32_t vtx_fmt)
1332 {
1333         int vtx_size;
1334         vtx_size = 2;
1335         /* ordered according to bits in spec */
1336         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1337                 vtx_size++;
1338         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1339                 vtx_size += 3;
1340         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1341                 vtx_size++;
1342         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1343                 vtx_size++;
1344         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1345                 vtx_size += 3;
1346         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1347                 vtx_size++;
1348         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1349                 vtx_size++;
1350         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1351                 vtx_size += 2;
1352         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1353                 vtx_size += 2;
1354         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1355                 vtx_size++;
1356         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1357                 vtx_size += 2;
1358         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1359                 vtx_size++;
1360         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1361                 vtx_size += 2;
1362         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1363                 vtx_size++;
1364         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1365                 vtx_size++;
1366         /* blend weight */
1367         if (vtx_fmt & (0x7 << 15))
1368                 vtx_size += (vtx_fmt >> 15) & 0x7;
1369         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1370                 vtx_size += 3;
1371         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1372                 vtx_size += 2;
1373         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1374                 vtx_size++;
1375         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1376                 vtx_size++;
1377         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1378                 vtx_size++;
1379         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1380                 vtx_size++;
1381         return vtx_size;
1382 }
1383
1384 static int r100_packet0_check(struct radeon_cs_parser *p,
1385                               struct radeon_cs_packet *pkt,
1386                               unsigned idx, unsigned reg)
1387 {
1388         struct radeon_cs_reloc *reloc;
1389         struct r100_cs_track *track;
1390         volatile uint32_t *ib;
1391         uint32_t tmp;
1392         int r;
1393         int i, face;
1394         u32 tile_flags = 0;
1395         u32 idx_value;
1396
1397         ib = p->ib->ptr;
1398         track = (struct r100_cs_track *)p->track;
1399
1400         idx_value = radeon_get_ib_value(p, idx);
1401
1402         switch (reg) {
1403         case RADEON_CRTC_GUI_TRIG_VLINE:
1404                 r = r100_cs_packet_parse_vline(p);
1405                 if (r) {
1406                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1407                                   idx, reg);
1408                         r100_cs_dump_packet(p, pkt);
1409                         return r;
1410                 }
1411                 break;
1412                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1413                  * range access */
1414         case RADEON_DST_PITCH_OFFSET:
1415         case RADEON_SRC_PITCH_OFFSET:
1416                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1417                 if (r)
1418                         return r;
1419                 break;
1420         case RADEON_RB3D_DEPTHOFFSET:
1421                 r = r100_cs_packet_next_reloc(p, &reloc);
1422                 if (r) {
1423                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1424                                   idx, reg);
1425                         r100_cs_dump_packet(p, pkt);
1426                         return r;
1427                 }
1428                 track->zb.robj = reloc->robj;
1429                 track->zb.offset = idx_value;
1430                 track->zb_dirty = true;
1431                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1432                 break;
1433         case RADEON_RB3D_COLOROFFSET:
1434                 r = r100_cs_packet_next_reloc(p, &reloc);
1435                 if (r) {
1436                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1437                                   idx, reg);
1438                         r100_cs_dump_packet(p, pkt);
1439                         return r;
1440                 }
1441                 track->cb[0].robj = reloc->robj;
1442                 track->cb[0].offset = idx_value;
1443                 track->cb_dirty = true;
1444                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1445                 break;
1446         case RADEON_PP_TXOFFSET_0:
1447         case RADEON_PP_TXOFFSET_1:
1448         case RADEON_PP_TXOFFSET_2:
1449                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1450                 r = r100_cs_packet_next_reloc(p, &reloc);
1451                 if (r) {
1452                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1453                                   idx, reg);
1454                         r100_cs_dump_packet(p, pkt);
1455                         return r;
1456                 }
1457                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1458                 track->textures[i].robj = reloc->robj;
1459                 track->tex_dirty = true;
1460                 break;
1461         case RADEON_PP_CUBIC_OFFSET_T0_0:
1462         case RADEON_PP_CUBIC_OFFSET_T0_1:
1463         case RADEON_PP_CUBIC_OFFSET_T0_2:
1464         case RADEON_PP_CUBIC_OFFSET_T0_3:
1465         case RADEON_PP_CUBIC_OFFSET_T0_4:
1466                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1467                 r = r100_cs_packet_next_reloc(p, &reloc);
1468                 if (r) {
1469                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1470                                   idx, reg);
1471                         r100_cs_dump_packet(p, pkt);
1472                         return r;
1473                 }
1474                 track->textures[0].cube_info[i].offset = idx_value;
1475                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1476                 track->textures[0].cube_info[i].robj = reloc->robj;
1477                 track->tex_dirty = true;
1478                 break;
1479         case RADEON_PP_CUBIC_OFFSET_T1_0:
1480         case RADEON_PP_CUBIC_OFFSET_T1_1:
1481         case RADEON_PP_CUBIC_OFFSET_T1_2:
1482         case RADEON_PP_CUBIC_OFFSET_T1_3:
1483         case RADEON_PP_CUBIC_OFFSET_T1_4:
1484                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1485                 r = r100_cs_packet_next_reloc(p, &reloc);
1486                 if (r) {
1487                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1488                                   idx, reg);
1489                         r100_cs_dump_packet(p, pkt);
1490                         return r;
1491                 }
1492                 track->textures[1].cube_info[i].offset = idx_value;
1493                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1494                 track->textures[1].cube_info[i].robj = reloc->robj;
1495                 track->tex_dirty = true;
1496                 break;
1497         case RADEON_PP_CUBIC_OFFSET_T2_0:
1498         case RADEON_PP_CUBIC_OFFSET_T2_1:
1499         case RADEON_PP_CUBIC_OFFSET_T2_2:
1500         case RADEON_PP_CUBIC_OFFSET_T2_3:
1501         case RADEON_PP_CUBIC_OFFSET_T2_4:
1502                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1503                 r = r100_cs_packet_next_reloc(p, &reloc);
1504                 if (r) {
1505                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1506                                   idx, reg);
1507                         r100_cs_dump_packet(p, pkt);
1508                         return r;
1509                 }
1510                 track->textures[2].cube_info[i].offset = idx_value;
1511                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1512                 track->textures[2].cube_info[i].robj = reloc->robj;
1513                 track->tex_dirty = true;
1514                 break;
1515         case RADEON_RE_WIDTH_HEIGHT:
1516                 track->maxy = ((idx_value >> 16) & 0x7FF);
1517                 track->cb_dirty = true;
1518                 track->zb_dirty = true;
1519                 break;
1520         case RADEON_RB3D_COLORPITCH:
1521                 r = r100_cs_packet_next_reloc(p, &reloc);
1522                 if (r) {
1523                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1524                                   idx, reg);
1525                         r100_cs_dump_packet(p, pkt);
1526                         return r;
1527                 }
1528
1529                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1530                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1531                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1532                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1533
1534                 tmp = idx_value & ~(0x7 << 16);
1535                 tmp |= tile_flags;
1536                 ib[idx] = tmp;
1537
1538                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1539                 track->cb_dirty = true;
1540                 break;
1541         case RADEON_RB3D_DEPTHPITCH:
1542                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1543                 track->zb_dirty = true;
1544                 break;
1545         case RADEON_RB3D_CNTL:
1546                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1547                 case 7:
1548                 case 8:
1549                 case 9:
1550                 case 11:
1551                 case 12:
1552                         track->cb[0].cpp = 1;
1553                         break;
1554                 case 3:
1555                 case 4:
1556                 case 15:
1557                         track->cb[0].cpp = 2;
1558                         break;
1559                 case 6:
1560                         track->cb[0].cpp = 4;
1561                         break;
1562                 default:
1563                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1564                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1565                         return -EINVAL;
1566                 }
1567                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1568                 track->cb_dirty = true;
1569                 track->zb_dirty = true;
1570                 break;
1571         case RADEON_RB3D_ZSTENCILCNTL:
1572                 switch (idx_value & 0xf) {
1573                 case 0:
1574                         track->zb.cpp = 2;
1575                         break;
1576                 case 2:
1577                 case 3:
1578                 case 4:
1579                 case 5:
1580                 case 9:
1581                 case 11:
1582                         track->zb.cpp = 4;
1583                         break;
1584                 default:
1585                         break;
1586                 }
1587                 track->zb_dirty = true;
1588                 break;
1589         case RADEON_RB3D_ZPASS_ADDR:
1590                 r = r100_cs_packet_next_reloc(p, &reloc);
1591                 if (r) {
1592                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1593                                   idx, reg);
1594                         r100_cs_dump_packet(p, pkt);
1595                         return r;
1596                 }
1597                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1598                 break;
1599         case RADEON_PP_CNTL:
1600                 {
1601                         uint32_t temp = idx_value >> 4;
1602                         for (i = 0; i < track->num_texture; i++)
1603                                 track->textures[i].enabled = !!(temp & (1 << i));
1604                         track->tex_dirty = true;
1605                 }
1606                 break;
1607         case RADEON_SE_VF_CNTL:
1608                 track->vap_vf_cntl = idx_value;
1609                 break;
1610         case RADEON_SE_VTX_FMT:
1611                 track->vtx_size = r100_get_vtx_size(idx_value);
1612                 break;
1613         case RADEON_PP_TEX_SIZE_0:
1614         case RADEON_PP_TEX_SIZE_1:
1615         case RADEON_PP_TEX_SIZE_2:
1616                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1617                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1618                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1619                 track->tex_dirty = true;
1620                 break;
1621         case RADEON_PP_TEX_PITCH_0:
1622         case RADEON_PP_TEX_PITCH_1:
1623         case RADEON_PP_TEX_PITCH_2:
1624                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1625                 track->textures[i].pitch = idx_value + 32;
1626                 track->tex_dirty = true;
1627                 break;
1628         case RADEON_PP_TXFILTER_0:
1629         case RADEON_PP_TXFILTER_1:
1630         case RADEON_PP_TXFILTER_2:
1631                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1632                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1633                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1634                 tmp = (idx_value >> 23) & 0x7;
1635                 if (tmp == 2 || tmp == 6)
1636                         track->textures[i].roundup_w = false;
1637                 tmp = (idx_value >> 27) & 0x7;
1638                 if (tmp == 2 || tmp == 6)
1639                         track->textures[i].roundup_h = false;
1640                 track->tex_dirty = true;
1641                 break;
1642         case RADEON_PP_TXFORMAT_0:
1643         case RADEON_PP_TXFORMAT_1:
1644         case RADEON_PP_TXFORMAT_2:
1645                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1646                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1647                         track->textures[i].use_pitch = 1;
1648                 } else {
1649                         track->textures[i].use_pitch = 0;
1650                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1651                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1652                 }
1653                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1654                         track->textures[i].tex_coord_type = 2;
1655                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1656                 case RADEON_TXFORMAT_I8:
1657                 case RADEON_TXFORMAT_RGB332:
1658                 case RADEON_TXFORMAT_Y8:
1659                         track->textures[i].cpp = 1;
1660                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1661                         break;
1662                 case RADEON_TXFORMAT_AI88:
1663                 case RADEON_TXFORMAT_ARGB1555:
1664                 case RADEON_TXFORMAT_RGB565:
1665                 case RADEON_TXFORMAT_ARGB4444:
1666                 case RADEON_TXFORMAT_VYUY422:
1667                 case RADEON_TXFORMAT_YVYU422:
1668                 case RADEON_TXFORMAT_SHADOW16:
1669                 case RADEON_TXFORMAT_LDUDV655:
1670                 case RADEON_TXFORMAT_DUDV88:
1671                         track->textures[i].cpp = 2;
1672                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1673                         break;
1674                 case RADEON_TXFORMAT_ARGB8888:
1675                 case RADEON_TXFORMAT_RGBA8888:
1676                 case RADEON_TXFORMAT_SHADOW32:
1677                 case RADEON_TXFORMAT_LDUDUV8888:
1678                         track->textures[i].cpp = 4;
1679                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1680                         break;
1681                 case RADEON_TXFORMAT_DXT1:
1682                         track->textures[i].cpp = 1;
1683                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1684                         break;
1685                 case RADEON_TXFORMAT_DXT23:
1686                 case RADEON_TXFORMAT_DXT45:
1687                         track->textures[i].cpp = 1;
1688                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1689                         break;
1690                 }
1691                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1692                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1693                 track->tex_dirty = true;
1694                 break;
1695         case RADEON_PP_CUBIC_FACES_0:
1696         case RADEON_PP_CUBIC_FACES_1:
1697         case RADEON_PP_CUBIC_FACES_2:
1698                 tmp = idx_value;
1699                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1700                 for (face = 0; face < 4; face++) {
1701                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1702                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1703                 }
1704                 track->tex_dirty = true;
1705                 break;
1706         default:
1707                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1708                        reg, idx);
1709                 return -EINVAL;
1710         }
1711         return 0;
1712 }
1713
1714 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1715                                          struct radeon_cs_packet *pkt,
1716                                          struct radeon_bo *robj)
1717 {
1718         unsigned idx;
1719         u32 value;
1720         idx = pkt->idx + 1;
1721         value = radeon_get_ib_value(p, idx + 2);
1722         if ((value + 1) > radeon_bo_size(robj)) {
1723                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1724                           "(need %u have %lu) !\n",
1725                           value + 1,
1726                           radeon_bo_size(robj));
1727                 return -EINVAL;
1728         }
1729         return 0;
1730 }
1731
1732 static int r100_packet3_check(struct radeon_cs_parser *p,
1733                               struct radeon_cs_packet *pkt)
1734 {
1735         struct radeon_cs_reloc *reloc;
1736         struct r100_cs_track *track;
1737         unsigned idx;
1738         volatile uint32_t *ib;
1739         int r;
1740
1741         ib = p->ib->ptr;
1742         idx = pkt->idx + 1;
1743         track = (struct r100_cs_track *)p->track;
1744         switch (pkt->opcode) {
1745         case PACKET3_3D_LOAD_VBPNTR:
1746                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1747                 if (r)
1748                         return r;
1749                 break;
1750         case PACKET3_INDX_BUFFER:
1751                 r = r100_cs_packet_next_reloc(p, &reloc);
1752                 if (r) {
1753                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1754                         r100_cs_dump_packet(p, pkt);
1755                         return r;
1756                 }
1757                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1758                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1759                 if (r) {
1760                         return r;
1761                 }
1762                 break;
1763         case 0x23:
1764                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1765                 r = r100_cs_packet_next_reloc(p, &reloc);
1766                 if (r) {
1767                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1768                         r100_cs_dump_packet(p, pkt);
1769                         return r;
1770                 }
1771                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1772                 track->num_arrays = 1;
1773                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1774
1775                 track->arrays[0].robj = reloc->robj;
1776                 track->arrays[0].esize = track->vtx_size;
1777
1778                 track->max_indx = radeon_get_ib_value(p, idx+1);
1779
1780                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1781                 track->immd_dwords = pkt->count - 1;
1782                 r = r100_cs_track_check(p->rdev, track);
1783                 if (r)
1784                         return r;
1785                 break;
1786         case PACKET3_3D_DRAW_IMMD:
1787                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1788                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1789                         return -EINVAL;
1790                 }
1791                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1792                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1793                 track->immd_dwords = pkt->count - 1;
1794                 r = r100_cs_track_check(p->rdev, track);
1795                 if (r)
1796                         return r;
1797                 break;
1798                 /* triggers drawing using in-packet vertex data */
1799         case PACKET3_3D_DRAW_IMMD_2:
1800                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1801                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1802                         return -EINVAL;
1803                 }
1804                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1805                 track->immd_dwords = pkt->count;
1806                 r = r100_cs_track_check(p->rdev, track);
1807                 if (r)
1808                         return r;
1809                 break;
1810                 /* triggers drawing using in-packet vertex data */
1811         case PACKET3_3D_DRAW_VBUF_2:
1812                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1813                 r = r100_cs_track_check(p->rdev, track);
1814                 if (r)
1815                         return r;
1816                 break;
1817                 /* triggers drawing of vertex buffers setup elsewhere */
1818         case PACKET3_3D_DRAW_INDX_2:
1819                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1820                 r = r100_cs_track_check(p->rdev, track);
1821                 if (r)
1822                         return r;
1823                 break;
1824                 /* triggers drawing using indices to vertex buffer */
1825         case PACKET3_3D_DRAW_VBUF:
1826                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1827                 r = r100_cs_track_check(p->rdev, track);
1828                 if (r)
1829                         return r;
1830                 break;
1831                 /* triggers drawing of vertex buffers setup elsewhere */
1832         case PACKET3_3D_DRAW_INDX:
1833                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1834                 r = r100_cs_track_check(p->rdev, track);
1835                 if (r)
1836                         return r;
1837                 break;
1838                 /* triggers drawing using indices to vertex buffer */
1839         case PACKET3_3D_CLEAR_HIZ:
1840         case PACKET3_3D_CLEAR_ZMASK:
1841                 if (p->rdev->hyperz_filp != p->filp)
1842                         return -EINVAL;
1843                 break;
1844         case PACKET3_NOP:
1845                 break;
1846         default:
1847                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1848                 return -EINVAL;
1849         }
1850         return 0;
1851 }
1852
1853 int r100_cs_parse(struct radeon_cs_parser *p)
1854 {
1855         struct radeon_cs_packet pkt;
1856         struct r100_cs_track *track;
1857         int r;
1858
1859         track = kzalloc(sizeof(*track), GFP_KERNEL);
1860         r100_cs_track_clear(p->rdev, track);
1861         p->track = track;
1862         do {
1863                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1864                 if (r) {
1865                         return r;
1866                 }
1867                 p->idx += pkt.count + 2;
1868                 switch (pkt.type) {
1869                         case PACKET_TYPE0:
1870                                 if (p->rdev->family >= CHIP_R200)
1871                                         r = r100_cs_parse_packet0(p, &pkt,
1872                                                                   p->rdev->config.r100.reg_safe_bm,
1873                                                                   p->rdev->config.r100.reg_safe_bm_size,
1874                                                                   &r200_packet0_check);
1875                                 else
1876                                         r = r100_cs_parse_packet0(p, &pkt,
1877                                                                   p->rdev->config.r100.reg_safe_bm,
1878                                                                   p->rdev->config.r100.reg_safe_bm_size,
1879                                                                   &r100_packet0_check);
1880                                 break;
1881                         case PACKET_TYPE2:
1882                                 break;
1883                         case PACKET_TYPE3:
1884                                 r = r100_packet3_check(p, &pkt);
1885                                 break;
1886                         default:
1887                                 DRM_ERROR("Unknown packet type %d !\n",
1888                                           pkt.type);
1889                                 return -EINVAL;
1890                 }
1891                 if (r) {
1892                         return r;
1893                 }
1894         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1895         return 0;
1896 }
1897
1898
1899 /*
1900  * Global GPU functions
1901  */
1902 void r100_errata(struct radeon_device *rdev)
1903 {
1904         rdev->pll_errata = 0;
1905
1906         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1907                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1908         }
1909
1910         if (rdev->family == CHIP_RV100 ||
1911             rdev->family == CHIP_RS100 ||
1912             rdev->family == CHIP_RS200) {
1913                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1914         }
1915 }
1916
1917 /* Wait for vertical sync on primary CRTC */
1918 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1919 {
1920         uint32_t crtc_gen_cntl, tmp;
1921         int i;
1922
1923         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1924         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1925             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1926                 return;
1927         }
1928         /* Clear the CRTC_VBLANK_SAVE bit */
1929         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1930         for (i = 0; i < rdev->usec_timeout; i++) {
1931                 tmp = RREG32(RADEON_CRTC_STATUS);
1932                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1933                         return;
1934                 }
1935                 DRM_UDELAY(1);
1936         }
1937 }
1938
1939 /* Wait for vertical sync on secondary CRTC */
1940 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1941 {
1942         uint32_t crtc2_gen_cntl, tmp;
1943         int i;
1944
1945         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1946         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1947             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1948                 return;
1949
1950         /* Clear the CRTC_VBLANK_SAVE bit */
1951         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1952         for (i = 0; i < rdev->usec_timeout; i++) {
1953                 tmp = RREG32(RADEON_CRTC2_STATUS);
1954                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1955                         return;
1956                 }
1957                 DRM_UDELAY(1);
1958         }
1959 }
1960
1961 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1962 {
1963         unsigned i;
1964         uint32_t tmp;
1965
1966         for (i = 0; i < rdev->usec_timeout; i++) {
1967                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1968                 if (tmp >= n) {
1969                         return 0;
1970                 }
1971                 DRM_UDELAY(1);
1972         }
1973         return -1;
1974 }
1975
1976 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1977 {
1978         unsigned i;
1979         uint32_t tmp;
1980
1981         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1982                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1983                        " Bad things might happen.\n");
1984         }
1985         for (i = 0; i < rdev->usec_timeout; i++) {
1986                 tmp = RREG32(RADEON_RBBM_STATUS);
1987                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1988                         return 0;
1989                 }
1990                 DRM_UDELAY(1);
1991         }
1992         return -1;
1993 }
1994
1995 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1996 {
1997         unsigned i;
1998         uint32_t tmp;
1999
2000         for (i = 0; i < rdev->usec_timeout; i++) {
2001                 /* read MC_STATUS */
2002                 tmp = RREG32(RADEON_MC_STATUS);
2003                 if (tmp & RADEON_MC_IDLE) {
2004                         return 0;
2005                 }
2006                 DRM_UDELAY(1);
2007         }
2008         return -1;
2009 }
2010
2011 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2012 {
2013         lockup->last_cp_rptr = cp->rptr;
2014         lockup->last_jiffies = jiffies;
2015 }
2016
2017 /**
2018  * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2019  * @rdev:       radeon device structure
2020  * @lockup:     r100_gpu_lockup structure holding CP lockup tracking informations
2021  * @cp:         radeon_cp structure holding CP information
2022  *
2023  * We don't need to initialize the lockup tracking information as we will either
2024  * have CP rptr to a different value of jiffies wrap around which will force
2025  * initialization of the lockup tracking informations.
2026  *
2027  * A possible false positivie is if we get call after while and last_cp_rptr ==
2028  * the current CP rptr, even if it's unlikely it might happen. To avoid this
2029  * if the elapsed time since last call is bigger than 2 second than we return
2030  * false and update the tracking information. Due to this the caller must call
2031  * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2032  * the fencing code should be cautious about that.
2033  *
2034  * Caller should write to the ring to force CP to do something so we don't get
2035  * false positive when CP is just gived nothing to do.
2036  *
2037  **/
2038 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2039 {
2040         unsigned long cjiffies, elapsed;
2041
2042         cjiffies = jiffies;
2043         if (!time_after(cjiffies, lockup->last_jiffies)) {
2044                 /* likely a wrap around */
2045                 lockup->last_cp_rptr = cp->rptr;
2046                 lockup->last_jiffies = jiffies;
2047                 return false;
2048         }
2049         if (cp->rptr != lockup->last_cp_rptr) {
2050                 /* CP is still working no lockup */
2051                 lockup->last_cp_rptr = cp->rptr;
2052                 lockup->last_jiffies = jiffies;
2053                 return false;
2054         }
2055         elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2056         if (elapsed >= 10000) {
2057                 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2058                 return true;
2059         }
2060         /* give a chance to the GPU ... */
2061         return false;
2062 }
2063
2064 bool r100_gpu_is_lockup(struct radeon_device *rdev)
2065 {
2066         u32 rbbm_status;
2067         int r;
2068
2069         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2070         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2071                 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2072                 return false;
2073         }
2074         /* force CP activities */
2075         r = radeon_ring_lock(rdev, 2);
2076         if (!r) {
2077                 /* PACKET2 NOP */
2078                 radeon_ring_write(rdev, 0x80000000);
2079                 radeon_ring_write(rdev, 0x80000000);
2080                 radeon_ring_unlock_commit(rdev);
2081         }
2082         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2083         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2084 }
2085
2086 void r100_bm_disable(struct radeon_device *rdev)
2087 {
2088         u32 tmp;
2089
2090         /* disable bus mastering */
2091         tmp = RREG32(R_000030_BUS_CNTL);
2092         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2093         mdelay(1);
2094         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2095         mdelay(1);
2096         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2097         tmp = RREG32(RADEON_BUS_CNTL);
2098         mdelay(1);
2099         pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2100         pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
2101         mdelay(1);
2102 }
2103
2104 int r100_asic_reset(struct radeon_device *rdev)
2105 {
2106         struct r100_mc_save save;
2107         u32 status, tmp;
2108         int ret = 0;
2109
2110         status = RREG32(R_000E40_RBBM_STATUS);
2111         if (!G_000E40_GUI_ACTIVE(status)) {
2112                 return 0;
2113         }
2114         r100_mc_stop(rdev, &save);
2115         status = RREG32(R_000E40_RBBM_STATUS);
2116         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2117         /* stop CP */
2118         WREG32(RADEON_CP_CSQ_CNTL, 0);
2119         tmp = RREG32(RADEON_CP_RB_CNTL);
2120         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2121         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2122         WREG32(RADEON_CP_RB_WPTR, 0);
2123         WREG32(RADEON_CP_RB_CNTL, tmp);
2124         /* save PCI state */
2125         pci_save_state(rdev->pdev);
2126         /* disable bus mastering */
2127         r100_bm_disable(rdev);
2128         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2129                                         S_0000F0_SOFT_RESET_RE(1) |
2130                                         S_0000F0_SOFT_RESET_PP(1) |
2131                                         S_0000F0_SOFT_RESET_RB(1));
2132         RREG32(R_0000F0_RBBM_SOFT_RESET);
2133         mdelay(500);
2134         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2135         mdelay(1);
2136         status = RREG32(R_000E40_RBBM_STATUS);
2137         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2138         /* reset CP */
2139         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2140         RREG32(R_0000F0_RBBM_SOFT_RESET);
2141         mdelay(500);
2142         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2143         mdelay(1);
2144         status = RREG32(R_000E40_RBBM_STATUS);
2145         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2146         /* restore PCI & busmastering */
2147         pci_restore_state(rdev->pdev);
2148         r100_enable_bm(rdev);
2149         /* Check if GPU is idle */
2150         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2151                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2152                 dev_err(rdev->dev, "failed to reset GPU\n");
2153                 rdev->gpu_lockup = true;
2154                 ret = -1;
2155         } else
2156                 dev_info(rdev->dev, "GPU reset succeed\n");
2157         r100_mc_resume(rdev, &save);
2158         return ret;
2159 }
2160
2161 void r100_set_common_regs(struct radeon_device *rdev)
2162 {
2163         struct drm_device *dev = rdev->ddev;
2164         bool force_dac2 = false;
2165         u32 tmp;
2166
2167         /* set these so they don't interfere with anything */
2168         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2169         WREG32(RADEON_SUBPIC_CNTL, 0);
2170         WREG32(RADEON_VIPH_CONTROL, 0);
2171         WREG32(RADEON_I2C_CNTL_1, 0);
2172         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2173         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2174         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2175
2176         /* always set up dac2 on rn50 and some rv100 as lots
2177          * of servers seem to wire it up to a VGA port but
2178          * don't report it in the bios connector
2179          * table.
2180          */
2181         switch (dev->pdev->device) {
2182                 /* RN50 */
2183         case 0x515e:
2184         case 0x5969:
2185                 force_dac2 = true;
2186                 break;
2187                 /* RV100*/
2188         case 0x5159:
2189         case 0x515a:
2190                 /* DELL triple head servers */
2191                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2192                     ((dev->pdev->subsystem_device == 0x016c) ||
2193                      (dev->pdev->subsystem_device == 0x016d) ||
2194                      (dev->pdev->subsystem_device == 0x016e) ||
2195                      (dev->pdev->subsystem_device == 0x016f) ||
2196                      (dev->pdev->subsystem_device == 0x0170) ||
2197                      (dev->pdev->subsystem_device == 0x017d) ||
2198                      (dev->pdev->subsystem_device == 0x017e) ||
2199                      (dev->pdev->subsystem_device == 0x0183) ||
2200                      (dev->pdev->subsystem_device == 0x018a) ||
2201                      (dev->pdev->subsystem_device == 0x019a)))
2202                         force_dac2 = true;
2203                 break;
2204         }
2205
2206         if (force_dac2) {
2207                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2208                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2209                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2210
2211                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2212                    enable it, even it's detected.
2213                 */
2214
2215                 /* force it to crtc0 */
2216                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2217                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2218                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2219
2220                 /* set up the TV DAC */
2221                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2222                                  RADEON_TV_DAC_STD_MASK |
2223                                  RADEON_TV_DAC_RDACPD |
2224                                  RADEON_TV_DAC_GDACPD |
2225                                  RADEON_TV_DAC_BDACPD |
2226                                  RADEON_TV_DAC_BGADJ_MASK |
2227                                  RADEON_TV_DAC_DACADJ_MASK);
2228                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2229                                 RADEON_TV_DAC_NHOLD |
2230                                 RADEON_TV_DAC_STD_PS2 |
2231                                 (0x58 << 16));
2232
2233                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2234                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2235                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2236         }
2237
2238         /* switch PM block to ACPI mode */
2239         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2240         tmp &= ~RADEON_PM_MODE_SEL;
2241         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2242
2243 }
2244
2245 /*
2246  * VRAM info
2247  */
2248 static void r100_vram_get_type(struct radeon_device *rdev)
2249 {
2250         uint32_t tmp;
2251
2252         rdev->mc.vram_is_ddr = false;
2253         if (rdev->flags & RADEON_IS_IGP)
2254                 rdev->mc.vram_is_ddr = true;
2255         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2256                 rdev->mc.vram_is_ddr = true;
2257         if ((rdev->family == CHIP_RV100) ||
2258             (rdev->family == CHIP_RS100) ||
2259             (rdev->family == CHIP_RS200)) {
2260                 tmp = RREG32(RADEON_MEM_CNTL);
2261                 if (tmp & RV100_HALF_MODE) {
2262                         rdev->mc.vram_width = 32;
2263                 } else {
2264                         rdev->mc.vram_width = 64;
2265                 }
2266                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2267                         rdev->mc.vram_width /= 4;
2268                         rdev->mc.vram_is_ddr = true;
2269                 }
2270         } else if (rdev->family <= CHIP_RV280) {
2271                 tmp = RREG32(RADEON_MEM_CNTL);
2272                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2273                         rdev->mc.vram_width = 128;
2274                 } else {
2275                         rdev->mc.vram_width = 64;
2276                 }
2277         } else {
2278                 /* newer IGPs */
2279                 rdev->mc.vram_width = 128;
2280         }
2281 }
2282
2283 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2284 {
2285         u32 aper_size;
2286         u8 byte;
2287
2288         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2289
2290         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2291          * that is has the 2nd generation multifunction PCI interface
2292          */
2293         if (rdev->family == CHIP_RV280 ||
2294             rdev->family >= CHIP_RV350) {
2295                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2296                        ~RADEON_HDP_APER_CNTL);
2297                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2298                 return aper_size * 2;
2299         }
2300
2301         /* Older cards have all sorts of funny issues to deal with. First
2302          * check if it's a multifunction card by reading the PCI config
2303          * header type... Limit those to one aperture size
2304          */
2305         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2306         if (byte & 0x80) {
2307                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2308                 DRM_INFO("Limiting VRAM to one aperture\n");
2309                 return aper_size;
2310         }
2311
2312         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2313          * have set it up. We don't write this as it's broken on some ASICs but
2314          * we expect the BIOS to have done the right thing (might be too optimistic...)
2315          */
2316         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2317                 return aper_size * 2;
2318         return aper_size;
2319 }
2320
2321 void r100_vram_init_sizes(struct radeon_device *rdev)
2322 {
2323         u64 config_aper_size;
2324
2325         /* work out accessible VRAM */
2326         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2327         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2328         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2329         /* FIXME we don't use the second aperture yet when we could use it */
2330         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2331                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2332         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
2333         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2334         if (rdev->flags & RADEON_IS_IGP) {
2335                 uint32_t tom;
2336                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2337                 tom = RREG32(RADEON_NB_TOM);
2338                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2339                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2340                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2341         } else {
2342                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2343                 /* Some production boards of m6 will report 0
2344                  * if it's 8 MB
2345                  */
2346                 if (rdev->mc.real_vram_size == 0) {
2347                         rdev->mc.real_vram_size = 8192 * 1024;
2348                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2349                 }
2350                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2351                  * Novell bug 204882 + along with lots of ubuntu ones
2352                  */
2353                 if (rdev->mc.aper_size > config_aper_size)
2354                         config_aper_size = rdev->mc.aper_size;
2355
2356                 if (config_aper_size > rdev->mc.real_vram_size)
2357                         rdev->mc.mc_vram_size = config_aper_size;
2358                 else
2359                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2360         }
2361 }
2362
2363 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2364 {
2365         uint32_t temp;
2366
2367         temp = RREG32(RADEON_CONFIG_CNTL);
2368         if (state == false) {
2369                 temp &= ~RADEON_CFG_VGA_RAM_EN;
2370                 temp |= RADEON_CFG_VGA_IO_DIS;
2371         } else {
2372                 temp &= ~RADEON_CFG_VGA_IO_DIS;
2373         }
2374         WREG32(RADEON_CONFIG_CNTL, temp);
2375 }
2376
2377 void r100_mc_init(struct radeon_device *rdev)
2378 {
2379         u64 base;
2380
2381         r100_vram_get_type(rdev);
2382         r100_vram_init_sizes(rdev);
2383         base = rdev->mc.aper_base;
2384         if (rdev->flags & RADEON_IS_IGP)
2385                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2386         radeon_vram_location(rdev, &rdev->mc, base);
2387         rdev->mc.gtt_base_align = 0;
2388         if (!(rdev->flags & RADEON_IS_AGP))
2389                 radeon_gtt_location(rdev, &rdev->mc);
2390         radeon_update_bandwidth_info(rdev);
2391 }
2392
2393
2394 /*
2395  * Indirect registers accessor
2396  */
2397 void r100_pll_errata_after_index(struct radeon_device *rdev)
2398 {
2399         if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2400                 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2401                 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2402         }
2403 }
2404
2405 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2406 {
2407         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2408          * or the chip could hang on a subsequent access
2409          */
2410         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2411                 udelay(5000);
2412         }
2413
2414         /* This function is required to workaround a hardware bug in some (all?)
2415          * revisions of the R300.  This workaround should be called after every
2416          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2417          * may not be correct.
2418          */
2419         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2420                 uint32_t save, tmp;
2421
2422                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2423                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2424                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2425                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2426                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2427         }
2428 }
2429
2430 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2431 {
2432         uint32_t data;
2433
2434         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2435         r100_pll_errata_after_index(rdev);
2436         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2437         r100_pll_errata_after_data(rdev);
2438         return data;
2439 }
2440
2441 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2442 {
2443         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2444         r100_pll_errata_after_index(rdev);
2445         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2446         r100_pll_errata_after_data(rdev);
2447 }
2448
2449 void r100_set_safe_registers(struct radeon_device *rdev)
2450 {
2451         if (ASIC_IS_RN50(rdev)) {
2452                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2453                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2454         } else if (rdev->family < CHIP_R200) {
2455                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2456                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2457         } else {
2458                 r200_set_safe_registers(rdev);
2459         }
2460 }
2461
2462 /*
2463  * Debugfs info
2464  */
2465 #if defined(CONFIG_DEBUG_FS)
2466 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2467 {
2468         struct drm_info_node *node = (struct drm_info_node *) m->private;
2469         struct drm_device *dev = node->minor->dev;
2470         struct radeon_device *rdev = dev->dev_private;
2471         uint32_t reg, value;
2472         unsigned i;
2473
2474         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2475         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2476         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2477         for (i = 0; i < 64; i++) {
2478                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2479                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2480                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2481                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2482                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2483         }
2484         return 0;
2485 }
2486
2487 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2488 {
2489         struct drm_info_node *node = (struct drm_info_node *) m->private;
2490         struct drm_device *dev = node->minor->dev;
2491         struct radeon_device *rdev = dev->dev_private;
2492         uint32_t rdp, wdp;
2493         unsigned count, i, j;
2494
2495         radeon_ring_free_size(rdev);
2496         rdp = RREG32(RADEON_CP_RB_RPTR);
2497         wdp = RREG32(RADEON_CP_RB_WPTR);
2498         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2499         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2500         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2501         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2502         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2503         seq_printf(m, "%u dwords in ring\n", count);
2504         for (j = 0; j <= count; j++) {
2505                 i = (rdp + j) & rdev->cp.ptr_mask;
2506                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2507         }
2508         return 0;
2509 }
2510
2511
2512 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2513 {
2514         struct drm_info_node *node = (struct drm_info_node *) m->private;
2515         struct drm_device *dev = node->minor->dev;
2516         struct radeon_device *rdev = dev->dev_private;
2517         uint32_t csq_stat, csq2_stat, tmp;
2518         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2519         unsigned i;
2520
2521         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2522         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2523         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2524         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2525         r_rptr = (csq_stat >> 0) & 0x3ff;
2526         r_wptr = (csq_stat >> 10) & 0x3ff;
2527         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2528         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2529         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2530         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2531         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2532         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2533         seq_printf(m, "Ring rptr %u\n", r_rptr);
2534         seq_printf(m, "Ring wptr %u\n", r_wptr);
2535         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2536         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2537         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2538         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2539         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2540          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2541         seq_printf(m, "Ring fifo:\n");
2542         for (i = 0; i < 256; i++) {
2543                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2544                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2545                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2546         }
2547         seq_printf(m, "Indirect1 fifo:\n");
2548         for (i = 256; i <= 512; i++) {
2549                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2550                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2551                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2552         }
2553         seq_printf(m, "Indirect2 fifo:\n");
2554         for (i = 640; i < ib1_wptr; i++) {
2555                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2556                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2557                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2558         }
2559         return 0;
2560 }
2561
2562 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2563 {
2564         struct drm_info_node *node = (struct drm_info_node *) m->private;
2565         struct drm_device *dev = node->minor->dev;
2566         struct radeon_device *rdev = dev->dev_private;
2567         uint32_t tmp;
2568
2569         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2570         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2571         tmp = RREG32(RADEON_MC_FB_LOCATION);
2572         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2573         tmp = RREG32(RADEON_BUS_CNTL);
2574         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2575         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2576         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2577         tmp = RREG32(RADEON_AGP_BASE);
2578         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2579         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2580         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2581         tmp = RREG32(0x01D0);
2582         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2583         tmp = RREG32(RADEON_AIC_LO_ADDR);
2584         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2585         tmp = RREG32(RADEON_AIC_HI_ADDR);
2586         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2587         tmp = RREG32(0x01E4);
2588         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2589         return 0;
2590 }
2591
2592 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2593         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2594 };
2595
2596 static struct drm_info_list r100_debugfs_cp_list[] = {
2597         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2598         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2599 };
2600
2601 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2602         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2603 };
2604 #endif
2605
2606 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2607 {
2608 #if defined(CONFIG_DEBUG_FS)
2609         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2610 #else
2611         return 0;
2612 #endif
2613 }
2614
2615 int r100_debugfs_cp_init(struct radeon_device *rdev)
2616 {
2617 #if defined(CONFIG_DEBUG_FS)
2618         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2619 #else
2620         return 0;
2621 #endif
2622 }
2623
2624 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2625 {
2626 #if defined(CONFIG_DEBUG_FS)
2627         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2628 #else
2629         return 0;
2630 #endif
2631 }
2632
2633 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2634                          uint32_t tiling_flags, uint32_t pitch,
2635                          uint32_t offset, uint32_t obj_size)
2636 {
2637         int surf_index = reg * 16;
2638         int flags = 0;
2639
2640         if (rdev->family <= CHIP_RS200) {
2641                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2642                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2643                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2644                 if (tiling_flags & RADEON_TILING_MACRO)
2645                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2646         } else if (rdev->family <= CHIP_RV280) {
2647                 if (tiling_flags & (RADEON_TILING_MACRO))
2648                         flags |= R200_SURF_TILE_COLOR_MACRO;
2649                 if (tiling_flags & RADEON_TILING_MICRO)
2650                         flags |= R200_SURF_TILE_COLOR_MICRO;
2651         } else {
2652                 if (tiling_flags & RADEON_TILING_MACRO)
2653                         flags |= R300_SURF_TILE_MACRO;
2654                 if (tiling_flags & RADEON_TILING_MICRO)
2655                         flags |= R300_SURF_TILE_MICRO;
2656         }
2657
2658         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2659                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2660         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2661                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2662
2663         /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2664         if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2665                 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2666                         if (ASIC_IS_RN50(rdev))
2667                                 pitch /= 16;
2668         }
2669
2670         /* r100/r200 divide by 16 */
2671         if (rdev->family < CHIP_R300)
2672                 flags |= pitch / 16;
2673         else
2674                 flags |= pitch / 8;
2675
2676
2677         DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2678         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2679         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2680         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2681         return 0;
2682 }
2683
2684 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2685 {
2686         int surf_index = reg * 16;
2687         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2688 }
2689
2690 void r100_bandwidth_update(struct radeon_device *rdev)
2691 {
2692         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2693         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2694         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2695         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2696         fixed20_12 memtcas_ff[8] = {
2697                 dfixed_init(1),
2698                 dfixed_init(2),
2699                 dfixed_init(3),
2700                 dfixed_init(0),
2701                 dfixed_init_half(1),
2702                 dfixed_init_half(2),
2703                 dfixed_init(0),
2704         };
2705         fixed20_12 memtcas_rs480_ff[8] = {
2706                 dfixed_init(0),
2707                 dfixed_init(1),
2708                 dfixed_init(2),
2709                 dfixed_init(3),
2710                 dfixed_init(0),
2711                 dfixed_init_half(1),
2712                 dfixed_init_half(2),
2713                 dfixed_init_half(3),
2714         };
2715         fixed20_12 memtcas2_ff[8] = {
2716                 dfixed_init(0),
2717                 dfixed_init(1),
2718                 dfixed_init(2),
2719                 dfixed_init(3),
2720                 dfixed_init(4),
2721                 dfixed_init(5),
2722                 dfixed_init(6),
2723                 dfixed_init(7),
2724         };
2725         fixed20_12 memtrbs[8] = {
2726                 dfixed_init(1),
2727                 dfixed_init_half(1),
2728                 dfixed_init(2),
2729                 dfixed_init_half(2),
2730                 dfixed_init(3),
2731                 dfixed_init_half(3),
2732                 dfixed_init(4),
2733                 dfixed_init_half(4)
2734         };
2735         fixed20_12 memtrbs_r4xx[8] = {
2736                 dfixed_init(4),
2737                 dfixed_init(5),
2738                 dfixed_init(6),
2739                 dfixed_init(7),
2740                 dfixed_init(8),
2741                 dfixed_init(9),
2742                 dfixed_init(10),
2743                 dfixed_init(11)
2744         };
2745         fixed20_12 min_mem_eff;
2746         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2747         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2748         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2749                 disp_drain_rate2, read_return_rate;
2750         fixed20_12 time_disp1_drop_priority;
2751         int c;
2752         int cur_size = 16;       /* in octawords */
2753         int critical_point = 0, critical_point2;
2754 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2755         int stop_req, max_stop_req;
2756         struct drm_display_mode *mode1 = NULL;
2757         struct drm_display_mode *mode2 = NULL;
2758         uint32_t pixel_bytes1 = 0;
2759         uint32_t pixel_bytes2 = 0;
2760
2761         radeon_update_display_priority(rdev);
2762
2763         if (rdev->mode_info.crtcs[0]->base.enabled) {
2764                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2765                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2766         }
2767         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2768                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2769                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2770                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2771                 }
2772         }
2773
2774         min_mem_eff.full = dfixed_const_8(0);
2775         /* get modes */
2776         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2777                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2778                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2779                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2780                 /* check crtc enables */
2781                 if (mode2)
2782                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2783                 if (mode1)
2784                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2785                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2786         }
2787
2788         /*
2789          * determine is there is enough bw for current mode
2790          */
2791         sclk_ff = rdev->pm.sclk;
2792         mclk_ff = rdev->pm.mclk;
2793
2794         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2795         temp_ff.full = dfixed_const(temp);
2796         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2797
2798         pix_clk.full = 0;
2799         pix_clk2.full = 0;
2800         peak_disp_bw.full = 0;
2801         if (mode1) {
2802                 temp_ff.full = dfixed_const(1000);
2803                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2804                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2805                 temp_ff.full = dfixed_const(pixel_bytes1);
2806                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2807         }
2808         if (mode2) {
2809                 temp_ff.full = dfixed_const(1000);
2810                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2811                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2812                 temp_ff.full = dfixed_const(pixel_bytes2);
2813                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2814         }
2815
2816         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2817         if (peak_disp_bw.full >= mem_bw.full) {
2818                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2819                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2820         }
2821
2822         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2823         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2824         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2825                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2826                 mem_trp  = ((temp & 0x3)) + 1;
2827                 mem_tras = ((temp & 0x70) >> 4) + 1;
2828         } else if (rdev->family == CHIP_R300 ||
2829                    rdev->family == CHIP_R350) { /* r300, r350 */
2830                 mem_trcd = (temp & 0x7) + 1;
2831                 mem_trp = ((temp >> 8) & 0x7) + 1;
2832                 mem_tras = ((temp >> 11) & 0xf) + 4;
2833         } else if (rdev->family == CHIP_RV350 ||
2834                    rdev->family <= CHIP_RV380) {
2835                 /* rv3x0 */
2836                 mem_trcd = (temp & 0x7) + 3;
2837                 mem_trp = ((temp >> 8) & 0x7) + 3;
2838                 mem_tras = ((temp >> 11) & 0xf) + 6;
2839         } else if (rdev->family == CHIP_R420 ||
2840                    rdev->family == CHIP_R423 ||
2841                    rdev->family == CHIP_RV410) {
2842                 /* r4xx */
2843                 mem_trcd = (temp & 0xf) + 3;
2844                 if (mem_trcd > 15)
2845                         mem_trcd = 15;
2846                 mem_trp = ((temp >> 8) & 0xf) + 3;
2847                 if (mem_trp > 15)
2848                         mem_trp = 15;
2849                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2850                 if (mem_tras > 31)
2851                         mem_tras = 31;
2852         } else { /* RV200, R200 */
2853                 mem_trcd = (temp & 0x7) + 1;
2854                 mem_trp = ((temp >> 8) & 0x7) + 1;
2855                 mem_tras = ((temp >> 12) & 0xf) + 4;
2856         }
2857         /* convert to FF */
2858         trcd_ff.full = dfixed_const(mem_trcd);
2859         trp_ff.full = dfixed_const(mem_trp);
2860         tras_ff.full = dfixed_const(mem_tras);
2861
2862         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2863         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2864         data = (temp & (7 << 20)) >> 20;
2865         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2866                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2867                         tcas_ff = memtcas_rs480_ff[data];
2868                 else
2869                         tcas_ff = memtcas_ff[data];
2870         } else
2871                 tcas_ff = memtcas2_ff[data];
2872
2873         if (rdev->family == CHIP_RS400 ||
2874             rdev->family == CHIP_RS480) {
2875                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2876                 data = (temp >> 23) & 0x7;
2877                 if (data < 5)
2878                         tcas_ff.full += dfixed_const(data);
2879         }
2880
2881         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2882                 /* on the R300, Tcas is included in Trbs.
2883                  */
2884                 temp = RREG32(RADEON_MEM_CNTL);
2885                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2886                 if (data == 1) {
2887                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2888                                 temp = RREG32(R300_MC_IND_INDEX);
2889                                 temp &= ~R300_MC_IND_ADDR_MASK;
2890                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2891                                 WREG32(R300_MC_IND_INDEX, temp);
2892                                 temp = RREG32(R300_MC_IND_DATA);
2893                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2894                         } else {
2895                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2896                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2897                         }
2898                 } else {
2899                         temp = RREG32(R300_MC_READ_CNTL_AB);
2900                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2901                 }
2902                 if (rdev->family == CHIP_RV410 ||
2903                     rdev->family == CHIP_R420 ||
2904                     rdev->family == CHIP_R423)
2905                         trbs_ff = memtrbs_r4xx[data];
2906                 else
2907                         trbs_ff = memtrbs[data];
2908                 tcas_ff.full += trbs_ff.full;
2909         }
2910
2911         sclk_eff_ff.full = sclk_ff.full;
2912
2913         if (rdev->flags & RADEON_IS_AGP) {
2914                 fixed20_12 agpmode_ff;
2915                 agpmode_ff.full = dfixed_const(radeon_agpmode);
2916                 temp_ff.full = dfixed_const_666(16);
2917                 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
2918         }
2919         /* TODO PCIE lanes may affect this - agpmode == 16?? */
2920
2921         if (ASIC_IS_R300(rdev)) {
2922                 sclk_delay_ff.full = dfixed_const(250);
2923         } else {
2924                 if ((rdev->family == CHIP_RV100) ||
2925                     rdev->flags & RADEON_IS_IGP) {
2926                         if (rdev->mc.vram_is_ddr)
2927                                 sclk_delay_ff.full = dfixed_const(41);
2928                         else
2929                                 sclk_delay_ff.full = dfixed_const(33);
2930                 } else {
2931                         if (rdev->mc.vram_width == 128)
2932                                 sclk_delay_ff.full = dfixed_const(57);
2933                         else
2934                                 sclk_delay_ff.full = dfixed_const(41);
2935                 }
2936         }
2937
2938         mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
2939
2940         if (rdev->mc.vram_is_ddr) {
2941                 if (rdev->mc.vram_width == 32) {
2942                         k1.full = dfixed_const(40);
2943                         c  = 3;
2944                 } else {
2945                         k1.full = dfixed_const(20);
2946                         c  = 1;
2947                 }
2948         } else {
2949                 k1.full = dfixed_const(40);
2950                 c  = 3;
2951         }
2952
2953         temp_ff.full = dfixed_const(2);
2954         mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
2955         temp_ff.full = dfixed_const(c);
2956         mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
2957         temp_ff.full = dfixed_const(4);
2958         mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
2959         mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
2960         mc_latency_mclk.full += k1.full;
2961
2962         mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
2963         mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
2964
2965         /*
2966           HW cursor time assuming worst case of full size colour cursor.
2967         */
2968         temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2969         temp_ff.full += trcd_ff.full;
2970         if (temp_ff.full < tras_ff.full)
2971                 temp_ff.full = tras_ff.full;
2972         cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
2973
2974         temp_ff.full = dfixed_const(cur_size);
2975         cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
2976         /*
2977           Find the total latency for the display data.
2978         */
2979         disp_latency_overhead.full = dfixed_const(8);
2980         disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
2981         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2982         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2983
2984         if (mc_latency_mclk.full > mc_latency_sclk.full)
2985                 disp_latency.full = mc_latency_mclk.full;
2986         else
2987                 disp_latency.full = mc_latency_sclk.full;
2988
2989         /* setup Max GRPH_STOP_REQ default value */
2990         if (ASIC_IS_RV100(rdev))
2991                 max_stop_req = 0x5c;
2992         else
2993                 max_stop_req = 0x7c;
2994
2995         if (mode1) {
2996                 /*  CRTC1
2997                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2998                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2999                 */
3000                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3001
3002                 if (stop_req > max_stop_req)
3003                         stop_req = max_stop_req;
3004
3005                 /*
3006                   Find the drain rate of the display buffer.
3007                 */
3008                 temp_ff.full = dfixed_const((16/pixel_bytes1));
3009                 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3010
3011                 /*
3012                   Find the critical point of the display buffer.
3013                 */
3014                 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3015                 crit_point_ff.full += dfixed_const_half(0);
3016
3017                 critical_point = dfixed_trunc(crit_point_ff);
3018
3019                 if (rdev->disp_priority == 2) {
3020                         critical_point = 0;
3021                 }
3022
3023                 /*
3024                   The critical point should never be above max_stop_req-4.  Setting
3025                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3026                 */
3027                 if (max_stop_req - critical_point < 4)
3028                         critical_point = 0;
3029
3030                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3031                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3032                         critical_point = 0x10;
3033                 }
3034
3035                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3036                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3037                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3038                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3039                 if ((rdev->family == CHIP_R350) &&
3040                     (stop_req > 0x15)) {
3041                         stop_req -= 0x10;
3042                 }
3043                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3044                 temp |= RADEON_GRPH_BUFFER_SIZE;
3045                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3046                           RADEON_GRPH_CRITICAL_AT_SOF |
3047                           RADEON_GRPH_STOP_CNTL);
3048                 /*
3049                   Write the result into the register.
3050                 */
3051                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3052                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3053
3054 #if 0
3055                 if ((rdev->family == CHIP_RS400) ||
3056                     (rdev->family == CHIP_RS480)) {
3057                         /* attempt to program RS400 disp regs correctly ??? */
3058                         temp = RREG32(RS400_DISP1_REG_CNTL);
3059                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3060                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3061                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3062                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3063                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3064                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3065                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3066                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3067                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3068                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3069                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3070                 }
3071 #endif
3072
3073                 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3074                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3075                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3076         }
3077
3078         if (mode2) {
3079                 u32 grph2_cntl;
3080                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3081
3082                 if (stop_req > max_stop_req)
3083                         stop_req = max_stop_req;
3084
3085                 /*
3086                   Find the drain rate of the display buffer.
3087                 */
3088                 temp_ff.full = dfixed_const((16/pixel_bytes2));
3089                 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3090
3091                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3092                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3093                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3094                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3095                 if ((rdev->family == CHIP_R350) &&
3096                     (stop_req > 0x15)) {
3097                         stop_req -= 0x10;
3098                 }
3099                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3100                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3101                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3102                           RADEON_GRPH_CRITICAL_AT_SOF |
3103                           RADEON_GRPH_STOP_CNTL);
3104
3105                 if ((rdev->family == CHIP_RS100) ||
3106                     (rdev->family == CHIP_RS200))
3107                         critical_point2 = 0;
3108                 else {
3109                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3110                         temp_ff.full = dfixed_const(temp);
3111                         temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3112                         if (sclk_ff.full < temp_ff.full)
3113                                 temp_ff.full = sclk_ff.full;
3114
3115                         read_return_rate.full = temp_ff.full;
3116
3117                         if (mode1) {
3118                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3119                                 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3120                         } else {
3121                                 time_disp1_drop_priority.full = 0;
3122                         }
3123                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3124                         crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3125                         crit_point_ff.full += dfixed_const_half(0);
3126
3127                         critical_point2 = dfixed_trunc(crit_point_ff);
3128
3129                         if (rdev->disp_priority == 2) {
3130                                 critical_point2 = 0;
3131                         }
3132
3133                         if (max_stop_req - critical_point2 < 4)
3134                                 critical_point2 = 0;
3135
3136                 }
3137
3138                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3139                         /* some R300 cards have problem with this set to 0 */
3140                         critical_point2 = 0x10;
3141                 }
3142
3143                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3144                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3145
3146                 if ((rdev->family == CHIP_RS400) ||
3147                     (rdev->family == CHIP_RS480)) {
3148 #if 0
3149                         /* attempt to program RS400 disp2 regs correctly ??? */
3150                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3151                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3152                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3153                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3154                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3155                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3156                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3157                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3158                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3159                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3160                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3161                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3162 #endif
3163                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3164                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3165                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3166                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3167                 }
3168
3169                 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3170                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3171         }
3172 }
3173
3174 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3175 {
3176         DRM_ERROR("pitch                      %d\n", t->pitch);
3177         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
3178         DRM_ERROR("width                      %d\n", t->width);
3179         DRM_ERROR("width_11                   %d\n", t->width_11);
3180         DRM_ERROR("height                     %d\n", t->height);
3181         DRM_ERROR("height_11                  %d\n", t->height_11);
3182         DRM_ERROR("num levels                 %d\n", t->num_levels);
3183         DRM_ERROR("depth                      %d\n", t->txdepth);
3184         DRM_ERROR("bpp                        %d\n", t->cpp);
3185         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
3186         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
3187         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3188         DRM_ERROR("compress format            %d\n", t->compress_format);
3189 }
3190
3191 static int r100_track_compress_size(int compress_format, int w, int h)
3192 {
3193         int block_width, block_height, block_bytes;
3194         int wblocks, hblocks;
3195         int min_wblocks;
3196         int sz;
3197
3198         block_width = 4;
3199         block_height = 4;
3200
3201         switch (compress_format) {
3202         case R100_TRACK_COMP_DXT1:
3203                 block_bytes = 8;
3204                 min_wblocks = 4;
3205                 break;
3206         default:
3207         case R100_TRACK_COMP_DXT35:
3208                 block_bytes = 16;
3209                 min_wblocks = 2;
3210                 break;
3211         }
3212
3213         hblocks = (h + block_height - 1) / block_height;
3214         wblocks = (w + block_width - 1) / block_width;
3215         if (wblocks < min_wblocks)
3216                 wblocks = min_wblocks;
3217         sz = wblocks * hblocks * block_bytes;
3218         return sz;
3219 }
3220
3221 static int r100_cs_track_cube(struct radeon_device *rdev,
3222                               struct r100_cs_track *track, unsigned idx)
3223 {
3224         unsigned face, w, h;
3225         struct radeon_bo *cube_robj;
3226         unsigned long size;
3227         unsigned compress_format = track->textures[idx].compress_format;
3228
3229         for (face = 0; face < 5; face++) {
3230                 cube_robj = track->textures[idx].cube_info[face].robj;
3231                 w = track->textures[idx].cube_info[face].width;
3232                 h = track->textures[idx].cube_info[face].height;
3233
3234                 if (compress_format) {
3235                         size = r100_track_compress_size(compress_format, w, h);
3236                 } else
3237                         size = w * h;
3238                 size *= track->textures[idx].cpp;
3239
3240                 size += track->textures[idx].cube_info[face].offset;
3241
3242                 if (size > radeon_bo_size(cube_robj)) {
3243                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3244                                   size, radeon_bo_size(cube_robj));
3245                         r100_cs_track_texture_print(&track->textures[idx]);
3246                         return -1;
3247                 }
3248         }
3249         return 0;
3250 }
3251
3252 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3253                                        struct r100_cs_track *track)
3254 {
3255         struct radeon_bo *robj;
3256         unsigned long size;
3257         unsigned u, i, w, h, d;
3258         int ret;
3259
3260         for (u = 0; u < track->num_texture; u++) {
3261                 if (!track->textures[u].enabled)
3262                         continue;
3263                 if (track->textures[u].lookup_disable)
3264                         continue;
3265                 robj = track->textures[u].robj;
3266                 if (robj == NULL) {
3267                         DRM_ERROR("No texture bound to unit %u\n", u);
3268                         return -EINVAL;
3269                 }
3270                 size = 0;
3271                 for (i = 0; i <= track->textures[u].num_levels; i++) {
3272                         if (track->textures[u].use_pitch) {
3273                                 if (rdev->family < CHIP_R300)
3274                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3275                                 else
3276                                         w = track->textures[u].pitch / (1 << i);
3277                         } else {
3278                                 w = track->textures[u].width;
3279                                 if (rdev->family >= CHIP_RV515)
3280                                         w |= track->textures[u].width_11;
3281                                 w = w / (1 << i);
3282                                 if (track->textures[u].roundup_w)
3283                                         w = roundup_pow_of_two(w);
3284                         }
3285                         h = track->textures[u].height;
3286                         if (rdev->family >= CHIP_RV515)
3287                                 h |= track->textures[u].height_11;
3288                         h = h / (1 << i);
3289                         if (track->textures[u].roundup_h)
3290                                 h = roundup_pow_of_two(h);
3291                         if (track->textures[u].tex_coord_type == 1) {
3292                                 d = (1 << track->textures[u].txdepth) / (1 << i);
3293                                 if (!d)
3294                                         d = 1;
3295                         } else {
3296                                 d = 1;
3297                         }
3298                         if (track->textures[u].compress_format) {
3299
3300                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3301                                 /* compressed textures are block based */
3302                         } else
3303                                 size += w * h * d;
3304                 }
3305                 size *= track->textures[u].cpp;
3306
3307                 switch (track->textures[u].tex_coord_type) {
3308                 case 0:
3309                 case 1:
3310                         break;
3311                 case 2:
3312                         if (track->separate_cube) {
3313                                 ret = r100_cs_track_cube(rdev, track, u);
3314                                 if (ret)
3315                                         return ret;
3316                         } else
3317                                 size *= 6;
3318                         break;
3319                 default:
3320                         DRM_ERROR("Invalid texture coordinate type %u for unit "
3321                                   "%u\n", track->textures[u].tex_coord_type, u);
3322                         return -EINVAL;
3323                 }
3324                 if (size > radeon_bo_size(robj)) {
3325                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3326                                   "%lu\n", u, size, radeon_bo_size(robj));
3327                         r100_cs_track_texture_print(&track->textures[u]);
3328                         return -EINVAL;
3329                 }
3330         }
3331         return 0;
3332 }
3333
3334 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3335 {
3336         unsigned i;
3337         unsigned long size;
3338         unsigned prim_walk;
3339         unsigned nverts;
3340         unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
3341
3342         if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
3343             !track->blend_read_enable)
3344                 num_cb = 0;
3345
3346         for (i = 0; i < num_cb; i++) {
3347                 if (track->cb[i].robj == NULL) {
3348                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3349                         return -EINVAL;
3350                 }
3351                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3352                 size += track->cb[i].offset;
3353                 if (size > radeon_bo_size(track->cb[i].robj)) {
3354                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
3355                                   "(need %lu have %lu) !\n", i, size,
3356                                   radeon_bo_size(track->cb[i].robj));
3357                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3358                                   i, track->cb[i].pitch, track->cb[i].cpp,
3359                                   track->cb[i].offset, track->maxy);
3360                         return -EINVAL;
3361                 }
3362         }
3363         track->cb_dirty = false;
3364
3365         if (track->zb_dirty && track->z_enabled) {
3366                 if (track->zb.robj == NULL) {
3367                         DRM_ERROR("[drm] No buffer for z buffer !\n");
3368                         return -EINVAL;
3369                 }
3370                 size = track->zb.pitch * track->zb.cpp * track->maxy;
3371                 size += track->zb.offset;
3372                 if (size > radeon_bo_size(track->zb.robj)) {
3373                         DRM_ERROR("[drm] Buffer too small for z buffer "
3374                                   "(need %lu have %lu) !\n", size,
3375                                   radeon_bo_size(track->zb.robj));
3376                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3377                                   track->zb.pitch, track->zb.cpp,
3378                                   track->zb.offset, track->maxy);
3379                         return -EINVAL;
3380                 }
3381         }
3382         track->zb_dirty = false;
3383
3384         if (track->aa_dirty && track->aaresolve) {
3385                 if (track->aa.robj == NULL) {
3386                         DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3387                         return -EINVAL;
3388                 }
3389                 /* I believe the format comes from colorbuffer0. */
3390                 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3391                 size += track->aa.offset;
3392                 if (size > radeon_bo_size(track->aa.robj)) {
3393                         DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3394                                   "(need %lu have %lu) !\n", i, size,
3395                                   radeon_bo_size(track->aa.robj));
3396                         DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3397                                   i, track->aa.pitch, track->cb[0].cpp,
3398                                   track->aa.offset, track->maxy);
3399                         return -EINVAL;
3400                 }
3401         }
3402         track->aa_dirty = false;
3403
3404         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3405         if (track->vap_vf_cntl & (1 << 14)) {
3406                 nverts = track->vap_alt_nverts;
3407         } else {
3408                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3409         }
3410         switch (prim_walk) {
3411         case 1:
3412                 for (i = 0; i < track->num_arrays; i++) {
3413                         size = track->arrays[i].esize * track->max_indx * 4;
3414                         if (track->arrays[i].robj == NULL) {
3415                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3416                                           "bound\n", prim_walk, i);
3417                                 return -EINVAL;
3418                         }
3419                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3420                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3421                                         "need %lu dwords have %lu dwords\n",
3422                                         prim_walk, i, size >> 2,
3423                                         radeon_bo_size(track->arrays[i].robj)
3424                                         >> 2);
3425                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3426                                 return -EINVAL;
3427                         }
3428                 }
3429                 break;
3430         case 2:
3431                 for (i = 0; i < track->num_arrays; i++) {
3432                         size = track->arrays[i].esize * (nverts - 1) * 4;
3433                         if (track->arrays[i].robj == NULL) {
3434                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3435                                           "bound\n", prim_walk, i);
3436                                 return -EINVAL;
3437                         }
3438                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3439                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3440                                         "need %lu dwords have %lu dwords\n",
3441                                         prim_walk, i, size >> 2,
3442                                         radeon_bo_size(track->arrays[i].robj)
3443                                         >> 2);
3444                                 return -EINVAL;
3445                         }
3446                 }
3447                 break;
3448         case 3:
3449                 size = track->vtx_size * nverts;
3450                 if (size != track->immd_dwords) {
3451                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3452                                   track->immd_dwords, size);
3453                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3454                                   nverts, track->vtx_size);
3455                         return -EINVAL;
3456                 }
3457                 break;
3458         default:
3459                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3460                           prim_walk);
3461                 return -EINVAL;
3462         }
3463
3464         if (track->tex_dirty) {
3465                 track->tex_dirty = false;
3466                 return r100_cs_track_texture_check(rdev, track);
3467         }
3468         return 0;
3469 }
3470
3471 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3472 {
3473         unsigned i, face;
3474
3475         track->cb_dirty = true;
3476         track->zb_dirty = true;
3477         track->tex_dirty = true;
3478         track->aa_dirty = true;
3479
3480         if (rdev->family < CHIP_R300) {
3481                 track->num_cb = 1;
3482                 if (rdev->family <= CHIP_RS200)
3483                         track->num_texture = 3;
3484                 else
3485                         track->num_texture = 6;
3486                 track->maxy = 2048;
3487                 track->separate_cube = 1;
3488         } else {
3489                 track->num_cb = 4;
3490                 track->num_texture = 16;
3491                 track->maxy = 4096;
3492                 track->separate_cube = 0;
3493                 track->aaresolve = false;
3494                 track->aa.robj = NULL;
3495         }
3496
3497         for (i = 0; i < track->num_cb; i++) {
3498                 track->cb[i].robj = NULL;
3499                 track->cb[i].pitch = 8192;
3500                 track->cb[i].cpp = 16;
3501                 track->cb[i].offset = 0;
3502         }
3503         track->z_enabled = true;
3504         track->zb.robj = NULL;
3505         track->zb.pitch = 8192;
3506         track->zb.cpp = 4;
3507         track->zb.offset = 0;
3508         track->vtx_size = 0x7F;
3509         track->immd_dwords = 0xFFFFFFFFUL;
3510         track->num_arrays = 11;
3511         track->max_indx = 0x00FFFFFFUL;
3512         for (i = 0; i < track->num_arrays; i++) {
3513                 track->arrays[i].robj = NULL;
3514                 track->arrays[i].esize = 0x7F;
3515         }
3516         for (i = 0; i < track->num_texture; i++) {
3517                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3518                 track->textures[i].pitch = 16536;
3519                 track->textures[i].width = 16536;
3520                 track->textures[i].height = 16536;
3521                 track->textures[i].width_11 = 1 << 11;
3522                 track->textures[i].height_11 = 1 << 11;
3523                 track->textures[i].num_levels = 12;
3524                 if (rdev->family <= CHIP_RS200) {
3525                         track->textures[i].tex_coord_type = 0;
3526                         track->textures[i].txdepth = 0;
3527                 } else {
3528                         track->textures[i].txdepth = 16;
3529                         track->textures[i].tex_coord_type = 1;
3530                 }
3531                 track->textures[i].cpp = 64;
3532                 track->textures[i].robj = NULL;
3533                 /* CS IB emission code makes sure texture unit are disabled */
3534                 track->textures[i].enabled = false;
3535                 track->textures[i].lookup_disable = false;
3536                 track->textures[i].roundup_w = true;
3537                 track->textures[i].roundup_h = true;
3538                 if (track->separate_cube)
3539                         for (face = 0; face < 5; face++) {
3540                                 track->textures[i].cube_info[face].robj = NULL;
3541                                 track->textures[i].cube_info[face].width = 16536;
3542                                 track->textures[i].cube_info[face].height = 16536;
3543                                 track->textures[i].cube_info[face].offset = 0;
3544                         }
3545         }
3546 }
3547
3548 int r100_ring_test(struct radeon_device *rdev)
3549 {
3550         uint32_t scratch;
3551         uint32_t tmp = 0;
3552         unsigned i;
3553         int r;
3554
3555         r = radeon_scratch_get(rdev, &scratch);
3556         if (r) {
3557                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3558                 return r;
3559         }
3560         WREG32(scratch, 0xCAFEDEAD);
3561         r = radeon_ring_lock(rdev, 2);
3562         if (r) {
3563                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3564                 radeon_scratch_free(rdev, scratch);
3565                 return r;
3566         }
3567         radeon_ring_write(rdev, PACKET0(scratch, 0));
3568         radeon_ring_write(rdev, 0xDEADBEEF);
3569         radeon_ring_unlock_commit(rdev);
3570         for (i = 0; i < rdev->usec_timeout; i++) {
3571                 tmp = RREG32(scratch);
3572                 if (tmp == 0xDEADBEEF) {
3573                         break;
3574                 }
3575                 DRM_UDELAY(1);
3576         }
3577         if (i < rdev->usec_timeout) {
3578                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3579         } else {
3580                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3581                           scratch, tmp);
3582                 r = -EINVAL;
3583         }
3584         radeon_scratch_free(rdev, scratch);
3585         return r;
3586 }
3587
3588 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3589 {
3590         radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3591         radeon_ring_write(rdev, ib->gpu_addr);
3592         radeon_ring_write(rdev, ib->length_dw);
3593 }
3594
3595 int r100_ib_test(struct radeon_device *rdev)
3596 {
3597         struct radeon_ib *ib;
3598         uint32_t scratch;
3599         uint32_t tmp = 0;
3600         unsigned i;
3601         int r;
3602
3603         r = radeon_scratch_get(rdev, &scratch);
3604         if (r) {
3605                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3606                 return r;
3607         }
3608         WREG32(scratch, 0xCAFEDEAD);
3609         r = radeon_ib_get(rdev, &ib);
3610         if (r) {
3611                 return r;
3612         }
3613         ib->ptr[0] = PACKET0(scratch, 0);
3614         ib->ptr[1] = 0xDEADBEEF;
3615         ib->ptr[2] = PACKET2(0);
3616         ib->ptr[3] = PACKET2(0);
3617         ib->ptr[4] = PACKET2(0);
3618         ib->ptr[5] = PACKET2(0);
3619         ib->ptr[6] = PACKET2(0);
3620         ib->ptr[7] = PACKET2(0);
3621         ib->length_dw = 8;
3622         r = radeon_ib_schedule(rdev, ib);
3623         if (r) {
3624                 radeon_scratch_free(rdev, scratch);
3625                 radeon_ib_free(rdev, &ib);
3626                 return r;
3627         }
3628         r = radeon_fence_wait(ib->fence, false);
3629         if (r) {
3630                 return r;
3631         }
3632         for (i = 0; i < rdev->usec_timeout; i++) {
3633                 tmp = RREG32(scratch);
3634                 if (tmp == 0xDEADBEEF) {
3635                         break;
3636                 }
3637                 DRM_UDELAY(1);
3638         }
3639         if (i < rdev->usec_timeout) {
3640                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3641         } else {
3642                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3643                           scratch, tmp);
3644                 r = -EINVAL;
3645         }
3646         radeon_scratch_free(rdev, scratch);
3647         radeon_ib_free(rdev, &ib);
3648         return r;
3649 }
3650
3651 void r100_ib_fini(struct radeon_device *rdev)
3652 {
3653         radeon_ib_pool_fini(rdev);
3654 }
3655
3656 int r100_ib_init(struct radeon_device *rdev)
3657 {
3658         int r;
3659
3660         r = radeon_ib_pool_init(rdev);
3661         if (r) {
3662                 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3663                 r100_ib_fini(rdev);
3664                 return r;
3665         }
3666         r = r100_ib_test(rdev);
3667         if (r) {
3668                 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3669                 r100_ib_fini(rdev);
3670                 return r;
3671         }
3672         return 0;
3673 }
3674
3675 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3676 {
3677         /* Shutdown CP we shouldn't need to do that but better be safe than
3678          * sorry
3679          */
3680         rdev->cp.ready = false;
3681         WREG32(R_000740_CP_CSQ_CNTL, 0);
3682
3683         /* Save few CRTC registers */
3684         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3685         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3686         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3687         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3688         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3689                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3690                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3691         }
3692
3693         /* Disable VGA aperture access */
3694         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3695         /* Disable cursor, overlay, crtc */
3696         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3697         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3698                                         S_000054_CRTC_DISPLAY_DIS(1));
3699         WREG32(R_000050_CRTC_GEN_CNTL,
3700                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3701                         S_000050_CRTC_DISP_REQ_EN_B(1));
3702         WREG32(R_000420_OV0_SCALE_CNTL,
3703                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3704         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3705         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3706                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3707                                                 S_000360_CUR2_LOCK(1));
3708                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3709                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3710                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3711                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3712                 WREG32(R_000360_CUR2_OFFSET,
3713                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3714         }
3715 }
3716
3717 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3718 {
3719         /* Update base address for crtc */
3720         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3721         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3722                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3723         }
3724         /* Restore CRTC registers */
3725         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3726         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3727         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3728         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3729                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3730         }
3731 }
3732
3733 void r100_vga_render_disable(struct radeon_device *rdev)
3734 {
3735         u32 tmp;
3736
3737         tmp = RREG8(R_0003C2_GENMO_WT);
3738         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3739 }
3740
3741 static void r100_debugfs(struct radeon_device *rdev)
3742 {
3743         int r;
3744
3745         r = r100_debugfs_mc_info_init(rdev);
3746         if (r)
3747                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3748 }
3749
3750 static void r100_mc_program(struct radeon_device *rdev)
3751 {
3752         struct r100_mc_save save;
3753
3754         /* Stops all mc clients */
3755         r100_mc_stop(rdev, &save);
3756         if (rdev->flags & RADEON_IS_AGP) {
3757                 WREG32(R_00014C_MC_AGP_LOCATION,
3758                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3759                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3760                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3761                 if (rdev->family > CHIP_RV200)
3762                         WREG32(R_00015C_AGP_BASE_2,
3763                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3764         } else {
3765                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3766                 WREG32(R_000170_AGP_BASE, 0);
3767                 if (rdev->family > CHIP_RV200)
3768                         WREG32(R_00015C_AGP_BASE_2, 0);
3769         }
3770         /* Wait for mc idle */
3771         if (r100_mc_wait_for_idle(rdev))
3772                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3773         /* Program MC, should be a 32bits limited address space */
3774         WREG32(R_000148_MC_FB_LOCATION,
3775                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3776                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3777         r100_mc_resume(rdev, &save);
3778 }
3779
3780 void r100_clock_startup(struct radeon_device *rdev)
3781 {
3782         u32 tmp;
3783
3784         if (radeon_dynclks != -1 && radeon_dynclks)
3785                 radeon_legacy_set_clock_gating(rdev, 1);
3786         /* We need to force on some of the block */
3787         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3788         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3789         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3790                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3791         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3792 }
3793
3794 static int r100_startup(struct radeon_device *rdev)
3795 {
3796         int r;
3797
3798         /* set common regs */
3799         r100_set_common_regs(rdev);
3800         /* program mc */
3801         r100_mc_program(rdev);
3802         /* Resume clock */
3803         r100_clock_startup(rdev);
3804         /* Initialize GART (initialize after TTM so we can allocate
3805          * memory through TTM but finalize after TTM) */
3806         r100_enable_bm(rdev);
3807         if (rdev->flags & RADEON_IS_PCI) {
3808                 r = r100_pci_gart_enable(rdev);
3809                 if (r)
3810                         return r;
3811         }
3812
3813         /* allocate wb buffer */
3814         r = radeon_wb_init(rdev);
3815         if (r)
3816                 return r;
3817
3818         /* Enable IRQ */
3819         r100_irq_set(rdev);
3820         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3821         /* 1M ring buffer */
3822         r = r100_cp_init(rdev, 1024 * 1024);
3823         if (r) {
3824                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3825                 return r;
3826         }
3827         r = r100_ib_init(rdev);
3828         if (r) {
3829                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3830                 return r;
3831         }
3832         return 0;
3833 }
3834
3835 int r100_resume(struct radeon_device *rdev)
3836 {
3837         /* Make sur GART are not working */
3838         if (rdev->flags & RADEON_IS_PCI)
3839                 r100_pci_gart_disable(rdev);
3840         /* Resume clock before doing reset */
3841         r100_clock_startup(rdev);
3842         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3843         if (radeon_asic_reset(rdev)) {
3844                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3845                         RREG32(R_000E40_RBBM_STATUS),
3846                         RREG32(R_0007C0_CP_STAT));
3847         }
3848         /* post */
3849         radeon_combios_asic_init(rdev->ddev);
3850         /* Resume clock after posting */
3851         r100_clock_startup(rdev);
3852         /* Initialize surface registers */
3853         radeon_surface_init(rdev);
3854         return r100_startup(rdev);
3855 }
3856
3857 int r100_suspend(struct radeon_device *rdev)
3858 {
3859         r100_cp_disable(rdev);
3860         radeon_wb_disable(rdev);
3861         r100_irq_disable(rdev);
3862         if (rdev->flags & RADEON_IS_PCI)
3863                 r100_pci_gart_disable(rdev);
3864         return 0;
3865 }
3866
3867 void r100_fini(struct radeon_device *rdev)
3868 {
3869         r100_cp_fini(rdev);
3870         radeon_wb_fini(rdev);
3871         r100_ib_fini(rdev);
3872         radeon_gem_fini(rdev);
3873         if (rdev->flags & RADEON_IS_PCI)
3874                 r100_pci_gart_fini(rdev);
3875         radeon_agp_fini(rdev);
3876         radeon_irq_kms_fini(rdev);
3877         radeon_fence_driver_fini(rdev);
3878         radeon_bo_fini(rdev);
3879         radeon_atombios_fini(rdev);
3880         kfree(rdev->bios);
3881         rdev->bios = NULL;
3882 }
3883
3884 /*
3885  * Due to how kexec works, it can leave the hw fully initialised when it
3886  * boots the new kernel. However doing our init sequence with the CP and
3887  * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3888  * do some quick sanity checks and restore sane values to avoid this
3889  * problem.
3890  */
3891 void r100_restore_sanity(struct radeon_device *rdev)
3892 {
3893         u32 tmp;
3894
3895         tmp = RREG32(RADEON_CP_CSQ_CNTL);
3896         if (tmp) {
3897                 WREG32(RADEON_CP_CSQ_CNTL, 0);
3898         }
3899         tmp = RREG32(RADEON_CP_RB_CNTL);
3900         if (tmp) {
3901                 WREG32(RADEON_CP_RB_CNTL, 0);
3902         }
3903         tmp = RREG32(RADEON_SCRATCH_UMSK);
3904         if (tmp) {
3905                 WREG32(RADEON_SCRATCH_UMSK, 0);
3906         }
3907 }
3908
3909 int r100_init(struct radeon_device *rdev)
3910 {
3911         int r;
3912
3913         /* Register debugfs file specific to this group of asics */
3914         r100_debugfs(rdev);
3915         /* Disable VGA */
3916         r100_vga_render_disable(rdev);
3917         /* Initialize scratch registers */
3918         radeon_scratch_init(rdev);
3919         /* Initialize surface registers */
3920         radeon_surface_init(rdev);
3921         /* sanity check some register to avoid hangs like after kexec */
3922         r100_restore_sanity(rdev);
3923         /* TODO: disable VGA need to use VGA request */
3924         /* BIOS*/
3925         if (!radeon_get_bios(rdev)) {
3926                 if (ASIC_IS_AVIVO(rdev))
3927                         return -EINVAL;
3928         }
3929         if (rdev->is_atom_bios) {
3930                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3931                 return -EINVAL;
3932         } else {
3933                 r = radeon_combios_init(rdev);
3934                 if (r)
3935                         return r;
3936         }
3937         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3938         if (radeon_asic_reset(rdev)) {
3939                 dev_warn(rdev->dev,
3940                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3941                         RREG32(R_000E40_RBBM_STATUS),
3942                         RREG32(R_0007C0_CP_STAT));
3943         }
3944         /* check if cards are posted or not */
3945         if (radeon_boot_test_post_card(rdev) == false)
3946                 return -EINVAL;
3947         /* Set asic errata */
3948         r100_errata(rdev);
3949         /* Initialize clocks */
3950         radeon_get_clock_info(rdev->ddev);
3951         /* initialize AGP */
3952         if (rdev->flags & RADEON_IS_AGP) {
3953                 r = radeon_agp_init(rdev);
3954                 if (r) {
3955                         radeon_agp_disable(rdev);
3956                 }
3957         }
3958         /* initialize VRAM */
3959         r100_mc_init(rdev);
3960         /* Fence driver */
3961         r = radeon_fence_driver_init(rdev);
3962         if (r)
3963                 return r;
3964         r = radeon_irq_kms_init(rdev);
3965         if (r)
3966                 return r;
3967         /* Memory manager */
3968         r = radeon_bo_init(rdev);
3969         if (r)
3970                 return r;
3971         if (rdev->flags & RADEON_IS_PCI) {
3972                 r = r100_pci_gart_init(rdev);
3973                 if (r)
3974                         return r;
3975         }
3976         r100_set_safe_registers(rdev);
3977         rdev->accel_working = true;
3978         r = r100_startup(rdev);
3979         if (r) {
3980                 /* Somethings want wront with the accel init stop accel */
3981                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3982                 r100_cp_fini(rdev);
3983                 radeon_wb_fini(rdev);
3984                 r100_ib_fini(rdev);
3985                 radeon_irq_kms_fini(rdev);
3986                 if (rdev->flags & RADEON_IS_PCI)
3987                         r100_pci_gart_fini(rdev);
3988                 rdev->accel_working = false;
3989         }
3990         return 0;
3991 }