drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "radeon_drm.h"
  32 #include "radeon_reg.h"
  33 #include "radeon.h"
  34 #include "radeon_asic.h"
  35 #include "r100d.h"
  36 #include "rs100d.h"
  37 #include "rv200d.h"
  38 #include "rv250d.h"
  39
  40 #include <linux/firmware.h>
  41 #include <linux/platform_device.h>
  42
  43 #include "r100_reg_safe.h"
  44 #include "rn50_reg_safe.h"
  45
  46 /* Firmware Names */
  47 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  48 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  49 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  50 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  51 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  52 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  53 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  54
  55 MODULE_FIRMWARE(FIRMWARE_R100);
  56 MODULE_FIRMWARE(FIRMWARE_R200);
  57 MODULE_FIRMWARE(FIRMWARE_R300);
  58 MODULE_FIRMWARE(FIRMWARE_R420);
  59 MODULE_FIRMWARE(FIRMWARE_RS690);
  60 MODULE_FIRMWARE(FIRMWARE_RS600);
  61 MODULE_FIRMWARE(FIRMWARE_R520);
  62
  63 #include "r100_track.h"
  64
  65 /* This files gather functions specifics to:
  66  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  67  */
  68
  69 /* hpd for digital panel detect/disconnect */
  70 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  71 {
  72         bool connected = false;
  73
  74         switch (hpd) {
  75         case RADEON_HPD_1:
  76                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
  77                         connected = true;
  78                 break;
  79         case RADEON_HPD_2:
  80                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
  81                         connected = true;
  82                 break;
  83         default:
  84                 break;
  85         }
  86         return connected;
  87 }
  88
  89 void r100_hpd_set_polarity(struct radeon_device *rdev,
  90                            enum radeon_hpd_id hpd)
  91 {
  92         u32 tmp;
  93         bool connected = r100_hpd_sense(rdev, hpd);
  94
  95         switch (hpd) {
  96         case RADEON_HPD_1:
  97                 tmp = RREG32(RADEON_FP_GEN_CNTL);
  98                 if (connected)
  99                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 100                 else
 101                         tmp |= RADEON_FP_DETECT_INT_POL;
 102                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 103                 break;
 104         case RADEON_HPD_2:
 105                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 106                 if (connected)
 107                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 108                 else
 109                         tmp |= RADEON_FP2_DETECT_INT_POL;
 110                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 111                 break;
 112         default:
 113                 break;
 114         }
 115 }
 116
 117 void r100_hpd_init(struct radeon_device *rdev)
 118 {
 119         struct drm_device *dev = rdev->ddev;
 120         struct drm_connector *connector;
 121
 122         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 123                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 124                 switch (radeon_connector->hpd.hpd) {
 125                 case RADEON_HPD_1:
 126                         rdev->irq.hpd[0] = true;
 127                         break;
 128                 case RADEON_HPD_2:
 129                         rdev->irq.hpd[1] = true;
 130                         break;
 131                 default:
 132                         break;
 133                 }
 134         }
 135         if (rdev->irq.installed)
 136                 r100_irq_set(rdev);
 137 }
 138
 139 void r100_hpd_fini(struct radeon_device *rdev)
 140 {
 141         struct drm_device *dev = rdev->ddev;
 142         struct drm_connector *connector;
 143
 144         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 145                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 146                 switch (radeon_connector->hpd.hpd) {
 147                 case RADEON_HPD_1:
 148                         rdev->irq.hpd[0] = false;
 149                         break;
 150                 case RADEON_HPD_2:
 151                         rdev->irq.hpd[1] = false;
 152                         break;
 153                 default:
 154                         break;
 155                 }
 156         }
 157 }
 158
 159 /*
 160  * PCI GART
 161  */
 162 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 163 {
 164         /* TODO: can we do somethings here ? */
 165         /* It seems hw only cache one entry so we should discard this
 166          * entry otherwise if first GPU GART read hit this entry it
 167          * could end up in wrong address. */
 168 }
 169
 170 int r100_pci_gart_init(struct radeon_device *rdev)
 171 {
 172         int r;
 173
 174         if (rdev->gart.table.ram.ptr) {
 175                 WARN(1, "R100 PCI GART already initialized.\n");
 176                 return 0;
 177         }
 178         /* Initialize common gart structure */
 179         r = radeon_gart_init(rdev);
 180         if (r)
 181                 return r;
 182         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 183         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 184         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 185         return radeon_gart_table_ram_alloc(rdev);
 186 }
 187
 188 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 189 void r100_enable_bm(struct radeon_device *rdev)
 190 {
 191         uint32_t tmp;
 192         /* Enable bus mastering */
 193         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 194         WREG32(RADEON_BUS_CNTL, tmp);
 195 }
 196
 197 int r100_pci_gart_enable(struct radeon_device *rdev)
 198 {
 199         uint32_t tmp;
 200
 201         radeon_gart_restore(rdev);
 202         /* discard memory request outside of configured range */
 203         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 204         WREG32(RADEON_AIC_CNTL, tmp);
 205         /* set address range for PCI address translate */
 206         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 207         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 208         /* set PCI GART page-table base address */
 209         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 210         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 211         WREG32(RADEON_AIC_CNTL, tmp);
 212         r100_pci_gart_tlb_flush(rdev);
 213         rdev->gart.ready = true;
 214         return 0;
 215 }
 216
 217 void r100_pci_gart_disable(struct radeon_device *rdev)
 218 {
 219         uint32_t tmp;
 220
 221         /* discard memory request outside of configured range */
 222         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 223         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 224         WREG32(RADEON_AIC_LO_ADDR, 0);
 225         WREG32(RADEON_AIC_HI_ADDR, 0);
 226 }
 227
 228 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 229 {
 230         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 231                 return -EINVAL;
 232         }
 233         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
 234         return 0;
 235 }
 236
 237 void r100_pci_gart_fini(struct radeon_device *rdev)
 238 {
 239         radeon_gart_fini(rdev);
 240         r100_pci_gart_disable(rdev);
 241         radeon_gart_table_ram_free(rdev);
 242 }
 243
 244 int r100_irq_set(struct radeon_device *rdev)
 245 {
 246         uint32_t tmp = 0;
 247
 248         if (!rdev->irq.installed) {
 249                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
 250                 WREG32(R_000040_GEN_INT_CNTL, 0);
 251                 return -EINVAL;
 252         }
 253         if (rdev->irq.sw_int) {
 254                 tmp |= RADEON_SW_INT_ENABLE;
 255         }
 256         if (rdev->irq.crtc_vblank_int[0]) {
 257                 tmp |= RADEON_CRTC_VBLANK_MASK;
 258         }
 259         if (rdev->irq.crtc_vblank_int[1]) {
 260                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 261         }
 262         if (rdev->irq.hpd[0]) {
 263                 tmp |= RADEON_FP_DETECT_MASK;
 264         }
 265         if (rdev->irq.hpd[1]) {
 266                 tmp |= RADEON_FP2_DETECT_MASK;
 267         }
 268         WREG32(RADEON_GEN_INT_CNTL, tmp);
 269         return 0;
 270 }
 271
 272 void r100_irq_disable(struct radeon_device *rdev)
 273 {
 274         u32 tmp;
 275
 276         WREG32(R_000040_GEN_INT_CNTL, 0);
 277         /* Wait and acknowledge irq */
 278         mdelay(1);
 279         tmp = RREG32(R_000044_GEN_INT_STATUS);
 280         WREG32(R_000044_GEN_INT_STATUS, tmp);
 281 }
 282
 283 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
 284 {
 285         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 286         uint32_t irq_mask = RADEON_SW_INT_TEST |
 287                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 288                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 289
 290         if (irqs) {
 291                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 292         }
 293         return irqs & irq_mask;
 294 }
 295
 296 int r100_irq_process(struct radeon_device *rdev)
 297 {
 298         uint32_t status, msi_rearm;
 299         bool queue_hotplug = false;
 300
 301         status = r100_irq_ack(rdev);
 302         if (!status) {
 303                 return IRQ_NONE;
 304         }
 305         if (rdev->shutdown) {
 306                 return IRQ_NONE;
 307         }
 308         while (status) {
 309                 /* SW interrupt */
 310                 if (status & RADEON_SW_INT_TEST) {
 311                         radeon_fence_process(rdev);
 312                 }
 313                 /* Vertical blank interrupts */
 314                 if (status & RADEON_CRTC_VBLANK_STAT) {
 315                         drm_handle_vblank(rdev->ddev, 0);
 316                         rdev->pm.vblank_sync = true;
 317                         wake_up(&rdev->irq.vblank_queue);
 318                 }
 319                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 320                         drm_handle_vblank(rdev->ddev, 1);
 321                         rdev->pm.vblank_sync = true;
 322                         wake_up(&rdev->irq.vblank_queue);
 323                 }
 324                 if (status & RADEON_FP_DETECT_STAT) {
 325                         queue_hotplug = true;
 326                         DRM_DEBUG("HPD1\n");
 327                 }
 328                 if (status & RADEON_FP2_DETECT_STAT) {
 329                         queue_hotplug = true;
 330                         DRM_DEBUG("HPD2\n");
 331                 }
 332                 status = r100_irq_ack(rdev);
 333         }
 334         if (queue_hotplug)
 335                 queue_work(rdev->wq, &rdev->hotplug_work);
 336         if (rdev->msi_enabled) {
 337                 switch (rdev->family) {
 338                 case CHIP_RS400:
 339                 case CHIP_RS480:
 340                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 341                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 342                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 343                         break;
 344                 default:
 345                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 346                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 347                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 348                         break;
 349                 }
 350         }
 351         return IRQ_HANDLED;
 352 }
 353
 354 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 355 {
 356         if (crtc == 0)
 357                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 358         else
 359                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 360 }
 361
 362 /* Who ever call radeon_fence_emit should call ring_lock and ask
 363  * for enough space (today caller are ib schedule and buffer move) */
 364 void r100_fence_ring_emit(struct radeon_device *rdev,
 365                           struct radeon_fence *fence)
 366 {
 367         /* We have to make sure that caches are flushed before
 368          * CPU might read something from VRAM. */
 369         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 370         radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
 371         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 372         radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
 373         /* Wait until IDLE & CLEAN */
 374         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 375         radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 376         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 377         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
 378                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 379         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 380         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
 381         /* Emit fence sequence & fire IRQ */
 382         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 383         radeon_ring_write(rdev, fence->seq);
 384         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 385         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 386 }
 387
 388 int r100_wb_init(struct radeon_device *rdev)
 389 {
 390         int r;
 391
 392         if (rdev->wb.wb_obj == NULL) {
 393                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
 394                                         RADEON_GEM_DOMAIN_GTT,
 395                                         &rdev->wb.wb_obj);
 396                 if (r) {
 397                         dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
 398                         return r;
 399                 }
 400                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 401                 if (unlikely(r != 0))
 402                         return r;
 403                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
 404                                         &rdev->wb.gpu_addr);
 405                 if (r) {
 406                         dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
 407                         radeon_bo_unreserve(rdev->wb.wb_obj);
 408                         return r;
 409                 }
 410                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 411                 radeon_bo_unreserve(rdev->wb.wb_obj);
 412                 if (r) {
 413                         dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
 414                         return r;
 415                 }
 416         }
 417         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
 418         WREG32(R_00070C_CP_RB_RPTR_ADDR,
 419                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
 420         WREG32(R_000770_SCRATCH_UMSK, 0xff);
 421         return 0;
 422 }
 423
 424 void r100_wb_disable(struct radeon_device *rdev)
 425 {
 426         WREG32(R_000770_SCRATCH_UMSK, 0);
 427 }
 428
 429 void r100_wb_fini(struct radeon_device *rdev)
 430 {
 431         int r;
 432
 433         r100_wb_disable(rdev);
 434         if (rdev->wb.wb_obj) {
 435                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 436                 if (unlikely(r != 0)) {
 437                         dev_err(rdev->dev, "(%d) can't finish WB\n", r);
 438                         return;
 439                 }
 440                 radeon_bo_kunmap(rdev->wb.wb_obj);
 441                 radeon_bo_unpin(rdev->wb.wb_obj);
 442                 radeon_bo_unreserve(rdev->wb.wb_obj);
 443                 radeon_bo_unref(&rdev->wb.wb_obj);
 444                 rdev->wb.wb = NULL;
 445                 rdev->wb.wb_obj = NULL;
 446         }
 447 }
 448
 449 int r100_copy_blit(struct radeon_device *rdev,
 450                    uint64_t src_offset,
 451                    uint64_t dst_offset,
 452                    unsigned num_pages,
 453                    struct radeon_fence *fence)
 454 {
 455         uint32_t cur_pages;
 456         uint32_t stride_bytes = PAGE_SIZE;
 457         uint32_t pitch;
 458         uint32_t stride_pixels;
 459         unsigned ndw;
 460         int num_loops;
 461         int r = 0;
 462
 463         /* radeon limited to 16k stride */
 464         stride_bytes &= 0x3fff;
 465         /* radeon pitch is /64 */
 466         pitch = stride_bytes / 64;
 467         stride_pixels = stride_bytes / 4;
 468         num_loops = DIV_ROUND_UP(num_pages, 8191);
 469
 470         /* Ask for enough room for blit + flush + fence */
 471         ndw = 64 + (10 * num_loops);
 472         r = radeon_ring_lock(rdev, ndw);
 473         if (r) {
 474                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 475                 return -EINVAL;
 476         }
 477         while (num_pages > 0) {
 478                 cur_pages = num_pages;
 479                 if (cur_pages > 8191) {
 480                         cur_pages = 8191;
 481                 }
 482                 num_pages -= cur_pages;
 483
 484                 /* pages are in Y direction - height
 485                    page width in X direction - width */
 486                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 487                 radeon_ring_write(rdev,
 488                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 489                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 490                                   RADEON_GMC_SRC_CLIPPING |
 491                                   RADEON_GMC_DST_CLIPPING |
 492                                   RADEON_GMC_BRUSH_NONE |
 493                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 494                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 495                                   RADEON_ROP3_S |
 496                                   RADEON_DP_SRC_SOURCE_MEMORY |
 497                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 498                                   RADEON_GMC_WR_MSK_DIS);
 499                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 500                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 501                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 502                 radeon_ring_write(rdev, 0);
 503                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 504                 radeon_ring_write(rdev, num_pages);
 505                 radeon_ring_write(rdev, num_pages);
 506                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 507         }
 508         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 509         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 510         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 511         radeon_ring_write(rdev,
 512                           RADEON_WAIT_2D_IDLECLEAN |
 513                           RADEON_WAIT_HOST_IDLECLEAN |
 514                           RADEON_WAIT_DMA_GUI_IDLE);
 515         if (fence) {
 516                 r = radeon_fence_emit(rdev, fence);
 517         }
 518         radeon_ring_unlock_commit(rdev);
 519         return r;
 520 }
 521
 522 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 523 {
 524         unsigned i;
 525         u32 tmp;
 526
 527         for (i = 0; i < rdev->usec_timeout; i++) {
 528                 tmp = RREG32(R_000E40_RBBM_STATUS);
 529                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 530                         return 0;
 531                 }
 532                 udelay(1);
 533         }
 534         return -1;
 535 }
 536
 537 void r100_ring_start(struct radeon_device *rdev)
 538 {
 539         int r;
 540
 541         r = radeon_ring_lock(rdev, 2);
 542         if (r) {
 543                 return;
 544         }
 545         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 546         radeon_ring_write(rdev,
 547                           RADEON_ISYNC_ANY2D_IDLE3D |
 548                           RADEON_ISYNC_ANY3D_IDLE2D |
 549                           RADEON_ISYNC_WAIT_IDLEGUI |
 550                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 551         radeon_ring_unlock_commit(rdev);
 552 }
 553
 554
 555 /* Load the microcode for the CP */
 556 static int r100_cp_init_microcode(struct radeon_device *rdev)
 557 {
 558         struct platform_device *pdev;
 559         const char *fw_name = NULL;
 560         int err;
 561
 562         DRM_DEBUG("\n");
 563
 564         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 565         err = IS_ERR(pdev);
 566         if (err) {
 567                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 568                 return -EINVAL;
 569         }
 570         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 571             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 572             (rdev->family == CHIP_RS200)) {
 573                 DRM_INFO("Loading R100 Microcode\n");
 574                 fw_name = FIRMWARE_R100;
 575         } else if ((rdev->family == CHIP_R200) ||
 576                    (rdev->family == CHIP_RV250) ||
 577                    (rdev->family == CHIP_RV280) ||
 578                    (rdev->family == CHIP_RS300)) {
 579                 DRM_INFO("Loading R200 Microcode\n");
 580                 fw_name = FIRMWARE_R200;
 581         } else if ((rdev->family == CHIP_R300) ||
 582                    (rdev->family == CHIP_R350) ||
 583                    (rdev->family == CHIP_RV350) ||
 584                    (rdev->family == CHIP_RV380) ||
 585                    (rdev->family == CHIP_RS400) ||
 586                    (rdev->family == CHIP_RS480)) {
 587                 DRM_INFO("Loading R300 Microcode\n");
 588                 fw_name = FIRMWARE_R300;
 589         } else if ((rdev->family == CHIP_R420) ||
 590                    (rdev->family == CHIP_R423) ||
 591                    (rdev->family == CHIP_RV410)) {
 592                 DRM_INFO("Loading R400 Microcode\n");
 593                 fw_name = FIRMWARE_R420;
 594         } else if ((rdev->family == CHIP_RS690) ||
 595                    (rdev->family == CHIP_RS740)) {
 596                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 597                 fw_name = FIRMWARE_RS690;
 598         } else if (rdev->family == CHIP_RS600) {
 599                 DRM_INFO("Loading RS600 Microcode\n");
 600                 fw_name = FIRMWARE_RS600;
 601         } else if ((rdev->family == CHIP_RV515) ||
 602                    (rdev->family == CHIP_R520) ||
 603                    (rdev->family == CHIP_RV530) ||
 604                    (rdev->family == CHIP_R580) ||
 605                    (rdev->family == CHIP_RV560) ||
 606                    (rdev->family == CHIP_RV570)) {
 607                 DRM_INFO("Loading R500 Microcode\n");
 608                 fw_name = FIRMWARE_R520;
 609         }
 610
 611         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 612         platform_device_unregister(pdev);
 613         if (err) {
 614                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 615                        fw_name);
 616         } else if (rdev->me_fw->size % 8) {
 617                 printk(KERN_ERR
 618                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 619                        rdev->me_fw->size, fw_name);
 620                 err = -EINVAL;
 621                 release_firmware(rdev->me_fw);
 622                 rdev->me_fw = NULL;
 623         }
 624         return err;
 625 }
 626
 627 static void r100_cp_load_microcode(struct radeon_device *rdev)
 628 {
 629         const __be32 *fw_data;
 630         int i, size;
 631
 632         if (r100_gui_wait_for_idle(rdev)) {
 633                 printk(KERN_WARNING "Failed to wait GUI idle while "
 634                        "programming pipes. Bad things might happen.\n");
 635         }
 636
 637         if (rdev->me_fw) {
 638                 size = rdev->me_fw->size / 4;
 639                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
 640                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 641                 for (i = 0; i < size; i += 2) {
 642                         WREG32(RADEON_CP_ME_RAM_DATAH,
 643                                be32_to_cpup(&fw_data[i]));
 644                         WREG32(RADEON_CP_ME_RAM_DATAL,
 645                                be32_to_cpup(&fw_data[i + 1]));
 646                 }
 647         }
 648 }
 649
 650 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 651 {
 652         unsigned rb_bufsz;
 653         unsigned rb_blksz;
 654         unsigned max_fetch;
 655         unsigned pre_write_timer;
 656         unsigned pre_write_limit;
 657         unsigned indirect2_start;
 658         unsigned indirect1_start;
 659         uint32_t tmp;
 660         int r;
 661
 662         if (r100_debugfs_cp_init(rdev)) {
 663                 DRM_ERROR("Failed to register debugfs file for CP !\n");
 664         }
 665         if (!rdev->me_fw) {
 666                 r = r100_cp_init_microcode(rdev);
 667                 if (r) {
 668                         DRM_ERROR("Failed to load firmware!\n");
 669                         return r;
 670                 }
 671         }
 672
 673         /* Align ring size */
 674         rb_bufsz = drm_order(ring_size / 8);
 675         ring_size = (1 << (rb_bufsz + 1)) * 4;
 676         r100_cp_load_microcode(rdev);
 677         r = radeon_ring_init(rdev, ring_size);
 678         if (r) {
 679                 return r;
 680         }
 681         /* Each time the cp read 1024 bytes (16 dword/quadword) update
 682          * the rptr copy in system ram */
 683         rb_blksz = 9;
 684         /* cp will read 128bytes at a time (4 dwords) */
 685         max_fetch = 1;
 686         rdev->cp.align_mask = 16 - 1;
 687         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
 688         pre_write_timer = 64;
 689         /* Force CP_RB_WPTR write if written more than one time before the
 690          * delay expire
 691          */
 692         pre_write_limit = 0;
 693         /* Setup the cp cache like this (cache size is 96 dwords) :
 694          *      RING            0  to 15
 695          *      INDIRECT1       16 to 79
 696          *      INDIRECT2       80 to 95
 697          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 698          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
 699          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 700          * Idea being that most of the gpu cmd will be through indirect1 buffer
 701          * so it gets the bigger cache.
 702          */
 703         indirect2_start = 80;
 704         indirect1_start = 16;
 705         /* cp setup */
 706         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
 707         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
 708                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
 709                REG_SET(RADEON_MAX_FETCH, max_fetch) |
 710                RADEON_RB_NO_UPDATE);
 711 #ifdef __BIG_ENDIAN
 712         tmp |= RADEON_BUF_SWAP_32BIT;
 713 #endif
 714         WREG32(RADEON_CP_RB_CNTL, tmp);
 715
 716         /* Set ring address */
 717         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
 718         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
 719         /* Force read & write ptr to 0 */
 720         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 721         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 722         WREG32(RADEON_CP_RB_WPTR, 0);
 723         WREG32(RADEON_CP_RB_CNTL, tmp);
 724         udelay(10);
 725         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
 726         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
 727         /* protect against crazy HW on resume */
 728         rdev->cp.wptr &= rdev->cp.ptr_mask;
 729         /* Set cp mode to bus mastering & enable cp*/
 730         WREG32(RADEON_CP_CSQ_MODE,
 731                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
 732                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
 733         WREG32(0x718, 0);
 734         WREG32(0x744, 0x00004D4D);
 735         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
 736         radeon_ring_start(rdev);
 737         r = radeon_ring_test(rdev);
 738         if (r) {
 739                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
 740                 return r;
 741         }
 742         rdev->cp.ready = true;
 743         return 0;
 744 }
 745
 746 void r100_cp_fini(struct radeon_device *rdev)
 747 {
 748         if (r100_cp_wait_for_idle(rdev)) {
 749                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
 750         }
 751         /* Disable ring */
 752         r100_cp_disable(rdev);
 753         radeon_ring_fini(rdev);
 754         DRM_INFO("radeon: cp finalized\n");
 755 }
 756
 757 void r100_cp_disable(struct radeon_device *rdev)
 758 {
 759         /* Disable ring */
 760         rdev->cp.ready = false;
 761         WREG32(RADEON_CP_CSQ_MODE, 0);
 762         WREG32(RADEON_CP_CSQ_CNTL, 0);
 763         if (r100_gui_wait_for_idle(rdev)) {
 764                 printk(KERN_WARNING "Failed to wait GUI idle while "
 765                        "programming pipes. Bad things might happen.\n");
 766         }
 767 }
 768
 769 void r100_cp_commit(struct radeon_device *rdev)
 770 {
 771         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
 772         (void)RREG32(RADEON_CP_RB_WPTR);
 773 }
 774
 775
 776 /*
 777  * CS functions
 778  */
 779 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 780                           struct radeon_cs_packet *pkt,
 781                           const unsigned *auth, unsigned n,
 782                           radeon_packet0_check_t check)
 783 {
 784         unsigned reg;
 785         unsigned i, j, m;
 786         unsigned idx;
 787         int r;
 788
 789         idx = pkt->idx + 1;
 790         reg = pkt->reg;
 791         /* Check that register fall into register range
 792          * determined by the number of entry (n) in the
 793          * safe register bitmap.
 794          */
 795         if (pkt->one_reg_wr) {
 796                 if ((reg >> 7) > n) {
 797                         return -EINVAL;
 798                 }
 799         } else {
 800                 if (((reg + (pkt->count << 2)) >> 7) > n) {
 801                         return -EINVAL;
 802                 }
 803         }
 804         for (i = 0; i <= pkt->count; i++, idx++) {
 805                 j = (reg >> 7);
 806                 m = 1 << ((reg >> 2) & 31);
 807                 if (auth[j] & m) {
 808                         r = check(p, pkt, idx, reg);
 809                         if (r) {
 810                                 return r;
 811                         }
 812                 }
 813                 if (pkt->one_reg_wr) {
 814                         if (!(auth[j] & m)) {
 815                                 break;
 816                         }
 817                 } else {
 818                         reg += 4;
 819                 }
 820         }
 821         return 0;
 822 }
 823
 824 void r100_cs_dump_packet(struct radeon_cs_parser *p,
 825                          struct radeon_cs_packet *pkt)
 826 {
 827         volatile uint32_t *ib;
 828         unsigned i;
 829         unsigned idx;
 830
 831         ib = p->ib->ptr;
 832         idx = pkt->idx;
 833         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
 834                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
 835         }
 836 }
 837
 838 /**
 839  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
 840  * @parser:     parser structure holding parsing context.
 841  * @pkt:        where to store packet informations
 842  *
 843  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 844  * if packet is bigger than remaining ib size. or if packets is unknown.
 845  **/
 846 int r100_cs_packet_parse(struct radeon_cs_parser *p,
 847                          struct radeon_cs_packet *pkt,
 848                          unsigned idx)
 849 {
 850         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 851         uint32_t header;
 852
 853         if (idx >= ib_chunk->length_dw) {
 854                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 855                           idx, ib_chunk->length_dw);
 856                 return -EINVAL;
 857         }
 858         header = radeon_get_ib_value(p, idx);
 859         pkt->idx = idx;
 860         pkt->type = CP_PACKET_GET_TYPE(header);
 861         pkt->count = CP_PACKET_GET_COUNT(header);
 862         switch (pkt->type) {
 863         case PACKET_TYPE0:
 864                 pkt->reg = CP_PACKET0_GET_REG(header);
 865                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
 866                 break;
 867         case PACKET_TYPE3:
 868                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
 869                 break;
 870         case PACKET_TYPE2:
 871                 pkt->count = -1;
 872                 break;
 873         default:
 874                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 875                 return -EINVAL;
 876         }
 877         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 878                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 879                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 880                 return -EINVAL;
 881         }
 882         return 0;
 883 }
 884
 885 /**
 886  * r100_cs_packet_next_vline() - parse userspace VLINE packet
 887  * @parser:             parser structure holding parsing context.
 888  *
 889  * Userspace sends a special sequence for VLINE waits.
 890  * PACKET0 - VLINE_START_END + value
 891  * PACKET0 - WAIT_UNTIL +_value
 892  * RELOC (P3) - crtc_id in reloc.
 893  *
 894  * This function parses this and relocates the VLINE START END
 895  * and WAIT UNTIL packets to the correct crtc.
 896  * It also detects a switched off crtc and nulls out the
 897  * wait in that case.
 898  */
 899 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
 900 {
 901         struct drm_mode_object *obj;
 902         struct drm_crtc *crtc;
 903         struct radeon_crtc *radeon_crtc;
 904         struct radeon_cs_packet p3reloc, waitreloc;
 905         int crtc_id;
 906         int r;
 907         uint32_t header, h_idx, reg;
 908         volatile uint32_t *ib;
 909
 910         ib = p->ib->ptr;
 911
 912         /* parse the wait until */
 913         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
 914         if (r)
 915                 return r;
 916
 917         /* check its a wait until and only 1 count */
 918         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
 919             waitreloc.count != 0) {
 920                 DRM_ERROR("vline wait had illegal wait until segment\n");
 921                 r = -EINVAL;
 922                 return r;
 923         }
 924
 925         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
 926                 DRM_ERROR("vline wait had illegal wait until\n");
 927                 r = -EINVAL;
 928                 return r;
 929         }
 930
 931         /* jump over the NOP */
 932         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
 933         if (r)
 934                 return r;
 935
 936         h_idx = p->idx - 2;
 937         p->idx += waitreloc.count + 2;
 938         p->idx += p3reloc.count + 2;
 939
 940         header = radeon_get_ib_value(p, h_idx);
 941         crtc_id = radeon_get_ib_value(p, h_idx + 5);
 942         reg = CP_PACKET0_GET_REG(header);
 943         mutex_lock(&p->rdev->ddev->mode_config.mutex);
 944         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
 945         if (!obj) {
 946                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
 947                 r = -EINVAL;
 948                 goto out;
 949         }
 950         crtc = obj_to_crtc(obj);
 951         radeon_crtc = to_radeon_crtc(crtc);
 952         crtc_id = radeon_crtc->crtc_id;
 953
 954         if (!crtc->enabled) {
 955                 /* if the CRTC isn't enabled - we need to nop out the wait until */
 956                 ib[h_idx + 2] = PACKET2(0);
 957                 ib[h_idx + 3] = PACKET2(0);
 958         } else if (crtc_id == 1) {
 959                 switch (reg) {
 960                 case AVIVO_D1MODE_VLINE_START_END:
 961                         header &= ~R300_CP_PACKET0_REG_MASK;
 962                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
 963                         break;
 964                 case RADEON_CRTC_GUI_TRIG_VLINE:
 965                         header &= ~R300_CP_PACKET0_REG_MASK;
 966                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
 967                         break;
 968                 default:
 969                         DRM_ERROR("unknown crtc reloc\n");
 970                         r = -EINVAL;
 971                         goto out;
 972                 }
 973                 ib[h_idx] = header;
 974                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
 975         }
 976 out:
 977         mutex_unlock(&p->rdev->ddev->mode_config.mutex);
 978         return r;
 979 }
 980
 981 /**
 982  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
 983  * @parser:             parser structure holding parsing context.
 984  * @data:               pointer to relocation data
 985  * @offset_start:       starting offset
 986  * @offset_mask:        offset mask (to align start offset on)
 987  * @reloc:              reloc informations
 988  *
 989  * Check next packet is relocation packet3, do bo validation and compute
 990  * GPU offset using the provided start.
 991  **/
 992 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
 993                               struct radeon_cs_reloc **cs_reloc)
 994 {
 995         struct radeon_cs_chunk *relocs_chunk;
 996         struct radeon_cs_packet p3reloc;
 997         unsigned idx;
 998         int r;
 999
1000         if (p->chunk_relocs_idx == -1) {
1001                 DRM_ERROR("No relocation chunk !\n");
1002                 return -EINVAL;
1003         }
1004         *cs_reloc = NULL;
1005         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1006         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1007         if (r) {
1008                 return r;
1009         }
1010         p->idx += p3reloc.count + 2;
1011         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1012                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1013                           p3reloc.idx);
1014                 r100_cs_dump_packet(p, &p3reloc);
1015                 return -EINVAL;
1016         }
1017         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1018         if (idx >= relocs_chunk->length_dw) {
1019                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1020                           idx, relocs_chunk->length_dw);
1021                 r100_cs_dump_packet(p, &p3reloc);
1022                 return -EINVAL;
1023         }
1024         /* FIXME: we assume reloc size is 4 dwords */
1025         *cs_reloc = p->relocs_ptr[(idx / 4)];
1026         return 0;
1027 }
1028
1029 static int r100_get_vtx_size(uint32_t vtx_fmt)
1030 {
1031         int vtx_size;
1032         vtx_size = 2;
1033         /* ordered according to bits in spec */
1034         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1035                 vtx_size++;
1036         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1037                 vtx_size += 3;
1038         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1039                 vtx_size++;
1040         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1041                 vtx_size++;
1042         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1043                 vtx_size += 3;
1044         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1045                 vtx_size++;
1046         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1047                 vtx_size++;
1048         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1049                 vtx_size += 2;
1050         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1051                 vtx_size += 2;
1052         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1053                 vtx_size++;
1054         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1055                 vtx_size += 2;
1056         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1057                 vtx_size++;
1058         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1059                 vtx_size += 2;
1060         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1061                 vtx_size++;
1062         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1063                 vtx_size++;
1064         /* blend weight */
1065         if (vtx_fmt & (0x7 << 15))
1066                 vtx_size += (vtx_fmt >> 15) & 0x7;
1067         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1068                 vtx_size += 3;
1069         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1070                 vtx_size += 2;
1071         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1072                 vtx_size++;
1073         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1074                 vtx_size++;
1075         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1076                 vtx_size++;
1077         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1078                 vtx_size++;
1079         return vtx_size;
1080 }
1081
1082 static int r100_packet0_check(struct radeon_cs_parser *p,
1083                               struct radeon_cs_packet *pkt,
1084                               unsigned idx, unsigned reg)
1085 {
1086         struct radeon_cs_reloc *reloc;
1087         struct r100_cs_track *track;
1088         volatile uint32_t *ib;
1089         uint32_t tmp;
1090         int r;
1091         int i, face;
1092         u32 tile_flags = 0;
1093         u32 idx_value;
1094
1095         ib = p->ib->ptr;
1096         track = (struct r100_cs_track *)p->track;
1097
1098         idx_value = radeon_get_ib_value(p, idx);
1099
1100         switch (reg) {
1101         case RADEON_CRTC_GUI_TRIG_VLINE:
1102                 r = r100_cs_packet_parse_vline(p);
1103                 if (r) {
1104                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1105                                   idx, reg);
1106                         r100_cs_dump_packet(p, pkt);
1107                         return r;
1108                 }
1109                 break;
1110                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1111                  * range access */
1112         case RADEON_DST_PITCH_OFFSET:
1113         case RADEON_SRC_PITCH_OFFSET:
1114                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1115                 if (r)
1116                         return r;
1117                 break;
1118         case RADEON_RB3D_DEPTHOFFSET:
1119                 r = r100_cs_packet_next_reloc(p, &reloc);
1120                 if (r) {
1121                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1122                                   idx, reg);
1123                         r100_cs_dump_packet(p, pkt);
1124                         return r;
1125                 }
1126                 track->zb.robj = reloc->robj;
1127                 track->zb.offset = idx_value;
1128                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1129                 break;
1130         case RADEON_RB3D_COLOROFFSET:
1131                 r = r100_cs_packet_next_reloc(p, &reloc);
1132                 if (r) {
1133                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1134                                   idx, reg);
1135                         r100_cs_dump_packet(p, pkt);
1136                         return r;
1137                 }
1138                 track->cb[0].robj = reloc->robj;
1139                 track->cb[0].offset = idx_value;
1140                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1141                 break;
1142         case RADEON_PP_TXOFFSET_0:
1143         case RADEON_PP_TXOFFSET_1:
1144         case RADEON_PP_TXOFFSET_2:
1145                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1146                 r = r100_cs_packet_next_reloc(p, &reloc);
1147                 if (r) {
1148                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1149                                   idx, reg);
1150                         r100_cs_dump_packet(p, pkt);
1151                         return r;
1152                 }
1153                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1154                 track->textures[i].robj = reloc->robj;
1155                 break;
1156         case RADEON_PP_CUBIC_OFFSET_T0_0:
1157         case RADEON_PP_CUBIC_OFFSET_T0_1:
1158         case RADEON_PP_CUBIC_OFFSET_T0_2:
1159         case RADEON_PP_CUBIC_OFFSET_T0_3:
1160         case RADEON_PP_CUBIC_OFFSET_T0_4:
1161                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1162                 r = r100_cs_packet_next_reloc(p, &reloc);
1163                 if (r) {
1164                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1165                                   idx, reg);
1166                         r100_cs_dump_packet(p, pkt);
1167                         return r;
1168                 }
1169                 track->textures[0].cube_info[i].offset = idx_value;
1170                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1171                 track->textures[0].cube_info[i].robj = reloc->robj;
1172                 break;
1173         case RADEON_PP_CUBIC_OFFSET_T1_0:
1174         case RADEON_PP_CUBIC_OFFSET_T1_1:
1175         case RADEON_PP_CUBIC_OFFSET_T1_2:
1176         case RADEON_PP_CUBIC_OFFSET_T1_3:
1177         case RADEON_PP_CUBIC_OFFSET_T1_4:
1178                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1179                 r = r100_cs_packet_next_reloc(p, &reloc);
1180                 if (r) {
1181                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1182                                   idx, reg);
1183                         r100_cs_dump_packet(p, pkt);
1184                         return r;
1185                 }
1186                 track->textures[1].cube_info[i].offset = idx_value;
1187                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1188                 track->textures[1].cube_info[i].robj = reloc->robj;
1189                 break;
1190         case RADEON_PP_CUBIC_OFFSET_T2_0:
1191         case RADEON_PP_CUBIC_OFFSET_T2_1:
1192         case RADEON_PP_CUBIC_OFFSET_T2_2:
1193         case RADEON_PP_CUBIC_OFFSET_T2_3:
1194         case RADEON_PP_CUBIC_OFFSET_T2_4:
1195                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1196                 r = r100_cs_packet_next_reloc(p, &reloc);
1197                 if (r) {
1198                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1199                                   idx, reg);
1200                         r100_cs_dump_packet(p, pkt);
1201                         return r;
1202                 }
1203                 track->textures[2].cube_info[i].offset = idx_value;
1204                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1205                 track->textures[2].cube_info[i].robj = reloc->robj;
1206                 break;
1207         case RADEON_RE_WIDTH_HEIGHT:
1208                 track->maxy = ((idx_value >> 16) & 0x7FF);
1209                 break;
1210         case RADEON_RB3D_COLORPITCH:
1211                 r = r100_cs_packet_next_reloc(p, &reloc);
1212                 if (r) {
1213                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1214                                   idx, reg);
1215                         r100_cs_dump_packet(p, pkt);
1216                         return r;
1217                 }
1218
1219                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1220                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1221                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1222                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1223
1224                 tmp = idx_value & ~(0x7 << 16);
1225                 tmp |= tile_flags;
1226                 ib[idx] = tmp;
1227
1228                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1229                 break;
1230         case RADEON_RB3D_DEPTHPITCH:
1231                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1232                 break;
1233         case RADEON_RB3D_CNTL:
1234                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1235                 case 7:
1236                 case 8:
1237                 case 9:
1238                 case 11:
1239                 case 12:
1240                         track->cb[0].cpp = 1;
1241                         break;
1242                 case 3:
1243                 case 4:
1244                 case 15:
1245                         track->cb[0].cpp = 2;
1246                         break;
1247                 case 6:
1248                         track->cb[0].cpp = 4;
1249                         break;
1250                 default:
1251                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1252                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1253                         return -EINVAL;
1254                 }
1255                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1256                 break;
1257         case RADEON_RB3D_ZSTENCILCNTL:
1258                 switch (idx_value & 0xf) {
1259                 case 0:
1260                         track->zb.cpp = 2;
1261                         break;
1262                 case 2:
1263                 case 3:
1264                 case 4:
1265                 case 5:
1266                 case 9:
1267                 case 11:
1268                         track->zb.cpp = 4;
1269                         break;
1270                 default:
1271                         break;
1272                 }
1273                 break;
1274         case RADEON_RB3D_ZPASS_ADDR:
1275                 r = r100_cs_packet_next_reloc(p, &reloc);
1276                 if (r) {
1277                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1278                                   idx, reg);
1279                         r100_cs_dump_packet(p, pkt);
1280                         return r;
1281                 }
1282                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1283                 break;
1284         case RADEON_PP_CNTL:
1285                 {
1286                         uint32_t temp = idx_value >> 4;
1287                         for (i = 0; i < track->num_texture; i++)
1288                                 track->textures[i].enabled = !!(temp & (1 << i));
1289                 }
1290                 break;
1291         case RADEON_SE_VF_CNTL:
1292                 track->vap_vf_cntl = idx_value;
1293                 break;
1294         case RADEON_SE_VTX_FMT:
1295                 track->vtx_size = r100_get_vtx_size(idx_value);
1296                 break;
1297         case RADEON_PP_TEX_SIZE_0:
1298         case RADEON_PP_TEX_SIZE_1:
1299         case RADEON_PP_TEX_SIZE_2:
1300                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1301                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1302                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1303                 break;
1304         case RADEON_PP_TEX_PITCH_0:
1305         case RADEON_PP_TEX_PITCH_1:
1306         case RADEON_PP_TEX_PITCH_2:
1307                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1308                 track->textures[i].pitch = idx_value + 32;
1309                 break;
1310         case RADEON_PP_TXFILTER_0:
1311         case RADEON_PP_TXFILTER_1:
1312         case RADEON_PP_TXFILTER_2:
1313                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1314                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1315                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1316                 tmp = (idx_value >> 23) & 0x7;
1317                 if (tmp == 2 || tmp == 6)
1318                         track->textures[i].roundup_w = false;
1319                 tmp = (idx_value >> 27) & 0x7;
1320                 if (tmp == 2 || tmp == 6)
1321                         track->textures[i].roundup_h = false;
1322                 break;
1323         case RADEON_PP_TXFORMAT_0:
1324         case RADEON_PP_TXFORMAT_1:
1325         case RADEON_PP_TXFORMAT_2:
1326                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1327                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1328                         track->textures[i].use_pitch = 1;
1329                 } else {
1330                         track->textures[i].use_pitch = 0;
1331                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1332                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1333                 }
1334                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1335                         track->textures[i].tex_coord_type = 2;
1336                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1337                 case RADEON_TXFORMAT_I8:
1338                 case RADEON_TXFORMAT_RGB332:
1339                 case RADEON_TXFORMAT_Y8:
1340                         track->textures[i].cpp = 1;
1341                         break;
1342                 case RADEON_TXFORMAT_AI88:
1343                 case RADEON_TXFORMAT_ARGB1555:
1344                 case RADEON_TXFORMAT_RGB565:
1345                 case RADEON_TXFORMAT_ARGB4444:
1346                 case RADEON_TXFORMAT_VYUY422:
1347                 case RADEON_TXFORMAT_YVYU422:
1348                 case RADEON_TXFORMAT_SHADOW16:
1349                 case RADEON_TXFORMAT_LDUDV655:
1350                 case RADEON_TXFORMAT_DUDV88:
1351                         track->textures[i].cpp = 2;
1352                         break;
1353                 case RADEON_TXFORMAT_ARGB8888:
1354                 case RADEON_TXFORMAT_RGBA8888:
1355                 case RADEON_TXFORMAT_SHADOW32:
1356                 case RADEON_TXFORMAT_LDUDUV8888:
1357                         track->textures[i].cpp = 4;
1358                         break;
1359                 case RADEON_TXFORMAT_DXT1:
1360                         track->textures[i].cpp = 1;
1361                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1362                         break;
1363                 case RADEON_TXFORMAT_DXT23:
1364                 case RADEON_TXFORMAT_DXT45:
1365                         track->textures[i].cpp = 1;
1366                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1367                         break;
1368                 }
1369                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1370                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1371                 break;
1372         case RADEON_PP_CUBIC_FACES_0:
1373         case RADEON_PP_CUBIC_FACES_1:
1374         case RADEON_PP_CUBIC_FACES_2:
1375                 tmp = idx_value;
1376                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1377                 for (face = 0; face < 4; face++) {
1378                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1379                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1380                 }
1381                 break;
1382         default:
1383                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1384                        reg, idx);
1385                 return -EINVAL;
1386         }
1387         return 0;
1388 }
1389
1390 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1391                                          struct radeon_cs_packet *pkt,
1392                                          struct radeon_bo *robj)
1393 {
1394         unsigned idx;
1395         u32 value;
1396         idx = pkt->idx + 1;
1397         value = radeon_get_ib_value(p, idx + 2);
1398         if ((value + 1) > radeon_bo_size(robj)) {
1399                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1400                           "(need %u have %lu) !\n",
1401                           value + 1,
1402                           radeon_bo_size(robj));
1403                 return -EINVAL;
1404         }
1405         return 0;
1406 }
1407
1408 static int r100_packet3_check(struct radeon_cs_parser *p,
1409                               struct radeon_cs_packet *pkt)
1410 {
1411         struct radeon_cs_reloc *reloc;
1412         struct r100_cs_track *track;
1413         unsigned idx;
1414         volatile uint32_t *ib;
1415         int r;
1416
1417         ib = p->ib->ptr;
1418         idx = pkt->idx + 1;
1419         track = (struct r100_cs_track *)p->track;
1420         switch (pkt->opcode) {
1421         case PACKET3_3D_LOAD_VBPNTR:
1422                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1423                 if (r)
1424                         return r;
1425                 break;
1426         case PACKET3_INDX_BUFFER:
1427                 r = r100_cs_packet_next_reloc(p, &reloc);
1428                 if (r) {
1429                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1430                         r100_cs_dump_packet(p, pkt);
1431                         return r;
1432                 }
1433                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1434                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1435                 if (r) {
1436                         return r;
1437                 }
1438                 break;
1439         case 0x23:
1440                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1441                 r = r100_cs_packet_next_reloc(p, &reloc);
1442                 if (r) {
1443                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1444                         r100_cs_dump_packet(p, pkt);
1445                         return r;
1446                 }
1447                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1448                 track->num_arrays = 1;
1449                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1450
1451                 track->arrays[0].robj = reloc->robj;
1452                 track->arrays[0].esize = track->vtx_size;
1453
1454                 track->max_indx = radeon_get_ib_value(p, idx+1);
1455
1456                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1457                 track->immd_dwords = pkt->count - 1;
1458                 r = r100_cs_track_check(p->rdev, track);
1459                 if (r)
1460                         return r;
1461                 break;
1462         case PACKET3_3D_DRAW_IMMD:
1463                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1464                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1465                         return -EINVAL;
1466                 }
1467                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1468                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1469                 track->immd_dwords = pkt->count - 1;
1470                 r = r100_cs_track_check(p->rdev, track);
1471                 if (r)
1472                         return r;
1473                 break;
1474                 /* triggers drawing using in-packet vertex data */
1475         case PACKET3_3D_DRAW_IMMD_2:
1476                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1477                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1478                         return -EINVAL;
1479                 }
1480                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1481                 track->immd_dwords = pkt->count;
1482                 r = r100_cs_track_check(p->rdev, track);
1483                 if (r)
1484                         return r;
1485                 break;
1486                 /* triggers drawing using in-packet vertex data */
1487         case PACKET3_3D_DRAW_VBUF_2:
1488                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1489                 r = r100_cs_track_check(p->rdev, track);
1490                 if (r)
1491                         return r;
1492                 break;
1493                 /* triggers drawing of vertex buffers setup elsewhere */
1494         case PACKET3_3D_DRAW_INDX_2:
1495                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1496                 r = r100_cs_track_check(p->rdev, track);
1497                 if (r)
1498                         return r;
1499                 break;
1500                 /* triggers drawing using indices to vertex buffer */
1501         case PACKET3_3D_DRAW_VBUF:
1502                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1503                 r = r100_cs_track_check(p->rdev, track);
1504                 if (r)
1505                         return r;
1506                 break;
1507                 /* triggers drawing of vertex buffers setup elsewhere */
1508         case PACKET3_3D_DRAW_INDX:
1509                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1510                 r = r100_cs_track_check(p->rdev, track);
1511                 if (r)
1512                         return r;
1513                 break;
1514                 /* triggers drawing using indices to vertex buffer */
1515         case PACKET3_NOP:
1516                 break;
1517         default:
1518                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1519                 return -EINVAL;
1520         }
1521         return 0;
1522 }
1523
1524 int r100_cs_parse(struct radeon_cs_parser *p)
1525 {
1526         struct radeon_cs_packet pkt;
1527         struct r100_cs_track *track;
1528         int r;
1529
1530         track = kzalloc(sizeof(*track), GFP_KERNEL);
1531         r100_cs_track_clear(p->rdev, track);
1532         p->track = track;
1533         do {
1534                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1535                 if (r) {
1536                         return r;
1537                 }
1538                 p->idx += pkt.count + 2;
1539                 switch (pkt.type) {
1540                         case PACKET_TYPE0:
1541                                 if (p->rdev->family >= CHIP_R200)
1542                                         r = r100_cs_parse_packet0(p, &pkt,
1543                                                                   p->rdev->config.r100.reg_safe_bm,
1544                                                                   p->rdev->config.r100.reg_safe_bm_size,
1545                                                                   &r200_packet0_check);
1546                                 else
1547                                         r = r100_cs_parse_packet0(p, &pkt,
1548                                                                   p->rdev->config.r100.reg_safe_bm,
1549                                                                   p->rdev->config.r100.reg_safe_bm_size,
1550                                                                   &r100_packet0_check);
1551                                 break;
1552                         case PACKET_TYPE2:
1553                                 break;
1554                         case PACKET_TYPE3:
1555                                 r = r100_packet3_check(p, &pkt);
1556                                 break;
1557                         default:
1558                                 DRM_ERROR("Unknown packet type %d !\n",
1559                                           pkt.type);
1560                                 return -EINVAL;
1561                 }
1562                 if (r) {
1563                         return r;
1564                 }
1565         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1566         return 0;
1567 }
1568
1569
1570 /*
1571  * Global GPU functions
1572  */
1573 void r100_errata(struct radeon_device *rdev)
1574 {
1575         rdev->pll_errata = 0;
1576
1577         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1578                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1579         }
1580
1581         if (rdev->family == CHIP_RV100 ||
1582             rdev->family == CHIP_RS100 ||
1583             rdev->family == CHIP_RS200) {
1584                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1585         }
1586 }
1587
1588 /* Wait for vertical sync on primary CRTC */
1589 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1590 {
1591         uint32_t crtc_gen_cntl, tmp;
1592         int i;
1593
1594         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1595         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1596             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1597                 return;
1598         }
1599         /* Clear the CRTC_VBLANK_SAVE bit */
1600         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1601         for (i = 0; i < rdev->usec_timeout; i++) {
1602                 tmp = RREG32(RADEON_CRTC_STATUS);
1603                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1604                         return;
1605                 }
1606                 DRM_UDELAY(1);
1607         }
1608 }
1609
1610 /* Wait for vertical sync on secondary CRTC */
1611 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1612 {
1613         uint32_t crtc2_gen_cntl, tmp;
1614         int i;
1615
1616         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1617         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1618             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1619                 return;
1620
1621         /* Clear the CRTC_VBLANK_SAVE bit */
1622         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1623         for (i = 0; i < rdev->usec_timeout; i++) {
1624                 tmp = RREG32(RADEON_CRTC2_STATUS);
1625                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1626                         return;
1627                 }
1628                 DRM_UDELAY(1);
1629         }
1630 }
1631
1632 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1633 {
1634         unsigned i;
1635         uint32_t tmp;
1636
1637         for (i = 0; i < rdev->usec_timeout; i++) {
1638                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1639                 if (tmp >= n) {
1640                         return 0;
1641                 }
1642                 DRM_UDELAY(1);
1643         }
1644         return -1;
1645 }
1646
1647 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1648 {
1649         unsigned i;
1650         uint32_t tmp;
1651
1652         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1653                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1654                        " Bad things might happen.\n");
1655         }
1656         for (i = 0; i < rdev->usec_timeout; i++) {
1657                 tmp = RREG32(RADEON_RBBM_STATUS);
1658                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1659                         return 0;
1660                 }
1661                 DRM_UDELAY(1);
1662         }
1663         return -1;
1664 }
1665
1666 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1667 {
1668         unsigned i;
1669         uint32_t tmp;
1670
1671         for (i = 0; i < rdev->usec_timeout; i++) {
1672                 /* read MC_STATUS */
1673                 tmp = RREG32(RADEON_MC_STATUS);
1674                 if (tmp & RADEON_MC_IDLE) {
1675                         return 0;
1676                 }
1677                 DRM_UDELAY(1);
1678         }
1679         return -1;
1680 }
1681
1682 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
1683 {
1684         lockup->last_cp_rptr = cp->rptr;
1685         lockup->last_jiffies = jiffies;
1686 }
1687
1688 /**
1689  * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
1690  * @rdev:       radeon device structure
1691  * @lockup:     r100_gpu_lockup structure holding CP lockup tracking informations
1692  * @cp:         radeon_cp structure holding CP information
1693  *
1694  * We don't need to initialize the lockup tracking information as we will either
1695  * have CP rptr to a different value of jiffies wrap around which will force
1696  * initialization of the lockup tracking informations.
1697  *
1698  * A possible false positivie is if we get call after while and last_cp_rptr ==
1699  * the current CP rptr, even if it's unlikely it might happen. To avoid this
1700  * if the elapsed time since last call is bigger than 2 second than we return
1701  * false and update the tracking information. Due to this the caller must call
1702  * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
1703  * the fencing code should be cautious about that.
1704  *
1705  * Caller should write to the ring to force CP to do something so we don't get
1706  * false positive when CP is just gived nothing to do.
1707  *
1708  **/
1709 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
1710 {
1711         unsigned long cjiffies, elapsed;
1712
1713         cjiffies = jiffies;
1714         if (!time_after(cjiffies, lockup->last_jiffies)) {
1715                 /* likely a wrap around */
1716                 lockup->last_cp_rptr = cp->rptr;
1717                 lockup->last_jiffies = jiffies;
1718                 return false;
1719         }
1720         if (cp->rptr != lockup->last_cp_rptr) {
1721                 /* CP is still working no lockup */
1722                 lockup->last_cp_rptr = cp->rptr;
1723                 lockup->last_jiffies = jiffies;
1724                 return false;
1725         }
1726         elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
1727         if (elapsed >= 3000) {
1728                 /* very likely the improbable case where current
1729                  * rptr is equal to last recorded, a while ago, rptr
1730                  * this is more likely a false positive update tracking
1731                  * information which should force us to be recall at
1732                  * latter point
1733                  */
1734                 lockup->last_cp_rptr = cp->rptr;
1735                 lockup->last_jiffies = jiffies;
1736                 return false;
1737         }
1738         if (elapsed >= 1000) {
1739                 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
1740                 return true;
1741         }
1742         /* give a chance to the GPU ... */
1743         return false;
1744 }
1745
1746 bool r100_gpu_is_lockup(struct radeon_device *rdev)
1747 {
1748         u32 rbbm_status;
1749         int r;
1750
1751         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
1752         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
1753                 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
1754                 return false;
1755         }
1756         /* force CP activities */
1757         r = radeon_ring_lock(rdev, 2);
1758         if (!r) {
1759                 /* PACKET2 NOP */
1760                 radeon_ring_write(rdev, 0x80000000);
1761                 radeon_ring_write(rdev, 0x80000000);
1762                 radeon_ring_unlock_commit(rdev);
1763         }
1764         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1765         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
1766 }
1767
1768 void r100_bm_disable(struct radeon_device *rdev)
1769 {
1770         u32 tmp;
1771
1772         /* disable bus mastering */
1773         tmp = RREG32(R_000030_BUS_CNTL);
1774         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
1775         mdelay(1);
1776         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
1777         mdelay(1);
1778         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
1779         tmp = RREG32(RADEON_BUS_CNTL);
1780         mdelay(1);
1781         pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
1782         pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
1783         mdelay(1);
1784 }
1785
1786 int r100_asic_reset(struct radeon_device *rdev)
1787 {
1788         struct r100_mc_save save;
1789         u32 status, tmp;
1790
1791         r100_mc_stop(rdev, &save);
1792         status = RREG32(R_000E40_RBBM_STATUS);
1793         if (!G_000E40_GUI_ACTIVE(status)) {
1794                 return 0;
1795         }
1796         status = RREG32(R_000E40_RBBM_STATUS);
1797         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
1798         /* stop CP */
1799         WREG32(RADEON_CP_CSQ_CNTL, 0);
1800         tmp = RREG32(RADEON_CP_RB_CNTL);
1801         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
1802         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1803         WREG32(RADEON_CP_RB_WPTR, 0);
1804         WREG32(RADEON_CP_RB_CNTL, tmp);
1805         /* save PCI state */
1806         pci_save_state(rdev->pdev);
1807         /* disable bus mastering */
1808         r100_bm_disable(rdev);
1809         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
1810                                         S_0000F0_SOFT_RESET_RE(1) |
1811                                         S_0000F0_SOFT_RESET_PP(1) |
1812                                         S_0000F0_SOFT_RESET_RB(1));
1813         RREG32(R_0000F0_RBBM_SOFT_RESET);
1814         mdelay(500);
1815         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
1816         mdelay(1);
1817         status = RREG32(R_000E40_RBBM_STATUS);
1818         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
1819         /* reset CP */
1820         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
1821         RREG32(R_0000F0_RBBM_SOFT_RESET);
1822         mdelay(500);
1823         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
1824         mdelay(1);
1825         status = RREG32(R_000E40_RBBM_STATUS);
1826         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
1827         /* restore PCI & busmastering */
1828         pci_restore_state(rdev->pdev);
1829         r100_enable_bm(rdev);
1830         /* Check if GPU is idle */
1831         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
1832                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
1833                 dev_err(rdev->dev, "failed to reset GPU\n");
1834                 rdev->gpu_lockup = true;
1835                 return -1;
1836         }
1837         r100_mc_resume(rdev, &save);
1838         dev_info(rdev->dev, "GPU reset succeed\n");
1839         return 0;
1840 }
1841
1842 void r100_set_common_regs(struct radeon_device *rdev)
1843 {
1844         struct drm_device *dev = rdev->ddev;
1845         bool force_dac2 = false;
1846         u32 tmp;
1847
1848         /* set these so they don't interfere with anything */
1849         WREG32(RADEON_OV0_SCALE_CNTL, 0);
1850         WREG32(RADEON_SUBPIC_CNTL, 0);
1851         WREG32(RADEON_VIPH_CONTROL, 0);
1852         WREG32(RADEON_I2C_CNTL_1, 0);
1853         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1854         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1855         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1856
1857         /* always set up dac2 on rn50 and some rv100 as lots
1858          * of servers seem to wire it up to a VGA port but
1859          * don't report it in the bios connector
1860          * table.
1861          */
1862         switch (dev->pdev->device) {
1863                 /* RN50 */
1864         case 0x515e:
1865         case 0x5969:
1866                 force_dac2 = true;
1867                 break;
1868                 /* RV100*/
1869         case 0x5159:
1870         case 0x515a:
1871                 /* DELL triple head servers */
1872                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
1873                     ((dev->pdev->subsystem_device == 0x016c) ||
1874                      (dev->pdev->subsystem_device == 0x016d) ||
1875                      (dev->pdev->subsystem_device == 0x016e) ||
1876                      (dev->pdev->subsystem_device == 0x016f) ||
1877                      (dev->pdev->subsystem_device == 0x0170) ||
1878                      (dev->pdev->subsystem_device == 0x017d) ||
1879                      (dev->pdev->subsystem_device == 0x017e) ||
1880                      (dev->pdev->subsystem_device == 0x0183) ||
1881                      (dev->pdev->subsystem_device == 0x018a) ||
1882                      (dev->pdev->subsystem_device == 0x019a)))
1883                         force_dac2 = true;
1884                 break;
1885         }
1886
1887         if (force_dac2) {
1888                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1889                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1890                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
1891
1892                 /* For CRT on DAC2, don't turn it on if BIOS didn't
1893                    enable it, even it's detected.
1894                 */
1895
1896                 /* force it to crtc0 */
1897                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
1898                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
1899                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1900
1901                 /* set up the TV DAC */
1902                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
1903                                  RADEON_TV_DAC_STD_MASK |
1904                                  RADEON_TV_DAC_RDACPD |
1905                                  RADEON_TV_DAC_GDACPD |
1906                                  RADEON_TV_DAC_BDACPD |
1907                                  RADEON_TV_DAC_BGADJ_MASK |
1908                                  RADEON_TV_DAC_DACADJ_MASK);
1909                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
1910                                 RADEON_TV_DAC_NHOLD |
1911                                 RADEON_TV_DAC_STD_PS2 |
1912                                 (0x58 << 16));
1913
1914                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1915                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1916                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1917         }
1918
1919         /* switch PM block to ACPI mode */
1920         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
1921         tmp &= ~RADEON_PM_MODE_SEL;
1922         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
1923
1924 }
1925
1926 /*
1927  * VRAM info
1928  */
1929 static void r100_vram_get_type(struct radeon_device *rdev)
1930 {
1931         uint32_t tmp;
1932
1933         rdev->mc.vram_is_ddr = false;
1934         if (rdev->flags & RADEON_IS_IGP)
1935                 rdev->mc.vram_is_ddr = true;
1936         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1937                 rdev->mc.vram_is_ddr = true;
1938         if ((rdev->family == CHIP_RV100) ||
1939             (rdev->family == CHIP_RS100) ||
1940             (rdev->family == CHIP_RS200)) {
1941                 tmp = RREG32(RADEON_MEM_CNTL);
1942                 if (tmp & RV100_HALF_MODE) {
1943                         rdev->mc.vram_width = 32;
1944                 } else {
1945                         rdev->mc.vram_width = 64;
1946                 }
1947                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1948                         rdev->mc.vram_width /= 4;
1949                         rdev->mc.vram_is_ddr = true;
1950                 }
1951         } else if (rdev->family <= CHIP_RV280) {
1952                 tmp = RREG32(RADEON_MEM_CNTL);
1953                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1954                         rdev->mc.vram_width = 128;
1955                 } else {
1956                         rdev->mc.vram_width = 64;
1957                 }
1958         } else {
1959                 /* newer IGPs */
1960                 rdev->mc.vram_width = 128;
1961         }
1962 }
1963
1964 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1965 {
1966         u32 aper_size;
1967         u8 byte;
1968
1969         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1970
1971         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1972          * that is has the 2nd generation multifunction PCI interface
1973          */
1974         if (rdev->family == CHIP_RV280 ||
1975             rdev->family >= CHIP_RV350) {
1976                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1977                        ~RADEON_HDP_APER_CNTL);
1978                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1979                 return aper_size * 2;
1980         }
1981
1982         /* Older cards have all sorts of funny issues to deal with. First
1983          * check if it's a multifunction card by reading the PCI config
1984          * header type... Limit those to one aperture size
1985          */
1986         pci_read_config_byte(rdev->pdev, 0xe, &byte);
1987         if (byte & 0x80) {
1988                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1989                 DRM_INFO("Limiting VRAM to one aperture\n");
1990                 return aper_size;
1991         }
1992
1993         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1994          * have set it up. We don't write this as it's broken on some ASICs but
1995          * we expect the BIOS to have done the right thing (might be too optimistic...)
1996          */
1997         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1998                 return aper_size * 2;
1999         return aper_size;
2000 }
2001
2002 void r100_vram_init_sizes(struct radeon_device *rdev)
2003 {
2004         u64 config_aper_size;
2005
2006         /* work out accessible VRAM */
2007         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
2008         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2009         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2010         /* FIXME we don't use the second aperture yet when we could use it */
2011         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2012                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2013         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2014         if (rdev->flags & RADEON_IS_IGP) {
2015                 uint32_t tom;
2016                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2017                 tom = RREG32(RADEON_NB_TOM);
2018                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2019                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2020                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2021         } else {
2022                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2023                 /* Some production boards of m6 will report 0
2024                  * if it's 8 MB
2025                  */
2026                 if (rdev->mc.real_vram_size == 0) {
2027                         rdev->mc.real_vram_size = 8192 * 1024;
2028                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2029                 }
2030                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2031                  * Novell bug 204882 + along with lots of ubuntu ones
2032                  */
2033                 if (config_aper_size > rdev->mc.real_vram_size)
2034                         rdev->mc.mc_vram_size = config_aper_size;
2035                 else
2036                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2037         }
2038         /* FIXME remove this once we support unmappable VRAM */
2039         if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
2040                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
2041                 rdev->mc.real_vram_size = rdev->mc.aper_size;
2042         }
2043 }
2044
2045 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2046 {
2047         uint32_t temp;
2048
2049         temp = RREG32(RADEON_CONFIG_CNTL);
2050         if (state == false) {
2051                 temp &= ~(1<<8);
2052                 temp |= (1<<9);
2053         } else {
2054                 temp &= ~(1<<9);
2055         }
2056         WREG32(RADEON_CONFIG_CNTL, temp);
2057 }
2058
2059 void r100_mc_init(struct radeon_device *rdev)
2060 {
2061         u64 base;
2062
2063         r100_vram_get_type(rdev);
2064         r100_vram_init_sizes(rdev);
2065         base = rdev->mc.aper_base;
2066         if (rdev->flags & RADEON_IS_IGP)
2067                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2068         radeon_vram_location(rdev, &rdev->mc, base);
2069         if (!(rdev->flags & RADEON_IS_AGP))
2070                 radeon_gtt_location(rdev, &rdev->mc);
2071         radeon_update_bandwidth_info(rdev);
2072 }
2073
2074
2075 /*
2076  * Indirect registers accessor
2077  */
2078 void r100_pll_errata_after_index(struct radeon_device *rdev)
2079 {
2080         if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2081                 return;
2082         }
2083         (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2084         (void)RREG32(RADEON_CRTC_GEN_CNTL);
2085 }
2086
2087 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2088 {
2089         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2090          * or the chip could hang on a subsequent access
2091          */
2092         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2093                 udelay(5000);
2094         }
2095
2096         /* This function is required to workaround a hardware bug in some (all?)
2097          * revisions of the R300.  This workaround should be called after every
2098          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2099          * may not be correct.
2100          */
2101         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2102                 uint32_t save, tmp;
2103
2104                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2105                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2106                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2107                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2108                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2109         }
2110 }
2111
2112 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2113 {
2114         uint32_t data;
2115
2116         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2117         r100_pll_errata_after_index(rdev);
2118         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2119         r100_pll_errata_after_data(rdev);
2120         return data;
2121 }
2122
2123 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2124 {
2125         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2126         r100_pll_errata_after_index(rdev);
2127         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2128         r100_pll_errata_after_data(rdev);
2129 }
2130
2131 void r100_set_safe_registers(struct radeon_device *rdev)
2132 {
2133         if (ASIC_IS_RN50(rdev)) {
2134                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2135                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2136         } else if (rdev->family < CHIP_R200) {
2137                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2138                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2139         } else {
2140                 r200_set_safe_registers(rdev);
2141         }
2142 }
2143
2144 /*
2145  * Debugfs info
2146  */
2147 #if defined(CONFIG_DEBUG_FS)
2148 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2149 {
2150         struct drm_info_node *node = (struct drm_info_node *) m->private;
2151         struct drm_device *dev = node->minor->dev;
2152         struct radeon_device *rdev = dev->dev_private;
2153         uint32_t reg, value;
2154         unsigned i;
2155
2156         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2157         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2158         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2159         for (i = 0; i < 64; i++) {
2160                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2161                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2162                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2163                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2164                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2165         }
2166         return 0;
2167 }
2168
2169 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2170 {
2171         struct drm_info_node *node = (struct drm_info_node *) m->private;
2172         struct drm_device *dev = node->minor->dev;
2173         struct radeon_device *rdev = dev->dev_private;
2174         uint32_t rdp, wdp;
2175         unsigned count, i, j;
2176
2177         radeon_ring_free_size(rdev);
2178         rdp = RREG32(RADEON_CP_RB_RPTR);
2179         wdp = RREG32(RADEON_CP_RB_WPTR);
2180         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2181         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2182         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2183         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2184         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2185         seq_printf(m, "%u dwords in ring\n", count);
2186         for (j = 0; j <= count; j++) {
2187                 i = (rdp + j) & rdev->cp.ptr_mask;
2188                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2189         }
2190         return 0;
2191 }
2192
2193
2194 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2195 {
2196         struct drm_info_node *node = (struct drm_info_node *) m->private;
2197         struct drm_device *dev = node->minor->dev;
2198         struct radeon_device *rdev = dev->dev_private;
2199         uint32_t csq_stat, csq2_stat, tmp;
2200         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2201         unsigned i;
2202
2203         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2204         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2205         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2206         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2207         r_rptr = (csq_stat >> 0) & 0x3ff;
2208         r_wptr = (csq_stat >> 10) & 0x3ff;
2209         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2210         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2211         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2212         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2213         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2214         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2215         seq_printf(m, "Ring rptr %u\n", r_rptr);
2216         seq_printf(m, "Ring wptr %u\n", r_wptr);
2217         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2218         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2219         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2220         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2221         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2222          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2223         seq_printf(m, "Ring fifo:\n");
2224         for (i = 0; i < 256; i++) {
2225                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2226                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2227                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2228         }
2229         seq_printf(m, "Indirect1 fifo:\n");
2230         for (i = 256; i <= 512; i++) {
2231                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2232                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2233                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2234         }
2235         seq_printf(m, "Indirect2 fifo:\n");
2236         for (i = 640; i < ib1_wptr; i++) {
2237                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2238                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2239                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2240         }
2241         return 0;
2242 }
2243
2244 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2245 {
2246         struct drm_info_node *node = (struct drm_info_node *) m->private;
2247         struct drm_device *dev = node->minor->dev;
2248         struct radeon_device *rdev = dev->dev_private;
2249         uint32_t tmp;
2250
2251         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2252         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2253         tmp = RREG32(RADEON_MC_FB_LOCATION);
2254         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2255         tmp = RREG32(RADEON_BUS_CNTL);
2256         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2257         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2258         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2259         tmp = RREG32(RADEON_AGP_BASE);
2260         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2261         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2262         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2263         tmp = RREG32(0x01D0);
2264         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2265         tmp = RREG32(RADEON_AIC_LO_ADDR);
2266         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2267         tmp = RREG32(RADEON_AIC_HI_ADDR);
2268         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2269         tmp = RREG32(0x01E4);
2270         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2271         return 0;
2272 }
2273
2274 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2275         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2276 };
2277
2278 static struct drm_info_list r100_debugfs_cp_list[] = {
2279         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2280         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2281 };
2282
2283 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2284         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2285 };
2286 #endif
2287
2288 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2289 {
2290 #if defined(CONFIG_DEBUG_FS)
2291         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2292 #else
2293         return 0;
2294 #endif
2295 }
2296
2297 int r100_debugfs_cp_init(struct radeon_device *rdev)
2298 {
2299 #if defined(CONFIG_DEBUG_FS)
2300         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2301 #else
2302         return 0;
2303 #endif
2304 }
2305
2306 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2307 {
2308 #if defined(CONFIG_DEBUG_FS)
2309         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2310 #else
2311         return 0;
2312 #endif
2313 }
2314
2315 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2316                          uint32_t tiling_flags, uint32_t pitch,
2317                          uint32_t offset, uint32_t obj_size)
2318 {
2319         int surf_index = reg * 16;
2320         int flags = 0;
2321
2322         /* r100/r200 divide by 16 */
2323         if (rdev->family < CHIP_R300)
2324                 flags = pitch / 16;
2325         else
2326                 flags = pitch / 8;
2327
2328         if (rdev->family <= CHIP_RS200) {
2329                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2330                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2331                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2332                 if (tiling_flags & RADEON_TILING_MACRO)
2333                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2334         } else if (rdev->family <= CHIP_RV280) {
2335                 if (tiling_flags & (RADEON_TILING_MACRO))
2336                         flags |= R200_SURF_TILE_COLOR_MACRO;
2337                 if (tiling_flags & RADEON_TILING_MICRO)
2338                         flags |= R200_SURF_TILE_COLOR_MICRO;
2339         } else {
2340                 if (tiling_flags & RADEON_TILING_MACRO)
2341                         flags |= R300_SURF_TILE_MACRO;
2342                 if (tiling_flags & RADEON_TILING_MICRO)
2343                         flags |= R300_SURF_TILE_MICRO;
2344         }
2345
2346         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2347                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2348         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2349                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2350
2351         DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2352         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2353         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2354         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2355         return 0;
2356 }
2357
2358 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2359 {
2360         int surf_index = reg * 16;
2361         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2362 }
2363
2364 void r100_bandwidth_update(struct radeon_device *rdev)
2365 {
2366         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2367         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2368         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2369         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2370         fixed20_12 memtcas_ff[8] = {
2371                 fixed_init(1),
2372                 fixed_init(2),
2373                 fixed_init(3),
2374                 fixed_init(0),
2375                 fixed_init_half(1),
2376                 fixed_init_half(2),
2377                 fixed_init(0),
2378         };
2379         fixed20_12 memtcas_rs480_ff[8] = {
2380                 fixed_init(0),
2381                 fixed_init(1),
2382                 fixed_init(2),
2383                 fixed_init(3),
2384                 fixed_init(0),
2385                 fixed_init_half(1),
2386                 fixed_init_half(2),
2387                 fixed_init_half(3),
2388         };
2389         fixed20_12 memtcas2_ff[8] = {
2390                 fixed_init(0),
2391                 fixed_init(1),
2392                 fixed_init(2),
2393                 fixed_init(3),
2394                 fixed_init(4),
2395                 fixed_init(5),
2396                 fixed_init(6),
2397                 fixed_init(7),
2398         };
2399         fixed20_12 memtrbs[8] = {
2400                 fixed_init(1),
2401                 fixed_init_half(1),
2402                 fixed_init(2),
2403                 fixed_init_half(2),
2404                 fixed_init(3),
2405                 fixed_init_half(3),
2406                 fixed_init(4),
2407                 fixed_init_half(4)
2408         };
2409         fixed20_12 memtrbs_r4xx[8] = {
2410                 fixed_init(4),
2411                 fixed_init(5),
2412                 fixed_init(6),
2413                 fixed_init(7),
2414                 fixed_init(8),
2415                 fixed_init(9),
2416                 fixed_init(10),
2417                 fixed_init(11)
2418         };
2419         fixed20_12 min_mem_eff;
2420         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2421         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2422         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2423                 disp_drain_rate2, read_return_rate;
2424         fixed20_12 time_disp1_drop_priority;
2425         int c;
2426         int cur_size = 16;       /* in octawords */
2427         int critical_point = 0, critical_point2;
2428 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2429         int stop_req, max_stop_req;
2430         struct drm_display_mode *mode1 = NULL;
2431         struct drm_display_mode *mode2 = NULL;
2432         uint32_t pixel_bytes1 = 0;
2433         uint32_t pixel_bytes2 = 0;
2434
2435         radeon_update_display_priority(rdev);
2436
2437         if (rdev->mode_info.crtcs[0]->base.enabled) {
2438                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2439                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2440         }
2441         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2442                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2443                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2444                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2445                 }
2446         }
2447
2448         min_mem_eff.full = rfixed_const_8(0);
2449         /* get modes */
2450         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2451                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2452                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2453                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2454                 /* check crtc enables */
2455                 if (mode2)
2456                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2457                 if (mode1)
2458                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2459                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2460         }
2461
2462         /*
2463          * determine is there is enough bw for current mode
2464          */
2465         sclk_ff = rdev->pm.sclk;
2466         mclk_ff = rdev->pm.mclk;
2467
2468         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2469         temp_ff.full = rfixed_const(temp);
2470         mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2471
2472         pix_clk.full = 0;
2473         pix_clk2.full = 0;
2474         peak_disp_bw.full = 0;
2475         if (mode1) {
2476                 temp_ff.full = rfixed_const(1000);
2477                 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2478                 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2479                 temp_ff.full = rfixed_const(pixel_bytes1);
2480                 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2481         }
2482         if (mode2) {
2483                 temp_ff.full = rfixed_const(1000);
2484                 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2485                 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2486                 temp_ff.full = rfixed_const(pixel_bytes2);
2487                 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2488         }
2489
2490         mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2491         if (peak_disp_bw.full >= mem_bw.full) {
2492                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2493                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2494         }
2495
2496         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2497         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2498         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2499                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2500                 mem_trp  = ((temp & 0x3)) + 1;
2501                 mem_tras = ((temp & 0x70) >> 4) + 1;
2502         } else if (rdev->family == CHIP_R300 ||
2503                    rdev->family == CHIP_R350) { /* r300, r350 */
2504                 mem_trcd = (temp & 0x7) + 1;
2505                 mem_trp = ((temp >> 8) & 0x7) + 1;
2506                 mem_tras = ((temp >> 11) & 0xf) + 4;
2507         } else if (rdev->family == CHIP_RV350 ||
2508                    rdev->family <= CHIP_RV380) {
2509                 /* rv3x0 */
2510                 mem_trcd = (temp & 0x7) + 3;
2511                 mem_trp = ((temp >> 8) & 0x7) + 3;
2512                 mem_tras = ((temp >> 11) & 0xf) + 6;
2513         } else if (rdev->family == CHIP_R420 ||
2514                    rdev->family == CHIP_R423 ||
2515                    rdev->family == CHIP_RV410) {
2516                 /* r4xx */
2517                 mem_trcd = (temp & 0xf) + 3;
2518                 if (mem_trcd > 15)
2519                         mem_trcd = 15;
2520                 mem_trp = ((temp >> 8) & 0xf) + 3;
2521                 if (mem_trp > 15)
2522                         mem_trp = 15;
2523                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2524                 if (mem_tras > 31)
2525                         mem_tras = 31;
2526         } else { /* RV200, R200 */
2527                 mem_trcd = (temp & 0x7) + 1;
2528                 mem_trp = ((temp >> 8) & 0x7) + 1;
2529                 mem_tras = ((temp >> 12) & 0xf) + 4;
2530         }
2531         /* convert to FF */
2532         trcd_ff.full = rfixed_const(mem_trcd);
2533         trp_ff.full = rfixed_const(mem_trp);
2534         tras_ff.full = rfixed_const(mem_tras);
2535
2536         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2537         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2538         data = (temp & (7 << 20)) >> 20;
2539         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2540                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2541                         tcas_ff = memtcas_rs480_ff[data];
2542                 else
2543                         tcas_ff = memtcas_ff[data];
2544         } else
2545                 tcas_ff = memtcas2_ff[data];
2546
2547         if (rdev->family == CHIP_RS400 ||
2548             rdev->family == CHIP_RS480) {
2549                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2550                 data = (temp >> 23) & 0x7;
2551                 if (data < 5)
2552                         tcas_ff.full += rfixed_const(data);
2553         }
2554
2555         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2556                 /* on the R300, Tcas is included in Trbs.
2557                  */
2558                 temp = RREG32(RADEON_MEM_CNTL);
2559                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2560                 if (data == 1) {
2561                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2562                                 temp = RREG32(R300_MC_IND_INDEX);
2563                                 temp &= ~R300_MC_IND_ADDR_MASK;
2564                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2565                                 WREG32(R300_MC_IND_INDEX, temp);
2566                                 temp = RREG32(R300_MC_IND_DATA);
2567                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2568                         } else {
2569                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2570                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2571                         }
2572                 } else {
2573                         temp = RREG32(R300_MC_READ_CNTL_AB);
2574                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2575                 }
2576                 if (rdev->family == CHIP_RV410 ||
2577                     rdev->family == CHIP_R420 ||
2578                     rdev->family == CHIP_R423)
2579                         trbs_ff = memtrbs_r4xx[data];
2580                 else
2581                         trbs_ff = memtrbs[data];
2582                 tcas_ff.full += trbs_ff.full;
2583         }
2584
2585         sclk_eff_ff.full = sclk_ff.full;
2586
2587         if (rdev->flags & RADEON_IS_AGP) {
2588                 fixed20_12 agpmode_ff;
2589                 agpmode_ff.full = rfixed_const(radeon_agpmode);
2590                 temp_ff.full = rfixed_const_666(16);
2591                 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2592         }
2593         /* TODO PCIE lanes may affect this - agpmode == 16?? */
2594
2595         if (ASIC_IS_R300(rdev)) {
2596                 sclk_delay_ff.full = rfixed_const(250);
2597         } else {
2598                 if ((rdev->family == CHIP_RV100) ||
2599                     rdev->flags & RADEON_IS_IGP) {
2600                         if (rdev->mc.vram_is_ddr)
2601                                 sclk_delay_ff.full = rfixed_const(41);
2602                         else
2603                                 sclk_delay_ff.full = rfixed_const(33);
2604                 } else {
2605                         if (rdev->mc.vram_width == 128)
2606                                 sclk_delay_ff.full = rfixed_const(57);
2607                         else
2608                                 sclk_delay_ff.full = rfixed_const(41);
2609                 }
2610         }
2611
2612         mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2613
2614         if (rdev->mc.vram_is_ddr) {
2615                 if (rdev->mc.vram_width == 32) {
2616                         k1.full = rfixed_const(40);
2617                         c  = 3;
2618                 } else {
2619                         k1.full = rfixed_const(20);
2620                         c  = 1;
2621                 }
2622         } else {
2623                 k1.full = rfixed_const(40);
2624                 c  = 3;
2625         }
2626
2627         temp_ff.full = rfixed_const(2);
2628         mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2629         temp_ff.full = rfixed_const(c);
2630         mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2631         temp_ff.full = rfixed_const(4);
2632         mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2633         mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2634         mc_latency_mclk.full += k1.full;
2635
2636         mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2637         mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2638
2639         /*
2640           HW cursor time assuming worst case of full size colour cursor.
2641         */
2642         temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2643         temp_ff.full += trcd_ff.full;
2644         if (temp_ff.full < tras_ff.full)
2645                 temp_ff.full = tras_ff.full;
2646         cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2647
2648         temp_ff.full = rfixed_const(cur_size);
2649         cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2650         /*
2651           Find the total latency for the display data.
2652         */
2653         disp_latency_overhead.full = rfixed_const(8);
2654         disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2655         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2656         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2657
2658         if (mc_latency_mclk.full > mc_latency_sclk.full)
2659                 disp_latency.full = mc_latency_mclk.full;
2660         else
2661                 disp_latency.full = mc_latency_sclk.full;
2662
2663         /* setup Max GRPH_STOP_REQ default value */
2664         if (ASIC_IS_RV100(rdev))
2665                 max_stop_req = 0x5c;
2666         else
2667                 max_stop_req = 0x7c;
2668
2669         if (mode1) {
2670                 /*  CRTC1
2671                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2672                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2673                 */
2674                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2675
2676                 if (stop_req > max_stop_req)
2677                         stop_req = max_stop_req;
2678
2679                 /*
2680                   Find the drain rate of the display buffer.
2681                 */
2682                 temp_ff.full = rfixed_const((16/pixel_bytes1));
2683                 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2684
2685                 /*
2686                   Find the critical point of the display buffer.
2687                 */
2688                 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2689                 crit_point_ff.full += rfixed_const_half(0);
2690
2691                 critical_point = rfixed_trunc(crit_point_ff);
2692
2693                 if (rdev->disp_priority == 2) {
2694                         critical_point = 0;
2695                 }
2696
2697                 /*
2698                   The critical point should never be above max_stop_req-4.  Setting
2699                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2700                 */
2701                 if (max_stop_req - critical_point < 4)
2702                         critical_point = 0;
2703
2704                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2705                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2706                         critical_point = 0x10;
2707                 }
2708
2709                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2710                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2711                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2712                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2713                 if ((rdev->family == CHIP_R350) &&
2714                     (stop_req > 0x15)) {
2715                         stop_req -= 0x10;
2716                 }
2717                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2718                 temp |= RADEON_GRPH_BUFFER_SIZE;
2719                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2720                           RADEON_GRPH_CRITICAL_AT_SOF |
2721                           RADEON_GRPH_STOP_CNTL);
2722                 /*
2723                   Write the result into the register.
2724                 */
2725                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2726                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2727
2728 #if 0
2729                 if ((rdev->family == CHIP_RS400) ||
2730                     (rdev->family == CHIP_RS480)) {
2731                         /* attempt to program RS400 disp regs correctly ??? */
2732                         temp = RREG32(RS400_DISP1_REG_CNTL);
2733                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2734                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
2735                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2736                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2737                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2738                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
2739                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2740                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2741                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2742                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2743                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2744                 }
2745 #endif
2746
2747                 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2748                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
2749                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2750         }
2751
2752         if (mode2) {
2753                 u32 grph2_cntl;
2754                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2755
2756                 if (stop_req > max_stop_req)
2757                         stop_req = max_stop_req;
2758
2759                 /*
2760                   Find the drain rate of the display buffer.
2761                 */
2762                 temp_ff.full = rfixed_const((16/pixel_bytes2));
2763                 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2764
2765                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2766                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2767                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2768                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2769                 if ((rdev->family == CHIP_R350) &&
2770                     (stop_req > 0x15)) {
2771                         stop_req -= 0x10;
2772                 }
2773                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2774                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2775                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2776                           RADEON_GRPH_CRITICAL_AT_SOF |
2777                           RADEON_GRPH_STOP_CNTL);
2778
2779                 if ((rdev->family == CHIP_RS100) ||
2780                     (rdev->family == CHIP_RS200))
2781                         critical_point2 = 0;
2782                 else {
2783                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2784                         temp_ff.full = rfixed_const(temp);
2785                         temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2786                         if (sclk_ff.full < temp_ff.full)
2787                                 temp_ff.full = sclk_ff.full;
2788
2789                         read_return_rate.full = temp_ff.full;
2790
2791                         if (mode1) {
2792                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2793                                 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2794                         } else {
2795                                 time_disp1_drop_priority.full = 0;
2796                         }
2797                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2798                         crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2799                         crit_point_ff.full += rfixed_const_half(0);
2800
2801                         critical_point2 = rfixed_trunc(crit_point_ff);
2802
2803                         if (rdev->disp_priority == 2) {
2804                                 critical_point2 = 0;
2805                         }
2806
2807                         if (max_stop_req - critical_point2 < 4)
2808                                 critical_point2 = 0;
2809
2810                 }
2811
2812                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2813                         /* some R300 cards have problem with this set to 0 */
2814                         critical_point2 = 0x10;
2815                 }
2816
2817                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2818                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2819
2820                 if ((rdev->family == CHIP_RS400) ||
2821                     (rdev->family == CHIP_RS480)) {
2822 #if 0
2823                         /* attempt to program RS400 disp2 regs correctly ??? */
2824                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
2825                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2826                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
2827                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2828                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2829                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2830                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
2831                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2832                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2833                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2834                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2835                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2836 #endif
2837                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2838                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2839                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
2840                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2841                 }
2842
2843                 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2844                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2845         }
2846 }
2847
2848 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2849 {
2850         DRM_ERROR("pitch                      %d\n", t->pitch);
2851         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
2852         DRM_ERROR("width                      %d\n", t->width);
2853         DRM_ERROR("width_11                   %d\n", t->width_11);
2854         DRM_ERROR("height                     %d\n", t->height);
2855         DRM_ERROR("height_11                  %d\n", t->height_11);
2856         DRM_ERROR("num levels                 %d\n", t->num_levels);
2857         DRM_ERROR("depth                      %d\n", t->txdepth);
2858         DRM_ERROR("bpp                        %d\n", t->cpp);
2859         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
2860         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
2861         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2862         DRM_ERROR("compress format            %d\n", t->compress_format);
2863 }
2864
2865 static int r100_cs_track_cube(struct radeon_device *rdev,
2866                               struct r100_cs_track *track, unsigned idx)
2867 {
2868         unsigned face, w, h;
2869         struct radeon_bo *cube_robj;
2870         unsigned long size;
2871
2872         for (face = 0; face < 5; face++) {
2873                 cube_robj = track->textures[idx].cube_info[face].robj;
2874                 w = track->textures[idx].cube_info[face].width;
2875                 h = track->textures[idx].cube_info[face].height;
2876
2877                 size = w * h;
2878                 size *= track->textures[idx].cpp;
2879
2880                 size += track->textures[idx].cube_info[face].offset;
2881
2882                 if (size > radeon_bo_size(cube_robj)) {
2883                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2884                                   size, radeon_bo_size(cube_robj));
2885                         r100_cs_track_texture_print(&track->textures[idx]);
2886                         return -1;
2887                 }
2888         }
2889         return 0;
2890 }
2891
2892 static int r100_track_compress_size(int compress_format, int w, int h)
2893 {
2894         int block_width, block_height, block_bytes;
2895         int wblocks, hblocks;
2896         int min_wblocks;
2897         int sz;
2898
2899         block_width = 4;
2900         block_height = 4;
2901
2902         switch (compress_format) {
2903         case R100_TRACK_COMP_DXT1:
2904                 block_bytes = 8;
2905                 min_wblocks = 4;
2906                 break;
2907         default:
2908         case R100_TRACK_COMP_DXT35:
2909                 block_bytes = 16;
2910                 min_wblocks = 2;
2911                 break;
2912         }
2913
2914         hblocks = (h + block_height - 1) / block_height;
2915         wblocks = (w + block_width - 1) / block_width;
2916         if (wblocks < min_wblocks)
2917                 wblocks = min_wblocks;
2918         sz = wblocks * hblocks * block_bytes;
2919         return sz;
2920 }
2921
2922 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2923                                        struct r100_cs_track *track)
2924 {
2925         struct radeon_bo *robj;
2926         unsigned long size;
2927         unsigned u, i, w, h;
2928         int ret;
2929
2930         for (u = 0; u < track->num_texture; u++) {
2931                 if (!track->textures[u].enabled)
2932                         continue;
2933                 robj = track->textures[u].robj;
2934                 if (robj == NULL) {
2935                         DRM_ERROR("No texture bound to unit %u\n", u);
2936                         return -EINVAL;
2937                 }
2938                 size = 0;
2939                 for (i = 0; i <= track->textures[u].num_levels; i++) {
2940                         if (track->textures[u].use_pitch) {
2941                                 if (rdev->family < CHIP_R300)
2942                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2943                                 else
2944                                         w = track->textures[u].pitch / (1 << i);
2945                         } else {
2946                                 w = track->textures[u].width;
2947                                 if (rdev->family >= CHIP_RV515)
2948                                         w |= track->textures[u].width_11;
2949                                 w = w / (1 << i);
2950                                 if (track->textures[u].roundup_w)
2951                                         w = roundup_pow_of_two(w);
2952                         }
2953                         h = track->textures[u].height;
2954                         if (rdev->family >= CHIP_RV515)
2955                                 h |= track->textures[u].height_11;
2956                         h = h / (1 << i);
2957                         if (track->textures[u].roundup_h)
2958                                 h = roundup_pow_of_two(h);
2959                         if (track->textures[u].compress_format) {
2960
2961                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h);
2962                                 /* compressed textures are block based */
2963                         } else
2964                                 size += w * h;
2965                 }
2966                 size *= track->textures[u].cpp;
2967
2968                 switch (track->textures[u].tex_coord_type) {
2969                 case 0:
2970                         break;
2971                 case 1:
2972                         size *= (1 << track->textures[u].txdepth);
2973                         break;
2974                 case 2:
2975                         if (track->separate_cube) {
2976                                 ret = r100_cs_track_cube(rdev, track, u);
2977                                 if (ret)
2978                                         return ret;
2979                         } else
2980                                 size *= 6;
2981                         break;
2982                 default:
2983                         DRM_ERROR("Invalid texture coordinate type %u for unit "
2984                                   "%u\n", track->textures[u].tex_coord_type, u);
2985                         return -EINVAL;
2986                 }
2987                 if (size > radeon_bo_size(robj)) {
2988                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2989                                   "%lu\n", u, size, radeon_bo_size(robj));
2990                         r100_cs_track_texture_print(&track->textures[u]);
2991                         return -EINVAL;
2992                 }
2993         }
2994         return 0;
2995 }
2996
2997 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2998 {
2999         unsigned i;
3000         unsigned long size;
3001         unsigned prim_walk;
3002         unsigned nverts;
3003
3004         for (i = 0; i < track->num_cb; i++) {
3005                 if (track->cb[i].robj == NULL) {
3006                         if (!(track->fastfill || track->color_channel_mask ||
3007                               track->blend_read_enable)) {
3008                                 continue;
3009                         }
3010                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3011                         return -EINVAL;
3012                 }
3013                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3014                 size += track->cb[i].offset;
3015                 if (size > radeon_bo_size(track->cb[i].robj)) {
3016                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
3017                                   "(need %lu have %lu) !\n", i, size,
3018                                   radeon_bo_size(track->cb[i].robj));
3019                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3020                                   i, track->cb[i].pitch, track->cb[i].cpp,
3021                                   track->cb[i].offset, track->maxy);
3022                         return -EINVAL;
3023                 }
3024         }
3025         if (track->z_enabled) {
3026                 if (track->zb.robj == NULL) {
3027                         DRM_ERROR("[drm] No buffer for z buffer !\n");
3028                         return -EINVAL;
3029                 }
3030                 size = track->zb.pitch * track->zb.cpp * track->maxy;
3031                 size += track->zb.offset;
3032                 if (size > radeon_bo_size(track->zb.robj)) {
3033                         DRM_ERROR("[drm] Buffer too small for z buffer "
3034                                   "(need %lu have %lu) !\n", size,
3035                                   radeon_bo_size(track->zb.robj));
3036                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3037                                   track->zb.pitch, track->zb.cpp,
3038                                   track->zb.offset, track->maxy);
3039                         return -EINVAL;
3040                 }
3041         }
3042         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3043         nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3044         switch (prim_walk) {
3045         case 1:
3046                 for (i = 0; i < track->num_arrays; i++) {
3047                         size = track->arrays[i].esize * track->max_indx * 4;
3048                         if (track->arrays[i].robj == NULL) {
3049                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3050                                           "bound\n", prim_walk, i);
3051                                 return -EINVAL;
3052                         }
3053                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3054                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3055                                         "need %lu dwords have %lu dwords\n",
3056                                         prim_walk, i, size >> 2,
3057                                         radeon_bo_size(track->arrays[i].robj)
3058                                         >> 2);
3059                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3060                                 return -EINVAL;
3061                         }
3062                 }
3063                 break;
3064         case 2:
3065                 for (i = 0; i < track->num_arrays; i++) {
3066                         size = track->arrays[i].esize * (nverts - 1) * 4;
3067                         if (track->arrays[i].robj == NULL) {
3068                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3069                                           "bound\n", prim_walk, i);
3070                                 return -EINVAL;
3071                         }
3072                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3073                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3074                                         "need %lu dwords have %lu dwords\n",
3075                                         prim_walk, i, size >> 2,
3076                                         radeon_bo_size(track->arrays[i].robj)
3077                                         >> 2);
3078                                 return -EINVAL;
3079                         }
3080                 }
3081                 break;
3082         case 3:
3083                 size = track->vtx_size * nverts;
3084                 if (size != track->immd_dwords) {
3085                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3086                                   track->immd_dwords, size);
3087                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3088                                   nverts, track->vtx_size);
3089                         return -EINVAL;
3090                 }
3091                 break;
3092         default:
3093                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3094                           prim_walk);
3095                 return -EINVAL;
3096         }
3097         return r100_cs_track_texture_check(rdev, track);
3098 }
3099
3100 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3101 {
3102         unsigned i, face;
3103
3104         if (rdev->family < CHIP_R300) {
3105                 track->num_cb = 1;
3106                 if (rdev->family <= CHIP_RS200)
3107                         track->num_texture = 3;
3108                 else
3109                         track->num_texture = 6;
3110                 track->maxy = 2048;
3111                 track->separate_cube = 1;
3112         } else {
3113                 track->num_cb = 4;
3114                 track->num_texture = 16;
3115                 track->maxy = 4096;
3116                 track->separate_cube = 0;
3117         }
3118
3119         for (i = 0; i < track->num_cb; i++) {
3120                 track->cb[i].robj = NULL;
3121                 track->cb[i].pitch = 8192;
3122                 track->cb[i].cpp = 16;
3123                 track->cb[i].offset = 0;
3124         }
3125         track->z_enabled = true;
3126         track->zb.robj = NULL;
3127         track->zb.pitch = 8192;
3128         track->zb.cpp = 4;
3129         track->zb.offset = 0;
3130         track->vtx_size = 0x7F;
3131         track->immd_dwords = 0xFFFFFFFFUL;
3132         track->num_arrays = 11;
3133         track->max_indx = 0x00FFFFFFUL;
3134         for (i = 0; i < track->num_arrays; i++) {
3135                 track->arrays[i].robj = NULL;
3136                 track->arrays[i].esize = 0x7F;
3137         }
3138         for (i = 0; i < track->num_texture; i++) {
3139                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3140                 track->textures[i].pitch = 16536;
3141                 track->textures[i].width = 16536;
3142                 track->textures[i].height = 16536;
3143                 track->textures[i].width_11 = 1 << 11;
3144                 track->textures[i].height_11 = 1 << 11;
3145                 track->textures[i].num_levels = 12;
3146                 if (rdev->family <= CHIP_RS200) {
3147                         track->textures[i].tex_coord_type = 0;
3148                         track->textures[i].txdepth = 0;
3149                 } else {
3150                         track->textures[i].txdepth = 16;
3151                         track->textures[i].tex_coord_type = 1;
3152                 }
3153                 track->textures[i].cpp = 64;
3154                 track->textures[i].robj = NULL;
3155                 /* CS IB emission code makes sure texture unit are disabled */
3156                 track->textures[i].enabled = false;
3157                 track->textures[i].roundup_w = true;
3158                 track->textures[i].roundup_h = true;
3159                 if (track->separate_cube)
3160                         for (face = 0; face < 5; face++) {
3161                                 track->textures[i].cube_info[face].robj = NULL;
3162                                 track->textures[i].cube_info[face].width = 16536;
3163                                 track->textures[i].cube_info[face].height = 16536;
3164                                 track->textures[i].cube_info[face].offset = 0;
3165                         }
3166         }
3167 }
3168
3169 int r100_ring_test(struct radeon_device *rdev)
3170 {
3171         uint32_t scratch;
3172         uint32_t tmp = 0;
3173         unsigned i;
3174         int r;
3175
3176         r = radeon_scratch_get(rdev, &scratch);
3177         if (r) {
3178                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3179                 return r;
3180         }
3181         WREG32(scratch, 0xCAFEDEAD);
3182         r = radeon_ring_lock(rdev, 2);
3183         if (r) {
3184                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3185                 radeon_scratch_free(rdev, scratch);
3186                 return r;
3187         }
3188         radeon_ring_write(rdev, PACKET0(scratch, 0));
3189         radeon_ring_write(rdev, 0xDEADBEEF);
3190         radeon_ring_unlock_commit(rdev);
3191         for (i = 0; i < rdev->usec_timeout; i++) {
3192                 tmp = RREG32(scratch);
3193                 if (tmp == 0xDEADBEEF) {
3194                         break;
3195                 }
3196                 DRM_UDELAY(1);
3197         }
3198         if (i < rdev->usec_timeout) {
3199                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3200         } else {
3201                 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3202                           scratch, tmp);
3203                 r = -EINVAL;
3204         }
3205         radeon_scratch_free(rdev, scratch);
3206         return r;
3207 }
3208
3209 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3210 {
3211         radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3212         radeon_ring_write(rdev, ib->gpu_addr);
3213         radeon_ring_write(rdev, ib->length_dw);
3214 }
3215
3216 int r100_ib_test(struct radeon_device *rdev)
3217 {
3218         struct radeon_ib *ib;
3219         uint32_t scratch;
3220         uint32_t tmp = 0;
3221         unsigned i;
3222         int r;
3223
3224         r = radeon_scratch_get(rdev, &scratch);
3225         if (r) {
3226                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3227                 return r;
3228         }
3229         WREG32(scratch, 0xCAFEDEAD);
3230         r = radeon_ib_get(rdev, &ib);
3231         if (r) {
3232                 return r;
3233         }
3234         ib->ptr[0] = PACKET0(scratch, 0);
3235         ib->ptr[1] = 0xDEADBEEF;
3236         ib->ptr[2] = PACKET2(0);
3237         ib->ptr[3] = PACKET2(0);
3238         ib->ptr[4] = PACKET2(0);
3239         ib->ptr[5] = PACKET2(0);
3240         ib->ptr[6] = PACKET2(0);
3241         ib->ptr[7] = PACKET2(0);
3242         ib->length_dw = 8;
3243         r = radeon_ib_schedule(rdev, ib);
3244         if (r) {
3245                 radeon_scratch_free(rdev, scratch);
3246                 radeon_ib_free(rdev, &ib);
3247                 return r;
3248         }
3249         r = radeon_fence_wait(ib->fence, false);
3250         if (r) {
3251                 return r;
3252         }
3253         for (i = 0; i < rdev->usec_timeout; i++) {
3254                 tmp = RREG32(scratch);
3255                 if (tmp == 0xDEADBEEF) {
3256                         break;
3257                 }
3258                 DRM_UDELAY(1);
3259         }
3260         if (i < rdev->usec_timeout) {
3261                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3262         } else {
3263                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3264                           scratch, tmp);
3265                 r = -EINVAL;
3266         }
3267         radeon_scratch_free(rdev, scratch);
3268         radeon_ib_free(rdev, &ib);
3269         return r;
3270 }
3271
3272 void r100_ib_fini(struct radeon_device *rdev)
3273 {
3274         radeon_ib_pool_fini(rdev);
3275 }
3276
3277 int r100_ib_init(struct radeon_device *rdev)
3278 {
3279         int r;
3280
3281         r = radeon_ib_pool_init(rdev);
3282         if (r) {
3283                 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3284                 r100_ib_fini(rdev);
3285                 return r;
3286         }
3287         r = r100_ib_test(rdev);
3288         if (r) {
3289                 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3290                 r100_ib_fini(rdev);
3291                 return r;
3292         }
3293         return 0;
3294 }
3295
3296 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3297 {
3298         /* Shutdown CP we shouldn't need to do that but better be safe than
3299          * sorry
3300          */
3301         rdev->cp.ready = false;
3302         WREG32(R_000740_CP_CSQ_CNTL, 0);
3303
3304         /* Save few CRTC registers */
3305         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3306         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3307         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3308         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3309         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3310                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3311                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3312         }
3313
3314         /* Disable VGA aperture access */
3315         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3316         /* Disable cursor, overlay, crtc */
3317         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3318         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3319                                         S_000054_CRTC_DISPLAY_DIS(1));
3320         WREG32(R_000050_CRTC_GEN_CNTL,
3321                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3322                         S_000050_CRTC_DISP_REQ_EN_B(1));
3323         WREG32(R_000420_OV0_SCALE_CNTL,
3324                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3325         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3326         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3327                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3328                                                 S_000360_CUR2_LOCK(1));
3329                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3330                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3331                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3332                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3333                 WREG32(R_000360_CUR2_OFFSET,
3334                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3335         }
3336 }
3337
3338 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3339 {
3340         /* Update base address for crtc */
3341         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3342         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3343                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3344         }
3345         /* Restore CRTC registers */
3346         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3347         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3348         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3349         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3350                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3351         }
3352 }
3353
3354 void r100_vga_render_disable(struct radeon_device *rdev)
3355 {
3356         u32 tmp;
3357
3358         tmp = RREG8(R_0003C2_GENMO_WT);
3359         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3360 }
3361
3362 static void r100_debugfs(struct radeon_device *rdev)
3363 {
3364         int r;
3365
3366         r = r100_debugfs_mc_info_init(rdev);
3367         if (r)
3368                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3369 }
3370
3371 static void r100_mc_program(struct radeon_device *rdev)
3372 {
3373         struct r100_mc_save save;
3374
3375         /* Stops all mc clients */
3376         r100_mc_stop(rdev, &save);
3377         if (rdev->flags & RADEON_IS_AGP) {
3378                 WREG32(R_00014C_MC_AGP_LOCATION,
3379                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3380                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3381                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3382                 if (rdev->family > CHIP_RV200)
3383                         WREG32(R_00015C_AGP_BASE_2,
3384                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3385         } else {
3386                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3387                 WREG32(R_000170_AGP_BASE, 0);
3388                 if (rdev->family > CHIP_RV200)
3389                         WREG32(R_00015C_AGP_BASE_2, 0);
3390         }
3391         /* Wait for mc idle */
3392         if (r100_mc_wait_for_idle(rdev))
3393                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3394         /* Program MC, should be a 32bits limited address space */
3395         WREG32(R_000148_MC_FB_LOCATION,
3396                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3397                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3398         r100_mc_resume(rdev, &save);
3399 }
3400
3401 void r100_clock_startup(struct radeon_device *rdev)
3402 {
3403         u32 tmp;
3404
3405         if (radeon_dynclks != -1 && radeon_dynclks)
3406                 radeon_legacy_set_clock_gating(rdev, 1);
3407         /* We need to force on some of the block */
3408         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3409         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3410         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3411                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3412         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3413 }
3414
3415 static int r100_startup(struct radeon_device *rdev)
3416 {
3417         int r;
3418
3419         /* set common regs */
3420         r100_set_common_regs(rdev);
3421         /* program mc */
3422         r100_mc_program(rdev);
3423         /* Resume clock */
3424         r100_clock_startup(rdev);
3425         /* Initialize GPU configuration (# pipes, ...) */
3426 //      r100_gpu_init(rdev);
3427         /* Initialize GART (initialize after TTM so we can allocate
3428          * memory through TTM but finalize after TTM) */
3429         r100_enable_bm(rdev);
3430         if (rdev->flags & RADEON_IS_PCI) {
3431                 r = r100_pci_gart_enable(rdev);
3432                 if (r)
3433                         return r;
3434         }
3435         /* Enable IRQ */
3436         r100_irq_set(rdev);
3437         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3438         /* 1M ring buffer */
3439         r = r100_cp_init(rdev, 1024 * 1024);
3440         if (r) {
3441                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3442                 return r;
3443         }
3444         r = r100_wb_init(rdev);
3445         if (r)
3446                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3447         r = r100_ib_init(rdev);
3448         if (r) {
3449                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3450                 return r;
3451         }
3452         return 0;
3453 }
3454
3455 int r100_resume(struct radeon_device *rdev)
3456 {
3457         /* Make sur GART are not working */
3458         if (rdev->flags & RADEON_IS_PCI)
3459                 r100_pci_gart_disable(rdev);
3460         /* Resume clock before doing reset */
3461         r100_clock_startup(rdev);
3462         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3463         if (radeon_asic_reset(rdev)) {
3464                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3465                         RREG32(R_000E40_RBBM_STATUS),
3466                         RREG32(R_0007C0_CP_STAT));
3467         }
3468         /* post */
3469         radeon_combios_asic_init(rdev->ddev);
3470         /* Resume clock after posting */
3471         r100_clock_startup(rdev);
3472         /* Initialize surface registers */
3473         radeon_surface_init(rdev);
3474         return r100_startup(rdev);
3475 }
3476
3477 int r100_suspend(struct radeon_device *rdev)
3478 {
3479         r100_cp_disable(rdev);
3480         r100_wb_disable(rdev);
3481         r100_irq_disable(rdev);
3482         if (rdev->flags & RADEON_IS_PCI)
3483                 r100_pci_gart_disable(rdev);
3484         return 0;
3485 }
3486
3487 void r100_fini(struct radeon_device *rdev)
3488 {
3489         radeon_pm_fini(rdev);
3490         r100_cp_fini(rdev);
3491         r100_wb_fini(rdev);
3492         r100_ib_fini(rdev);
3493         radeon_gem_fini(rdev);
3494         if (rdev->flags & RADEON_IS_PCI)
3495                 r100_pci_gart_fini(rdev);
3496         radeon_agp_fini(rdev);
3497         radeon_irq_kms_fini(rdev);
3498         radeon_fence_driver_fini(rdev);
3499         radeon_bo_fini(rdev);
3500         radeon_atombios_fini(rdev);
3501         kfree(rdev->bios);
3502         rdev->bios = NULL;
3503 }
3504
3505 int r100_init(struct radeon_device *rdev)
3506 {
3507         int r;
3508
3509         /* Register debugfs file specific to this group of asics */
3510         r100_debugfs(rdev);
3511         /* Disable VGA */
3512         r100_vga_render_disable(rdev);
3513         /* Initialize scratch registers */
3514         radeon_scratch_init(rdev);
3515         /* Initialize surface registers */
3516         radeon_surface_init(rdev);
3517         /* TODO: disable VGA need to use VGA request */
3518         /* BIOS*/
3519         if (!radeon_get_bios(rdev)) {
3520                 if (ASIC_IS_AVIVO(rdev))
3521                         return -EINVAL;
3522         }
3523         if (rdev->is_atom_bios) {
3524                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3525                 return -EINVAL;
3526         } else {
3527                 r = radeon_combios_init(rdev);
3528                 if (r)
3529                         return r;
3530         }
3531         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3532         if (radeon_asic_reset(rdev)) {
3533                 dev_warn(rdev->dev,
3534                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3535                         RREG32(R_000E40_RBBM_STATUS),
3536                         RREG32(R_0007C0_CP_STAT));
3537         }
3538         /* check if cards are posted or not */
3539         if (radeon_boot_test_post_card(rdev) == false)
3540                 return -EINVAL;
3541         /* Set asic errata */
3542         r100_errata(rdev);
3543         /* Initialize clocks */
3544         radeon_get_clock_info(rdev->ddev);
3545         /* Initialize power management */
3546         radeon_pm_init(rdev);
3547         /* initialize AGP */
3548         if (rdev->flags & RADEON_IS_AGP) {
3549                 r = radeon_agp_init(rdev);
3550                 if (r) {
3551                         radeon_agp_disable(rdev);
3552                 }
3553         }
3554         /* initialize VRAM */
3555         r100_mc_init(rdev);
3556         /* Fence driver */
3557         r = radeon_fence_driver_init(rdev);
3558         if (r)
3559                 return r;
3560         r = radeon_irq_kms_init(rdev);
3561         if (r)
3562                 return r;
3563         /* Memory manager */
3564         r = radeon_bo_init(rdev);
3565         if (r)
3566                 return r;
3567         if (rdev->flags & RADEON_IS_PCI) {
3568                 r = r100_pci_gart_init(rdev);
3569                 if (r)
3570                         return r;
3571         }
3572         r100_set_safe_registers(rdev);
3573         rdev->accel_working = true;
3574         r = r100_startup(rdev);
3575         if (r) {
3576                 /* Somethings want wront with the accel init stop accel */
3577                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3578                 r100_cp_fini(rdev);
3579                 r100_wb_fini(rdev);
3580                 r100_ib_fini(rdev);
3581                 radeon_irq_kms_fini(rdev);
3582                 if (rdev->flags & RADEON_IS_PCI)
3583                         r100_pci_gart_fini(rdev);
3584                 rdev->accel_working = false;
3585         }
3586         return 0;
3587 }