drivers/gpu/drm/radeon/ni.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include "drmP.h"
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include "radeon_drm.h"
  31 #include "nid.h"
  32 #include "atom.h"
  33 #include "ni_reg.h"
  34 #include "cayman_blit_shaders.h"
  35
  36 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
  37 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
  38 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
  39 extern void evergreen_mc_program(struct radeon_device *rdev);
  40 extern void evergreen_irq_suspend(struct radeon_device *rdev);
  41 extern int evergreen_mc_init(struct radeon_device *rdev);
  42 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
  43 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  44
  45 #define EVERGREEN_PFP_UCODE_SIZE 1120
  46 #define EVERGREEN_PM4_UCODE_SIZE 1376
  47 #define EVERGREEN_RLC_UCODE_SIZE 768
  48 #define BTC_MC_UCODE_SIZE 6024
  49
  50 #define CAYMAN_PFP_UCODE_SIZE 2176
  51 #define CAYMAN_PM4_UCODE_SIZE 2176
  52 #define CAYMAN_RLC_UCODE_SIZE 1024
  53 #define CAYMAN_MC_UCODE_SIZE 6037
  54
  55 /* Firmware Names */
  56 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
  57 MODULE_FIRMWARE("radeon/BARTS_me.bin");
  58 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
  59 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
  60 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
  61 MODULE_FIRMWARE("radeon/TURKS_me.bin");
  62 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
  63 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
  64 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
  65 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
  66 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
  67 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
  68 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
  69 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
  70
  71 #define BTC_IO_MC_REGS_SIZE 29
  72
  73 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
  74         {0x00000077, 0xff010100},
  75         {0x00000078, 0x00000000},
  76         {0x00000079, 0x00001434},
  77         {0x0000007a, 0xcc08ec08},
  78         {0x0000007b, 0x00040000},
  79         {0x0000007c, 0x000080c0},
  80         {0x0000007d, 0x09000000},
  81         {0x0000007e, 0x00210404},
  82         {0x00000081, 0x08a8e800},
  83         {0x00000082, 0x00030444},
  84         {0x00000083, 0x00000000},
  85         {0x00000085, 0x00000001},
  86         {0x00000086, 0x00000002},
  87         {0x00000087, 0x48490000},
  88         {0x00000088, 0x20244647},
  89         {0x00000089, 0x00000005},
  90         {0x0000008b, 0x66030000},
  91         {0x0000008c, 0x00006603},
  92         {0x0000008d, 0x00000100},
  93         {0x0000008f, 0x00001c0a},
  94         {0x00000090, 0xff000001},
  95         {0x00000094, 0x00101101},
  96         {0x00000095, 0x00000fff},
  97         {0x00000096, 0x00116fff},
  98         {0x00000097, 0x60010000},
  99         {0x00000098, 0x10010000},
 100         {0x00000099, 0x00006000},
 101         {0x0000009a, 0x00001000},
 102         {0x0000009f, 0x00946a00}
 103 };
 104
 105 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 106         {0x00000077, 0xff010100},
 107         {0x00000078, 0x00000000},
 108         {0x00000079, 0x00001434},
 109         {0x0000007a, 0xcc08ec08},
 110         {0x0000007b, 0x00040000},
 111         {0x0000007c, 0x000080c0},
 112         {0x0000007d, 0x09000000},
 113         {0x0000007e, 0x00210404},
 114         {0x00000081, 0x08a8e800},
 115         {0x00000082, 0x00030444},
 116         {0x00000083, 0x00000000},
 117         {0x00000085, 0x00000001},
 118         {0x00000086, 0x00000002},
 119         {0x00000087, 0x48490000},
 120         {0x00000088, 0x20244647},
 121         {0x00000089, 0x00000005},
 122         {0x0000008b, 0x66030000},
 123         {0x0000008c, 0x00006603},
 124         {0x0000008d, 0x00000100},
 125         {0x0000008f, 0x00001c0a},
 126         {0x00000090, 0xff000001},
 127         {0x00000094, 0x00101101},
 128         {0x00000095, 0x00000fff},
 129         {0x00000096, 0x00116fff},
 130         {0x00000097, 0x60010000},
 131         {0x00000098, 0x10010000},
 132         {0x00000099, 0x00006000},
 133         {0x0000009a, 0x00001000},
 134         {0x0000009f, 0x00936a00}
 135 };
 136
 137 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 138         {0x00000077, 0xff010100},
 139         {0x00000078, 0x00000000},
 140         {0x00000079, 0x00001434},
 141         {0x0000007a, 0xcc08ec08},
 142         {0x0000007b, 0x00040000},
 143         {0x0000007c, 0x000080c0},
 144         {0x0000007d, 0x09000000},
 145         {0x0000007e, 0x00210404},
 146         {0x00000081, 0x08a8e800},
 147         {0x00000082, 0x00030444},
 148         {0x00000083, 0x00000000},
 149         {0x00000085, 0x00000001},
 150         {0x00000086, 0x00000002},
 151         {0x00000087, 0x48490000},
 152         {0x00000088, 0x20244647},
 153         {0x00000089, 0x00000005},
 154         {0x0000008b, 0x66030000},
 155         {0x0000008c, 0x00006603},
 156         {0x0000008d, 0x00000100},
 157         {0x0000008f, 0x00001c0a},
 158         {0x00000090, 0xff000001},
 159         {0x00000094, 0x00101101},
 160         {0x00000095, 0x00000fff},
 161         {0x00000096, 0x00116fff},
 162         {0x00000097, 0x60010000},
 163         {0x00000098, 0x10010000},
 164         {0x00000099, 0x00006000},
 165         {0x0000009a, 0x00001000},
 166         {0x0000009f, 0x00916a00}
 167 };
 168
 169 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 170         {0x00000077, 0xff010100},
 171         {0x00000078, 0x00000000},
 172         {0x00000079, 0x00001434},
 173         {0x0000007a, 0xcc08ec08},
 174         {0x0000007b, 0x00040000},
 175         {0x0000007c, 0x000080c0},
 176         {0x0000007d, 0x09000000},
 177         {0x0000007e, 0x00210404},
 178         {0x00000081, 0x08a8e800},
 179         {0x00000082, 0x00030444},
 180         {0x00000083, 0x00000000},
 181         {0x00000085, 0x00000001},
 182         {0x00000086, 0x00000002},
 183         {0x00000087, 0x48490000},
 184         {0x00000088, 0x20244647},
 185         {0x00000089, 0x00000005},
 186         {0x0000008b, 0x66030000},
 187         {0x0000008c, 0x00006603},
 188         {0x0000008d, 0x00000100},
 189         {0x0000008f, 0x00001c0a},
 190         {0x00000090, 0xff000001},
 191         {0x00000094, 0x00101101},
 192         {0x00000095, 0x00000fff},
 193         {0x00000096, 0x00116fff},
 194         {0x00000097, 0x60010000},
 195         {0x00000098, 0x10010000},
 196         {0x00000099, 0x00006000},
 197         {0x0000009a, 0x00001000},
 198         {0x0000009f, 0x00976b00}
 199 };
 200
 201 int ni_mc_load_microcode(struct radeon_device *rdev)
 202 {
 203         const __be32 *fw_data;
 204         u32 mem_type, running, blackout = 0;
 205         u32 *io_mc_regs;
 206         int i, ucode_size, regs_size;
 207
 208         if (!rdev->mc_fw)
 209                 return -EINVAL;
 210
 211         switch (rdev->family) {
 212         case CHIP_BARTS:
 213                 io_mc_regs = (u32 *)&barts_io_mc_regs;
 214                 ucode_size = BTC_MC_UCODE_SIZE;
 215                 regs_size = BTC_IO_MC_REGS_SIZE;
 216                 break;
 217         case CHIP_TURKS:
 218                 io_mc_regs = (u32 *)&turks_io_mc_regs;
 219                 ucode_size = BTC_MC_UCODE_SIZE;
 220                 regs_size = BTC_IO_MC_REGS_SIZE;
 221                 break;
 222         case CHIP_CAICOS:
 223         default:
 224                 io_mc_regs = (u32 *)&caicos_io_mc_regs;
 225                 ucode_size = BTC_MC_UCODE_SIZE;
 226                 regs_size = BTC_IO_MC_REGS_SIZE;
 227                 break;
 228         case CHIP_CAYMAN:
 229                 io_mc_regs = (u32 *)&cayman_io_mc_regs;
 230                 ucode_size = CAYMAN_MC_UCODE_SIZE;
 231                 regs_size = BTC_IO_MC_REGS_SIZE;
 232                 break;
 233         }
 234
 235         mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
 236         running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
 237
 238         if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
 239                 if (running) {
 240                         blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
 241                         WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
 242                 }
 243
 244                 /* reset the engine and set to writable */
 245                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 246                 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
 247
 248                 /* load mc io regs */
 249                 for (i = 0; i < regs_size; i++) {
 250                         WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
 251                         WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
 252                 }
 253                 /* load the MC ucode */
 254                 fw_data = (const __be32 *)rdev->mc_fw->data;
 255                 for (i = 0; i < ucode_size; i++)
 256                         WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
 257
 258                 /* put the engine back into the active state */
 259                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 260                 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
 261                 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
 262
 263                 /* wait for training to complete */
 264                 while (!(RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD))
 265                         udelay(10);
 266
 267                 if (running)
 268                         WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
 269         }
 270
 271         return 0;
 272 }
 273
 274 int ni_init_microcode(struct radeon_device *rdev)
 275 {
 276         struct platform_device *pdev;
 277         const char *chip_name;
 278         const char *rlc_chip_name;
 279         size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
 280         char fw_name[30];
 281         int err;
 282
 283         DRM_DEBUG("\n");
 284
 285         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 286         err = IS_ERR(pdev);
 287         if (err) {
 288                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 289                 return -EINVAL;
 290         }
 291
 292         switch (rdev->family) {
 293         case CHIP_BARTS:
 294                 chip_name = "BARTS";
 295                 rlc_chip_name = "BTC";
 296                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 297                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 298                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 299                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 300                 break;
 301         case CHIP_TURKS:
 302                 chip_name = "TURKS";
 303                 rlc_chip_name = "BTC";
 304                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 305                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 306                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 307                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 308                 break;
 309         case CHIP_CAICOS:
 310                 chip_name = "CAICOS";
 311                 rlc_chip_name = "BTC";
 312                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 313                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 314                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 315                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 316                 break;
 317         case CHIP_CAYMAN:
 318                 chip_name = "CAYMAN";
 319                 rlc_chip_name = "CAYMAN";
 320                 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
 321                 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
 322                 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
 323                 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
 324                 break;
 325         default: BUG();
 326         }
 327
 328         DRM_INFO("Loading %s Microcode\n", chip_name);
 329
 330         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 331         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
 332         if (err)
 333                 goto out;
 334         if (rdev->pfp_fw->size != pfp_req_size) {
 335                 printk(KERN_ERR
 336                        "ni_cp: Bogus length %zu in firmware \"%s\"\n",
 337                        rdev->pfp_fw->size, fw_name);
 338                 err = -EINVAL;
 339                 goto out;
 340         }
 341
 342         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 343         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 344         if (err)
 345                 goto out;
 346         if (rdev->me_fw->size != me_req_size) {
 347                 printk(KERN_ERR
 348                        "ni_cp: Bogus length %zu in firmware \"%s\"\n",
 349                        rdev->me_fw->size, fw_name);
 350                 err = -EINVAL;
 351         }
 352
 353         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
 354         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
 355         if (err)
 356                 goto out;
 357         if (rdev->rlc_fw->size != rlc_req_size) {
 358                 printk(KERN_ERR
 359                        "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
 360                        rdev->rlc_fw->size, fw_name);
 361                 err = -EINVAL;
 362         }
 363
 364         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 365         err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
 366         if (err)
 367                 goto out;
 368         if (rdev->mc_fw->size != mc_req_size) {
 369                 printk(KERN_ERR
 370                        "ni_mc: Bogus length %zu in firmware \"%s\"\n",
 371                        rdev->mc_fw->size, fw_name);
 372                 err = -EINVAL;
 373         }
 374 out:
 375         platform_device_unregister(pdev);
 376
 377         if (err) {
 378                 if (err != -EINVAL)
 379                         printk(KERN_ERR
 380                                "ni_cp: Failed to load firmware \"%s\"\n",
 381                                fw_name);
 382                 release_firmware(rdev->pfp_fw);
 383                 rdev->pfp_fw = NULL;
 384                 release_firmware(rdev->me_fw);
 385                 rdev->me_fw = NULL;
 386                 release_firmware(rdev->rlc_fw);
 387                 rdev->rlc_fw = NULL;
 388                 release_firmware(rdev->mc_fw);
 389                 rdev->mc_fw = NULL;
 390         }
 391         return err;
 392 }
 393
 394 /*
 395  * Core functions
 396  */
 397 static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
 398                                                u32 num_tile_pipes,
 399                                                u32 num_backends_per_asic,
 400                                                u32 *backend_disable_mask_per_asic,
 401                                                u32 num_shader_engines)
 402 {
 403         u32 backend_map = 0;
 404         u32 enabled_backends_mask = 0;
 405         u32 enabled_backends_count = 0;
 406         u32 num_backends_per_se;
 407         u32 cur_pipe;
 408         u32 swizzle_pipe[CAYMAN_MAX_PIPES];
 409         u32 cur_backend = 0;
 410         u32 i;
 411         bool force_no_swizzle;
 412
 413         /* force legal values */
 414         if (num_tile_pipes < 1)
 415                 num_tile_pipes = 1;
 416         if (num_tile_pipes > rdev->config.cayman.max_tile_pipes)
 417                 num_tile_pipes = rdev->config.cayman.max_tile_pipes;
 418         if (num_shader_engines < 1)
 419                 num_shader_engines = 1;
 420         if (num_shader_engines > rdev->config.cayman.max_shader_engines)
 421                 num_shader_engines = rdev->config.cayman.max_shader_engines;
 422         if (num_backends_per_asic < num_shader_engines)
 423                 num_backends_per_asic = num_shader_engines;
 424         if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines))
 425                 num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines;
 426
 427         /* make sure we have the same number of backends per se */
 428         num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
 429         /* set up the number of backends per se */
 430         num_backends_per_se = num_backends_per_asic / num_shader_engines;
 431         if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) {
 432                 num_backends_per_se = rdev->config.cayman.max_backends_per_se;
 433                 num_backends_per_asic = num_backends_per_se * num_shader_engines;
 434         }
 435
 436         /* create enable mask and count for enabled backends */
 437         for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
 438                 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
 439                         enabled_backends_mask |= (1 << i);
 440                         ++enabled_backends_count;
 441                 }
 442                 if (enabled_backends_count == num_backends_per_asic)
 443                         break;
 444         }
 445
 446         /* force the backends mask to match the current number of backends */
 447         if (enabled_backends_count != num_backends_per_asic) {
 448                 u32 this_backend_enabled;
 449                 u32 shader_engine;
 450                 u32 backend_per_se;
 451
 452                 enabled_backends_mask = 0;
 453                 enabled_backends_count = 0;
 454                 *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK;
 455                 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
 456                         /* calc the current se */
 457                         shader_engine = i / rdev->config.cayman.max_backends_per_se;
 458                         /* calc the backend per se */
 459                         backend_per_se = i % rdev->config.cayman.max_backends_per_se;
 460                         /* default to not enabled */
 461                         this_backend_enabled = 0;
 462                         if ((shader_engine < num_shader_engines) &&
 463                             (backend_per_se < num_backends_per_se))
 464                                 this_backend_enabled = 1;
 465                         if (this_backend_enabled) {
 466                                 enabled_backends_mask |= (1 << i);
 467                                 *backend_disable_mask_per_asic &= ~(1 << i);
 468                                 ++enabled_backends_count;
 469                         }
 470                 }
 471         }
 472
 473
 474         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES);
 475         switch (rdev->family) {
 476         case CHIP_CAYMAN:
 477                 force_no_swizzle = true;
 478                 break;
 479         default:
 480                 force_no_swizzle = false;
 481                 break;
 482         }
 483         if (force_no_swizzle) {
 484                 bool last_backend_enabled = false;
 485
 486                 force_no_swizzle = false;
 487                 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
 488                         if (((enabled_backends_mask >> i) & 1) == 1) {
 489                                 if (last_backend_enabled)
 490                                         force_no_swizzle = true;
 491                                 last_backend_enabled = true;
 492                         } else
 493                                 last_backend_enabled = false;
 494                 }
 495         }
 496
 497         switch (num_tile_pipes) {
 498         case 1:
 499         case 3:
 500         case 5:
 501         case 7:
 502                 DRM_ERROR("odd number of pipes!\n");
 503                 break;
 504         case 2:
 505                 swizzle_pipe[0] = 0;
 506                 swizzle_pipe[1] = 1;
 507                 break;
 508         case 4:
 509                 if (force_no_swizzle) {
 510                         swizzle_pipe[0] = 0;
 511                         swizzle_pipe[1] = 1;
 512                         swizzle_pipe[2] = 2;
 513                         swizzle_pipe[3] = 3;
 514                 } else {
 515                         swizzle_pipe[0] = 0;
 516                         swizzle_pipe[1] = 2;
 517                         swizzle_pipe[2] = 1;
 518                         swizzle_pipe[3] = 3;
 519                 }
 520                 break;
 521         case 6:
 522                 if (force_no_swizzle) {
 523                         swizzle_pipe[0] = 0;
 524                         swizzle_pipe[1] = 1;
 525                         swizzle_pipe[2] = 2;
 526                         swizzle_pipe[3] = 3;
 527                         swizzle_pipe[4] = 4;
 528                         swizzle_pipe[5] = 5;
 529                 } else {
 530                         swizzle_pipe[0] = 0;
 531                         swizzle_pipe[1] = 2;
 532                         swizzle_pipe[2] = 4;
 533                         swizzle_pipe[3] = 1;
 534                         swizzle_pipe[4] = 3;
 535                         swizzle_pipe[5] = 5;
 536                 }
 537                 break;
 538         case 8:
 539                 if (force_no_swizzle) {
 540                         swizzle_pipe[0] = 0;
 541                         swizzle_pipe[1] = 1;
 542                         swizzle_pipe[2] = 2;
 543                         swizzle_pipe[3] = 3;
 544                         swizzle_pipe[4] = 4;
 545                         swizzle_pipe[5] = 5;
 546                         swizzle_pipe[6] = 6;
 547                         swizzle_pipe[7] = 7;
 548                 } else {
 549                         swizzle_pipe[0] = 0;
 550                         swizzle_pipe[1] = 2;
 551                         swizzle_pipe[2] = 4;
 552                         swizzle_pipe[3] = 6;
 553                         swizzle_pipe[4] = 1;
 554                         swizzle_pipe[5] = 3;
 555                         swizzle_pipe[6] = 5;
 556                         swizzle_pipe[7] = 7;
 557                 }
 558                 break;
 559         }
 560
 561         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 562                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 563                         cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
 564
 565                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
 566
 567                 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
 568         }
 569
 570         return backend_map;
 571 }
 572
 573 static void cayman_program_channel_remap(struct radeon_device *rdev)
 574 {
 575         u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
 576
 577         tmp = RREG32(MC_SHARED_CHMAP);
 578         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 579         case 0:
 580         case 1:
 581         case 2:
 582         case 3:
 583         default:
 584                 /* default mapping */
 585                 mc_shared_chremap = 0x00fac688;
 586                 break;
 587         }
 588
 589         switch (rdev->family) {
 590         case CHIP_CAYMAN:
 591         default:
 592                 //tcp_chan_steer_lo = 0x54763210
 593                 tcp_chan_steer_lo = 0x76543210;
 594                 tcp_chan_steer_hi = 0x0000ba98;
 595                 break;
 596         }
 597
 598         WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
 599         WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
 600         WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
 601 }
 602
 603 static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
 604                                             u32 disable_mask_per_se,
 605                                             u32 max_disable_mask_per_se,
 606                                             u32 num_shader_engines)
 607 {
 608         u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
 609         u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
 610
 611         if (num_shader_engines == 1)
 612                 return disable_mask_per_asic;
 613         else if (num_shader_engines == 2)
 614                 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
 615         else
 616                 return 0xffffffff;
 617 }
 618
 619 static void cayman_gpu_init(struct radeon_device *rdev)
 620 {
 621         u32 cc_rb_backend_disable = 0;
 622         u32 cc_gc_shader_pipe_config;
 623         u32 gb_addr_config = 0;
 624         u32 mc_shared_chmap, mc_arb_ramcfg;
 625         u32 gb_backend_map;
 626         u32 cgts_tcc_disable;
 627         u32 sx_debug_1;
 628         u32 smx_dc_ctl0;
 629         u32 gc_user_shader_pipe_config;
 630         u32 gc_user_rb_backend_disable;
 631         u32 cgts_user_tcc_disable;
 632         u32 cgts_sm_ctrl_reg;
 633         u32 hdp_host_path_cntl;
 634         u32 tmp;
 635         int i, j;
 636
 637         switch (rdev->family) {
 638         case CHIP_CAYMAN:
 639         default:
 640                 rdev->config.cayman.max_shader_engines = 2;
 641                 rdev->config.cayman.max_pipes_per_simd = 4;
 642                 rdev->config.cayman.max_tile_pipes = 8;
 643                 rdev->config.cayman.max_simds_per_se = 12;
 644                 rdev->config.cayman.max_backends_per_se = 4;
 645                 rdev->config.cayman.max_texture_channel_caches = 8;
 646                 rdev->config.cayman.max_gprs = 256;
 647                 rdev->config.cayman.max_threads = 256;
 648                 rdev->config.cayman.max_gs_threads = 32;
 649                 rdev->config.cayman.max_stack_entries = 512;
 650                 rdev->config.cayman.sx_num_of_sets = 8;
 651                 rdev->config.cayman.sx_max_export_size = 256;
 652                 rdev->config.cayman.sx_max_export_pos_size = 64;
 653                 rdev->config.cayman.sx_max_export_smx_size = 192;
 654                 rdev->config.cayman.max_hw_contexts = 8;
 655                 rdev->config.cayman.sq_num_cf_insts = 2;
 656
 657                 rdev->config.cayman.sc_prim_fifo_size = 0x100;
 658                 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
 659                 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
 660                 break;
 661         }
 662
 663         /* Initialize HDP */
 664         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 665                 WREG32((0x2c14 + j), 0x00000000);
 666                 WREG32((0x2c18 + j), 0x00000000);
 667                 WREG32((0x2c1c + j), 0x00000000);
 668                 WREG32((0x2c20 + j), 0x00000000);
 669                 WREG32((0x2c24 + j), 0x00000000);
 670         }
 671
 672         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 673
 674         evergreen_fix_pci_max_read_req_size(rdev);
 675
 676         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
 677         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 678
 679         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
 680         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
 681         cgts_tcc_disable = 0xff000000;
 682         gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
 683         gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);
 684         cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
 685
 686         rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines;
 687         tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
 688         rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp);
 689         rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes;
 690         tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT;
 691         rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp);
 692         tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
 693         rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp);
 694         tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
 695         rdev->config.cayman.backend_disable_mask_per_asic =
 696                 cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK,
 697                                                  rdev->config.cayman.num_shader_engines);
 698         rdev->config.cayman.backend_map =
 699                 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
 700                                                     rdev->config.cayman.num_backends_per_se *
 701                                                     rdev->config.cayman.num_shader_engines,
 702                                                     &rdev->config.cayman.backend_disable_mask_per_asic,
 703                                                     rdev->config.cayman.num_shader_engines);
 704         tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
 705         rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp);
 706         tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT;
 707         rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
 708         if (rdev->config.cayman.mem_max_burst_length_bytes > 512)
 709                 rdev->config.cayman.mem_max_burst_length_bytes = 512;
 710         tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
 711         rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
 712         if (rdev->config.cayman.mem_row_size_in_kb > 4)
 713                 rdev->config.cayman.mem_row_size_in_kb = 4;
 714         /* XXX use MC settings? */
 715         rdev->config.cayman.shader_engine_tile_size = 32;
 716         rdev->config.cayman.num_gpus = 1;
 717         rdev->config.cayman.multi_gpu_tile_size = 64;
 718
 719         //gb_addr_config = 0x02011003
 720 #if 0
 721         gb_addr_config = RREG32(GB_ADDR_CONFIG);
 722 #else
 723         gb_addr_config = 0;
 724         switch (rdev->config.cayman.num_tile_pipes) {
 725         case 1:
 726         default:
 727                 gb_addr_config |= NUM_PIPES(0);
 728                 break;
 729         case 2:
 730                 gb_addr_config |= NUM_PIPES(1);
 731                 break;
 732         case 4:
 733                 gb_addr_config |= NUM_PIPES(2);
 734                 break;
 735         case 8:
 736                 gb_addr_config |= NUM_PIPES(3);
 737                 break;
 738         }
 739
 740         tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1;
 741         gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
 742         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1);
 743         tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1;
 744         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
 745         switch (rdev->config.cayman.num_gpus) {
 746         case 1:
 747         default:
 748                 gb_addr_config |= NUM_GPUS(0);
 749                 break;
 750         case 2:
 751                 gb_addr_config |= NUM_GPUS(1);
 752                 break;
 753         case 4:
 754                 gb_addr_config |= NUM_GPUS(2);
 755                 break;
 756         }
 757         switch (rdev->config.cayman.multi_gpu_tile_size) {
 758         case 16:
 759                 gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
 760                 break;
 761         case 32:
 762         default:
 763                 gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
 764                 break;
 765         case 64:
 766                 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
 767                 break;
 768         case 128:
 769                 gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
 770                 break;
 771         }
 772         switch (rdev->config.cayman.mem_row_size_in_kb) {
 773         case 1:
 774         default:
 775                 gb_addr_config |= ROW_SIZE(0);
 776                 break;
 777         case 2:
 778                 gb_addr_config |= ROW_SIZE(1);
 779                 break;
 780         case 4:
 781                 gb_addr_config |= ROW_SIZE(2);
 782                 break;
 783         }
 784 #endif
 785
 786         tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
 787         rdev->config.cayman.num_tile_pipes = (1 << tmp);
 788         tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
 789         rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
 790         tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
 791         rdev->config.cayman.num_shader_engines = tmp + 1;
 792         tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
 793         rdev->config.cayman.num_gpus = tmp + 1;
 794         tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
 795         rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
 796         tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
 797         rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
 798
 799         //gb_backend_map = 0x76541032;
 800 #if 0
 801         gb_backend_map = RREG32(GB_BACKEND_MAP);
 802 #else
 803         gb_backend_map =
 804                 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
 805                                                     rdev->config.cayman.num_backends_per_se *
 806                                                     rdev->config.cayman.num_shader_engines,
 807                                                     &rdev->config.cayman.backend_disable_mask_per_asic,
 808                                                     rdev->config.cayman.num_shader_engines);
 809 #endif
 810         /* setup tiling info dword.  gb_addr_config is not adequate since it does
 811          * not have bank info, so create a custom tiling dword.
 812          * bits 3:0   num_pipes
 813          * bits 7:4   num_banks
 814          * bits 11:8  group_size
 815          * bits 15:12 row_size
 816          */
 817         rdev->config.cayman.tile_config = 0;
 818         switch (rdev->config.cayman.num_tile_pipes) {
 819         case 1:
 820         default:
 821                 rdev->config.cayman.tile_config |= (0 << 0);
 822                 break;
 823         case 2:
 824                 rdev->config.cayman.tile_config |= (1 << 0);
 825                 break;
 826         case 4:
 827                 rdev->config.cayman.tile_config |= (2 << 0);
 828                 break;
 829         case 8:
 830                 rdev->config.cayman.tile_config |= (3 << 0);
 831                 break;
 832         }
 833         rdev->config.cayman.tile_config |=
 834                 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
 835         rdev->config.cayman.tile_config |=
 836                 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
 837         rdev->config.cayman.tile_config |=
 838                 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
 839
 840         rdev->config.cayman.backend_map = gb_backend_map;
 841         WREG32(GB_BACKEND_MAP, gb_backend_map);
 842         WREG32(GB_ADDR_CONFIG, gb_addr_config);
 843         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
 844         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
 845
 846         cayman_program_channel_remap(rdev);
 847
 848         /* primary versions */
 849         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 850         WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 851         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 852
 853         WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
 854         WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
 855
 856         /* user versions */
 857         WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 858         WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 859         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 860
 861         WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
 862         WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
 863
 864         /* reprogram the shader complex */
 865         cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
 866         for (i = 0; i < 16; i++)
 867                 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
 868         WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
 869
 870         /* set HW defaults for 3D engine */
 871         WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
 872
 873         sx_debug_1 = RREG32(SX_DEBUG_1);
 874         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
 875         WREG32(SX_DEBUG_1, sx_debug_1);
 876
 877         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
 878         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
 879         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
 880         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 881
 882         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
 883
 884         /* need to be explicitly zero-ed */
 885         WREG32(VGT_OFFCHIP_LDS_BASE, 0);
 886         WREG32(SQ_LSTMP_RING_BASE, 0);
 887         WREG32(SQ_HSTMP_RING_BASE, 0);
 888         WREG32(SQ_ESTMP_RING_BASE, 0);
 889         WREG32(SQ_GSTMP_RING_BASE, 0);
 890         WREG32(SQ_VSTMP_RING_BASE, 0);
 891         WREG32(SQ_PSTMP_RING_BASE, 0);
 892
 893         WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
 894
 895         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
 896                                         POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
 897                                         SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
 898
 899         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
 900                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
 901                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
 902
 903
 904         WREG32(VGT_NUM_INSTANCES, 1);
 905
 906         WREG32(CP_PERFMON_CNTL, 0);
 907
 908         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
 909                                   FETCH_FIFO_HIWATER(0x4) |
 910                                   DONE_FIFO_HIWATER(0xe0) |
 911                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
 912
 913         WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
 914         WREG32(SQ_CONFIG, (VC_ENABLE |
 915                            EXPORT_SRC_C |
 916                            GFX_PRIO(0) |
 917                            CS1_PRIO(0) |
 918                            CS2_PRIO(1)));
 919         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
 920
 921         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
 922                                           FORCE_EOV_MAX_REZ_CNT(255)));
 923
 924         WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
 925                AUTO_INVLD_EN(ES_AND_GS_AUTO));
 926
 927         WREG32(VGT_GS_VERTEX_REUSE, 16);
 928         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 929
 930         WREG32(CB_PERF_CTR0_SEL_0, 0);
 931         WREG32(CB_PERF_CTR0_SEL_1, 0);
 932         WREG32(CB_PERF_CTR1_SEL_0, 0);
 933         WREG32(CB_PERF_CTR1_SEL_1, 0);
 934         WREG32(CB_PERF_CTR2_SEL_0, 0);
 935         WREG32(CB_PERF_CTR2_SEL_1, 0);
 936         WREG32(CB_PERF_CTR3_SEL_0, 0);
 937         WREG32(CB_PERF_CTR3_SEL_1, 0);
 938
 939         tmp = RREG32(HDP_MISC_CNTL);
 940         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
 941         WREG32(HDP_MISC_CNTL, tmp);
 942
 943         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
 944         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 945
 946         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
 947
 948         udelay(50);
 949 }
 950
 951 /*
 952  * GART
 953  */
 954 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
 955 {
 956         /* flush hdp cache */
 957         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 958
 959         /* bits 0-7 are the VM contexts0-7 */
 960         WREG32(VM_INVALIDATE_REQUEST, 1);
 961 }
 962
 963 int cayman_pcie_gart_enable(struct radeon_device *rdev)
 964 {
 965         int r;
 966
 967         if (rdev->gart.table.vram.robj == NULL) {
 968                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 969                 return -EINVAL;
 970         }
 971         r = radeon_gart_table_vram_pin(rdev);
 972         if (r)
 973                 return r;
 974         radeon_gart_restore(rdev);
 975         /* Setup TLB control */
 976         WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB |
 977                ENABLE_L1_FRAGMENT_PROCESSING |
 978                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 979                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
 980         /* Setup L2 cache */
 981         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
 982                ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 983                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
 984                EFFECTIVE_L2_QUEUE_SIZE(7) |
 985                CONTEXT1_IDENTITY_ACCESS_MODE(1));
 986         WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
 987         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
 988                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
 989         /* setup context0 */
 990         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 991         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 992         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 993         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 994                         (u32)(rdev->dummy_page.addr >> 12));
 995         WREG32(VM_CONTEXT0_CNTL2, 0);
 996         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 997                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 998         /* disable context1-7 */
 999         WREG32(VM_CONTEXT1_CNTL2, 0);
1000         WREG32(VM_CONTEXT1_CNTL, 0);
1001
1002         cayman_pcie_gart_tlb_flush(rdev);
1003         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1004                  (unsigned)(rdev->mc.gtt_size >> 20),
1005                  (unsigned long long)rdev->gart.table_addr);
1006         rdev->gart.ready = true;
1007         return 0;
1008 }
1009
1010 void cayman_pcie_gart_disable(struct radeon_device *rdev)
1011 {
1012         int r;
1013
1014         /* Disable all tables */
1015         WREG32(VM_CONTEXT0_CNTL, 0);
1016         WREG32(VM_CONTEXT1_CNTL, 0);
1017         /* Setup TLB control */
1018         WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1019                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1020                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1021         /* Setup L2 cache */
1022         WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1023                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1024                EFFECTIVE_L2_QUEUE_SIZE(7) |
1025                CONTEXT1_IDENTITY_ACCESS_MODE(1));
1026         WREG32(VM_L2_CNTL2, 0);
1027         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1028                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1029         if (rdev->gart.table.vram.robj) {
1030                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1031                 if (likely(r == 0)) {
1032                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
1033                         radeon_bo_unpin(rdev->gart.table.vram.robj);
1034                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
1035                 }
1036         }
1037 }
1038
1039 void cayman_pcie_gart_fini(struct radeon_device *rdev)
1040 {
1041         cayman_pcie_gart_disable(rdev);
1042         radeon_gart_table_vram_free(rdev);
1043         radeon_gart_fini(rdev);
1044 }
1045
1046 /*
1047  * CP.
1048  */
1049 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1050 {
1051         if (enable)
1052                 WREG32(CP_ME_CNTL, 0);
1053         else {
1054                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1055                 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1056                 WREG32(SCRATCH_UMSK, 0);
1057         }
1058 }
1059
1060 static int cayman_cp_load_microcode(struct radeon_device *rdev)
1061 {
1062         const __be32 *fw_data;
1063         int i;
1064
1065         if (!rdev->me_fw || !rdev->pfp_fw)
1066                 return -EINVAL;
1067
1068         cayman_cp_enable(rdev, false);
1069
1070         fw_data = (const __be32 *)rdev->pfp_fw->data;
1071         WREG32(CP_PFP_UCODE_ADDR, 0);
1072         for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1073                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1074         WREG32(CP_PFP_UCODE_ADDR, 0);
1075
1076         fw_data = (const __be32 *)rdev->me_fw->data;
1077         WREG32(CP_ME_RAM_WADDR, 0);
1078         for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1079                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1080
1081         WREG32(CP_PFP_UCODE_ADDR, 0);
1082         WREG32(CP_ME_RAM_WADDR, 0);
1083         WREG32(CP_ME_RAM_RADDR, 0);
1084         return 0;
1085 }
1086
1087 static int cayman_cp_start(struct radeon_device *rdev)
1088 {
1089         int r, i;
1090
1091         r = radeon_ring_lock(rdev, 7);
1092         if (r) {
1093                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1094                 return r;
1095         }
1096         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1097         radeon_ring_write(rdev, 0x1);
1098         radeon_ring_write(rdev, 0x0);
1099         radeon_ring_write(rdev, rdev->config.cayman.max_hw_contexts - 1);
1100         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1101         radeon_ring_write(rdev, 0);
1102         radeon_ring_write(rdev, 0);
1103         radeon_ring_unlock_commit(rdev);
1104
1105         cayman_cp_enable(rdev, true);
1106
1107         r = radeon_ring_lock(rdev, cayman_default_size + 19);
1108         if (r) {
1109                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1110                 return r;
1111         }
1112
1113         /* setup clear context state */
1114         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1115         radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1116
1117         for (i = 0; i < cayman_default_size; i++)
1118                 radeon_ring_write(rdev, cayman_default_state[i]);
1119
1120         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1121         radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1122
1123         /* set clear context state */
1124         radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1125         radeon_ring_write(rdev, 0);
1126
1127         /* SQ_VTX_BASE_VTX_LOC */
1128         radeon_ring_write(rdev, 0xc0026f00);
1129         radeon_ring_write(rdev, 0x00000000);
1130         radeon_ring_write(rdev, 0x00000000);
1131         radeon_ring_write(rdev, 0x00000000);
1132
1133         /* Clear consts */
1134         radeon_ring_write(rdev, 0xc0036f00);
1135         radeon_ring_write(rdev, 0x00000bc4);
1136         radeon_ring_write(rdev, 0xffffffff);
1137         radeon_ring_write(rdev, 0xffffffff);
1138         radeon_ring_write(rdev, 0xffffffff);
1139
1140         radeon_ring_write(rdev, 0xc0026900);
1141         radeon_ring_write(rdev, 0x00000316);
1142         radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1143         radeon_ring_write(rdev, 0x00000010); /*  */
1144
1145         radeon_ring_unlock_commit(rdev);
1146
1147         /* XXX init other rings */
1148
1149         return 0;
1150 }
1151
1152 static void cayman_cp_fini(struct radeon_device *rdev)
1153 {
1154         cayman_cp_enable(rdev, false);
1155         radeon_ring_fini(rdev);
1156 }
1157
1158 int cayman_cp_resume(struct radeon_device *rdev)
1159 {
1160         u32 tmp;
1161         u32 rb_bufsz;
1162         int r;
1163
1164         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1165         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1166                                  SOFT_RESET_PA |
1167                                  SOFT_RESET_SH |
1168                                  SOFT_RESET_VGT |
1169                                  SOFT_RESET_SPI |
1170                                  SOFT_RESET_SX));
1171         RREG32(GRBM_SOFT_RESET);
1172         mdelay(15);
1173         WREG32(GRBM_SOFT_RESET, 0);
1174         RREG32(GRBM_SOFT_RESET);
1175
1176         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1177
1178         /* Set the write pointer delay */
1179         WREG32(CP_RB_WPTR_DELAY, 0);
1180
1181         WREG32(CP_DEBUG, (1 << 27));
1182
1183         /* ring 0 - compute and gfx */
1184         /* Set ring buffer size */
1185         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1186         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1187 #ifdef __BIG_ENDIAN
1188         tmp |= BUF_SWAP_32BIT;
1189 #endif
1190         WREG32(CP_RB0_CNTL, tmp);
1191
1192         /* Initialize the ring buffer's read and write pointers */
1193         WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1194         WREG32(CP_RB0_WPTR, 0);
1195
1196         /* set the wb address wether it's enabled or not */
1197         WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1198         WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1199         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1200
1201         if (rdev->wb.enabled)
1202                 WREG32(SCRATCH_UMSK, 0xff);
1203         else {
1204                 tmp |= RB_NO_UPDATE;
1205                 WREG32(SCRATCH_UMSK, 0);
1206         }
1207
1208         mdelay(1);
1209         WREG32(CP_RB0_CNTL, tmp);
1210
1211         WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8);
1212
1213         rdev->cp.rptr = RREG32(CP_RB0_RPTR);
1214         rdev->cp.wptr = RREG32(CP_RB0_WPTR);
1215
1216         /* ring1  - compute only */
1217         /* Set ring buffer size */
1218         rb_bufsz = drm_order(rdev->cp1.ring_size / 8);
1219         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1220 #ifdef __BIG_ENDIAN
1221         tmp |= BUF_SWAP_32BIT;
1222 #endif
1223         WREG32(CP_RB1_CNTL, tmp);
1224
1225         /* Initialize the ring buffer's read and write pointers */
1226         WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1227         WREG32(CP_RB1_WPTR, 0);
1228
1229         /* set the wb address wether it's enabled or not */
1230         WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
1231         WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
1232
1233         mdelay(1);
1234         WREG32(CP_RB1_CNTL, tmp);
1235
1236         WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8);
1237
1238         rdev->cp1.rptr = RREG32(CP_RB1_RPTR);
1239         rdev->cp1.wptr = RREG32(CP_RB1_WPTR);
1240
1241         /* ring2 - compute only */
1242         /* Set ring buffer size */
1243         rb_bufsz = drm_order(rdev->cp2.ring_size / 8);
1244         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1245 #ifdef __BIG_ENDIAN
1246         tmp |= BUF_SWAP_32BIT;
1247 #endif
1248         WREG32(CP_RB2_CNTL, tmp);
1249
1250         /* Initialize the ring buffer's read and write pointers */
1251         WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
1252         WREG32(CP_RB2_WPTR, 0);
1253
1254         /* set the wb address wether it's enabled or not */
1255         WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
1256         WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
1257
1258         mdelay(1);
1259         WREG32(CP_RB2_CNTL, tmp);
1260
1261         WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8);
1262
1263         rdev->cp2.rptr = RREG32(CP_RB2_RPTR);
1264         rdev->cp2.wptr = RREG32(CP_RB2_WPTR);
1265
1266         /* start the rings */
1267         cayman_cp_start(rdev);
1268         rdev->cp.ready = true;
1269         rdev->cp1.ready = true;
1270         rdev->cp2.ready = true;
1271         /* this only test cp0 */
1272         r = radeon_ring_test(rdev);
1273         if (r) {
1274                 rdev->cp.ready = false;
1275                 rdev->cp1.ready = false;
1276                 rdev->cp2.ready = false;
1277                 return r;
1278         }
1279
1280         return 0;
1281 }
1282
1283 bool cayman_gpu_is_lockup(struct radeon_device *rdev)
1284 {
1285         u32 srbm_status;
1286         u32 grbm_status;
1287         u32 grbm_status_se0, grbm_status_se1;
1288         struct r100_gpu_lockup *lockup = &rdev->config.cayman.lockup;
1289         int r;
1290
1291         srbm_status = RREG32(SRBM_STATUS);
1292         grbm_status = RREG32(GRBM_STATUS);
1293         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
1294         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
1295         if (!(grbm_status & GUI_ACTIVE)) {
1296                 r100_gpu_lockup_update(lockup, &rdev->cp);
1297                 return false;
1298         }
1299         /* force CP activities */
1300         r = radeon_ring_lock(rdev, 2);
1301         if (!r) {
1302                 /* PACKET2 NOP */
1303                 radeon_ring_write(rdev, 0x80000000);
1304                 radeon_ring_write(rdev, 0x80000000);
1305                 radeon_ring_unlock_commit(rdev);
1306         }
1307         /* XXX deal with CP0,1,2 */
1308         rdev->cp.rptr = RREG32(CP_RB0_RPTR);
1309         return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
1310 }
1311
1312 static int cayman_gpu_soft_reset(struct radeon_device *rdev)
1313 {
1314         struct evergreen_mc_save save;
1315         u32 grbm_reset = 0;
1316
1317         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1318                 return 0;
1319
1320         dev_info(rdev->dev, "GPU softreset \n");
1321         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1322                 RREG32(GRBM_STATUS));
1323         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1324                 RREG32(GRBM_STATUS_SE0));
1325         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1326                 RREG32(GRBM_STATUS_SE1));
1327         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1328                 RREG32(SRBM_STATUS));
1329         evergreen_mc_stop(rdev, &save);
1330         if (evergreen_mc_wait_for_idle(rdev)) {
1331                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1332         }
1333         /* Disable CP parsing/prefetching */
1334         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1335
1336         /* reset all the gfx blocks */
1337         grbm_reset = (SOFT_RESET_CP |
1338                       SOFT_RESET_CB |
1339                       SOFT_RESET_DB |
1340                       SOFT_RESET_GDS |
1341                       SOFT_RESET_PA |
1342                       SOFT_RESET_SC |
1343                       SOFT_RESET_SPI |
1344                       SOFT_RESET_SH |
1345                       SOFT_RESET_SX |
1346                       SOFT_RESET_TC |
1347                       SOFT_RESET_TA |
1348                       SOFT_RESET_VGT |
1349                       SOFT_RESET_IA);
1350
1351         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1352         WREG32(GRBM_SOFT_RESET, grbm_reset);
1353         (void)RREG32(GRBM_SOFT_RESET);
1354         udelay(50);
1355         WREG32(GRBM_SOFT_RESET, 0);
1356         (void)RREG32(GRBM_SOFT_RESET);
1357         /* Wait a little for things to settle down */
1358         udelay(50);
1359         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1360                 RREG32(GRBM_STATUS));
1361         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1362                 RREG32(GRBM_STATUS_SE0));
1363         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1364                 RREG32(GRBM_STATUS_SE1));
1365         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1366                 RREG32(SRBM_STATUS));
1367         evergreen_mc_resume(rdev, &save);
1368         return 0;
1369 }
1370
1371 int cayman_asic_reset(struct radeon_device *rdev)
1372 {
1373         return cayman_gpu_soft_reset(rdev);
1374 }
1375
1376 static int cayman_startup(struct radeon_device *rdev)
1377 {
1378         int r;
1379
1380         /* enable pcie gen2 link */
1381         evergreen_pcie_gen2_enable(rdev);
1382
1383         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1384                 r = ni_init_microcode(rdev);
1385                 if (r) {
1386                         DRM_ERROR("Failed to load firmware!\n");
1387                         return r;
1388                 }
1389         }
1390         r = ni_mc_load_microcode(rdev);
1391         if (r) {
1392                 DRM_ERROR("Failed to load MC firmware!\n");
1393                 return r;
1394         }
1395
1396         evergreen_mc_program(rdev);
1397         r = cayman_pcie_gart_enable(rdev);
1398         if (r)
1399                 return r;
1400         cayman_gpu_init(rdev);
1401
1402         r = evergreen_blit_init(rdev);
1403         if (r) {
1404                 evergreen_blit_fini(rdev);
1405                 rdev->asic->copy = NULL;
1406                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1407         }
1408
1409         /* allocate wb buffer */
1410         r = radeon_wb_init(rdev);
1411         if (r)
1412                 return r;
1413
1414         /* Enable IRQ */
1415         r = r600_irq_init(rdev);
1416         if (r) {
1417                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1418                 radeon_irq_kms_fini(rdev);
1419                 return r;
1420         }
1421         evergreen_irq_set(rdev);
1422
1423         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1424         if (r)
1425                 return r;
1426         r = cayman_cp_load_microcode(rdev);
1427         if (r)
1428                 return r;
1429         r = cayman_cp_resume(rdev);
1430         if (r)
1431                 return r;
1432
1433         return 0;
1434 }
1435
1436 int cayman_resume(struct radeon_device *rdev)
1437 {
1438         int r;
1439
1440         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1441          * posting will perform necessary task to bring back GPU into good
1442          * shape.
1443          */
1444         /* post card */
1445         atom_asic_init(rdev->mode_info.atom_context);
1446
1447         r = cayman_startup(rdev);
1448         if (r) {
1449                 DRM_ERROR("cayman startup failed on resume\n");
1450                 return r;
1451         }
1452
1453         r = r600_ib_test(rdev);
1454         if (r) {
1455                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1456                 return r;
1457         }
1458
1459         return r;
1460
1461 }
1462
1463 int cayman_suspend(struct radeon_device *rdev)
1464 {
1465         int r;
1466
1467         /* FIXME: we should wait for ring to be empty */
1468         cayman_cp_enable(rdev, false);
1469         rdev->cp.ready = false;
1470         evergreen_irq_suspend(rdev);
1471         radeon_wb_disable(rdev);
1472         cayman_pcie_gart_disable(rdev);
1473
1474         /* unpin shaders bo */
1475         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1476         if (likely(r == 0)) {
1477                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1478                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1479         }
1480
1481         return 0;
1482 }
1483
1484 /* Plan is to move initialization in that function and use
1485  * helper function so that radeon_device_init pretty much
1486  * do nothing more than calling asic specific function. This
1487  * should also allow to remove a bunch of callback function
1488  * like vram_info.
1489  */
1490 int cayman_init(struct radeon_device *rdev)
1491 {
1492         int r;
1493
1494         /* This don't do much */
1495         r = radeon_gem_init(rdev);
1496         if (r)
1497                 return r;
1498         /* Read BIOS */
1499         if (!radeon_get_bios(rdev)) {
1500                 if (ASIC_IS_AVIVO(rdev))
1501                         return -EINVAL;
1502         }
1503         /* Must be an ATOMBIOS */
1504         if (!rdev->is_atom_bios) {
1505                 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1506                 return -EINVAL;
1507         }
1508         r = radeon_atombios_init(rdev);
1509         if (r)
1510                 return r;
1511
1512         /* Post card if necessary */
1513         if (!radeon_card_posted(rdev)) {
1514                 if (!rdev->bios) {
1515                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1516                         return -EINVAL;
1517                 }
1518                 DRM_INFO("GPU not posted. posting now...\n");
1519                 atom_asic_init(rdev->mode_info.atom_context);
1520         }
1521         /* Initialize scratch registers */
1522         r600_scratch_init(rdev);
1523         /* Initialize surface registers */
1524         radeon_surface_init(rdev);
1525         /* Initialize clocks */
1526         radeon_get_clock_info(rdev->ddev);
1527         /* Fence driver */
1528         r = radeon_fence_driver_init(rdev);
1529         if (r)
1530                 return r;
1531         /* initialize memory controller */
1532         r = evergreen_mc_init(rdev);
1533         if (r)
1534                 return r;
1535         /* Memory manager */
1536         r = radeon_bo_init(rdev);
1537         if (r)
1538                 return r;
1539
1540         r = radeon_irq_kms_init(rdev);
1541         if (r)
1542                 return r;
1543
1544         rdev->cp.ring_obj = NULL;
1545         r600_ring_init(rdev, 1024 * 1024);
1546
1547         rdev->ih.ring_obj = NULL;
1548         r600_ih_ring_init(rdev, 64 * 1024);
1549
1550         r = r600_pcie_gart_init(rdev);
1551         if (r)
1552                 return r;
1553
1554         rdev->accel_working = true;
1555         r = cayman_startup(rdev);
1556         if (r) {
1557                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1558                 cayman_cp_fini(rdev);
1559                 r600_irq_fini(rdev);
1560                 radeon_wb_fini(rdev);
1561                 radeon_irq_kms_fini(rdev);
1562                 cayman_pcie_gart_fini(rdev);
1563                 rdev->accel_working = false;
1564         }
1565         if (rdev->accel_working) {
1566                 r = radeon_ib_pool_init(rdev);
1567                 if (r) {
1568                         DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
1569                         rdev->accel_working = false;
1570                 }
1571                 r = r600_ib_test(rdev);
1572                 if (r) {
1573                         DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1574                         rdev->accel_working = false;
1575                 }
1576         }
1577
1578         /* Don't start up if the MC ucode is missing.
1579          * The default clocks and voltages before the MC ucode
1580          * is loaded are not suffient for advanced operations.
1581          */
1582         if (!rdev->mc_fw) {
1583                 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1584                 return -EINVAL;
1585         }
1586
1587         return 0;
1588 }
1589
1590 void cayman_fini(struct radeon_device *rdev)
1591 {
1592         evergreen_blit_fini(rdev);
1593         cayman_cp_fini(rdev);
1594         r600_irq_fini(rdev);
1595         radeon_wb_fini(rdev);
1596         radeon_ib_pool_fini(rdev);
1597         radeon_irq_kms_fini(rdev);
1598         cayman_pcie_gart_fini(rdev);
1599         radeon_gem_fini(rdev);
1600         radeon_fence_driver_fini(rdev);
1601         radeon_bo_fini(rdev);
1602         radeon_atombios_fini(rdev);
1603         kfree(rdev->bios);
1604         rdev->bios = NULL;
1605 }
1606